| commit | abfbd89595e91d5108f807e10bbd2152bc55f36b | [log] [tgz] |
|---|---|---|
| author | Max Filippov <jcmvbkbc@gmail.com> | Mon Aug 24 19:44:46 2015 +0300 |
| committer | Chris Zankel <chris@zankel.net> | Fri Mar 11 08:53:31 2016 +0000 |
| tree | fea9190c224b121a092723b450f3d03a9b84a992 | |
| parent | 4611bf7eb52599cb7549eed10f1ab609cbcdfa4b [diff] |
xtensa: xtfpga: fix serial port register width and endianness Serial port is attached to XTFPGA boards as native endian device, mark it as such in DTS and pass correct endianness in platform data. Set register width in DTS to 4, this way it matches the platform data and works correctly on big-endian CPUs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>