| commit | ac03d8b3a592a0b562fce2376030baf9a572f7c1 | [log] [tgz] |
|---|---|---|
| author | Gabriel Fernandez <gabriel.fernandez@st.com> | Thu Mar 16 09:16:41 2017 +0100 |
| committer | Michael Turquette <mturquette@baylibre.com> | Wed Apr 12 18:50:56 2017 +0200 |
| tree | edabb6be5fc1fa580b0a7d7c61f141f93d263980 | |
| parent | d5a0945fdf89ad293ccaa2be588635f4bfc0cd62 [diff] |
clk: stm32f4: fix timeout management for pll and ready gate
Use a classic polling to test bit ready.
And the shift of the bit ready of LSE & LSI were wrongs.
Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>