mfd: max77836: Add MAX77836 support to max14577 driver
Add Maxim 77836 support to max14577 driver. The chipsets have same MUIC
component so the extcon, charger and regulators are almost the same. The
MAX77836 however has also PMIC and Fuel Gauge.
The MAX77836 uses three I2C slave addresses and has additional interrupts
(related to PMIC and Fuel Gauge). It has also Interrupt Source register,
just like MAX77686 and MAX77693.
The MAX77836 PMIC's TOPSYS and INTSRC interrupts are reported in the
PMIC block. The PMIC block has different I2C slave address and uses own
regmap so another regmap_irq_chip is needed.
Since we have two regmap_irq_chip, use shared interrupts on MAX77836.
This patch adds additional defines and functions to the max14577 MFD core
driver so the driver will handle both chipsets. Also this patch replaces
"0x1 << N" with BIT(N) in defines for register masks.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
diff --git a/include/linux/mfd/max14577-private.h b/include/linux/mfd/max14577-private.h
index 989183d..e301bd1 100644
--- a/include/linux/mfd/max14577-private.h
+++ b/include/linux/mfd/max14577-private.h
@@ -1,7 +1,7 @@
/*
- * max14577-private.h - Common API for the Maxim 14577 internal sub chip
+ * max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip
*
- * Copyright (C) 2013 Samsung Electrnoics
+ * Copyright (C) 2014 Samsung Electrnoics
* Chanwoo Choi <cw00.choi@samsung.com>
* Krzysztof Kozlowski <k.kozlowski@samsung.com>
*
@@ -22,9 +22,14 @@
#include <linux/i2c.h>
#include <linux/regmap.h>
+#define I2C_ADDR_PMIC (0x46 >> 1)
+#define I2C_ADDR_MUIC (0x4A >> 1)
+#define I2C_ADDR_FG (0x6C >> 1)
+
enum maxim_device_type {
MAXIM_DEVICE_TYPE_UNKNOWN = 0,
MAXIM_DEVICE_TYPE_MAX14577,
+ MAXIM_DEVICE_TYPE_MAX77836,
MAXIM_DEVICE_TYPE_NUM,
};
@@ -88,6 +93,7 @@
#define MAX14577_INT2_DCDTMR_MASK BIT(2)
#define MAX14577_INT2_DBCHG_MASK BIT(3)
#define MAX14577_INT2_VBVOLT_MASK BIT(4)
+#define MAX77836_INT2_VIDRM_MASK BIT(5)
#define MAX14577_INT3_EOC_MASK BIT(0)
#define MAX14577_INT3_CGMBC_MASK BIT(1)
@@ -104,9 +110,11 @@
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCLOW_SHIFT 5
#define STATUS1_ADCERR_SHIFT 6
+#define MAX77836_STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
-#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
-#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
+#define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT)
+#define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT)
+#define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT)
/* MAX14577 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
@@ -114,11 +122,13 @@
#define STATUS2_DCDTMR_SHIFT 4
#define STATUS2_DBCHG_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
+#define MAX77836_STATUS2_VIDRM_SHIFT 7
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
-#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
-#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
-#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
-#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
+#define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
+#define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
+#define STATUS2_DBCHG_MASK BIT(STATUS2_DBCHG_SHIFT)
+#define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
+#define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT)
/* MAX14577 CONTROL1 register */
#define COMN1SW_SHIFT 0
@@ -127,8 +137,8 @@
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
-#define MICEN_MASK (0x1 << MICEN_SHIFT)
-#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
+#define MICEN_MASK BIT(MICEN_SHIFT)
+#define IDBEN_MASK BIT(IDBEN_SHIFT)
#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \
| (1 << COMN1SW_SHIFT))
@@ -148,14 +158,14 @@
#define CTRL2_ACCDET_SHIFT (5)
#define CTRL2_USBCPINT_SHIFT (6)
#define CTRL2_RCPS_SHIFT (7)
-#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
-#define CTRL2_ADCEN_MASK (0x1 << CTRL2_ADCEN_SHIFT)
-#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
-#define CTRL2_SFOUTASRT_MASK (0x1 << CTRL2_SFOUTASRT_SHIFT)
-#define CTRL2_SFOUTORD_MASK (0x1 << CTRL2_SFOUTORD_SHIFT)
-#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
-#define CTRL2_USBCPINT_MASK (0x1 << CTRL2_USBCPINT_SHIFT)
-#define CTRL2_RCPS_MASK (0x1 << CTR2_RCPS_SHIFT)
+#define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT)
+#define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT)
+#define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT)
+#define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT)
+#define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT)
+#define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT)
+#define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT)
+#define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT)
#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
(0 << CTRL2_LOWPWR_SHIFT))
@@ -203,14 +213,14 @@
#define CDETCTRL1_DBEXIT_SHIFT 5
#define CDETCTRL1_DBIDLE_SHIFT 6
#define CDETCTRL1_CDPDET_SHIFT 7
-#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
-#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
-#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
-#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
-#define CDETCTRL1_DCHKTM_MASK (0x1 << CDETCTRL1_DCHKTM_SHIFT)
-#define CDETCTRL1_DBEXIT_MASK (0x1 << CDETCTRL1_DBEXIT_SHIFT)
-#define CDETCTRL1_DBIDLE_MASK (0x1 << CDETCTRL1_DBIDLE_SHIFT)
-#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
+#define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT)
+#define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT)
+#define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT)
+#define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT)
+#define CDETCTRL1_DCHKTM_MASK BIT(CDETCTRL1_DCHKTM_SHIFT)
+#define CDETCTRL1_DBEXIT_MASK BIT(CDETCTRL1_DBEXIT_SHIFT)
+#define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT)
+#define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT)
/* MAX14577 CHGCTRL1 register */
#define CHGCTRL1_TCHW_SHIFT 4
@@ -218,9 +228,9 @@
/* MAX14577 CHGCTRL2 register */
#define CHGCTRL2_MBCHOSTEN_SHIFT 6
-#define CHGCTRL2_MBCHOSTEN_MASK (0x1 << CHGCTRL2_MBCHOSTEN_SHIFT)
+#define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT)
#define CHGCTRL2_VCHGR_RC_SHIFT 7
-#define CHGCTRL2_VCHGR_RC_MASK (0x1 << CHGCTRL2_VCHGR_RC_SHIFT)
+#define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT)
/* MAX14577 CHGCTRL3 register */
#define CHGCTRL3_MBCCVWRC_SHIFT 0
@@ -230,7 +240,7 @@
#define CHGCTRL4_MBCICHWRCH_SHIFT 0
#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
#define CHGCTRL4_MBCICHWRCL_SHIFT 4
-#define CHGCTRL4_MBCICHWRCL_MASK (0x1 << CHGCTRL4_MBCICHWRCL_SHIFT)
+#define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT)
/* MAX14577 CHGCTRL5 register */
#define CHGCTRL5_EOCS_SHIFT 0
@@ -238,7 +248,7 @@
/* MAX14577 CHGCTRL6 register */
#define CHGCTRL6_AUTOSTOP_SHIFT 5
-#define CHGCTRL6_AUTOSTOP_MASK (0x1 << CHGCTRL6_AUTOSTOP_SHIFT)
+#define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT)
/* MAX14577 CHGCTRL7 register */
#define CHGCTRL7_OTPCGHCVS_SHIFT 0
@@ -253,6 +263,70 @@
/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
+/* Slave addr = 0x46: PMIC */
+enum max77836_pmic_reg {
+ MAX77836_PMIC_REG_PMIC_ID = 0x20,
+ MAX77836_PMIC_REG_PMIC_REV = 0x21,
+ MAX77836_PMIC_REG_INTSRC = 0x22,
+ MAX77836_PMIC_REG_INTSRC_MASK = 0x23,
+ MAX77836_PMIC_REG_TOPSYS_INT = 0x24,
+ MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26,
+ MAX77836_PMIC_REG_TOPSYS_STAT = 0x28,
+ MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A,
+ MAX77836_PMIC_REG_LSCNFG = 0x2B,
+
+ MAX77836_LDO_REG_CNFG1_LDO1 = 0x51,
+ MAX77836_LDO_REG_CNFG2_LDO1 = 0x52,
+ MAX77836_LDO_REG_CNFG1_LDO2 = 0x53,
+ MAX77836_LDO_REG_CNFG2_LDO2 = 0x54,
+ MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55,
+
+ MAX77836_COMP_REG_COMP1 = 0x60,
+
+ MAX77836_PMIC_REG_END,
+};
+
+#define MAX77836_INTSRC_MASK_TOP_INT_SHIFT 1
+#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3
+#define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT)
+#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT)
+
+/* MAX77836 PMIC interrupts */
+#define MAX77836_TOPSYS_INT_T120C_SHIFT 0
+#define MAX77836_TOPSYS_INT_T140C_SHIFT 1
+#define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT)
+#define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT)
+
+/* Slave addr = 0x6C: Fuel-Gauge/Battery */
+enum max77836_fg_reg {
+ MAX77836_FG_REG_VCELL_MSB = 0x02,
+ MAX77836_FG_REG_VCELL_LSB = 0x03,
+ MAX77836_FG_REG_SOC_MSB = 0x04,
+ MAX77836_FG_REG_SOC_LSB = 0x05,
+ MAX77836_FG_REG_MODE_H = 0x06,
+ MAX77836_FG_REG_MODE_L = 0x07,
+ MAX77836_FG_REG_VERSION_MSB = 0x08,
+ MAX77836_FG_REG_VERSION_LSB = 0x09,
+ MAX77836_FG_REG_HIBRT_H = 0x0A,
+ MAX77836_FG_REG_HIBRT_L = 0x0B,
+ MAX77836_FG_REG_CONFIG_H = 0x0C,
+ MAX77836_FG_REG_CONFIG_L = 0x0D,
+ MAX77836_FG_REG_VALRT_MIN = 0x14,
+ MAX77836_FG_REG_VALRT_MAX = 0x15,
+ MAX77836_FG_REG_CRATE_MSB = 0x16,
+ MAX77836_FG_REG_CRATE_LSB = 0x17,
+ MAX77836_FG_REG_VRESET = 0x18,
+ MAX77836_FG_REG_FGID = 0x19,
+ MAX77836_FG_REG_STATUS_H = 0x1A,
+ MAX77836_FG_REG_STATUS_L = 0x1B,
+ /*
+ * TODO: TABLE registers
+ * TODO: CMD register
+ */
+
+ MAX77836_FG_REG_END,
+};
+
enum max14577_irq {
/* INT1 */
MAX14577_IRQ_INT1_ADC,
@@ -272,17 +346,24 @@
MAX14577_IRQ_INT3_OVP,
MAX14577_IRQ_INT3_MBCCHGERR,
+ /* TOPSYS_INT, only MAX77836 */
+ MAX77836_IRQ_TOPSYS_T140C,
+ MAX77836_IRQ_TOPSYS_T120C,
+
MAX14577_IRQ_NUM,
};
struct max14577 {
struct device *dev;
struct i2c_client *i2c; /* Slave addr = 0x4A */
+ struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */
enum maxim_device_type dev_type;
- struct regmap *regmap;
+ struct regmap *regmap; /* For MUIC and Charger */
+ struct regmap *regmap_pmic;
- struct regmap_irq_chip_data *irq_data;
+ struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */
+ struct regmap_irq_chip_data *irq_data_pmic;
int irq;
};