| commit | 4553474d977d1ee8a81067cfbc588f1df84ce3e9 | [log] [tgz] |
|---|---|---|
| author | Stafford Horne <shorne@gmail.com> | Fri Jul 07 06:06:30 2017 +0900 |
| committer | Stafford Horne <shorne@gmail.com> | Fri Nov 03 14:01:16 2017 +0900 |
| tree | 4e74260eb9134fd94a7bc20fc3ab23e4ecb3a7e1 | |
| parent | 78cdfb5cf15e0f9fb4c2a9176a13a907a1d024f0 [diff] |
openrisc: add tick timer multi-core sync logic In case timers are not in sync when cpus start (i.e. hot plug / offset resets) we need to synchronize the secondary cpus internal timer with the main cpu. This is needed as in OpenRISC SMP there is only one clocksource registered which reads from the same ttcr register on each cpu. This synchronization routine heavily borrows from mips implementation that does something similar. Signed-off-by: Stafford Horne <shorne@gmail.com>