| commit | b29de2de5049e064d172862b1feeddeb650c3ee8 | [log] [tgz] |
|---|---|---|
| author | Xing Zheng <zhengxing@rock-chips.com> | Thu Jan 07 20:17:34 2016 +0800 |
| committer | Heiko Stuebner <heiko@sntech.de> | Sat Jan 16 16:01:21 2016 +0100 |
| tree | 7c91f5af0e59c1d2f213335ae5f57bb8e7908372 | |
| parent | 99222c9e4de7feb22c93b19a92b35fcdad73ed42 [diff] |
clk: rockchip: rk3036: fix uarts clock error Due to a copy-paste error the uart1 and uart2 clock div set incorrect, fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>