| commit | 16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c | [log] [tgz] |
|---|---|---|
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | Tue Nov 02 17:30:46 2010 +0800 |
| committer | Chris Wilson <chris@chris-wilson.co.uk> | Thu Nov 04 09:39:50 2010 +0000 |
| tree | 8a4d083794272b7d7bf82aad75076a7722164b23 | |
| parent | 8d0f56708292ca5c256ee3b7187d124afee81d93 [diff] |
agp/intel: fix cache control for sandybridge This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>