| commit | b5964708532f4713e9cfb1b8b1a6ac8544fc66af | [log] [tgz] |
|---|---|---|
| author | Mark Langsdorf <mark.langsdorf@calxeda.com> | Mon Jan 28 16:13:13 2013 +0000 |
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | Sat Feb 02 00:01:15 2013 +0100 |
| tree | ac0b962debf44ef6a15a6ea0a652633f1afe372f | |
| parent | bd603455f366bd66a5e1870bc285c05c9cb6a72d [diff] |
clk / highbank: Prevent glitches in non-bypass reset mode The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>