| commit | 2f3b4f96861913008f96ceaedabad7605b164345 | [log] [tgz] |
|---|---|---|
| author | Andre Przywara <andre.przywara@arm.com> | Wed Jan 23 00:59:11 2019 +0000 |
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | Sat Mar 23 20:09:47 2019 +0100 |
| tree | feecc3925643e697b24afd3779f9639abc0d4f36 | |
| parent | cacf3c0d82889b7628e98952bf1207aff398389a [diff] |
clk: sunxi: A31: Fix wrong AHB gate number
[ Upstream commit ee0b27a3a4da0b0ed2318aa092f8856896e9450b ]
According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.
Fix the gate bit definitions in the clock driver.
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>