tree d6fc73de26b1344736a59965b336bb7c6b245a31
parent 0dde52a9f5330eec240660191a94b51bd911ffcd
author Benoit Cousson <b-cousson@ti.com> 1299750795 +0100
committer Benoit Cousson <b-cousson@ti.com> 1299751440 +0100

OMAP3: hwmod data: Fix incorrect SmartReflex -> L4 CORE interconnect links

Commit d34427267186827dfd62bd8cf726601fffb22534 ("OMAP3: PM: Adding
smartreflex hwmod data") added data that claims that the L4 CORE has
two slave interfaces that originate from the SmartReflex modules,
omap3_l4_core__sr1 and omap3_l4_core__sr2.  But as those two data
structure records show, it's L4 CORE that has a master port towards
SR1 and SR2.
Move the incorrect data from slaves list to master list.

Based on a path by Paul Walmsley <paul@pwsan.com>

    https://patchwork.kernel.org/patch/623171/

That is based on a patch by Benoît Cousson <b-cousson@ti.com>:

    https://patchwork.kernel.org/patch/590561/

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoît Cousson <b-cousson@ti.com>
Cc: Sanjeev Premi <premi@ti.com>
Cc: Thara Gopinath <thara@ti.com>