| commit | bba1431211e6fdc56680d98d2bdabaab1fd13b79 | [log] [tgz] |
|---|---|---|
| author | Jianqun Xu <jay.xu@rock-chips.com> | Wed Dec 24 17:37:01 2014 +0800 |
| committer | Mark Brown <broonie@kernel.org> | Wed Dec 24 12:43:40 2014 +0000 |
| tree | 69315f8545ec2e035fbebe70e1f14f78a88d8be8 | |
| parent | 97bf6af1f928216fd6c5a66e8a57bfa95a659672 [diff] |
ASoC: rockchip: i2s: set TDL and RDL to 16 samples Set Transmit Data Level(TDL) and Receive Data Level(RDL) to 16 samples. Without this setting, the TDL is default to be 0x00 (means 0 sample), and the RDL is default to be 0x1f (means 32 samples). Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>