tree 051da254ea09ce51759123472fbcc52002c0ad53
parent b57bd2de8c6c9aa03f1b899edd6f5582cc8b5b08
author Jack Miller <jack@codezen.org> 1465439469 +1000
committer Michael Ellerman <mpe@ellerman.id.au> 1466487050 +1000

powerpc: Load Monitor Register Support

This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.

This patch disables the FSCR LM control bit on task init and enables
that bit when a load monitor facility unavailable exception is taken
for using it. On context switch, this bit is then used to determine
whether the two relevant registers are saved and restored. This is
done lazily for performance reasons.

Signed-off-by: Jack Miller <jack@codezen.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>