MIPS: Alchemy: DB1xxx: Explicitly set 50MHz clock for I2C/SPI units.
Add an explicit call to set the desired rate to get the correct
clock routing for the PSC clocks. It wasn't broken before, but
now it's less affected by bootloader changes.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7554/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index ef93ee3..e476ae9 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -762,9 +762,10 @@
__raw_writel(PSC_SEL_CLK_SERCLK,
(void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
wmb();
- /* I2C uses internal 48MHz EXTCLK1 */
+ /* I2C driver wants 50MHz, get as close as possible */
c = clk_get(NULL, "psc3_intclk");
if (!IS_ERR(c)) {
+ clk_set_rate(c, 50000000);
clk_prepare_enable(c);
clk_put(c);
}