| commit | c3480a603773cfc5d8aa44dbbee6c96e0f9d4d9d | [log] [tgz] |
|---|---|---|
| author | Michael Chan <michael.chan@broadcom.com> | Wed Jan 17 03:21:15 2018 -0500 |
| committer | David S. Miller <davem@davemloft.net> | Wed Jan 17 14:48:27 2018 -0500 |
| tree | d0814e265b4ba099bf7fdd43e26da5acda882054 | |
| parent | 91cdda40714178497cbd182261b2ea6ec5cb9276 [diff] |
bnxt_en: Add cache line size setting to optimize performance. The chip supports 64-byte and 128-byte cache line size for more optimal DMA performance when matched to the CPU cache line size. The default is 64. If the system is using 128-byte cache line size, set it to 128. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>