| commit | 7ea653efa98d8144345227576fc084ed7a356cf8 | [log] [tgz] |
|---|---|---|
| author | Philipp Zabel <p.zabel@pengutronix.de> | Mon Feb 24 14:51:50 2014 +0100 |
| committer | Shawn Guo <shawn.guo@linaro.org> | Wed Mar 05 10:40:48 2014 +0800 |
| tree | c749da48570ce6b0554608eb2aed982468602fa0 | |
| parent | ef3adc187ca6418a376774ebf55d1258d1dc2c31 [diff] |
ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority This is needed so that the IPU framebuffer scanout cannot be starved by VPU or GPU activity. Some boards like the SabreLite and SabreSD seem to set this in the DCD already, but the documented register reset values do not contain the necessary settings. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>