ARM: at91: dt: at91sam9260: split rts and cts pinctrl not
as we just use the rts and not the rts & cts for rs485
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 56ce896..dc9a4ee 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -139,10 +139,14 @@
1 18 0x1 0x0>; /* PB18 periph A */
};
- pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
+ pinctrl_usart0_rts: usart0_rts-0 {
atmel,pins =
- <1 17 0x2 0x0 /* PB17 periph B */
- 1 15 0x2 0x0>; /* PB15 periph B */
+ <1 17 0x2 0x0>; /* PB17 periph B */
+ };
+
+ pinctrl_usart0_cts: usart0_cts-0 {
+ atmel,pins =
+ <1 15 0x2 0x0>; /* PB15 periph B */
};
};
@@ -153,10 +157,14 @@
1 5 0x1 0x0>; /* PB5 periph A */
};
- pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
+ pinctrl_usart1_rts: usart1_rts-0 {
atmel,pins =
- <3 16 0x1 0x0 /* PD16 periph A */
- 3 17 0x1 0x0>; /* PD17 periph A */
+ <3 16 0x1 0x0>; /* PD16 periph A */
+ };
+
+ pinctrl_usart1_cts: usart1_cts-0 {
+ atmel,pins =
+ <3 17 0x1 0x0>; /* PD17 periph A */
};
};
@@ -167,10 +175,14 @@
1 7 0x1 0x0>; /* PB7 periph A */
};
- pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
+ pinctrl_usart2_rts: usart2_rts-0 {
atmel,pins =
- <2 9 0x2 0x0 /* PC9 periph B */
- 2 11 0x2 0x0>; /* PC11 periph B */
+ <2 9 0x2 0x0>; /* PC9 periph B */
+ };
+
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins =
+ <2 11 0x2 0x0>; /* PC11 periph B */
};
};
@@ -181,10 +193,14 @@
1 9 0x1 0x0>; /* PB8 periph A */
};
- pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
+ pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
- <0 23 0x2 0x0 /* PA23 periph B */
- 0 24 0x2 0x0>; /* PA24 periph B */
+ <0 23 0x2 0x0>; /* PA23 periph B */
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ <0 24 0x2 0x0>; /* PA24 periph B */
};
};