| commit | d0f02ce3b1685ef6ffe43692034599790f83e7ab | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Fri Apr 04 15:55:13 2014 +0200 |
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Thu Apr 17 14:12:34 2014 +0300 |
| tree | 08b7289a4e5db66417e3d1455577345f29114ed1 | |
| parent | c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 [diff] |
clk: tegra: Fix PLLE programming PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider fields the corresponding masks were never shifted, thereby clearing only the lowest bits of the register. This lead to a situation where the PLLE programming would only work if the register hadn't been touched before. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>