tree a15b8966a3f960af551c7c80128e043997fe949f
parent 7ad00d1ac12bf461d0f0b69bf4e0e883b9e23c53
author Arun Siluvery <arun.siluvery@linux.intel.com> 1434735433 +0100
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1435060901 +0200

drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw

v2: Add LRI commands to set/reset bit that invalidates coherent lines,
update WA to include programming restrictions and exclude CHV as
it is not required (Ville)

v3: Avoid unnecessary read when it can be done by reading register once (Chris).

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>