| commit | c955bf3998efa3355790a4d8c82874582f1bc727 | [log] [tgz] |
|---|---|---|
| author | Chen Zhong <chen.zhong@mediatek.com> | Thu Oct 05 11:50:23 2017 +0800 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Thu Nov 02 01:07:51 2017 -0700 |
| tree | 4df4e73b5bd0d3d4ba1405bdb20950b7b5070308 | |
| parent | 808ecf4ad087f80c2eee99af67549f05d5315694 [diff] |
clk: mediatek: add the option for determining PLL source clock Since the previous setup always sets the PLL using crystal 26MHz, this doesn't always happen in every MediaTek platform. So the patch added flexibility for assigning extra member for determining the PLL source clock. Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>