tree 1f2cc0671c1f84c8928c261700f370771d510cbb
parent d3f3cf859db17cc5f8156c5bfcd032413e44483b
author Simon Guinot <sguinot@lacie.com> 1284759231 +0200
committer Dan Williams <dan.j.williams@intel.com> 1285276462 -0700

dmaengine: fix interrupt clearing for mv_xor

When using simultaneously the two DMA channels on a same engine, some
transfers are never completed. For example, an endless lock can occur
while writing heavily on a RAID5 array (with async-tx offload support
enabled).

Note that this issue can also be reproduced by using the DMA test
client.

On a same engine, the interrupt cause register is shared between two
DMA channels. This patch make sure that the cause bit is only cleared
for the requested channel.

Signed-off-by: Simon Guinot <sguinot@lacie.com>
Tested-by: Luc Saillard <luc@saillard.org>
Acked-by: saeed bishara <saeed.bishara@gmail.com>
Cc: <stable@kernel.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>