| commit | cd30798a6c17c1fa182e9b0bb85bd973776ff193 | [log] [tgz] |
|---|---|---|
| author | Zhi Mao <zhi.mao@mediatek.com> | Fri Jun 30 14:05:17 2017 +0800 |
| committer | Thierry Reding <thierry.reding@gmail.com> | Mon Aug 21 10:39:09 2017 +0200 |
| tree | 3572bfe3bb23753643c6355852481c36e89c39bb | |
| parent | aa12d7a7a978ac5f3202cac8f2f671fd267bf5e3 [diff] |
pwm: mediatek: Fix PWM source clock selection In original code, the PWM output frequency is not correct when set bit<3>=1 to PWMCON register. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>