| commit | cee8113a295acfc4cd25728d7c3d44e6bc3bbff9 | [log] [tgz] |
|---|---|---|
| author | Dhaval Shah <dhaval.shah@xilinx.com> | Thu Dec 21 10:33:06 2017 -0800 |
| committer | Michal Simek <michal.simek@xilinx.com> | Mon Jan 08 13:42:47 2018 +0100 |
| tree | 9f5bf6d034f9120fb26e46593fbab85dbf4cc8d0 | |
| parent | b7511552f920c8c273912353a8c8bf65e8f84fdc [diff] |
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>