| commit | cfd044b02873b02236bcd93ff398504d489ddc13 | [log] [tgz] |
|---|---|---|
| author | Alexandre Courbot <acourbot@nvidia.com> | Thu Jan 26 16:49:43 2017 +0900 |
| committer | Ben Skeggs <bskeggs@redhat.com> | Tue Mar 07 17:05:13 2017 +1000 |
| tree | b32d65654f367799b149ad755e954fe259465aa4 | |
| parent | ad147b7f57547a5597ed338f2c46f03809d7792e [diff] |
drm/nouveau/falcon: fix base address of FBIF registers All falcons have their FBIF registers starting at offset 0x600, with the exception of the PMU and NVENC engines. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>