tree b32d65654f367799b149ad755e954fe259465aa4
parent ad147b7f57547a5597ed338f2c46f03809d7792e
author Alexandre Courbot <acourbot@nvidia.com> 1485416983 +0900
committer Ben Skeggs <bskeggs@redhat.com> 1488870313 +1000

drm/nouveau/falcon: fix base address of FBIF registers

All falcons have their FBIF registers starting at offset 0x600, with the
exception of the PMU and NVENC engines.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>