tree feb8a6188667c7a62edef67e2d11fab873a482bf
parent d49a340d6eb6de45c1a886b71469d110f2dbb57b
author Ville Syrjälä <ville.syrjala@linux.intel.com> 1403910239 +0300
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1407512622 +0200

drm/i915: Leave DPLL ref clocks on

We enable the DPLL refclock already when bringing up the cmnlane power
well, so also leave it on when otherwise disabling the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>