| commit | d83dcacea185da4f664c909e4c04034336b463ab | [log] [tgz] |
|---|---|---|
| author | Abhishek Sahu <absahu@codeaurora.org> | Fri Nov 25 21:11:29 2016 +0530 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Wed Dec 21 15:57:26 2016 -0800 |
| tree | bd6baf8a65b45326770347c82dfa90632a1112bc | |
| parent | 4577aa01a5d12737c6f8109013651c97535a79b5 [diff] |
clk: qcom: ipq4019: Add the apss cpu pll divider clock node The current ipq4019 clock driver does not have support for all the frequency supported by APSS CPU. APSS CPU frequency is provided with APSS CPU PLL divider which divides down the VCO frequency. This divider is nonlinear and specific to IPQ4019 so the standard divider code cannot be used for this. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>