| commit | 74ab0e7a836a7df772af50cac21267eb43688841 | [log] [tgz] |
|---|---|---|
| author | Yazen Ghannam <Yazen.Ghannam@amd.com> | Mon Sep 12 09:59:27 2016 +0200 |
| committer | Thomas Gleixner <tglx@linutronix.de> | Tue Sep 13 15:23:06 2016 +0200 |
| tree | 3d23e831b87c7f3c41c1f01b77cdccd4844772d2 | |
| parent | ffb173e657fa8123bffa2a169e124b4bca0b5bc4 [diff] |
x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks() Change MSR_IA32_MCx_MISC() macro to msr_ops.misc() because SMCA machines define a different set of MSRs and msr_ops will give you the correct MISC register. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/1468269447-8808-1-git-send-email-Yazen.Ghannam@amd.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>