tree 257446bd5b37fe55ae44880afc4b2da50aa30fbd
parent ed0f72f4eacb49ed8a57e751a09d5b096b433199
parent 5dcbeca615ef12047a5f4097b91030cbf995b1d2
author Linus Torvalds <torvalds@linux-foundation.org> 1507332308 -0700
committer Linus Torvalds <torvalds@linux-foundation.org> 1507332308 -0700
mergetag object 5dcbeca615ef12047a5f4097b91030cbf995b1d2
 type commit
 tag clk-fixes-for-linus
 tagger Stephen Boyd <sboyd@codeaurora.org> 1507331741 -0700
 
  - Build fix to export the clk_bulk_prepare() symbol
 
  - Suspend fix for Samsung Exynos SoCs where we need to keep clks on
    across suspend
 
  - Two critical clk markings for clks that shouldn't ever turn off on
    Rockchip SoCs
 
  - A fix for a copy-paste mistake on Rockchip rk3128 causing some clks to
    touch the same bit and trample over one another
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:

 - build fix to export the clk_bulk_prepare() symbol

 - suspend fix for Samsung Exynos SoCs where we need to keep clks on
   across suspend

 - two critical clk markings for clks that shouldn't ever turn off on
   Rockchip SoCs

 - a fix for a copy-paste mistake on Rockchip rk3128 causing some clks
   to touch the same bit and trample over one another

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
  clk: Export clk_bulk_prepare()
  clk: rockchip: add sclk_timer5 as critical clock on rk3128
  clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error
  clk: rockchip: add pclk_pmu as critical clock on rk3128