arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi - kernel/msm-4.19 - Gitiles

 /*
  * Copyright (C) 2016 ARM Ltd.
  * based on the Allwinner H3 dtsi:
  *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
  * licensing only applies to this file, and not this project as a
  * whole.
  *
  *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
  *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
  *     obtaining a copy of this software and associated documentation
  *     files (the "Software"), to deal in the Software without
  *     restriction, including without limitation the rights to use,
  *     copy, modify, merge, publish, distribute, sublicense, and/or
  *     sell copies of the Software, and to permit persons to whom the
  *     Software is furnished to do so, subject to the following
  *     conditions:
  *
  *     The above copyright notice and this permission notice shall be
  *     included in all copies or substantial portions of the Software.
  *
  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */

 #include <dt-bindings/clock/sun50i-a64-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>

 / {
 	interrupt-parent = <&gic>;
 	#address-cells = <1>;
 	#size-cells = <1>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu0: cpu@0 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <0>;
 			enable-method = "psci";
 		};

 		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
 		};

 		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
 		};

 		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			device_type = "cpu";
 			reg = <3>;
 			enable-method = "psci";
 		};
 	};

 	osc24M: osc24M_clk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
 		clock-output-names = "osc24M";
 	};

 	osc32k: osc32k_clk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 		clock-output-names = "osc32k";
 	};

 	iosc: internal-osc-clk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <16000000>;
 		clock-accuracy = <300000000>;
 		clock-output-names = "iosc";
 	};

 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
 	};

 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 14
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 11
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 10
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};

 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;

 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun50i-a64-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 			clock-names = "ahb", "mmc";
 			resets = <&ccu RST_BUS_MMC0>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 			max-frequency = <150000000>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		mmc1: mmc@1c10000 {
 			compatible = "allwinner,sun50i-a64-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 			clock-names = "ahb", "mmc";
 			resets = <&ccu RST_BUS_MMC1>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			max-frequency = <150000000>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		mmc2: mmc@1c11000 {
 			compatible = "allwinner,sun50i-a64-emmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 			clock-names = "ahb", "mmc";
 			resets = <&ccu RST_BUS_MMC2>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			max-frequency = <200000000>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		usb_otg: usb@01c19000 {
 			compatible = "allwinner,sun8i-a33-musb";
 			reg = <0x01c19000 0x0400>;
 			clocks = <&ccu CLK_BUS_OTG>;
 			resets = <&ccu RST_BUS_OTG>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc";
 			phys = <&usbphy 0>;
 			phy-names = "usb";
 			extcon = <&usbphy 0>;
 			status = "disabled";
 		};

 		usbphy: phy@01c19400 {
 			compatible = "allwinner,sun50i-a64-usb-phy";
 			reg = <0x01c19400 0x14>,
 			      <0x01c1a800 0x4>,
 			      <0x01c1b800 0x4>;
 			reg-names = "phy_ctrl",
 				    "pmu0",
 				    "pmu1";
 			clocks = <&ccu CLK_USB_PHY0>,
 				 <&ccu CLK_USB_PHY1>;
 			clock-names = "usb0_phy",
 				      "usb1_phy";
 			resets = <&ccu RST_USB_PHY0>,
 				 <&ccu RST_USB_PHY1>;
 			reset-names = "usb0_reset",
 				      "usb1_reset";
 			status = "disabled";
 			#phy-cells = <1>;
 		};

 		ehci1: usb@01c1b000 {
 			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 			reg = <0x01c1b000 0x100>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_OHCI1>,
 				 <&ccu CLK_BUS_EHCI1>,
 				 <&ccu CLK_USB_OHCI1>;
 			resets = <&ccu RST_BUS_OHCI1>,
 				 <&ccu RST_BUS_EHCI1>;
 			phys = <&usbphy 1>;
 			phy-names = "usb";
 			status = "disabled";
 		};

 		ohci1: usb@01c1b400 {
 			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 			reg = <0x01c1b400 0x100>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_OHCI1>,
 				 <&ccu CLK_USB_OHCI1>;
 			resets = <&ccu RST_BUS_OHCI1>;
 			phys = <&usbphy 1>;
 			phy-names = "usb";
 			status = "disabled";
 		};

 		ccu: clock@01c20000 {
 			compatible = "allwinner,sun50i-a64-ccu";
 			reg = <0x01c20000 0x400>;
 			clocks = <&osc24M>, <&osc32k>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};

 		pio: pinctrl@1c20800 {
 			compatible = "allwinner,sun50i-a64-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu 58>;
 			gpio-controller;
 			#gpio-cells = <3>;
 			interrupt-controller;
 			#interrupt-cells = <3>;

 			i2c1_pins: i2c1_pins {
 				pins = "PH2", "PH3";
 				function = "i2c1";
 			};

 			mmc0_pins: mmc0-pins {
 				pins = "PF0", "PF1", "PF2", "PF3",
 				       "PF4", "PF5";
 				function = "mmc0";
 				drive-strength = <30>;
 				bias-pull-up;
 			};

 			mmc1_pins: mmc1-pins {
 				pins = "PG0", "PG1", "PG2", "PG3",
 				       "PG4", "PG5";
 				function = "mmc1";
 				drive-strength = <30>;
 				bias-pull-up;
 			};

 			mmc2_pins: mmc2-pins {
 				pins = "PC1", "PC5", "PC6", "PC8", "PC9",
 				       "PC10","PC11", "PC12", "PC13",
 				       "PC14", "PC15", "PC16";
 				function = "mmc2";
 				drive-strength = <30>;
 				bias-pull-up;
 			};

 			uart0_pins_a: uart0@0 {
 				pins = "PB8", "PB9";
 				function = "uart0";
 			};

 			uart1_pins: uart1_pins {
 				pins = "PG6", "PG7";
 				function = "uart1";
 			};

 			uart1_rts_cts_pins: uart1_rts_cts_pins {
 				pins = "PG8", "PG9";
 				function = "uart1";
 			};
 		};

 		uart0: serial@1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu 67>;
 			resets = <&ccu 46>;
 			status = "disabled";
 		};

 		uart1: serial@1c28400 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28400 0x400>;
 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu 68>;
 			resets = <&ccu 47>;
 			status = "disabled";
 		};

 		uart2: serial@1c28800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28800 0x400>;
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu 69>;
 			resets = <&ccu 48>;
 			status = "disabled";
 		};

 		uart3: serial@1c28c00 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28c00 0x400>;
 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu 70>;
 			resets = <&ccu 49>;
 			status = "disabled";
 		};

 		uart4: serial@1c29000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c29000 0x400>;
 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu 71>;
 			resets = <&ccu 50>;
 			status = "disabled";
 		};

 		i2c0: i2c@1c2ac00 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2ac00 0x400>;
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu 63>;
 			resets = <&ccu 42>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		i2c1: i2c@1c2b000 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2b000 0x400>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu 64>;
 			resets = <&ccu 43>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		i2c2: i2c@1c2b400 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2b400 0x400>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu 65>;
 			resets = <&ccu 44>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		gic: interrupt-controller@1c81000 {
 			compatible = "arm,gic-400";
 			reg = <0x01c81000 0x1000>,
 			      <0x01c82000 0x2000>,
 			      <0x01c84000 0x2000>,
 			      <0x01c86000 0x2000>;
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 			interrupt-controller;
 			#interrupt-cells = <3>;
 		};

 		rtc: rtc@1f00000 {
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		r_ccu: clock@1f01400 {
 			compatible = "allwinner,sun50i-a64-r-ccu";
 			reg = <0x01f01400 0x100>;
 			clocks = <&osc24M>, <&osc32k>, <&iosc>,
 				 <&ccu 11>;
 			clock-names = "hosc", "losc", "iosc", "pll-periph";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};

 		r_pio: pinctrl@01f02c00 {
 			compatible = "allwinner,sun50i-a64-r-pinctrl";
 			reg = <0x01f02c00 0x400>;
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
 			interrupt-controller;
 			#interrupt-cells = <3>;
 		};
 	};
 };
	/*
	* Copyright (C) 2016 ARM Ltd.
	* based on the Allwinner H3 dtsi:
	* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/clock/sun50i-a64-ccu.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/reset/sun50i-a64-ccu.h>

	/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a53", "arm,armv8";
	device_type = "cpu";
	reg = <0>;
	enable-method = "psci";
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a53", "arm,armv8";
	device_type = "cpu";
	reg = <1>;
	enable-method = "psci";
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a53", "arm,armv8";
	device_type = "cpu";
	reg = <2>;
	enable-method = "psci";
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a53", "arm,armv8";
	device_type = "cpu";
	reg = <3>;
	enable-method = "psci";
	};
	};

	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "osc24M";
	};

	osc32k: osc32k_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-output-names = "osc32k";
	};

	iosc: internal-osc-clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <16000000>;
	clock-accuracy = <300000000>;
	clock-output-names = "iosc";
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10
	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun50i-a64-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	max-frequency = <150000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun50i-a64-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	max-frequency = <150000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun50i-a64-emmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
	clock-names = "ahb", "mmc";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	max-frequency = <200000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	usb_otg: usb@01c19000 {
	compatible = "allwinner,sun8i-a33-musb";
	reg = <0x01c19000 0x0400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	status = "disabled";
	};

	usbphy: phy@01c19400 {
	compatible = "allwinner,sun50i-a64-usb-phy";
	reg = <0x01c19400 0x14>,
	<0x01c1a800 0x4>,
	<0x01c1b800 0x4>;
	reg-names = "phy_ctrl",
	"pmu0",
	"pmu1";
	clocks = <&ccu CLK_USB_PHY0>,
	<&ccu CLK_USB_PHY1>;
	clock-names = "usb0_phy",
	"usb1_phy";
	resets = <&ccu RST_USB_PHY0>,
	<&ccu RST_USB_PHY1>;
	reset-names = "usb0_reset",
	"usb1_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ehci1: usb@01c1b000 {
	compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
	reg = <0x01c1b000 0x100>;
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI1>,
	<&ccu CLK_BUS_EHCI1>,
	<&ccu CLK_USB_OHCI1>;
	resets = <&ccu RST_BUS_OHCI1>,
	<&ccu RST_BUS_EHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ohci1: usb@01c1b400 {
	compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
	reg = <0x01c1b400 0x100>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_OHCI1>,
	<&ccu CLK_USB_OHCI1>;
	resets = <&ccu RST_BUS_OHCI1>;
	phys = <&usbphy 1>;
	phy-names = "usb";
	status = "disabled";
	};

	ccu: clock@01c20000 {
	compatible = "allwinner,sun50i-a64-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&osc32k>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun50i-a64-pinctrl";
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu 58>;
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	i2c1_pins: i2c1_pins {
	pins = "PH2", "PH3";
	function = "i2c1";
	};

	mmc0_pins: mmc0-pins {
	pins = "PF0", "PF1", "PF2", "PF3",
	"PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pins: mmc1-pins {
	pins = "PG0", "PG1", "PG2", "PG3",
	"PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc2_pins: mmc2-pins {
	pins = "PC1", "PC5", "PC6", "PC8", "PC9",
	"PC10","PC11", "PC12", "PC13",
	"PC14", "PC15", "PC16";
	function = "mmc2";
	drive-strength = <30>;
	bias-pull-up;
	};

	uart0_pins_a: uart0@0 {
	pins = "PB8", "PB9";
	function = "uart0";
	};

	uart1_pins: uart1_pins {
	pins = "PG6", "PG7";
	function = "uart1";
	};

	uart1_rts_cts_pins: uart1_rts_cts_pins {
	pins = "PG8", "PG9";
	function = "uart1";
	};
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu 67>;
	resets = <&ccu 46>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu 68>;
	resets = <&ccu 47>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu 69>;
	resets = <&ccu 48>;
	status = "disabled";
	};

	uart3: serial@1c28c00 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28c00 0x400>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu 70>;
	resets = <&ccu 49>;
	status = "disabled";
	};

	uart4: serial@1c29000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c29000 0x400>;
	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu 71>;
	resets = <&ccu 50>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu 63>;
	resets = <&ccu 42>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu 64>;
	resets = <&ccu 43>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c2: i2c@1c2b400 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b400 0x400>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu 65>;
	resets = <&ccu 44>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,gic-400";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x2000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-controller;
	#interrupt-cells = <3>;
	};

	rtc: rtc@1f00000 {
	compatible = "allwinner,sun6i-a31-rtc";
	reg = <0x01f00000 0x54>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	};

	r_ccu: clock@1f01400 {
	compatible = "allwinner,sun50i-a64-r-ccu";
	reg = <0x01f01400 0x100>;
	clocks = <&osc24M>, <&osc32k>, <&iosc>,
	<&ccu 11>;
	clock-names = "hosc", "losc", "iosc", "pll-periph";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	r_pio: pinctrl@01f02c00 {
	compatible = "allwinner,sun50i-a64-r-pinctrl";
	reg = <0x01f02c00 0x400>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;
	};
	};
	};