| commit | 955d809bdeaea3663cf6ac1ee72cd50775bbab9d | [log] [tgz] |
|---|---|---|
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | Sat Jan 23 17:55:30 2016 +0900 |
| committer | Thierry Reding <treding@nvidia.com> | Tue Apr 12 17:09:28 2016 +0200 |
| tree | 8cc239724e40264746c379065f322ffa7a50d482 | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca [diff] |
ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select
These two are both ARMv7 SoCs. They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.
Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>