| commit | e235f7b86f33beea7e096b46db1802dbf5d7d22e | [log] [tgz] |
|---|---|---|
| author | Peter Chen <peter.chen@freescale.com> | Fri Jan 16 18:29:01 2015 +0800 |
| committer | Felipe Balbi <balbi@ti.com> | Tue Jan 27 09:40:49 2015 -0600 |
| tree | d7fb5e5b8949829c3b58a328ea0d4ebbf990647c | |
| parent | efdbd3a5d6e6108f1565ab4dc4c53e77aba6fe0a [diff] |
usb: phy: mxs: add delay before set phyctrl.clkgate There is a request from IC engineer that if we doesn't set phypwd as 0xffffffff, we need to delay about five 32Khz cycles before set phy's pwd register, otherwise, the wakeup signal may can't wake up controller. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>