| commit | e29b72f5e129b4dd4b77dc01dba340006bb103f8 | [log] [tgz] |
|---|---|---|
| author | John Crispin <blogic@openwrt.org> | Sun Jul 22 08:55:57 2012 +0200 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Wed Aug 01 17:57:04 2012 +0200 |
| tree | f0425aa961e2becc0e4454eba8d04832be6eda74 | |
| parent | 2e3ee613480563a6d5c01b57d342e65cc58c06df [diff] |
MIPS: Lantiq: Fix interface clock and PCI control register offset The XRX200 based SoC have a different register offset for the interface clock and PCI control registers. This patch detects the SoC and sets the register offset at runtime. This make PCI work on the VR9 SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>