tree 2d3f70cdf729d920d20d9b70af22391f71a2056b
parent d0593c363f04ccc4bc7b6939c24a0ee65391c779
author Takeshi Kihara <takeshi.kihara.df@renesas.com> 1496142918 +0900
committer Geert Uytterhoeven <geert+renesas@glider.be> 1500281491 +0200

pinctrl: sh-pfc: r8a7795: Fix MSIOF3_{SS1,SS2}_E pin function definitions

This patch fixes the incorrect IPSR register value definitions for
MSIOF3_{SS1,SS2}_E pin functions.

This is a correction to the incorrect implementation of IPSR register pin
assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car
Gen3 Hardware User's Manual Rev.0.53E.

Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Reword, update Fixes for upstream]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>