tree 2c9efd078b5e4041dc77a4e5a2424bbfc850ab5b
parent 7fd562b75d7752ed50c61d65f27b558cd93a359b
author Qiuxu Zhuo <qiuxu.zhuo@intel.com> 1495498051 +0800
committer Borislav Petkov <bp@suse.de> 1495715841 +0200

EDAC, sb_edac: Assign EDAC memory controller per h/w controller

Tony pointed out: "currently the driver pretends there is one big
8-channel memory controller per socket instead of 2 4-channel
controllers. This is fine with all memory controller populated with
symmetrical DIMM configurations, but runs into difficulties on
asymmetrical setups".

Restructure the driver to assign an EDAC memory controller to each real
h/w memory controller to resolve the issue.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170523000731.87793-1-qiuxu.zhuo@intel.com
[ Break some lines at convenient points. ]
Signed-off-by: Borislav Petkov <bp@suse.de>