| commit | 5a63426e2a18775ed05b20e3bc90c68bacb1f68a | [log] [tgz] |
|---|---|---|
| author | Len Brown <len.brown@intel.com> | Wed Apr 06 17:15:55 2016 -0400 |
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | Thu Apr 07 22:18:32 2016 +0200 |
| tree | 851ad05e09e5b5a865a6284b1d0538f17b3e1afc | |
| parent | 8ae7225591fd15aac89769cbebb3b5ecc8b12fe5 [diff] |
tools/power turbostat: print IRTL MSRs Some processors use the Interrupt Response Time Limit (IRTL) MSR value to describe the maximum IRQ response time latency for deep package C-states. (Though others have the register, but do not use it) Lets print it out to give insight into the cases where it is used. IRTL begain in SNB, with PC3/PC6/PC7, and HSW added PC8/PC9/PC10. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>