MIPS: Convert the irq functions to the new names
Scripted with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index f91c43a..596ad00 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -142,8 +142,8 @@
bcsr_csc_base = csc_start;
for (irq = csc_start; irq <= csc_end; irq++)
- set_irq_chip_and_handler_name(irq, &bcsr_irq_type,
- handle_level_irq, "level");
+ irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
+ handle_level_irq, "level");
- set_irq_chained_handler(hook_irq, bcsr_csc_handler);
+ irq_set_chained_handler(hook_irq, bcsr_csc_handler);
}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
index a4e0400..4a89800 100644
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -63,7 +63,7 @@
static int __init db1200_arch_init(void)
{
/* GPIO7 is low-level triggered CPLD cascade */
- set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
/* insert/eject pairs: one of both is always screaming. To avoid
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 9e45971..05f120f 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -215,35 +215,35 @@
static int __init db1x00_init_irq(void)
{
#if defined(CONFIG_MIPS_MIRAGE)
- set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
+ irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
#elif defined(CONFIG_MIPS_DB1550)
- set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
- set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
- set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
- set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
- set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
- set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+ irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+ irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
+ irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+ irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+ irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+ irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1500)
- set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
- set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
- set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
- set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
- set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
- set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+ irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+ irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+ irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+ irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+ irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+ irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1100)
- set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
- set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
- set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
- set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
- set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
- set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+ irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+ irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+ irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+ irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+ irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+ irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1000)
- set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
- set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
- set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
- set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
- set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
- set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+ irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+ irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+ irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+ irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+ irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+ irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#endif
return 0;
}
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index f6540ec..2d85c4b 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -197,7 +197,7 @@
static int __init pb1000_init_irq(void)
{
- set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
return 0;
}
arch_initcall(pb1000_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 90dda5f..d108fd5 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -117,10 +117,10 @@
static int __init pb1100_init_irq(void)
{
- set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
- set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
- set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
- set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
+ irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
+ irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
+ irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
+ irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
return 0;
}
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 8b4466f..6d06b07 100644
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -142,7 +142,7 @@
panic("Game over. Your score is 0.");
}
- set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
return 0;
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 9cd9dfa..83f4621 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -134,14 +134,14 @@
static int __init pb1500_init_irq(void)
{
- set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
- set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
- set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
- set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
- set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
+ irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
+ irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+ irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+ irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
return 0;
}
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index 9d7d6ed..b790213 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -73,9 +73,9 @@
static int __init pb1550_init_irq(void)
{
- set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
+ irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
/* enable both PCMCIA card irqs in the shared line */
alchemy_gpio2_enable_int(201);
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 40b84b9..cf436ab 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -123,11 +123,11 @@
static int __init mtx1_init_irq(void)
{
- set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
- set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+ irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
return 0;
}
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 80c521e..febfb0fb 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -85,19 +85,19 @@
static int __init xxs1500_init_irq(void)
{
- set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
- set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+ irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
- set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
- set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
+ irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
+ irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
return 0;
}
diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c
index a6484b6..03db3da 100644
--- a/arch/mips/ar7/irq.c
+++ b/arch/mips/ar7/irq.c
@@ -119,11 +119,11 @@
for (i = 0; i < 40; i++) {
writel(i, REG(CHNL_OFFSET(i)));
/* Primary IRQ's */
- set_irq_chip_and_handler(base + i, &ar7_irq_type,
+ irq_set_chip_and_handler(base + i, &ar7_irq_type,
handle_level_irq);
/* Secondary IRQ's */
if (i < 32)
- set_irq_chip_and_handler(base + i + 40,
+ irq_set_chip_and_handler(base + i + 40,
&ar7_sec_irq_type,
handle_level_irq);
}
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 7c02bc9..ac610d5 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -124,11 +124,11 @@
for (i = ATH79_MISC_IRQ_BASE;
i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
- set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
+ irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
handle_level_irq);
}
- set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
+ irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
}
asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 1691531..cea6021c 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -230,11 +230,11 @@
mips_cpu_irq_init();
for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
- set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
+ irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
handle_level_irq);
for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
- set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
+ irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
handle_edge_irq);
setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 8d9a5fc..824e08c 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -68,10 +68,10 @@
fast_iob();
for (i = base; i < base + IO_INR_DMA; i++)
- set_irq_chip_and_handler(i, &ioasic_irq_type,
+ irq_set_chip_and_handler(i, &ioasic_irq_type,
handle_level_irq);
for (; i < base + IO_IRQ_LINES; i++)
- set_irq_chip(i, &ioasic_dma_irq_type);
+ irq_set_chip(i, &ioasic_dma_irq_type);
ioasic_irq_base = base;
}
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index ef31d98..37199f7 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -73,7 +73,7 @@
iob();
for (i = base; i < base + KN02_IRQ_LINES; i++)
- set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
kn02_irq_base = base;
}
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9b1207a..3dbd7a5 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -69,7 +69,7 @@
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
- set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
+ irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq, "level");
}
@@ -105,7 +105,7 @@
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
- set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
+ irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq, "level");
}
@@ -162,7 +162,7 @@
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
- set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
+ irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller,
handle_edge_irq, "edge");
}
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 40f7c6b..260df47 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -56,7 +56,7 @@
int i;
for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
- set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
index bd2fc29..73031f7 100644
--- a/arch/mips/jz4740/gpio.c
+++ b/arch/mips/jz4740/gpio.c
@@ -306,7 +306,7 @@
uint32_t flag;
unsigned int gpio_irq;
unsigned int gpio_bank;
- struct jz_gpio_chip *chip = get_irq_desc_data(desc);
+ struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
gpio_bank = JZ4740_IRQ_GPIO0 - irq;
@@ -416,7 +416,7 @@
chip->wakeup &= ~IRQ_TO_BIT(data->irq);
spin_unlock(&chip->lock);
- set_irq_wake(chip->irq, on);
+ irq_set_irq_wake(chip->irq, on);
return 0;
}
@@ -510,14 +510,14 @@
gpiochip_add(&chip->gpio_chip);
chip->irq = JZ4740_IRQ_INTC_GPIO(id);
- set_irq_data(chip->irq, chip);
- set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
+ irq_set_handler_data(chip->irq, chip);
+ irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
irq_set_lockdep_class(irq, &gpio_lock_class);
- set_irq_chip_data(irq, chip);
- set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
- handle_level_irq);
+ irq_set_chip_data(irq, chip);
+ irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
+ handle_level_irq);
}
return 0;
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index dcc5593..d82c0c4 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -104,8 +104,8 @@
writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
- set_irq_chip_data(i, (void *)IRQ_BIT(i));
- set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+ irq_set_chip_data(i, (void *)IRQ_BIT(i));
+ irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
}
setup_irq(2, &jz4740_cascade_action);
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index e221662..c018696 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -110,7 +110,7 @@
void make_8259A_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
+ irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
enable_irq(irq);
}
@@ -336,8 +336,8 @@
init_8259A(0);
for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
- set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
- set_irq_probe(i);
+ irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
+ irq_set_probe(i);
}
setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 43cd962..0c527f6 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -229,7 +229,7 @@
vpe_local_setup(numvpes);
for (i = _irqbase; i < (_irqbase + numintrs); i++)
- set_irq_chip(i, &gic_irq_controller);
+ irq_set_chip(i, &gic_irq_controller);
}
void __init gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index 7fd176f..883fc6c 100644
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -126,6 +126,6 @@
* bit31: logical or of bits[25:1].
*/
for (i = 1; i < 30; i++)
- set_irq_chip_and_handler(GT641XX_IRQ_BASE + i,
- >641xx_irq_chip, handle_level_irq);
+ irq_set_chip_and_handler(GT641XX_IRQ_BASE + i,
+ >641xx_irq_chip, handle_level_irq);
}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index fc800cd..0c6afee 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -137,16 +137,20 @@
switch (imp->im_type) {
case MSC01_IRQ_EDGE:
- set_irq_chip_and_handler_name(irqbase + n,
- &msc_edgeirq_type, handle_edge_irq, "edge");
+ irq_set_chip_and_handler_name(irqbase + n,
+ &msc_edgeirq_type,
+ handle_edge_irq,
+ "edge");
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
else
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
break;
case MSC01_IRQ_LEVEL:
- set_irq_chip_and_handler_name(irqbase+n,
- &msc_levelirq_type, handle_level_irq, "level");
+ irq_set_chip_and_handler_name(irqbase + n,
+ &msc_levelirq_type,
+ handle_level_irq,
+ "level");
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
else
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index fd24fd9..a8a8977 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -45,6 +45,6 @@
clear_c0_intcontrol(0x00000f00); /* Mask all */
for (i = base; i < base + 4; i++)
- set_irq_chip_and_handler(i, &rm7k_irq_controller,
+ irq_set_chip_and_handler(i, &rm7k_irq_controller,
handle_percpu_irq);
}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index ca463ec..38874a4 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -98,10 +98,10 @@
clear_c0_intcontrol(0x0000f000); /* Mask all */
for (i = base; i < base + 4; i++)
- set_irq_chip_and_handler(i, &rm9k_irq_controller,
+ irq_set_chip_and_handler(i, &rm9k_irq_controller,
handle_level_irq);
rm9000_perfcount_irq = base + 1;
- set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
+ irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
handle_percpu_irq);
}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 1b68ebe..9b734d7 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -102,7 +102,7 @@
#endif
for (i = 0; i < NR_IRQS; i++)
- set_irq_noprobe(i);
+ irq_set_noprobe(i);
arch_init_irq();
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index fd945c5..6e71b28 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -109,10 +109,10 @@
*/
if (cpu_has_mipsmt)
for (i = irq_base; i < irq_base + 2; i++)
- set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
+ irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
handle_percpu_irq);
for (i = irq_base + 2; i < irq_base + 8; i++)
- set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
+ irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
handle_percpu_irq);
}
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
index 526e158..b0c55b5 100644
--- a/arch/mips/kernel/irq_txx9.c
+++ b/arch/mips/kernel/irq_txx9.c
@@ -154,8 +154,8 @@
for (i = 0; i < TXx9_MAX_IR; i++) {
txx9irq[i].level = 4; /* middle level */
txx9irq[i].mode = TXx9_IRCR_LOW;
- set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
- &txx9_irq_chip, handle_level_irq);
+ irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip,
+ handle_level_irq);
}
/* mask all IRC interrupts */
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f7e2c78..5a88cc4 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1146,7 +1146,7 @@
setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
- set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
+ irq_set_handler(cpu_ipi_irq, handle_percpu_irq);
}
/*
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 670e3e7..de4c165 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -128,7 +128,7 @@
mips_cpu_irq_init();
for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
- set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
setup_irq(LASAT_CASCADE_IRQ, &cascade);
}
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 1549361..f27d7cc 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -44,7 +44,8 @@
u32 i;
for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
- set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &bonito_irq_type,
+ handle_level_irq);
#ifdef CONFIG_CPU_LOONGSON2E
setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index b79b24a..9027061 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -472,7 +472,7 @@
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
setup_irq(irq, action);
- set_irq_handler(irq, handle_percpu_irq);
+ irq_set_handler(irq, handle_percpu_irq);
}
void __init arch_init_irq(void)
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 3c6f190..1620b83 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -119,7 +119,7 @@
set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
#ifdef CONFIG_SMP
- set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
+ irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
#endif
}
}
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index eebaf56..5d530f8 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -172,7 +172,7 @@
pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
control);
- set_irq_msi(irq, desc);
+ irq_set_msi_desc(irq, desc);
write_msi_msg(irq, &msg);
return 0;
}
@@ -388,7 +388,7 @@
}
for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
- set_irq_chip_and_handler(irq, msi, handle_simple_irq);
+ irq_set_chip_and_handler(irq, msi, handle_simple_irq);
if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
index 352f29d..c4fa2d7 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -182,7 +182,7 @@
/* initialize all the IRQ descriptors */
for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
- set_irq_chip_and_handler(i, &msp_cic_irq_controller,
+ irq_set_chip_and_handler(i, &msp_cic_irq_controller,
handle_level_irq);
#ifdef CONFIG_MIPS_MT_SMTC
/* Mask of CIC interrupt */
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
index 8f51e4a..5bbcc47 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
@@ -77,7 +77,7 @@
/* initialize all the IRQ descriptors */
for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++)
- set_irq_chip_and_handler(i, &msp_slp_irq_controller,
+ irq_set_chip_and_handler(i, &msp_slp_irq_controller,
handle_level_irq);
}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
index 43a9e26..bec1790 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_smp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
@@ -64,7 +64,7 @@
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
setup_irq(irq, action);
- set_irq_handler(irq, handle_percpu_irq);
+ irq_set_handler(irq, handle_percpu_irq);
}
void __init msp_vsmp_int_init(void)
diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index b226bcb..adc171c 100644
--- a/arch/mips/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
@@ -259,11 +259,13 @@
/* Set IRQ information in irq_desc */
for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
pnx833x_hard_disable_pic_irq(irq);
- set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
+ irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
+ handle_simple_irq);
}
for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
- set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
+ irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
+ handle_simple_irq);
/* Set PIC priority limiter register to 0 */
PNX833X_PIC_INT_PRIORITY = 0;
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index dbdc35c..6b93c81 100644
--- a/arch/mips/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
@@ -183,7 +183,7 @@
int configPR;
for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
- set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
/* init of GIC/IPC interrupts */
/* should be done before cp0 since cp0 init enables the GIC int */
@@ -206,7 +206,7 @@
/* mask/priority is still 0 so we will not get any
* interrupts until it is unmasked */
- set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
}
/* Priority level 0 */
@@ -215,20 +215,20 @@
/* Set int vector table address */
PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
- set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
+ irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
handle_level_irq);
setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
/* init of Timer interrupts */
for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
- set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
/* Stop Timer 1-3 */
configPR = read_c0_config7();
configPR |= 0x00000038;
write_c0_config7(configPR);
- set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
+ irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
handle_level_irq);
setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
index 6f1c8ef..7fb97fb 100644
--- a/arch/mips/powertv/asic/irq_asic.c
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -112,5 +112,5 @@
* Initialize interrupt handlers.
*/
for (i = 0; i < NR_IRQS; i++)
- set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
+ irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
}
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index b32a768..7c6db74 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -207,8 +207,8 @@
pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
for (i = 0; i < RC32434_NR_IRQS; i++)
- set_irq_chip_and_handler(i, &rc32434_irq_type,
- handle_level_irq);
+ irq_set_chip_and_handler(i, &rc32434_irq_type,
+ handle_level_irq);
}
/* Main Interrupt dispatcher */
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index e6e6475..476423a 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -312,7 +312,7 @@
else
handler = &ip22_local3_irq_type;
- set_irq_chip_and_handler(i, handler, handle_level_irq);
+ irq_set_chip_and_handler(i, handler, handle_level_irq);
}
/* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index f2d09d7..1148871 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -337,7 +337,7 @@
void __devinit register_bridge_irq(unsigned int irq)
{
- set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
}
int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index c01f558..a152538 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -153,7 +153,7 @@
panic("Allocation of irq number for timer failed");
} while (xchg(&rt_timer_irq, irq));
- set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
+ irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
setup_irq(irq, &hub_rt_irqaction);
}
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index e0a3ce4..c65ea76 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -451,43 +451,51 @@
for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
switch (irq) {
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
- set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
- handle_level_irq, "level");
+ irq_set_chip_and_handler_name(irq,
+ &ip32_mace_interrupt,
+ handle_level_irq,
+ "level");
break;
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
- set_irq_chip_and_handler_name(irq,
- &ip32_macepci_interrupt, handle_level_irq,
- "level");
+ irq_set_chip_and_handler_name(irq,
+ &ip32_macepci_interrupt,
+ handle_level_irq,
+ "level");
break;
case CRIME_CPUERR_IRQ:
case CRIME_MEMERR_IRQ:
- set_irq_chip_and_handler_name(irq,
- &crime_level_interrupt, handle_level_irq,
- "level");
+ irq_set_chip_and_handler_name(irq,
+ &crime_level_interrupt,
+ handle_level_irq,
+ "level");
break;
case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
case CRIME_VICE_IRQ:
- set_irq_chip_and_handler_name(irq,
- &crime_edge_interrupt, handle_edge_irq, "edge");
+ irq_set_chip_and_handler_name(irq,
+ &crime_edge_interrupt,
+ handle_edge_irq,
+ "edge");
break;
case MACEISA_PARALLEL_IRQ:
case MACEISA_SERIAL1_TDMAPR_IRQ:
case MACEISA_SERIAL2_TDMAPR_IRQ:
- set_irq_chip_and_handler_name(irq,
- &ip32_maceisa_edge_interrupt, handle_edge_irq,
- "edge");
+ irq_set_chip_and_handler_name(irq,
+ &ip32_maceisa_edge_interrupt,
+ handle_edge_irq,
+ "edge");
break;
default:
- set_irq_chip_and_handler_name(irq,
- &ip32_maceisa_level_interrupt, handle_level_irq,
- "level");
+ irq_set_chip_and_handler_name(irq,
+ &ip32_maceisa_level_interrupt,
+ handle_level_irq,
+ "level");
break;
}
}
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 89e8188a..09740d6 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -216,7 +216,8 @@
int i;
for (i = 0; i < BCM1480_NR_IRQS; i++) {
- set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &bcm1480_irq_type,
+ handle_level_irq);
bcm1480_irq_owner[i] = 0;
}
}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index fd269ea..be4460a 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -190,7 +190,8 @@
int i;
for (i = 0; i < SB1250_NR_IRQS; i++) {
- set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &sb1250_irq_type,
+ handle_level_irq);
sb1250_irq_owner[i] = 0;
}
}
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 72b9415..c48194c 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -209,7 +209,7 @@
int i;
for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
- set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
sni_hwint = a20r_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index cfcc68a..ed3b3d317 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -296,7 +296,7 @@
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
- set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
sni_hwint = sni_pcimt_hwint;
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
}
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 0846e99..b524637 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -238,7 +238,7 @@
mips_cpu_irq_init();
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
- set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
*(volatile u32 *)SNI_PCIT_INT_REG = 0;
sni_hwint = sni_pcit_hwint;
change_c0_status(ST0_IM, IE_IRQ1);
@@ -251,7 +251,7 @@
mips_cpu_irq_init();
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
- set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
sni_hwint = sni_pcit_hwint_cplus;
change_c0_status(ST0_IM, IE_IRQ0);
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index f05d8e5..a7e5a6d 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -413,7 +413,7 @@
sni_rm200_init_8259A();
for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++)
- set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip,
+ irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip,
handle_level_irq);
setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2);
@@ -477,7 +477,7 @@
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
- set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
+ irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
sni_hwint = sni_rm200_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index e1828e8..7e3ac57 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -35,7 +35,7 @@
mips_cpu_irq_init();
txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
- set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
+ irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
handle_simple_irq);
/* raise priority for errors, timers, SIO */
txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index a6e6e80..aace856 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -23,7 +23,7 @@
mips_cpu_irq_init();
txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
- set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
+ irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
handle_simple_irq);
/* raise priority for errors, timers, SIO */
txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
index 93b6edb..6b067db 100644
--- a/arch/mips/txx9/generic/irq_tx4939.c
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -176,8 +176,8 @@
for (i = 1; i < TX4939_NUM_IR; i++) {
tx4939irq[i].level = 4; /* middle level */
tx4939irq[i].mode = TXx9_IRCR_LOW;
- set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
- &tx4939_irq_chip, handle_level_irq);
+ irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip,
+ handle_level_irq);
}
/* mask all IRC interrupts */
@@ -193,7 +193,7 @@
__raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
__raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
- set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
+ irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
handle_simple_irq);
/* raise priority for errors, timers, sio */
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 92a5c1b..c22c859 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -120,8 +120,9 @@
tx3927_irq_init();
for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
- set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
+ irq_set_chip_and_handler(i, &jmr3927_irq_ioc,
+ handle_level_irq);
/* setup IOC interrupt 1 (PCI, MODEM) */
- set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
+ irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
}
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 7c0a048..6c22c49 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -164,9 +164,9 @@
for (i = RBTX4927_IRQ_IOC;
i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
- set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
+ irq_set_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
handle_level_irq);
- set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
+ irq_set_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
}
static int rbtx4927_irq_dispatch(int pending)
@@ -194,5 +194,5 @@
tx4927_irq_init();
toshiba_rbtx4927_irq_ioc_init();
/* Onboard 10M Ether: High Active */
- set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
+ irq_set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
}
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index 2ec4fe1..58cd7a9 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -132,10 +132,10 @@
for (i = RBTX4938_IRQ_IOC;
i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
- set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
+ irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
handle_level_irq);
- set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
+ irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
}
void __init rbtx4938_irq_setup(void)
@@ -153,5 +153,5 @@
tx4938_irq_init();
toshiba_rbtx4938_irq_ioc_init();
/* Onboard 10M Ether: High Active */
- set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
+ irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
}
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
index 7007463..69a8061 100644
--- a/arch/mips/txx9/rbtx4939/irq.c
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -88,8 +88,8 @@
tx4939_irq_init();
for (i = RBTX4939_IRQ_IOC;
i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
- set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
+ irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
handle_level_irq);
- set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
+ irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
}
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index f53156b..a39ef32 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -710,11 +710,11 @@
icu2_write(MGIUINTHREG, 0xffff);
for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
- set_irq_chip_and_handler(i, &sysint1_irq_type,
+ irq_set_chip_and_handler(i, &sysint1_irq_type,
handle_level_irq);
for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
- set_irq_chip_and_handler(i, &sysint2_irq_type,
+ irq_set_chip_and_handler(i, &sysint2_irq_type,
handle_level_irq);
cascade_irq(INT0_IRQ, icu_get_irq);