tree 2dbb4a80450a4693d6eefba97ec05a16469d6b7e
parent db1b049fad8b12062edffade8272d604b4019eb7
author Heiner Kallweit <hkallweit1@gmail.com> 1477596476 +0200
committer Mark Brown <broonie@kernel.org> 1477679987 +0100

spi: fsl-espi: make better use of the RX FIFO

So far an interrupt is triggered whenever there's at least one byte
in the RX FIFO. This results in a unnecessarily high number of
interrupts.
Change this to generate an interrupt if
- RX FIFO is half full (except if all bytes to read fit into the
  RX FIFO anyway)
- end of transfer has been reached

This way the number of interrupts can be significantly reduced.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>