Merge tag 'drm-for-v4.15' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
"This is the main drm pull request for v4.15.
Core:
- Atomic object lifetime fixes
- Atomic iterator improvements
- Sparse/smatch fixes
- Legacy kms ioctls to be interruptible
- EDID override improvements
- fb/gem helper cleanups
- Simple outreachy patches
- Documentation improvements
- Fix dma-buf rcu races
- DRM mode object leasing for improving VR use cases.
- vgaarb improvements for non-x86 platforms.
New driver:
- tve200: Faraday Technology TVE200 block.
This "TV Encoder" encodes a ITU-T BT.656 stream and can be found in
the StorLink SL3516 (later Cortina Systems CS3516) as well as the
Grain Media GM8180.
New bridges:
- SiI9234 support
New panels:
- S6E63J0X03, OTM8009A, Seiko 43WVF1G, 7" rpi touch panel, Toshiba
LT089AC19000, Innolux AT043TN24
i915:
- Remove Coffeelake from alpha support
- Cannonlake workarounds
- Infoframe refactoring for DisplayPort
- VBT updates
- DisplayPort vswing/emph/buffer translation refactoring
- CCS fixes
- Restore GPU clock boost on missed vblanks
- Scatter list updates for userptr allocations
- Gen9+ transition watermarks
- Display IPC (Isochronous Priority Control)
- Private PAT management
- GVT: improved error handling and pci config sanitizing
- Execlist refactoring
- Transparent Huge Page support
- User defined priorities support
- HuC/GuC firmware refactoring
- DP MST fixes
- eDP power sequencing fixes
- Use RCU instead of stop_machine
- PSR state tracking support
- Eviction fixes
- BDW DP aux channel timeout fixes
- LSPCON fixes
- Cannonlake PLL fixes
amdgpu:
- Per VM BO support
- Powerplay cleanups
- CI powerplay support
- PASID mgr for kfd
- SR-IOV fixes
- initial GPU reset for vega10
- Prime mmap support
- TTM updates
- Clock query interface for Raven
- Fence to handle ioctl
- UVD encode ring support on Polaris
- Transparent huge page DMA support
- Compute LRU pipe tweaks
- BO flag to allow buffers to opt out of implicit sync
- CTX priority setting API
- VRAM lost infrastructure plumbing
qxl:
- fix flicker since atomic rework
amdkfd:
- Further improvements from internal AMD tree
- Usermode events
- Drop radeon support
nouveau:
- Pascal temperature sensor support
- Improved BAR2 handling
- MMU rework to support Pascal MMU
exynos:
- Improved HDMI/mixer support
- HDMI audio interface support
tegra:
- Prep work for tegra186
- Cleanup/fixes
msm:
- Preemption support for a5xx
- Display fixes for 8x96 (snapdragon 820)
- Async cursor plane fixes
- FW loading rework
- GPU debugging improvements
vc4:
- Prep for DSI panels
- fix T-format tiling scanout
- New madvise ioctl
Rockchip:
- LVDS support
omapdrm:
- omap4 HDMI CEC support
etnaviv:
- GPU performance counters groundwork
sun4i:
- refactor driver load + TCON backend
- HDMI improvements
- A31 support
- Misc fixes
udl:
- Probe/EDID read fixes.
tilcdc:
- Misc fixes.
pl111:
- Support more variants
adv7511:
- Improve EDID handling.
- HDMI CEC support
sii8620:
- Add remote control support"
* tag 'drm-for-v4.15' of git://people.freedesktop.org/~airlied/linux: (1480 commits)
drm/rockchip: analogix_dp: Use mutex rather than spinlock
drm/mode_object: fix documentation for object lookups.
drm/i915: Reorder context-close to avoid calling i915_vma_close() under RCU
drm/i915: Move init_clock_gating() back to where it was
drm/i915: Prune the reservation shared fence array
drm/i915: Idle the GPU before shinking everything
drm/i915: Lock llist_del_first() vs llist_del_all()
drm/i915: Calculate ironlake intermediate watermarks correctly, v2.
drm/i915: Disable lazy PPGTT page table optimization for vGPU
drm/i915/execlists: Remove the priority "optimisation"
drm/i915: Filter out spurious execlists context-switch interrupts
drm/amdgpu: use irq-safe lock for kiq->ring_lock
drm/amdgpu: bypass lru touch for KIQ ring submission
drm/amdgpu: Potential uninitialized variable in amdgpu_vm_update_directories()
drm/amdgpu: potential uninitialized variable in amdgpu_vce_ring_parse_cs()
drm/amd/powerplay: initialize a variable before using it
drm/amd/powerplay: suppress KASAN out of bounds warning in vega10_populate_all_memory_levels
drm/amd/amdgpu: fix evicted VRAM bo adjudgement condition
drm/vblank: Tune drm_crtc_accurate_vblank_count() WARN down to a debug
drm/rockchip: add CONFIG_OF dependency for lvds
...
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 567b037..7fc42e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -26,7 +26,7 @@
amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
- amdgpu_queue_mgr.o amdgpu_vf_error.o
+ amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
@@ -134,5 +134,3 @@
amdgpu-y += $(AMD_POWERPLAY_FILES)
obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
-
-CFLAGS_amdgpu_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 103635a..cbcb6a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -65,6 +65,7 @@
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
#include "amdgpu_vcn.h"
+#include "amdgpu_mn.h"
#include "gpu_scheduler.h"
#include "amdgpu_virt.h"
@@ -91,7 +92,7 @@ extern int amdgpu_dpm;
extern int amdgpu_fw_load_type;
extern int amdgpu_aspm;
extern int amdgpu_runtime_pm;
-extern unsigned amdgpu_ip_block_mask;
+extern uint amdgpu_ip_block_mask;
extern int amdgpu_bapm;
extern int amdgpu_deep_color;
extern int amdgpu_vm_size;
@@ -104,14 +105,14 @@ extern int amdgpu_sched_jobs;
extern int amdgpu_sched_hw_submission;
extern int amdgpu_no_evict;
extern int amdgpu_direct_gma_size;
-extern unsigned amdgpu_pcie_gen_cap;
-extern unsigned amdgpu_pcie_lane_cap;
-extern unsigned amdgpu_cg_mask;
-extern unsigned amdgpu_pg_mask;
-extern unsigned amdgpu_sdma_phase_quantum;
+extern uint amdgpu_pcie_gen_cap;
+extern uint amdgpu_pcie_lane_cap;
+extern uint amdgpu_cg_mask;
+extern uint amdgpu_pg_mask;
+extern uint amdgpu_sdma_phase_quantum;
extern char *amdgpu_disable_cu;
extern char *amdgpu_virtual_display;
-extern unsigned amdgpu_pp_feature_mask;
+extern uint amdgpu_pp_feature_mask;
extern int amdgpu_vram_page_split;
extern int amdgpu_ngg;
extern int amdgpu_prim_buf_per_se;
@@ -120,6 +121,7 @@ extern int amdgpu_cntl_sb_buf_per_se;
extern int amdgpu_param_buf_per_se;
extern int amdgpu_job_hang_limit;
extern int amdgpu_lbpw;
+extern int amdgpu_compute_multipipe;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
@@ -178,6 +180,7 @@ struct amdgpu_cs_parser;
struct amdgpu_job;
struct amdgpu_irq_src;
struct amdgpu_fpriv;
+struct amdgpu_bo_va_mapping;
enum amdgpu_cp_irq {
AMDGPU_CP_IRQ_GFX_EOP = 0,
@@ -292,14 +295,25 @@ struct amdgpu_buffer_funcs {
/* provided by hw blocks that can write ptes, e.g., sdma */
struct amdgpu_vm_pte_funcs {
+ /* number of dw to reserve per operation */
+ unsigned copy_pte_num_dw;
+
/* copy pte entries from GART */
void (*copy_pte)(struct amdgpu_ib *ib,
uint64_t pe, uint64_t src,
unsigned count);
+
/* write pte one entry at a time with addr mapping */
void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
uint64_t value, unsigned count,
uint32_t incr);
+
+ /* maximum nums of PTEs/PDEs in a single operation */
+ uint32_t set_max_nums_pte_pde;
+
+ /* number of dw to reserve per operation */
+ unsigned set_pte_pde_num_dw;
+
/* for linear pte/pde updates without addr mapping */
void (*set_pte_pde)(struct amdgpu_ib *ib,
uint64_t pe,
@@ -332,6 +346,7 @@ struct amdgpu_gart_funcs {
struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
u32 (*get_wptr)(struct amdgpu_device *adev);
+ bool (*prescreen_iv)(struct amdgpu_device *adev);
void (*decode_iv)(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry);
void (*set_rptr)(struct amdgpu_device *adev);
@@ -399,6 +414,7 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
+int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
/* sub-allocation manager, it has to be protected by another lock.
@@ -455,9 +471,10 @@ struct amdgpu_sa_bo {
*/
void amdgpu_gem_force_release(struct amdgpu_device *adev);
int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
- int alignment, u32 initial_domain,
- u64 flags, bool kernel,
- struct drm_gem_object **obj);
+ int alignment, u32 initial_domain,
+ u64 flags, bool kernel,
+ struct reservation_object *resv,
+ struct drm_gem_object **obj);
int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
@@ -715,10 +732,14 @@ struct amdgpu_ctx {
struct amdgpu_device *adev;
struct amdgpu_queue_mgr queue_mgr;
unsigned reset_counter;
+ uint32_t vram_lost_counter;
spinlock_t ring_lock;
struct dma_fence **fences;
struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
- bool preamble_presented;
+ bool preamble_presented;
+ enum amd_sched_priority init_priority;
+ enum amd_sched_priority override_priority;
+ struct mutex lock;
};
struct amdgpu_ctx_mgr {
@@ -731,17 +752,22 @@ struct amdgpu_ctx_mgr {
struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
-uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
- struct dma_fence *fence);
+int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
+ struct dma_fence *fence, uint64_t *seq);
struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
struct amdgpu_ring *ring, uint64_t seq);
+void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
+ enum amd_sched_priority priority);
int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
+int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
+
void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
+
/*
* file private structure
*/
@@ -753,7 +779,6 @@ struct amdgpu_fpriv {
struct mutex bo_list_lock;
struct idr bo_list_handles;
struct amdgpu_ctx_mgr ctx_mgr;
- u32 vram_lost_counter;
};
/*
@@ -854,7 +879,7 @@ struct amdgpu_mec {
struct amdgpu_kiq {
u64 eop_gpu_addr;
struct amdgpu_bo *eop_obj;
- struct mutex ring_mutex;
+ spinlock_t ring_lock;
struct amdgpu_ring ring;
struct amdgpu_irq_src irq;
};
@@ -1014,11 +1039,14 @@ struct amdgpu_gfx {
/* reset mask */
uint32_t grbm_soft_reset;
uint32_t srbm_soft_reset;
- bool in_reset;
/* s3/s4 mask */
bool in_suspend;
/* NGG */
struct amdgpu_ngg ngg;
+
+ /* pipe reservation */
+ struct mutex pipe_reserve_mutex;
+ DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
};
int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -1056,6 +1084,7 @@ struct amdgpu_cs_parser {
/* buffer objects */
struct ww_acquire_ctx ticket;
struct amdgpu_bo_list *bo_list;
+ struct amdgpu_mn *mn;
struct amdgpu_bo_list_entry vm_pd;
struct list_head validated;
struct dma_fence *fence;
@@ -1096,6 +1125,7 @@ struct amdgpu_job {
uint32_t gds_base, gds_size;
uint32_t gws_base, gws_size;
uint32_t oa_base, oa_size;
+ uint32_t vram_lost_counter;
/* user fence handling */
uint64_t uf_addr;
@@ -1121,7 +1151,7 @@ static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
/*
* Writeback
*/
-#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
+#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
struct amdgpu_wb {
struct amdgpu_bo *wb_obj;
@@ -1183,6 +1213,9 @@ struct amdgpu_firmware {
/* gpu info firmware data pointer */
const struct firmware *gpu_info_fw;
+
+ void *fw_buf_ptr;
+ uint64_t fw_buf_mc;
};
/*
@@ -1197,20 +1230,6 @@ void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
void amdgpu_test_moves(struct amdgpu_device *adev);
/*
- * MMU Notifier
- */
-#if defined(CONFIG_MMU_NOTIFIER)
-int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
-void amdgpu_mn_unregister(struct amdgpu_bo *bo);
-#else
-static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
-{
- return -ENODEV;
-}
-static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
-#endif
-
-/*
* Debugfs
*/
struct amdgpu_debugfs {
@@ -1305,6 +1324,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
@@ -1371,6 +1392,18 @@ struct amdgpu_atcs {
};
/*
+ * Firmware VRAM reservation
+ */
+struct amdgpu_fw_vram_usage {
+ u64 start_offset;
+ u64 size;
+ struct amdgpu_bo *reserved_bo;
+ void *va;
+};
+
+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
+
+/*
* CGS
*/
struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
@@ -1519,7 +1552,6 @@ struct amdgpu_device {
/* powerplay */
struct amd_powerplay powerplay;
- bool pp_enabled;
bool pp_force_state_enabled;
/* dpm */
@@ -1575,6 +1607,8 @@ struct amdgpu_device {
struct delayed_work late_init_work;
struct amdgpu_virt virt;
+ /* firmware VRAM reservation */
+ struct amdgpu_fw_vram_usage fw_vram_usage;
/* link all shadow bo */
struct list_head shadow_list;
@@ -1592,6 +1626,7 @@ struct amdgpu_device {
/* record last mm index being written through WREG32*/
unsigned long last_mm_index;
+ bool in_sriov_reset;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1759,6 +1794,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
+#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
@@ -1791,18 +1827,6 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
u64 num_vis_bytes);
void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
-int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
-int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
- uint32_t flags);
-bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
-struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
-bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
- unsigned long end);
-bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
- int *last_invalidated);
-bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
-uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
- struct ttm_mem_reg *mem);
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
@@ -1836,8 +1860,6 @@ static inline bool amdgpu_has_atpx(void) { return false; }
extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
extern const int amdgpu_max_kms_ioctl;
-bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
- struct amdgpu_fpriv *fpriv);
int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
void amdgpu_driver_unload_kms(struct drm_device *dev);
void amdgpu_driver_lastclose_kms(struct drm_device *dev);
@@ -1885,10 +1907,9 @@ static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
#endif
-struct amdgpu_bo_va_mapping *
-amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
- uint64_t addr, struct amdgpu_bo **bo);
-int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
+int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
+ uint64_t addr, struct amdgpu_bo **bo,
+ struct amdgpu_bo_va_mapping **mapping);
#include "amdgpu_object.h"
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index ebca223..c04f44a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -35,41 +35,50 @@
#include "acp_gfx_if.h"
-#define ACP_TILE_ON_MASK 0x03
-#define ACP_TILE_OFF_MASK 0x02
-#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
-#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
+#define ACP_TILE_ON_MASK 0x03
+#define ACP_TILE_OFF_MASK 0x02
+#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
+#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
-#define ACP_TILE_P1_MASK 0x3e
-#define ACP_TILE_P2_MASK 0x3d
-#define ACP_TILE_DSP0_MASK 0x3b
-#define ACP_TILE_DSP1_MASK 0x37
+#define ACP_TILE_P1_MASK 0x3e
+#define ACP_TILE_P2_MASK 0x3d
+#define ACP_TILE_DSP0_MASK 0x3b
+#define ACP_TILE_DSP1_MASK 0x37
-#define ACP_TILE_DSP2_MASK 0x2f
+#define ACP_TILE_DSP2_MASK 0x2f
-#define ACP_DMA_REGS_END 0x146c0
-#define ACP_I2S_PLAY_REGS_START 0x14840
-#define ACP_I2S_PLAY_REGS_END 0x148b4
-#define ACP_I2S_CAP_REGS_START 0x148b8
-#define ACP_I2S_CAP_REGS_END 0x1496c
+#define ACP_DMA_REGS_END 0x146c0
+#define ACP_I2S_PLAY_REGS_START 0x14840
+#define ACP_I2S_PLAY_REGS_END 0x148b4
+#define ACP_I2S_CAP_REGS_START 0x148b8
+#define ACP_I2S_CAP_REGS_END 0x1496c
-#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
-#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
-#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
-#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
+#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
+#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
+#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
+#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
-#define mmACP_PGFSM_RETAIN_REG 0x51c9
-#define mmACP_PGFSM_CONFIG_REG 0x51ca
-#define mmACP_PGFSM_READ_REG_0 0x51cc
+#define mmACP_PGFSM_RETAIN_REG 0x51c9
+#define mmACP_PGFSM_CONFIG_REG 0x51ca
+#define mmACP_PGFSM_READ_REG_0 0x51cc
-#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
-#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
-#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
-#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
+#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
+#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
+#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
+#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
-#define ACP_TIMEOUT_LOOP 0x000000FF
-#define ACP_DEVS 3
-#define ACP_SRC_ID 162
+#define mmACP_CONTROL 0x5131
+#define mmACP_STATUS 0x5133
+#define mmACP_SOFT_RESET 0x5134
+#define ACP_CONTROL__ClkEn_MASK 0x1
+#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
+#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
+#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
+#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
+
+#define ACP_TIMEOUT_LOOP 0x000000FF
+#define ACP_DEVS 3
+#define ACP_SRC_ID 162
enum {
ACP_TILE_P1 = 0,
@@ -260,6 +269,8 @@ static int acp_hw_init(void *handle)
{
int r, i;
uint64_t acp_base;
+ u32 val = 0;
+ u32 count = 0;
struct device *dev;
struct i2s_platform_data *i2s_pdata;
@@ -402,6 +413,46 @@ static int acp_hw_init(void *handle)
}
}
+ /* Assert Soft reset of ACP */
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
+
+ val |= ACP_SOFT_RESET__SoftResetAud_MASK;
+ cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
+
+ count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
+ while (true) {
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
+ if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
+ (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
+ break;
+ if (--count == 0) {
+ dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
+ return -ETIMEDOUT;
+ }
+ udelay(100);
+ }
+ /* Enable clock to ACP and wait until the clock is enabled */
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
+ val = val | ACP_CONTROL__ClkEn_MASK;
+ cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
+
+ count = ACP_CLOCK_EN_TIME_OUT_VALUE;
+
+ while (true) {
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
+ if (val & (u32) 0x1)
+ break;
+ if (--count == 0) {
+ dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
+ return -ETIMEDOUT;
+ }
+ udelay(100);
+ }
+ /* Deassert the SOFT RESET flags */
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
+ val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
+ cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
+
return 0;
}
@@ -414,6 +465,8 @@ static int acp_hw_init(void *handle)
static int acp_hw_fini(void *handle)
{
int i, ret;
+ u32 val = 0;
+ u32 count = 0;
struct device *dev;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -421,6 +474,42 @@ static int acp_hw_fini(void *handle)
if (!adev->acp.acp_cell)
return 0;
+ /* Assert Soft reset of ACP */
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
+
+ val |= ACP_SOFT_RESET__SoftResetAud_MASK;
+ cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
+
+ count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
+ while (true) {
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
+ if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
+ (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
+ break;
+ if (--count == 0) {
+ dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
+ return -ETIMEDOUT;
+ }
+ udelay(100);
+ }
+ /* Disable ACP clock */
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
+ val &= ~ACP_CONTROL__ClkEn_MASK;
+ cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
+
+ count = ACP_CLOCK_EN_TIME_OUT_VALUE;
+
+ while (true) {
+ val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
+ if (val & (u32) 0x1)
+ break;
+ if (--count == 0) {
+ dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
+ return -ETIMEDOUT;
+ }
+ udelay(100);
+ }
+
if (adev->acp.acp_genpd) {
for (i = 0; i < ACP_DEVS ; i++) {
dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index b9dbbf9..47d1c13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -169,6 +169,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
.get_vmem_size = get_vmem_size,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
+ .alloc_pasid = amdgpu_vm_alloc_pasid,
+ .free_pasid = amdgpu_vm_free_pasid,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
.init_pipeline = kgd_init_pipeline,
@@ -336,6 +338,7 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
struct cik_mqd *m;
uint32_t *mqd_hqd;
uint32_t reg, wptr_val, data;
+ bool valid_wptr = false;
m = get_mqd(mqd);
@@ -354,7 +357,14 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
- if (read_user_wptr(mm, wptr, wptr_val))
+ /* read_user_ptr may take the mm->mmap_sem.
+ * release srbm_mutex to avoid circular dependency between
+ * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
+ */
+ release_queue(kgd);
+ valid_wptr = read_user_wptr(mm, wptr, wptr_val);
+ acquire_queue(kgd, pipe_id, queue_id);
+ if (valid_wptr)
WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 309f241..056929b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -128,6 +128,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
.get_vmem_size = get_vmem_size,
.get_gpu_clock_counter = get_gpu_clock_counter,
.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
+ .alloc_pasid = amdgpu_vm_alloc_pasid,
+ .free_pasid = amdgpu_vm_free_pasid,
.program_sh_mem_settings = kgd_program_sh_mem_settings,
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
.init_pipeline = kgd_init_pipeline,
@@ -290,6 +292,7 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
struct vi_mqd *m;
uint32_t *mqd_hqd;
uint32_t reg, wptr_val, data;
+ bool valid_wptr = false;
m = get_mqd(mqd);
@@ -337,7 +340,14 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
- if (read_user_wptr(mm, wptr, wptr_val))
+ /* read_user_ptr may take the mm->mmap_sem.
+ * release srbm_mutex to avoid circular dependency between
+ * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
+ */
+ release_queue(kgd);
+ valid_wptr = read_user_wptr(mm, wptr, wptr_val);
+ acquire_queue(kgd, pipe_id, queue_id);
+ if (valid_wptr)
WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index ce44358..f450b69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1766,34 +1766,32 @@ bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
return true;
}
-/* Atom needs data in little endian format
- * so swap as appropriate when copying data to
- * or from atom. Note that atom operates on
- * dw units.
+/* Atom needs data in little endian format so swap as appropriate when copying
+ * data to or from atom. Note that atom operates on dw units.
+ *
+ * Use to_le=true when sending data to atom and provide at least
+ * ALIGN(num_bytes,4) bytes in the dst buffer.
+ *
+ * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
+ * byes in the src buffer.
*/
void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
{
#ifdef __BIG_ENDIAN
- u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
- u32 *dst32, *src32;
+ u32 src_tmp[5], dst_tmp[5];
int i;
+ u8 align_num_bytes = ALIGN(num_bytes, 4);
- memcpy(src_tmp, src, num_bytes);
- src32 = (u32 *)src_tmp;
- dst32 = (u32 *)dst_tmp;
if (to_le) {
- for (i = 0; i < ((num_bytes + 3) / 4); i++)
- dst32[i] = cpu_to_le32(src32[i]);
- memcpy(dst, dst_tmp, num_bytes);
+ memcpy(src_tmp, src, num_bytes);
+ for (i = 0; i < align_num_bytes / 4; i++)
+ dst_tmp[i] = cpu_to_le32(src_tmp[i]);
+ memcpy(dst, dst_tmp, align_num_bytes);
} else {
- u8 dws = num_bytes & ~3;
- for (i = 0; i < ((num_bytes + 3) / 4); i++)
- dst32[i] = le32_to_cpu(src32[i]);
- memcpy(dst, dst_tmp, dws);
- if (num_bytes % 4) {
- for (i = 0; i < (num_bytes % 4); i++)
- dst[dws+i] = dst_tmp[dws+i];
- }
+ memcpy(src_tmp, src, align_num_bytes);
+ for (i = 0; i < align_num_bytes / 4; i++)
+ dst_tmp[i] = le32_to_cpu(src_tmp[i]);
+ memcpy(dst, dst_tmp, num_bytes);
}
#else
memcpy(dst, src, num_bytes);
@@ -1807,6 +1805,8 @@ int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
uint16_t data_offset;
int usage_bytes = 0;
struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
+ u64 start_addr;
+ u64 size;
if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
@@ -1815,7 +1815,21 @@ int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
- usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
+ start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
+ size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
+
+ if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+ (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
+ ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+ /* Firmware request VRAM reservation for SR-IOV */
+ adev->fw_vram_usage.start_offset = (start_addr &
+ (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+ adev->fw_vram_usage.size = size << 10;
+ /* Use the default scratch size */
+ usage_bytes = 0;
+ } else {
+ usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
+ }
}
ctx->scratch_size_bytes = 0;
if (usage_bytes == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index f9ffe8e..ff8efd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -71,19 +71,33 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
struct atom_context *ctx = adev->mode_info.atom_context;
int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
vram_usagebyfirmware);
+ struct vram_usagebyfirmware_v2_1 * firmware_usage;
+ uint32_t start_addr, size;
uint16_t data_offset;
int usage_bytes = 0;
if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
- struct vram_usagebyfirmware_v2_1 *firmware_usage =
- (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
-
+ firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
le32_to_cpu(firmware_usage->start_address_in_kb),
le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
le16_to_cpu(firmware_usage->used_by_driver_in_kb));
- usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) * 1024;
+ start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
+ size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
+
+ if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+ (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
+ ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+ /* Firmware request VRAM reservation for SR-IOV */
+ adev->fw_vram_usage.start_offset = (start_addr &
+ (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+ adev->fw_vram_usage.size = size << 10;
+ /* Use the default scratch size */
+ usage_bytes = 0;
+ } else {
+ usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
+ }
}
ctx->scratch_size_bytes = 0;
if (usage_bytes == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index fd435a9..a7afe55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -42,10 +42,31 @@ struct amdgpu_cgs_device {
struct amdgpu_device *adev = \
((struct amdgpu_cgs_device *)cgs_device)->adev
+static void *amdgpu_cgs_register_pp_handle(struct cgs_device *cgs_device,
+ int (*call_back_func)(struct amd_pp_init *, void **))
+{
+ CGS_FUNC_ADEV;
+ struct amd_pp_init pp_init;
+ struct amd_powerplay *amd_pp;
+
+ if (call_back_func == NULL)
+ return NULL;
+
+ amd_pp = &(adev->powerplay);
+ pp_init.chip_family = adev->family;
+ pp_init.chip_id = adev->asic_type;
+ pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
+ pp_init.feature_mask = amdgpu_pp_feature_mask;
+ pp_init.device = cgs_device;
+ if (call_back_func(&pp_init, &(amd_pp->pp_handle)))
+ return NULL;
+
+ return adev->powerplay.pp_handle;
+}
+
static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
enum cgs_gpu_mem_type type,
uint64_t size, uint64_t align,
- uint64_t min_offset, uint64_t max_offset,
cgs_handle_t *handle)
{
CGS_FUNC_ADEV;
@@ -53,13 +74,6 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
int ret = 0;
uint32_t domain = 0;
struct amdgpu_bo *obj;
- struct ttm_placement placement;
- struct ttm_place place;
-
- if (min_offset > max_offset) {
- BUG_ON(1);
- return -EINVAL;
- }
/* fail if the alignment is not a power of 2 */
if (((align != 1) && (align & (align - 1)))
@@ -73,41 +87,19 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
- if (max_offset > adev->mc.real_vram_size)
- return -EINVAL;
- place.fpfn = min_offset >> PAGE_SHIFT;
- place.lpfn = max_offset >> PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
- TTM_PL_FLAG_VRAM;
break;
case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
- if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
- place.fpfn =
- max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
- place.lpfn =
- min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
- TTM_PL_FLAG_VRAM;
- }
-
break;
case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
domain = AMDGPU_GEM_DOMAIN_GTT;
- place.fpfn = min_offset >> PAGE_SHIFT;
- place.lpfn = max_offset >> PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
break;
case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
domain = AMDGPU_GEM_DOMAIN_GTT;
- place.fpfn = min_offset >> PAGE_SHIFT;
- place.lpfn = max_offset >> PAGE_SHIFT;
- place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
- TTM_PL_FLAG_UNCACHED;
break;
default:
return -EINVAL;
@@ -116,15 +108,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
*handle = 0;
- placement.placement = &place;
- placement.num_placement = 1;
- placement.busy_placement = &place;
- placement.num_busy_placement = 1;
-
- ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
- true, domain, flags,
- NULL, &placement, NULL,
- 0, &obj);
+ ret = amdgpu_bo_create(adev, size, align, true, domain, flags,
+ NULL, NULL, 0, &obj);
if (ret) {
DRM_ERROR("(%d) bo create failed\n", ret);
return ret;
@@ -155,19 +140,14 @@ static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t h
uint64_t *mcaddr)
{
int r;
- u64 min_offset, max_offset;
struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
WARN_ON_ONCE(obj->placement.num_placement > 1);
- min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
- max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
-
r = amdgpu_bo_reserve(obj, true);
if (unlikely(r != 0))
return r;
- r = amdgpu_bo_pin_restricted(obj, obj->preferred_domains,
- min_offset, max_offset, mcaddr);
+ r = amdgpu_bo_pin(obj, obj->preferred_domains, mcaddr);
amdgpu_bo_unreserve(obj);
return r;
}
@@ -675,6 +655,85 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
if (!adev->pm.fw) {
switch (adev->asic_type) {
+ case CHIP_TAHITI:
+ strcpy(fw_name, "radeon/tahiti_smc.bin");
+ break;
+ case CHIP_PITCAIRN:
+ if ((adev->pdev->revision == 0x81) &&
+ ((adev->pdev->device == 0x6810) ||
+ (adev->pdev->device == 0x6811))) {
+ info->is_kicker = true;
+ strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
+ } else {
+ strcpy(fw_name, "radeon/pitcairn_smc.bin");
+ }
+ break;
+ case CHIP_VERDE:
+ if (((adev->pdev->device == 0x6820) &&
+ ((adev->pdev->revision == 0x81) ||
+ (adev->pdev->revision == 0x83))) ||
+ ((adev->pdev->device == 0x6821) &&
+ ((adev->pdev->revision == 0x83) ||
+ (adev->pdev->revision == 0x87))) ||
+ ((adev->pdev->revision == 0x87) &&
+ ((adev->pdev->device == 0x6823) ||
+ (adev->pdev->device == 0x682b)))) {
+ info->is_kicker = true;
+ strcpy(fw_name, "radeon/verde_k_smc.bin");
+ } else {
+ strcpy(fw_name, "radeon/verde_smc.bin");
+ }
+ break;
+ case CHIP_OLAND:
+ if (((adev->pdev->revision == 0x81) &&
+ ((adev->pdev->device == 0x6600) ||
+ (adev->pdev->device == 0x6604) ||
+ (adev->pdev->device == 0x6605) ||
+ (adev->pdev->device == 0x6610))) ||
+ ((adev->pdev->revision == 0x83) &&
+ (adev->pdev->device == 0x6610))) {
+ info->is_kicker = true;
+ strcpy(fw_name, "radeon/oland_k_smc.bin");
+ } else {
+ strcpy(fw_name, "radeon/oland_smc.bin");
+ }
+ break;
+ case CHIP_HAINAN:
+ if (((adev->pdev->revision == 0x81) &&
+ (adev->pdev->device == 0x6660)) ||
+ ((adev->pdev->revision == 0x83) &&
+ ((adev->pdev->device == 0x6660) ||
+ (adev->pdev->device == 0x6663) ||
+ (adev->pdev->device == 0x6665) ||
+ (adev->pdev->device == 0x6667)))) {
+ info->is_kicker = true;
+ strcpy(fw_name, "radeon/hainan_k_smc.bin");
+ } else if ((adev->pdev->revision == 0xc3) &&
+ (adev->pdev->device == 0x6665)) {
+ info->is_kicker = true;
+ strcpy(fw_name, "radeon/banks_k_2_smc.bin");
+ } else {
+ strcpy(fw_name, "radeon/hainan_smc.bin");
+ }
+ break;
+ case CHIP_BONAIRE:
+ if ((adev->pdev->revision == 0x80) ||
+ (adev->pdev->revision == 0x81) ||
+ (adev->pdev->device == 0x665f)) {
+ info->is_kicker = true;
+ strcpy(fw_name, "radeon/bonaire_k_smc.bin");
+ } else {
+ strcpy(fw_name, "radeon/bonaire_smc.bin");
+ }
+ break;
+ case CHIP_HAWAII:
+ if (adev->pdev->revision == 0x80) {
+ info->is_kicker = true;
+ strcpy(fw_name, "radeon/hawaii_k_smc.bin");
+ } else {
+ strcpy(fw_name, "radeon/hawaii_smc.bin");
+ }
+ break;
case CHIP_TOPAZ:
if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
@@ -838,6 +897,9 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
sys_info->value = adev->pdev->subsystem_vendor;
break;
+ case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
+ sys_info->value = adev->pdev->devfn;
+ break;
default:
return -ENODEV;
}
@@ -1139,6 +1201,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
+ .register_pp_handle = amdgpu_cgs_register_pp_handle,
};
static const struct cgs_os_ops amdgpu_cgs_os_ops = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 8d1cf2d..df9cbc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -231,7 +231,7 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
if (connector->encoder_ids[i] == 0)
break;
- encoder = drm_encoder_find(connector->dev,
+ encoder = drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[i]);
if (!encoder)
continue;
@@ -256,7 +256,7 @@ amdgpu_connector_find_encoder(struct drm_connector *connector,
for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
if (connector->encoder_ids[i] == 0)
break;
- encoder = drm_encoder_find(connector->dev,
+ encoder = drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[i]);
if (!encoder)
continue;
@@ -346,10 +346,8 @@ static void amdgpu_connector_free_edid(struct drm_connector *connector)
{
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
- if (amdgpu_connector->edid) {
- kfree(amdgpu_connector->edid);
- amdgpu_connector->edid = NULL;
- }
+ kfree(amdgpu_connector->edid);
+ amdgpu_connector->edid = NULL;
}
static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
@@ -374,7 +372,7 @@ amdgpu_connector_best_single_encoder(struct drm_connector *connector)
/* pick the encoder ids */
if (enc_id)
- return drm_encoder_find(connector->dev, enc_id);
+ return drm_encoder_find(connector->dev, NULL, enc_id);
return NULL;
}
@@ -1079,7 +1077,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
if (connector->encoder_ids[i] == 0)
break;
- encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+ encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
if (!encoder)
continue;
@@ -1136,7 +1134,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector)
if (connector->encoder_ids[i] == 0)
break;
- encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+ encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
if (!encoder)
continue;
@@ -1155,7 +1153,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector)
/* then check use digitial */
/* pick the first one */
if (enc_id)
- return drm_encoder_find(connector->dev, enc_id);
+ return drm_encoder_find(connector->dev, NULL, enc_id);
return NULL;
}
@@ -1296,7 +1294,7 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
if (connector->encoder_ids[i] == 0)
break;
- encoder = drm_encoder_find(connector->dev,
+ encoder = drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[i]);
if (!encoder)
continue;
@@ -1325,7 +1323,7 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
if (connector->encoder_ids[i] == 0)
break;
- encoder = drm_encoder_find(connector->dev,
+ encoder = drm_encoder_find(connector->dev, NULL,
connector->encoder_ids[i]);
if (!encoder)
continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index cd66483..6c78623 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -25,6 +25,7 @@
* Jerome Glisse <glisse@freedesktop.org>
*/
#include <linux/pagemap.h>
+#include <linux/sync_file.h>
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include <drm/drm_syncobj.h>
@@ -89,12 +90,14 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
goto free_chunk;
}
+ mutex_lock(&p->ctx->lock);
+
/* get chunks */
chunk_array_user = u64_to_user_ptr(cs->in.chunks);
if (copy_from_user(chunk_array, chunk_array_user,
sizeof(uint64_t)*cs->in.num_chunks)) {
ret = -EFAULT;
- goto put_ctx;
+ goto free_chunk;
}
p->nchunks = cs->in.num_chunks;
@@ -102,7 +105,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
GFP_KERNEL);
if (!p->chunks) {
ret = -ENOMEM;
- goto put_ctx;
+ goto free_chunk;
}
for (i = 0; i < p->nchunks; i++) {
@@ -169,6 +172,11 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
if (ret)
goto free_all_kdata;
+ if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
+ ret = -ECANCELED;
+ goto free_all_kdata;
+ }
+
if (p->uf_entry.robj)
p->job->uf_addr = uf_offset;
kfree(chunk_array);
@@ -182,8 +190,6 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
kfree(p->chunks);
p->chunks = NULL;
p->nchunks = 0;
-put_ctx:
- amdgpu_ctx_put(p->ctx);
free_chunk:
kfree(chunk_array);
@@ -473,11 +479,16 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
return -EPERM;
/* Check if we have user pages and nobody bound the BO already */
- if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
- size_t size = sizeof(struct page *);
-
- size *= bo->tbo.ttm->num_pages;
- memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
+ if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
+ lobj->user_pages) {
+ amdgpu_ttm_placement_from_domain(bo,
+ AMDGPU_GEM_DOMAIN_CPU);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, true,
+ false);
+ if (r)
+ return r;
+ amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
+ lobj->user_pages);
binding_userptr = true;
}
@@ -502,7 +513,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
struct amdgpu_bo_list_entry *e;
struct list_head duplicates;
- bool need_mmap_lock = false;
unsigned i, tries = 10;
int r;
@@ -510,9 +520,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
if (p->bo_list) {
- need_mmap_lock = p->bo_list->first_userptr !=
- p->bo_list->num_entries;
amdgpu_bo_list_get_list(p->bo_list, &p->validated);
+ if (p->bo_list->first_userptr != p->bo_list->num_entries)
+ p->mn = amdgpu_mn_get(p->adev);
}
INIT_LIST_HEAD(&duplicates);
@@ -521,9 +531,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
if (p->uf_entry.robj)
list_add(&p->uf_entry.tv.head, &p->validated);
- if (need_mmap_lock)
- down_read(¤t->mm->mmap_sem);
-
while (1) {
struct list_head need_pages;
unsigned i;
@@ -543,22 +550,24 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
INIT_LIST_HEAD(&need_pages);
for (i = p->bo_list->first_userptr;
i < p->bo_list->num_entries; ++i) {
+ struct amdgpu_bo *bo;
e = &p->bo_list->array[i];
+ bo = e->robj;
- if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
+ if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
&e->user_invalidated) && e->user_pages) {
/* We acquired a page array, but somebody
* invalidated it. Free it and try again
*/
release_pages(e->user_pages,
- e->robj->tbo.ttm->num_pages);
+ bo->tbo.ttm->num_pages);
kvfree(e->user_pages);
e->user_pages = NULL;
}
- if (e->robj->tbo.ttm->state != tt_bound &&
+ if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
!e->user_pages) {
list_del(&e->tv.head);
list_add(&e->tv.head, &need_pages);
@@ -635,9 +644,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
p->bytes_moved_vis);
- fpriv->vm.last_eviction_counter =
- atomic64_read(&p->adev->num_evictions);
-
if (p->bo_list) {
struct amdgpu_bo *gds = p->bo_list->gds_obj;
struct amdgpu_bo *gws = p->bo_list->gws_obj;
@@ -678,9 +684,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
error_free_pages:
- if (need_mmap_lock)
- up_read(¤t->mm->mmap_sem);
-
if (p->bo_list) {
for (i = p->bo_list->first_userptr;
i < p->bo_list->num_entries; ++i) {
@@ -705,7 +708,8 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
list_for_each_entry(e, &p->validated, tv.head) {
struct reservation_object *resv = e->robj->tbo.resv;
- r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
+ r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
+ amdgpu_bo_explicit_sync(e->robj));
if (r)
return r;
@@ -726,11 +730,7 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
{
unsigned i;
- if (!error)
- ttm_eu_fence_buffer_objects(&parser->ticket,
- &parser->validated,
- parser->fence);
- else if (backoff)
+ if (error && backoff)
ttm_eu_backoff_reservation(&parser->ticket,
&parser->validated);
@@ -740,8 +740,10 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
dma_fence_put(parser->fence);
- if (parser->ctx)
+ if (parser->ctx) {
+ mutex_unlock(&parser->ctx->lock);
amdgpu_ctx_put(parser->ctx);
+ }
if (parser->bo_list)
amdgpu_bo_list_put(parser->bo_list);
@@ -766,10 +768,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
if (r)
return r;
- r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
- if (r)
- return r;
-
r = amdgpu_vm_clear_freed(adev, vm, NULL);
if (r)
return r;
@@ -823,7 +821,13 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
}
- r = amdgpu_vm_clear_moved(adev, vm, &p->job->sync);
+ r = amdgpu_vm_handle_moved(adev, vm);
+ if (r)
+ return r;
+
+ r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update);
+ if (r)
+ return r;
if (amdgpu_vm_debug && p->bo_list) {
/* Invalidate all BOs to test for userspace bugs */
@@ -833,7 +837,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
if (!bo)
continue;
- amdgpu_vm_bo_invalidate(adev, bo);
+ amdgpu_vm_bo_invalidate(adev, bo, false);
}
}
@@ -846,19 +850,63 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_ring *ring = p->job->ring;
- int i, r;
+ int r;
/* Only for UVD/VCE VM emulation */
- if (ring->funcs->parse_cs) {
- for (i = 0; i < p->job->num_ibs; i++) {
- r = amdgpu_ring_parse_cs(ring, p, i);
+ if (p->job->ring->funcs->parse_cs) {
+ unsigned i, j;
+
+ for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
+ struct drm_amdgpu_cs_chunk_ib *chunk_ib;
+ struct amdgpu_bo_va_mapping *m;
+ struct amdgpu_bo *aobj = NULL;
+ struct amdgpu_cs_chunk *chunk;
+ struct amdgpu_ib *ib;
+ uint64_t offset;
+ uint8_t *kptr;
+
+ chunk = &p->chunks[i];
+ ib = &p->job->ibs[j];
+ chunk_ib = chunk->kdata;
+
+ if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
+ continue;
+
+ r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
+ &aobj, &m);
+ if (r) {
+ DRM_ERROR("IB va_start is invalid\n");
+ return r;
+ }
+
+ if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
+ (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
+ DRM_ERROR("IB va_start+ib_bytes is invalid\n");
+ return -EINVAL;
+ }
+
+ /* the IB should be reserved at this point */
+ r = amdgpu_bo_kmap(aobj, (void **)&kptr);
+ if (r) {
+ return r;
+ }
+
+ offset = m->start * AMDGPU_GPU_PAGE_SIZE;
+ kptr += chunk_ib->va_start - offset;
+
+ memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
+ amdgpu_bo_kunmap(aobj);
+
+ r = amdgpu_ring_parse_cs(ring, p, j);
if (r)
return r;
+
+ j++;
}
}
if (p->job->vm) {
- p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
+ p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
r = amdgpu_bo_vm_update_pte(p);
if (r)
@@ -920,54 +968,18 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
parser->job->ring = ring;
- if (ring->funcs->parse_cs) {
- struct amdgpu_bo_va_mapping *m;
- struct amdgpu_bo *aobj = NULL;
- uint64_t offset;
- uint8_t *kptr;
-
- m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
- &aobj);
- if (!aobj) {
- DRM_ERROR("IB va_start is invalid\n");
- return -EINVAL;
- }
-
- if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
- (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
- DRM_ERROR("IB va_start+ib_bytes is invalid\n");
- return -EINVAL;
- }
-
- /* the IB should be reserved at this point */
- r = amdgpu_bo_kmap(aobj, (void **)&kptr);
- if (r) {
- return r;
- }
-
- offset = m->start * AMDGPU_GPU_PAGE_SIZE;
- kptr += chunk_ib->va_start - offset;
-
- r = amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
- if (r) {
- DRM_ERROR("Failed to get ib !\n");
- return r;
- }
-
- memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
- amdgpu_bo_kunmap(aobj);
- } else {
- r = amdgpu_ib_get(adev, vm, 0, ib);
- if (r) {
- DRM_ERROR("Failed to get ib !\n");
- return r;
- }
-
+ r = amdgpu_ib_get(adev, vm,
+ ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
+ ib);
+ if (r) {
+ DRM_ERROR("Failed to get ib !\n");
+ return r;
}
ib->gpu_addr = chunk_ib->va_start;
ib->length_dw = chunk_ib->ib_bytes / 4;
ib->flags = chunk_ib->flags;
+
j++;
}
@@ -977,7 +989,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
return -EINVAL;
- return 0;
+ return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
}
static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
@@ -1131,14 +1143,31 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
struct amdgpu_ring *ring = p->job->ring;
struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
struct amdgpu_job *job;
+ unsigned i;
+ uint64_t seq;
+
int r;
+ amdgpu_mn_lock(p->mn);
+ if (p->bo_list) {
+ for (i = p->bo_list->first_userptr;
+ i < p->bo_list->num_entries; ++i) {
+ struct amdgpu_bo *bo = p->bo_list->array[i].robj;
+
+ if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
+ amdgpu_mn_unlock(p->mn);
+ return -ERESTARTSYS;
+ }
+ }
+ }
+
job = p->job;
p->job = NULL;
r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
if (r) {
amdgpu_job_free(job);
+ amdgpu_mn_unlock(p->mn);
return r;
}
@@ -1146,21 +1175,36 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
job->fence_ctx = entity->fence_context;
p->fence = dma_fence_get(&job->base.s_fence->finished);
+ r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
+ if (r) {
+ dma_fence_put(p->fence);
+ dma_fence_put(&job->base.s_fence->finished);
+ amdgpu_job_free(job);
+ amdgpu_mn_unlock(p->mn);
+ return r;
+ }
+
amdgpu_cs_post_dependencies(p);
- cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
- job->uf_sequence = cs->out.handle;
+ cs->out.handle = seq;
+ job->uf_sequence = seq;
+
amdgpu_job_free_resources(job);
+ amdgpu_ring_priority_get(job->ring,
+ amd_sched_get_job_priority(&job->base));
trace_amdgpu_cs_ioctl(job);
amd_sched_entity_push_job(&job->base);
+
+ ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
+ amdgpu_mn_unlock(p->mn);
+
return 0;
}
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
struct amdgpu_device *adev = dev->dev_private;
- struct amdgpu_fpriv *fpriv = filp->driver_priv;
union drm_amdgpu_cs *cs = data;
struct amdgpu_cs_parser parser = {};
bool reserved_buffers = false;
@@ -1168,8 +1212,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
if (!adev->accel_working)
return -EBUSY;
- if (amdgpu_kms_vram_lost(adev, fpriv))
- return -ENODEV;
parser.adev = adev;
parser.filp = filp;
@@ -1180,6 +1222,10 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
goto out;
}
+ r = amdgpu_cs_ib_fill(adev, &parser);
+ if (r)
+ goto out;
+
r = amdgpu_cs_parser_bos(&parser, data);
if (r) {
if (r == -ENOMEM)
@@ -1190,9 +1236,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
}
reserved_buffers = true;
- r = amdgpu_cs_ib_fill(adev, &parser);
- if (r)
- goto out;
r = amdgpu_cs_dependencies(adev, &parser);
if (r) {
@@ -1228,16 +1271,12 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
{
union drm_amdgpu_wait_cs *wait = data;
struct amdgpu_device *adev = dev->dev_private;
- struct amdgpu_fpriv *fpriv = filp->driver_priv;
unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
struct amdgpu_ring *ring = NULL;
struct amdgpu_ctx *ctx;
struct dma_fence *fence;
long r;
- if (amdgpu_kms_vram_lost(adev, fpriv))
- return -ENODEV;
-
ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
if (ctx == NULL)
return -EINVAL;
@@ -1255,6 +1294,8 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
r = PTR_ERR(fence);
else if (fence) {
r = dma_fence_wait_timeout(fence, true, timeout);
+ if (r > 0 && fence->error)
+ r = fence->error;
dma_fence_put(fence);
} else
r = 1;
@@ -1302,6 +1343,62 @@ static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
return fence;
}
+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ struct amdgpu_device *adev = dev->dev_private;
+ union drm_amdgpu_fence_to_handle *info = data;
+ struct dma_fence *fence;
+ struct drm_syncobj *syncobj;
+ struct sync_file *sync_file;
+ int fd, r;
+
+ fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
+ if (IS_ERR(fence))
+ return PTR_ERR(fence);
+
+ switch (info->in.what) {
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
+ r = drm_syncobj_create(&syncobj, 0, fence);
+ dma_fence_put(fence);
+ if (r)
+ return r;
+ r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
+ drm_syncobj_put(syncobj);
+ return r;
+
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
+ r = drm_syncobj_create(&syncobj, 0, fence);
+ dma_fence_put(fence);
+ if (r)
+ return r;
+ r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
+ drm_syncobj_put(syncobj);
+ return r;
+
+ case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
+ fd = get_unused_fd_flags(O_CLOEXEC);
+ if (fd < 0) {
+ dma_fence_put(fence);
+ return fd;
+ }
+
+ sync_file = sync_file_create(fence);
+ dma_fence_put(fence);
+ if (!sync_file) {
+ put_unused_fd(fd);
+ return -ENOMEM;
+ }
+
+ fd_install(fd, sync_file->file);
+ info->out.handle = fd;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
/**
* amdgpu_cs_wait_all_fence - wait on all fences to signal
*
@@ -1336,6 +1433,9 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
if (r == 0)
break;
+
+ if (fence->error)
+ return fence->error;
}
memset(wait, 0, sizeof(*wait));
@@ -1381,6 +1481,7 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
array[i] = fence;
} else { /* NULL, the fence has been already signaled */
r = 1;
+ first = i;
goto out;
}
}
@@ -1395,7 +1496,7 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
wait->out.status = (r > 0);
wait->out.first_signaled = first;
/* set return value 0 to indicate success */
- r = 0;
+ r = array[first]->error;
err_free_fence_array:
for (i = 0; i < fence_count; i++)
@@ -1416,15 +1517,12 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
struct amdgpu_device *adev = dev->dev_private;
- struct amdgpu_fpriv *fpriv = filp->driver_priv;
union drm_amdgpu_wait_fences *wait = data;
uint32_t fence_count = wait->in.fence_count;
struct drm_amdgpu_fence *fences_user;
struct drm_amdgpu_fence *fences;
int r;
- if (amdgpu_kms_vram_lost(adev, fpriv))
- return -ENODEV;
/* Get the fences from userspace */
fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
GFP_KERNEL);
@@ -1460,78 +1558,36 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
* virtual memory address. Returns allocation structure when found, NULL
* otherwise.
*/
-struct amdgpu_bo_va_mapping *
-amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
- uint64_t addr, struct amdgpu_bo **bo)
+int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
+ uint64_t addr, struct amdgpu_bo **bo,
+ struct amdgpu_bo_va_mapping **map)
{
+ struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
+ struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_bo_va_mapping *mapping;
- unsigned i;
-
- if (!parser->bo_list)
- return NULL;
+ int r;
addr /= AMDGPU_GPU_PAGE_SIZE;
- for (i = 0; i < parser->bo_list->num_entries; i++) {
- struct amdgpu_bo_list_entry *lobj;
+ mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
+ if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
+ return -EINVAL;
- lobj = &parser->bo_list->array[i];
- if (!lobj->bo_va)
- continue;
+ *bo = mapping->bo_va->base.bo;
+ *map = mapping;
- list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
- if (mapping->start > addr ||
- addr > mapping->last)
- continue;
+ /* Double check that the BO is reserved by this CS */
+ if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
+ return -EINVAL;
- *bo = lobj->bo_va->base.bo;
- return mapping;
- }
-
- list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
- if (mapping->start > addr ||
- addr > mapping->last)
- continue;
-
- *bo = lobj->bo_va->base.bo;
- return mapping;
- }
- }
-
- return NULL;
-}
-
-/**
- * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
- *
- * @parser: command submission parser context
- *
- * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
- */
-int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
-{
- unsigned i;
- int r;
-
- if (!parser->bo_list)
- return 0;
-
- for (i = 0; i < parser->bo_list->num_entries; i++) {
- struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
-
- r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
- if (unlikely(r))
- return r;
-
- if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
- continue;
-
- bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
- amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
- if (unlikely(r))
+ if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
+ (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
+ r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false,
+ false);
+ if (r)
return r;
}
- return 0;
+ return amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a11e443..c184468 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -23,13 +23,41 @@
*/
#include <drm/drmP.h>
+#include <drm/drm_auth.h>
#include "amdgpu.h"
+#include "amdgpu_sched.h"
-static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
+static int amdgpu_ctx_priority_permit(struct drm_file *filp,
+ enum amd_sched_priority priority)
+{
+ /* NORMAL and below are accessible by everyone */
+ if (priority <= AMD_SCHED_PRIORITY_NORMAL)
+ return 0;
+
+ if (capable(CAP_SYS_NICE))
+ return 0;
+
+ if (drm_is_current_master(filp))
+ return 0;
+
+ return -EACCES;
+}
+
+static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ enum amd_sched_priority priority,
+ struct drm_file *filp,
+ struct amdgpu_ctx *ctx)
{
unsigned i, j;
int r;
+ if (priority < 0 || priority >= AMD_SCHED_PRIORITY_MAX)
+ return -EINVAL;
+
+ r = amdgpu_ctx_priority_permit(filp, priority);
+ if (r)
+ return r;
+
memset(ctx, 0, sizeof(*ctx));
ctx->adev = adev;
kref_init(&ctx->refcount);
@@ -39,19 +67,24 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
if (!ctx->fences)
return -ENOMEM;
+ mutex_init(&ctx->lock);
+
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
ctx->rings[i].sequence = 1;
ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
}
ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
+ ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
+ ctx->init_priority = priority;
+ ctx->override_priority = AMD_SCHED_PRIORITY_UNSET;
/* create context entity for each ring */
for (i = 0; i < adev->num_rings; i++) {
struct amdgpu_ring *ring = adev->rings[i];
struct amd_sched_rq *rq;
- rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
+ rq = &ring->sched.sched_rq[priority];
if (ring == &adev->gfx.kiq.ring)
continue;
@@ -96,10 +129,14 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
&ctx->rings[i].entity);
amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
+
+ mutex_destroy(&ctx->lock);
}
static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv,
+ struct drm_file *filp,
+ enum amd_sched_priority priority,
uint32_t *id)
{
struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
@@ -117,8 +154,9 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
kfree(ctx);
return r;
}
+
*id = (uint32_t)r;
- r = amdgpu_ctx_init(adev, ctx);
+ r = amdgpu_ctx_init(adev, priority, filp, ctx);
if (r) {
idr_remove(&mgr->ctx_handles, *id);
*id = 0;
@@ -193,6 +231,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
{
int r;
uint32_t id;
+ enum amd_sched_priority priority;
union drm_amdgpu_ctx *args = data;
struct amdgpu_device *adev = dev->dev_private;
@@ -200,10 +239,16 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
r = 0;
id = args->in.ctx_id;
+ priority = amdgpu_to_sched_priority(args->in.priority);
+
+ /* For backwards compatibility reasons, we need to accept
+ * ioctls with garbage in the priority field */
+ if (priority == AMD_SCHED_PRIORITY_INVALID)
+ priority = AMD_SCHED_PRIORITY_NORMAL;
switch (args->in.op) {
case AMDGPU_CTX_OP_ALLOC_CTX:
- r = amdgpu_ctx_alloc(adev, fpriv, &id);
+ r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);
args->out.alloc.ctx_id = id;
break;
case AMDGPU_CTX_OP_FREE_CTX:
@@ -246,8 +291,8 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
return 0;
}
-uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
- struct dma_fence *fence)
+int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
+ struct dma_fence *fence, uint64_t* handler)
{
struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
uint64_t seq = cring->sequence;
@@ -256,12 +301,8 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
idx = seq & (amdgpu_sched_jobs - 1);
other = cring->fences[idx];
- if (other) {
- signed long r;
- r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
- if (r < 0)
- DRM_ERROR("Error (%ld) waiting for fence!\n", r);
- }
+ if (other)
+ BUG_ON(!dma_fence_is_signaled(other));
dma_fence_get(fence);
@@ -271,8 +312,10 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
spin_unlock(&ctx->ring_lock);
dma_fence_put(other);
+ if (handler)
+ *handler = seq;
- return seq;
+ return 0;
}
struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
@@ -303,6 +346,51 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
return fence;
}
+void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
+ enum amd_sched_priority priority)
+{
+ int i;
+ struct amdgpu_device *adev = ctx->adev;
+ struct amd_sched_rq *rq;
+ struct amd_sched_entity *entity;
+ struct amdgpu_ring *ring;
+ enum amd_sched_priority ctx_prio;
+
+ ctx->override_priority = priority;
+
+ ctx_prio = (ctx->override_priority == AMD_SCHED_PRIORITY_UNSET) ?
+ ctx->init_priority : ctx->override_priority;
+
+ for (i = 0; i < adev->num_rings; i++) {
+ ring = adev->rings[i];
+ entity = &ctx->rings[i].entity;
+ rq = &ring->sched.sched_rq[ctx_prio];
+
+ if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+ continue;
+
+ amd_sched_entity_set_rq(entity, rq);
+ }
+}
+
+int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id)
+{
+ struct amdgpu_ctx_ring *cring = &ctx->rings[ring_id];
+ unsigned idx = cring->sequence & (amdgpu_sched_jobs - 1);
+ struct dma_fence *other = cring->fences[idx];
+
+ if (other) {
+ signed long r;
+ r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
+ if (r < 0) {
+ DRM_ERROR("Error (%ld) waiting for fence!\n", r);
+ return r;
+ }
+ }
+
+ return 0;
+}
+
void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
{
mutex_init(&mgr->lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e630d91..efcacb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -56,6 +56,7 @@
#include "amdgpu_vf_error.h"
#include "amdgpu_amdkfd.h"
+#include "amdgpu_pm.h"
MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
@@ -65,6 +66,7 @@ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
+static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
static const char *amdgpu_asic_name[] = {
"TAHITI",
@@ -107,10 +109,8 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
{
uint32_t ret;
- if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
- BUG_ON(in_interrupt());
+ if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
return amdgpu_virt_kiq_rreg(adev, reg);
- }
if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
@@ -135,10 +135,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
adev->last_mm_index = v;
}
- if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
- BUG_ON(in_interrupt());
+ if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
return amdgpu_virt_kiq_wreg(adev, reg, v);
- }
if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
@@ -402,6 +400,15 @@ void amdgpu_pci_config_reset(struct amdgpu_device *adev)
*/
static int amdgpu_doorbell_init(struct amdgpu_device *adev)
{
+ /* No doorbell on SI hardware generation */
+ if (adev->asic_type < CHIP_BONAIRE) {
+ adev->doorbell.base = 0;
+ adev->doorbell.size = 0;
+ adev->doorbell.num_doorbells = 0;
+ adev->doorbell.ptr = NULL;
+ return 0;
+ }
+
/* doorbell bar mapping */
adev->doorbell.base = pci_resource_start(adev->pdev, 2);
adev->doorbell.size = pci_resource_len(adev->pdev, 2);
@@ -539,7 +546,7 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
if (offset < adev->wb.num_wb) {
__set_bit(offset, adev->wb.used);
- *wb = offset * 8; /* convert to dw offset */
+ *wb = offset << 3; /* convert to dw offset */
return 0;
} else {
return -EINVAL;
@@ -557,7 +564,7 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
{
if (wb < adev->wb.num_wb)
- __clear_bit(wb, adev->wb.used);
+ __clear_bit(wb >> 3, adev->wb.used);
}
/**
@@ -647,6 +654,81 @@ void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
}
/*
+ * Firmware Reservation functions
+ */
+/**
+ * amdgpu_fw_reserve_vram_fini - free fw reserved vram
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * free fw reserved vram if it has been reserved.
+ */
+void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
+{
+ amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
+ NULL, &adev->fw_vram_usage.va);
+}
+
+/**
+ * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * create bo vram reservation from fw.
+ */
+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
+{
+ int r = 0;
+ u64 gpu_addr;
+ u64 vram_size = adev->mc.visible_vram_size;
+
+ adev->fw_vram_usage.va = NULL;
+ adev->fw_vram_usage.reserved_bo = NULL;
+
+ if (adev->fw_vram_usage.size > 0 &&
+ adev->fw_vram_usage.size <= vram_size) {
+
+ r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
+ PAGE_SIZE, true, 0,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
+ &adev->fw_vram_usage.reserved_bo);
+ if (r)
+ goto error_create;
+
+ r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
+ if (r)
+ goto error_reserve;
+ r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ adev->fw_vram_usage.start_offset,
+ (adev->fw_vram_usage.start_offset +
+ adev->fw_vram_usage.size), &gpu_addr);
+ if (r)
+ goto error_pin;
+ r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
+ &adev->fw_vram_usage.va);
+ if (r)
+ goto error_kmap;
+
+ amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+ }
+ return r;
+
+error_kmap:
+ amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
+error_pin:
+ amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+error_reserve:
+ amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
+error_create:
+ adev->fw_vram_usage.va = NULL;
+ adev->fw_vram_usage.reserved_bo = NULL;
+ return r;
+}
+
+
+/*
* GPU helpers function.
*/
/**
@@ -662,27 +744,6 @@ bool amdgpu_need_post(struct amdgpu_device *adev)
{
uint32_t reg;
- if (adev->has_hw_reset) {
- adev->has_hw_reset = false;
- return true;
- }
-
- /* bios scratch used on CIK+ */
- if (adev->asic_type >= CHIP_BONAIRE)
- return amdgpu_atombios_scratch_need_asic_init(adev);
-
- /* check MEM_SIZE for older asics */
- reg = amdgpu_asic_get_config_memsize(adev);
-
- if ((reg != 0) && (reg != 0xffffffff))
- return false;
-
- return true;
-
-}
-
-static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
-{
if (amdgpu_sriov_vf(adev))
return false;
@@ -705,7 +766,23 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
return true;
}
}
- return amdgpu_need_post(adev);
+
+ if (adev->has_hw_reset) {
+ adev->has_hw_reset = false;
+ return true;
+ }
+
+ /* bios scratch used on CIK+ */
+ if (adev->asic_type >= CHIP_BONAIRE)
+ return amdgpu_atombios_scratch_need_asic_init(adev);
+
+ /* check MEM_SIZE for older asics */
+ reg = amdgpu_asic_get_config_memsize(adev);
+
+ if ((reg != 0) && (reg != 0xffffffff))
+ return false;
+
+ return true;
}
/**
@@ -887,6 +964,20 @@ static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
return r;
}
+static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+ struct atom_context *ctx = adev->mode_info.atom_context;
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
+}
+
+static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
+ NULL);
+
/**
* amdgpu_atombios_fini - free the driver info and callbacks for atombios
*
@@ -906,6 +997,7 @@ static void amdgpu_atombios_fini(struct amdgpu_device *adev)
adev->mode_info.atom_context = NULL;
kfree(adev->mode_info.atom_card_info);
adev->mode_info.atom_card_info = NULL;
+ device_remove_file(adev->dev, &dev_attr_vbios_version);
}
/**
@@ -922,6 +1014,7 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev)
{
struct card_info *atom_card_info =
kzalloc(sizeof(struct card_info), GFP_KERNEL);
+ int ret;
if (!atom_card_info)
return -ENOMEM;
@@ -958,6 +1051,13 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev)
amdgpu_atombios_scratch_regs_init(adev);
amdgpu_atombios_allocate_fb_scratch(adev);
}
+
+ ret = device_create_file(adev->dev, &dev_attr_vbios_version);
+ if (ret) {
+ DRM_ERROR("Failed to create device file for VBIOS version\n");
+ return ret;
+ }
+
return 0;
}
@@ -1757,10 +1857,8 @@ static int amdgpu_fini(struct amdgpu_device *adev)
adev->ip_blocks[i].status.late_initialized = false;
}
- if (amdgpu_sriov_vf(adev)) {
- amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
+ if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, false);
- }
return 0;
}
@@ -1848,6 +1946,7 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
static enum amd_ip_block_type ip_order[] = {
AMD_IP_BLOCK_TYPE_SMC,
+ AMD_IP_BLOCK_TYPE_PSP,
AMD_IP_BLOCK_TYPE_DCE,
AMD_IP_BLOCK_TYPE_GFX,
AMD_IP_BLOCK_TYPE_SDMA,
@@ -1933,12 +2032,17 @@ static int amdgpu_resume(struct amdgpu_device *adev)
static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
{
- if (adev->is_atom_fw) {
- if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
- adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
- } else {
- if (amdgpu_atombios_has_gpu_virtualization_table(adev))
- adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
+ if (amdgpu_sriov_vf(adev)) {
+ if (adev->is_atom_fw) {
+ if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
+ adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
+ } else {
+ if (amdgpu_atombios_has_gpu_virtualization_table(adev))
+ adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
+ }
+
+ if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
}
}
@@ -1979,6 +2083,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->vm_manager.vm_pte_num_rings = 0;
adev->gart.gart_funcs = NULL;
adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
+ bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
adev->smc_rreg = &amdgpu_invalid_rreg;
adev->smc_wreg = &amdgpu_invalid_wreg;
@@ -2007,8 +2112,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(&adev->pm.mutex);
mutex_init(&adev->gfx.gpu_clock_mutex);
mutex_init(&adev->srbm_mutex);
+ mutex_init(&adev->gfx.pipe_reserve_mutex);
mutex_init(&adev->grbm_idx_mutex);
mutex_init(&adev->mn_lock);
+ mutex_init(&adev->virt.vf_errors.lock);
hash_init(adev->mn_hash);
amdgpu_check_arguments(adev);
@@ -2051,9 +2158,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
- if (adev->asic_type >= CHIP_BONAIRE)
- /* doorbell bar mapping */
- amdgpu_doorbell_init(adev);
+ /* doorbell bar mapping */
+ amdgpu_doorbell_init(adev);
/* io port mapping */
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
@@ -2095,7 +2201,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atombios_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_atombios_init failed\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
goto failed;
}
@@ -2103,10 +2209,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_device_detect_sriov_bios(adev);
/* Post card if necessary */
- if (amdgpu_vpost_needed(adev)) {
+ if (amdgpu_need_post(adev)) {
if (!adev->bios) {
dev_err(adev->dev, "no vBIOS found\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
r = -EINVAL;
goto failed;
}
@@ -2114,7 +2219,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
if (r) {
dev_err(adev->dev, "gpu post error!\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0);
goto failed;
}
} else {
@@ -2126,7 +2230,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atomfirmware_get_clock_info(adev);
if (r) {
dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
goto failed;
}
} else {
@@ -2134,7 +2238,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atombios_get_clock_info(adev);
if (r) {
dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
goto failed;
}
/* init i2c buses */
@@ -2145,7 +2249,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_fence_driver_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
goto failed;
}
@@ -2155,7 +2259,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_init failed\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
amdgpu_fini(adev);
goto failed;
}
@@ -2175,7 +2279,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
goto failed;
}
@@ -2183,8 +2287,15 @@ int amdgpu_device_init(struct amdgpu_device *adev,
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_init_data_exchange(adev);
+
amdgpu_fbdev_init(adev);
+ r = amdgpu_pm_sysfs_init(adev);
+ if (r)
+ DRM_ERROR("registering pm debugfs failed (%d).\n", r);
+
r = amdgpu_gem_debugfs_init(adev);
if (r)
DRM_ERROR("registering gem debugfs failed (%d).\n", r);
@@ -2201,6 +2312,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
if (r)
DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
+ r = amdgpu_debugfs_vbios_dump_init(adev);
+ if (r)
+ DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);
+
if ((amdgpu_testing & 1)) {
if (adev->accel_working)
amdgpu_test_moves(adev);
@@ -2220,7 +2335,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_late_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_late_init failed\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
goto failed;
}
@@ -2252,6 +2367,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
/* evict vram memory */
amdgpu_bo_evict_vram(adev);
amdgpu_ib_pool_fini(adev);
+ amdgpu_fw_reserve_vram_fini(adev);
amdgpu_fence_driver_fini(adev);
amdgpu_fbdev_fini(adev);
r = amdgpu_fini(adev);
@@ -2276,8 +2392,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
adev->rio_mem = NULL;
iounmap(adev->rmmio);
adev->rmmio = NULL;
- if (adev->asic_type >= CHIP_BONAIRE)
- amdgpu_doorbell_fini(adev);
+ amdgpu_doorbell_fini(adev);
+ amdgpu_pm_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
}
@@ -2504,6 +2620,9 @@ static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
int i;
bool asic_hang = false;
+ if (amdgpu_sriov_vf(adev))
+ return true;
+
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
continue;
@@ -2546,7 +2665,8 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
- (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
+ (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
if (adev->ip_blocks[i].status.hang) {
DRM_INFO("Some block need full reset!\n");
return true;
@@ -2654,7 +2774,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
mutex_lock(&adev->virt.lock_reset);
atomic_inc(&adev->gpu_reset_counter);
- adev->gfx.in_reset = true;
+ adev->in_sriov_reset = true;
/* block TTM */
resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
@@ -2765,7 +2885,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
dev_info(adev->dev, "GPU reset successed!\n");
}
- adev->gfx.in_reset = false;
+ adev->in_sriov_reset = false;
mutex_unlock(&adev->virt.lock_reset);
return r;
}
@@ -2902,7 +3022,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
}
} else {
dev_err(adev->dev, "asic resume failed (%d).\n", r);
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r);
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
if (adev->rings[i] && adev->rings[i]->sched.thread) {
kthread_unpark(adev->rings[i]->sched.thread);
@@ -2916,7 +3035,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
if (r) {
/* bad news, how to tell it to userspace ? */
dev_info(adev->dev, "GPU reset failed\n");
- amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
}
else {
dev_info(adev->dev, "GPU reset successed!\n");
@@ -3463,10 +3581,7 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
valuesize = sizeof(values);
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
- r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
- else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
- r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
- &valuesize);
+ r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
else
return -EINVAL;
@@ -3754,6 +3869,28 @@ int amdgpu_debugfs_init(struct drm_minor *minor)
{
return 0;
}
+
+static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+
+ seq_write(m, adev->bios, adev->bios_size);
+ return 0;
+}
+
+static const struct drm_info_list amdgpu_vbios_dump_list[] = {
+ {"amdgpu_vbios",
+ amdgpu_debugfs_get_vbios_dump,
+ 0, NULL},
+};
+
+static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
+{
+ return amdgpu_debugfs_add_files(adev,
+ amdgpu_vbios_dump_list, 1);
+}
#else
static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
{
@@ -3763,5 +3900,9 @@ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
{
return 0;
}
+static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
+{
+ return 0;
+}
static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 1cb52fd..e997ebbe43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -960,8 +960,10 @@ u8 amdgpu_encode_pci_lane_width(u32 lanes)
}
struct amd_vce_state*
-amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx)
+amdgpu_get_vce_clock_state(void *handle, u32 idx)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (idx < adev->pm.dpm.num_of_vce_states)
return &adev->pm.dpm.vce_states[idx];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 8c96a4c..7279fb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -241,179 +241,125 @@ enum amdgpu_pcie_gen {
AMDGPU_PCIE_GEN_INVALID = 0xffff
};
-struct amdgpu_dpm_funcs {
- int (*get_temperature)(struct amdgpu_device *adev);
- int (*pre_set_power_state)(struct amdgpu_device *adev);
- int (*set_power_state)(struct amdgpu_device *adev);
- void (*post_set_power_state)(struct amdgpu_device *adev);
- void (*display_configuration_changed)(struct amdgpu_device *adev);
- u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
- u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
- void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
- void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
- int (*force_performance_level)(struct amdgpu_device *adev, enum amd_dpm_forced_level level);
- bool (*vblank_too_short)(struct amdgpu_device *adev);
- void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
- void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
- void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
- void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
- u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
- int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
- int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
- int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
- int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
- int (*get_sclk_od)(struct amdgpu_device *adev);
- int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
- int (*get_mclk_od)(struct amdgpu_device *adev);
- int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
- int (*check_state_equal)(struct amdgpu_device *adev,
- struct amdgpu_ps *cps,
- struct amdgpu_ps *rps,
- bool *equal);
- int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value,
- int *size);
+#define amdgpu_dpm_pre_set_power_state(adev) \
+ ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
- struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx);
- int (*reset_power_profile_state)(struct amdgpu_device *adev,
- struct amd_pp_profile *request);
- int (*get_power_profile_state)(struct amdgpu_device *adev,
- struct amd_pp_profile *query);
- int (*set_power_profile_state)(struct amdgpu_device *adev,
- struct amd_pp_profile *request);
- int (*switch_power_profile)(struct amdgpu_device *adev,
- enum amd_pp_profile_type type);
-};
+#define amdgpu_dpm_set_power_state(adev) \
+ ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
-#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
-#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
-#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
-#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
-#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
-#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
-#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
+#define amdgpu_dpm_post_set_power_state(adev) \
+ ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
+
+#define amdgpu_dpm_display_configuration_changed(adev) \
+ ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
+
+#define amdgpu_dpm_print_power_state(adev, ps) \
+ ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
+
+#define amdgpu_dpm_vblank_too_short(adev) \
+ ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
+
+#define amdgpu_dpm_enable_bapm(adev, e) \
+ ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
#define amdgpu_dpm_read_sensor(adev, idx, value, size) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value), (size)) : \
- (adev)->pm.funcs->read_sensor((adev), (idx), (value), (size)))
+ ((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
#define amdgpu_dpm_get_temperature(adev) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
- (adev)->pm.funcs->get_temperature((adev)))
+ ((adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle))
#define amdgpu_dpm_set_fan_control_mode(adev, m) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
- (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
+ ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
#define amdgpu_dpm_get_fan_control_mode(adev) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
- (adev)->pm.funcs->get_fan_control_mode((adev)))
+ ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
- (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
+ ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
- (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
+ ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \
- -EINVAL)
+ ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
#define amdgpu_dpm_get_sclk(adev, l) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
- (adev)->pm.funcs->get_sclk((adev), (l)))
+ ((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
#define amdgpu_dpm_get_mclk(adev, l) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
- (adev)->pm.funcs->get_mclk((adev), (l)))
-
+ ((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
#define amdgpu_dpm_force_performance_level(adev, l) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
- (adev)->pm.funcs->force_performance_level((adev), (l)))
+ ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
#define amdgpu_dpm_powergate_uvd(adev, g) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
- (adev)->pm.funcs->powergate_uvd((adev), (g)))
+ ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
#define amdgpu_dpm_powergate_vce(adev, g) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
- (adev)->pm.funcs->powergate_vce((adev), (g)))
+ ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
#define amdgpu_dpm_get_current_power_state(adev) \
- (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
+ ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
#define amdgpu_dpm_get_pp_num_states(adev, data) \
- (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
+ ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
#define amdgpu_dpm_get_pp_table(adev, table) \
- (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
+ ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
#define amdgpu_dpm_set_pp_table(adev, buf, size) \
- (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
+ ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
- (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
+ ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
#define amdgpu_dpm_force_clock_level(adev, type, level) \
- (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
+ ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
#define amdgpu_dpm_get_sclk_od(adev) \
- (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
+ ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
#define amdgpu_dpm_set_sclk_od(adev, value) \
- (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
+ ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
#define amdgpu_dpm_get_mclk_od(adev) \
- ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
+ ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
#define amdgpu_dpm_set_mclk_od(adev, value) \
- ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
+ ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
-#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
- (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
+#define amdgpu_dpm_dispatch_task(adev, task_id, input, output) \
+ ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output))
-#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal))
+#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
+ ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
#define amdgpu_dpm_get_vce_clock_state(adev, i) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
- (adev)->pm.funcs->get_vce_clock_state((adev), (i)))
+ ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
-#define amdgpu_dpm_get_performance_level(adev) \
- ((adev)->pp_enabled ? \
- (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) : \
- (adev)->pm.dpm.forced_level)
+#define amdgpu_dpm_get_performance_level(adev) \
+ ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
#define amdgpu_dpm_reset_power_profile_state(adev, request) \
- ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
+ ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
(adev)->powerplay.pp_handle, request))
#define amdgpu_dpm_get_power_profile_state(adev, query) \
- ((adev)->powerplay.pp_funcs->get_power_profile_state(\
+ ((adev)->powerplay.pp_funcs->get_power_profile_state(\
(adev)->powerplay.pp_handle, query))
#define amdgpu_dpm_set_power_profile_state(adev, request) \
- ((adev)->powerplay.pp_funcs->set_power_profile_state(\
+ ((adev)->powerplay.pp_funcs->set_power_profile_state(\
(adev)->powerplay.pp_handle, request))
#define amdgpu_dpm_switch_power_profile(adev, type) \
- ((adev)->powerplay.pp_funcs->switch_power_profile(\
+ ((adev)->powerplay.pp_funcs->switch_power_profile(\
(adev)->powerplay.pp_handle, type))
+#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
+ ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
+ (adev)->powerplay.pp_handle, msg_id))
+
struct amdgpu_dpm {
struct amdgpu_ps *ps;
/* number of valid power states */
@@ -485,7 +431,6 @@ struct amdgpu_pm {
struct amdgpu_dpm dpm;
const struct firmware *fw; /* SMC firmware */
uint32_t fw_version;
- const struct amdgpu_dpm_funcs *funcs;
uint32_t pcie_gen_mask;
uint32_t pcie_mlw_mask;
struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
@@ -551,6 +496,6 @@ u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
u8 amdgpu_encode_pci_lane_width(u32 lanes);
struct amd_vce_state*
-amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx);
+amdgpu_get_vce_clock_state(void *handle, u32 idx);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0f16986..dd2f060 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -69,9 +69,13 @@
* - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
* - 3.18.0 - Export gpu always on cu bitmap
* - 3.19.0 - Add support for UVD MJPEG decode
+ * - 3.20.0 - Add support for local BOs
+ * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
+ * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
+ * - 3.23.0 - Add query for VRAM lost counter
*/
#define KMS_DRIVER_MAJOR 3
-#define KMS_DRIVER_MINOR 19
+#define KMS_DRIVER_MINOR 23
#define KMS_DRIVER_PATCHLEVEL 0
int amdgpu_vram_limit = 0;
@@ -91,7 +95,7 @@ int amdgpu_dpm = -1;
int amdgpu_fw_load_type = -1;
int amdgpu_aspm = -1;
int amdgpu_runtime_pm = -1;
-unsigned amdgpu_ip_block_mask = 0xffffffff;
+uint amdgpu_ip_block_mask = 0xffffffff;
int amdgpu_bapm = -1;
int amdgpu_deep_color = 0;
int amdgpu_vm_size = -1;
@@ -106,14 +110,14 @@ int amdgpu_sched_jobs = 32;
int amdgpu_sched_hw_submission = 2;
int amdgpu_no_evict = 0;
int amdgpu_direct_gma_size = 0;
-unsigned amdgpu_pcie_gen_cap = 0;
-unsigned amdgpu_pcie_lane_cap = 0;
-unsigned amdgpu_cg_mask = 0xffffffff;
-unsigned amdgpu_pg_mask = 0xffffffff;
-unsigned amdgpu_sdma_phase_quantum = 32;
+uint amdgpu_pcie_gen_cap = 0;
+uint amdgpu_pcie_lane_cap = 0;
+uint amdgpu_cg_mask = 0xffffffff;
+uint amdgpu_pg_mask = 0xffffffff;
+uint amdgpu_sdma_phase_quantum = 32;
char *amdgpu_disable_cu = NULL;
char *amdgpu_virtual_display = NULL;
-unsigned amdgpu_pp_feature_mask = 0xffffffff;
+uint amdgpu_pp_feature_mask = 0xffffffff;
int amdgpu_ngg = 0;
int amdgpu_prim_buf_per_se = 0;
int amdgpu_pos_buf_per_se = 0;
@@ -121,6 +125,7 @@ int amdgpu_cntl_sb_buf_per_se = 0;
int amdgpu_param_buf_per_se = 0;
int amdgpu_job_hang_limit = 0;
int amdgpu_lbpw = -1;
+int amdgpu_compute_multipipe = -1;
MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -264,6 +269,9 @@ module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(lbpw, amdgpu_lbpw, int, 0444);
+MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
+module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
+
#ifdef CONFIG_DRM_AMDGPU_SI
#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
@@ -608,6 +616,8 @@ amdgpu_pci_remove(struct pci_dev *pdev)
drm_dev_unregister(dev);
drm_dev_unref(dev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
}
static void
@@ -852,6 +862,7 @@ static struct drm_driver kms_driver = {
.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
.gem_prime_vmap = amdgpu_gem_prime_vmap,
.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
+ .gem_prime_mmap = amdgpu_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 9afa9c0..562930b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -149,7 +149,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_VRAM_CLEARED,
- true, &gobj);
+ true, NULL, &gobj);
if (ret) {
pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
return -ENOMEM;
@@ -303,10 +303,10 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb
if (rfb->obj) {
amdgpufb_destroy_pinned_object(rfb->obj);
rfb->obj = NULL;
+ drm_framebuffer_unregister_private(&rfb->base);
+ drm_framebuffer_cleanup(&rfb->base);
}
drm_fb_helper_fini(&rfbdev->helper);
- drm_framebuffer_unregister_private(&rfb->base);
- drm_framebuffer_cleanup(&rfb->base);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 303b5e0..bd5b806 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -169,6 +169,32 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f)
}
/**
+ * amdgpu_fence_emit_polling - emit a fence on the requeste ring
+ *
+ * @ring: ring the fence is associated with
+ * @s: resulting sequence number
+ *
+ * Emits a fence command on the requested ring (all asics).
+ * Used For polling fence.
+ * Returns 0 on success, -ENOMEM on failure.
+ */
+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
+{
+ uint32_t seq;
+
+ if (!s)
+ return -EINVAL;
+
+ seq = ++ring->fence_drv.sync_seq;
+ amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
+ seq, AMDGPU_FENCE_FLAG_INT);
+
+ *s = seq;
+
+ return 0;
+}
+
+/**
* amdgpu_fence_schedule_fallback - schedule fallback check
*
* @ring: pointer to struct amdgpu_ring
@@ -282,6 +308,30 @@ int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
}
/**
+ * amdgpu_fence_wait_polling - busy wait for givn sequence number
+ *
+ * @ring: ring index the fence is associated with
+ * @wait_seq: sequence number to wait
+ * @timeout: the timeout for waiting in usecs
+ *
+ * Wait for all fences on the requested ring to signal (all asics).
+ * Returns left time if no timeout, 0 or minus if timeout.
+ */
+signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
+ uint32_t wait_seq,
+ signed long timeout)
+{
+ uint32_t seq;
+
+ do {
+ seq = amdgpu_fence_read(ring);
+ udelay(5);
+ timeout -= 5;
+ } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
+
+ return timeout > 0 ? timeout : 0;
+}
+/**
* amdgpu_fence_count_emitted - get the count of emitted fences
*
* @ring: ring the fence is associated with
@@ -641,6 +691,19 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
atomic_read(&ring->fence_drv.last_seq));
seq_printf(m, "Last emitted 0x%08x\n",
ring->fence_drv.sync_seq);
+
+ if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
+ continue;
+
+ /* set in CP_VMID_PREEMPT and preemption occurred */
+ seq_printf(m, "Last preempted 0x%08x\n",
+ le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
+ /* set in CP_VMID_RESET and reset occurred */
+ seq_printf(m, "Last reset 0x%08x\n",
+ le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
+ /* Both preemption and reset occurred */
+ seq_printf(m, "Last both 0x%08x\n",
+ le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
}
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index f437008..fe81850 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -332,12 +332,13 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
adev->gart.pages[p] = pagelist[i];
#endif
- if (adev->gart.ptr) {
- r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
- adev->gart.ptr);
- if (r)
- return r;
- }
+ if (!adev->gart.ptr)
+ return 0;
+
+ r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
+ adev->gart.ptr);
+ if (r)
+ return r;
mb();
amdgpu_gart_flush_gpu_tlb(adev, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 0bda8f2..a418df1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -44,11 +44,12 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj)
}
int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
- int alignment, u32 initial_domain,
- u64 flags, bool kernel,
- struct drm_gem_object **obj)
+ int alignment, u32 initial_domain,
+ u64 flags, bool kernel,
+ struct reservation_object *resv,
+ struct drm_gem_object **obj)
{
- struct amdgpu_bo *robj;
+ struct amdgpu_bo *bo;
int r;
*obj = NULL;
@@ -59,7 +60,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
retry:
r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
- flags, NULL, NULL, 0, &robj);
+ flags, NULL, resv, 0, &bo);
if (r) {
if (r != -ERESTARTSYS) {
if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
@@ -71,7 +72,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
}
return r;
}
- *obj = &robj->gem_base;
+ *obj = &bo->gem_base;
return 0;
}
@@ -112,7 +113,17 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj,
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_bo_va *bo_va;
+ struct mm_struct *mm;
int r;
+
+ mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
+ if (mm && mm != current->mm)
+ return -EPERM;
+
+ if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
+ abo->tbo.resv != vm->root.base.bo->tbo.resv)
+ return -EPERM;
+
r = amdgpu_bo_reserve(abo, false);
if (r)
return r;
@@ -127,35 +138,6 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj,
return 0;
}
-static int amdgpu_gem_vm_check(void *param, struct amdgpu_bo *bo)
-{
- /* if anything is swapped out don't swap it in here,
- just abort and wait for the next CS */
- if (!amdgpu_bo_gpu_accessible(bo))
- return -ERESTARTSYS;
-
- if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
- return -ERESTARTSYS;
-
- return 0;
-}
-
-static bool amdgpu_gem_vm_ready(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct list_head *list)
-{
- struct ttm_validate_buffer *entry;
-
- list_for_each_entry(entry, list, head) {
- struct amdgpu_bo *bo =
- container_of(entry->bo, struct amdgpu_bo, tbo);
- if (amdgpu_gem_vm_check(NULL, bo))
- return false;
- }
-
- return !amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_vm_check, NULL);
-}
-
void amdgpu_gem_object_close(struct drm_gem_object *obj,
struct drm_file *file_priv)
{
@@ -165,13 +147,14 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_bo_list_entry vm_pd;
- struct list_head list;
+ struct list_head list, duplicates;
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct amdgpu_bo_va *bo_va;
int r;
INIT_LIST_HEAD(&list);
+ INIT_LIST_HEAD(&duplicates);
tv.bo = &bo->tbo;
tv.shared = true;
@@ -179,7 +162,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
- r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
+ r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
if (r) {
dev_err(adev->dev, "leaking bo va because "
"we fail to reserve bo (%d)\n", r);
@@ -189,7 +172,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
if (bo_va && --bo_va->ref_count == 0) {
amdgpu_vm_bo_rmv(adev, bo_va);
- if (amdgpu_gem_vm_ready(adev, vm, &list)) {
+ if (amdgpu_vm_ready(vm)) {
struct dma_fence *fence = NULL;
r = amdgpu_vm_clear_freed(adev, vm, &fence);
@@ -214,18 +197,24 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
struct amdgpu_device *adev = dev->dev_private;
+ struct amdgpu_fpriv *fpriv = filp->driver_priv;
+ struct amdgpu_vm *vm = &fpriv->vm;
union drm_amdgpu_gem_create *args = data;
+ uint64_t flags = args->in.domain_flags;
uint64_t size = args->in.bo_size;
+ struct reservation_object *resv = NULL;
struct drm_gem_object *gobj;
uint32_t handle;
- bool kernel = false;
int r;
/* reject invalid gem flags */
- if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
- AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
- AMDGPU_GEM_CREATE_CPU_GTT_USWC |
- AMDGPU_GEM_CREATE_VRAM_CLEARED))
+ if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+ AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+ AMDGPU_GEM_CREATE_CPU_GTT_USWC |
+ AMDGPU_GEM_CREATE_VRAM_CLEARED |
+ AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
+ AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+
return -EINVAL;
/* reject invalid gem domains */
@@ -240,7 +229,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
/* create a gem object to contain this object in */
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
- kernel = true;
+ flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
size = size << AMDGPU_GDS_SHIFT;
else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
@@ -252,10 +241,25 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
}
size = roundup(size, PAGE_SIZE);
+ if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
+ r = amdgpu_bo_reserve(vm->root.base.bo, false);
+ if (r)
+ return r;
+
+ resv = vm->root.base.bo->tbo.resv;
+ }
+
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
(u32)(0xffffffff & args->in.domains),
- args->in.domain_flags,
- kernel, &gobj);
+ flags, false, resv, &gobj);
+ if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
+ if (!r) {
+ struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
+
+ abo->parent = amdgpu_bo_ref(vm->root.base.bo);
+ }
+ amdgpu_bo_unreserve(vm->root.base.bo);
+ }
if (r)
return r;
@@ -297,9 +301,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
}
/* create a gem object to contain this object in */
- r = amdgpu_gem_object_create(adev, args->size, 0,
- AMDGPU_GEM_DOMAIN_CPU, 0,
- 0, &gobj);
+ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
+ 0, 0, NULL, &gobj);
if (r)
return r;
@@ -317,8 +320,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
}
if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
- down_read(¤t->mm->mmap_sem);
-
r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
bo->tbo.ttm->pages);
if (r)
@@ -333,8 +334,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
amdgpu_bo_unreserve(bo);
if (r)
goto free_pages;
-
- up_read(¤t->mm->mmap_sem);
}
r = drm_gem_handle_create(filp, gobj, &handle);
@@ -511,10 +510,10 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
struct list_head *list,
uint32_t operation)
{
- int r = -ERESTARTSYS;
+ int r;
- if (!amdgpu_gem_vm_ready(adev, vm, list))
- goto error;
+ if (!amdgpu_vm_ready(vm))
+ return;
r = amdgpu_vm_update_directories(adev, vm);
if (r)
@@ -551,7 +550,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct amdgpu_bo_list_entry vm_pd;
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
- struct list_head list;
+ struct list_head list, duplicates;
uint64_t va_flags;
int r = 0;
@@ -580,13 +579,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->operation);
return -EINVAL;
}
- if ((args->operation == AMDGPU_VA_OP_MAP) ||
- (args->operation == AMDGPU_VA_OP_REPLACE)) {
- if (amdgpu_kms_vram_lost(adev, fpriv))
- return -ENODEV;
- }
INIT_LIST_HEAD(&list);
+ INIT_LIST_HEAD(&duplicates);
if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
!(args->flags & AMDGPU_VM_PAGE_PRT)) {
gobj = drm_gem_object_lookup(filp, args->handle);
@@ -603,7 +598,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
- r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
+ r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
if (r)
goto error_unref;
@@ -669,6 +664,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
+ struct amdgpu_device *adev = dev->dev_private;
struct drm_amdgpu_gem_op *args = data;
struct drm_gem_object *gobj;
struct amdgpu_bo *robj;
@@ -716,6 +712,9 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
+ if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
+ amdgpu_vm_bo_invalidate(adev, robj, true);
+
amdgpu_bo_unreserve(robj);
break;
default:
@@ -745,8 +744,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
r = amdgpu_gem_object_create(adev, args->size, 0,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
- ttm_bo_type_device,
- &gobj);
+ false, NULL, &gobj);
if (r)
return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 4f6c68f..ef04336 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -109,9 +109,26 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_s
}
}
+static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
+{
+ if (amdgpu_compute_multipipe != -1) {
+ DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
+ amdgpu_compute_multipipe);
+ return amdgpu_compute_multipipe == 1;
+ }
+
+ /* FIXME: spreading the queues across pipes causes perf regressions
+ * on POLARIS11 compute workloads */
+ if (adev->asic_type == CHIP_POLARIS11)
+ return false;
+
+ return adev->gfx.mec.num_mec > 1;
+}
+
void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
{
int i, queue, pipe, mec;
+ bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
/* policy for amdgpu compute queue ownership */
for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
@@ -125,8 +142,7 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
if (mec >= adev->gfx.mec.num_mec)
break;
- /* FIXME: spreading the queues across pipes causes perf regressions */
- if (0) {
+ if (multipipe_policy) {
/* policy: amdgpu owns the first two queues of the first MEC */
if (mec == 0 && queue < 2)
set_bit(i, adev->gfx.mec.queue_bitmap);
@@ -185,7 +201,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
struct amdgpu_kiq *kiq = &adev->gfx.kiq;
int r = 0;
- mutex_init(&kiq->ring_mutex);
+ spin_lock_init(&kiq->ring_lock);
r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
if (r)
@@ -260,8 +276,13 @@ int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
/* create MQD for KIQ */
ring = &adev->gfx.kiq.ring;
if (!ring->mqd_obj) {
+ /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
+ * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
+ * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
+ * KIQ MQD no matter SRIOV or Bare-metal
+ */
r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
+ AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
&ring->mqd_gpu_addr, &ring->mqd_ptr);
if (r) {
dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 0d15eb7..33535d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -169,7 +169,8 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
int r;
spin_lock(&mgr->lock);
- if (atomic64_read(&mgr->available) < mem->num_pages) {
+ if ((&tbo->mem == mem || tbo->mem.mem_type != TTM_PL_TT) &&
+ atomic64_read(&mgr->available) < mem->num_pages) {
spin_unlock(&mgr->lock);
return 0;
}
@@ -244,8 +245,9 @@ static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man,
uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man)
{
struct amdgpu_gtt_mgr *mgr = man->priv;
+ s64 result = man->size - atomic64_read(&mgr->available);
- return (u64)(man->size - atomic64_read(&mgr->available)) * PAGE_SIZE;
+ return (result > 0 ? result : 0) * PAGE_SIZE;
}
/**
@@ -265,7 +267,7 @@ static void amdgpu_gtt_mgr_debug(struct ttm_mem_type_manager *man,
drm_mm_print(&mgr->mm, printer);
spin_unlock(&mgr->lock);
- drm_printf(printer, "man size:%llu pages, gtt available:%llu pages, usage:%lluMB\n",
+ drm_printf(printer, "man size:%llu pages, gtt available:%lld pages, usage:%lluMB\n",
man->size, (u64)atomic64_read(&mgr->available),
amdgpu_gtt_mgr_usage(man) >> 20);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 3ab4c65..f5f27e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -169,6 +169,12 @@ int amdgpu_ih_process(struct amdgpu_device *adev)
while (adev->irq.ih.rptr != wptr) {
u32 ring_index = adev->irq.ih.rptr >> 2;
+ /* Prescreening of high-frequency interrupts */
+ if (!amdgpu_ih_prescreen_iv(adev)) {
+ adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
+ continue;
+ }
+
/* Before dispatching irq to IP blocks, send it to amdkfd */
amdgpu_amdkfd_interrupt(adev,
(const void *) &adev->irq.ih.ring[ring_index]);
@@ -190,3 +196,79 @@ int amdgpu_ih_process(struct amdgpu_device *adev)
return IRQ_HANDLED;
}
+
+/**
+ * amdgpu_ih_add_fault - Add a page fault record
+ *
+ * @adev: amdgpu device pointer
+ * @key: 64-bit encoding of PASID and address
+ *
+ * This should be called when a retry page fault interrupt is
+ * received. If this is a new page fault, it will be added to a hash
+ * table. The return value indicates whether this is a new fault, or
+ * a fault that was already known and is already being handled.
+ *
+ * If there are too many pending page faults, this will fail. Retry
+ * interrupts should be ignored in this case until there is enough
+ * free space.
+ *
+ * Returns 0 if the fault was added, 1 if the fault was already known,
+ * -ENOSPC if there are too many pending faults.
+ */
+int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key)
+{
+ unsigned long flags;
+ int r = -ENOSPC;
+
+ if (WARN_ON_ONCE(!adev->irq.ih.faults))
+ /* Should be allocated in <IP>_ih_sw_init on GPUs that
+ * support retry faults and require retry filtering.
+ */
+ return r;
+
+ spin_lock_irqsave(&adev->irq.ih.faults->lock, flags);
+
+ /* Only let the hash table fill up to 50% for best performance */
+ if (adev->irq.ih.faults->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1)))
+ goto unlock_out;
+
+ r = chash_table_copy_in(&adev->irq.ih.faults->hash, key, NULL);
+ if (!r)
+ adev->irq.ih.faults->count++;
+
+ /* chash_table_copy_in should never fail unless we're losing count */
+ WARN_ON_ONCE(r < 0);
+
+unlock_out:
+ spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags);
+ return r;
+}
+
+/**
+ * amdgpu_ih_clear_fault - Remove a page fault record
+ *
+ * @adev: amdgpu device pointer
+ * @key: 64-bit encoding of PASID and address
+ *
+ * This should be called when a page fault has been handled. Any
+ * future interrupt with this key will be processed as a new
+ * page fault.
+ */
+void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key)
+{
+ unsigned long flags;
+ int r;
+
+ if (!adev->irq.ih.faults)
+ return;
+
+ spin_lock_irqsave(&adev->irq.ih.faults->lock, flags);
+
+ r = chash_table_remove(&adev->irq.ih.faults->hash, key, NULL);
+ if (!WARN_ON_ONCE(r < 0)) {
+ adev->irq.ih.faults->count--;
+ WARN_ON_ONCE(adev->irq.ih.faults->count < 0);
+ }
+
+ spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 3de8e74..ada89358 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -24,6 +24,8 @@
#ifndef __AMDGPU_IH_H__
#define __AMDGPU_IH_H__
+#include <linux/chash.h>
+
struct amdgpu_device;
/*
* vega10+ IH clients
@@ -69,6 +71,13 @@ enum amdgpu_ih_clientid
#define AMDGPU_IH_CLIENTID_LEGACY 0
+#define AMDGPU_PAGEFAULT_HASH_BITS 8
+struct amdgpu_retryfault_hashtable {
+ DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
+ spinlock_t lock;
+ int count;
+};
+
/*
* R6xx+ IH ring
*/
@@ -87,6 +96,7 @@ struct amdgpu_ih_ring {
bool use_doorbell;
bool use_bus_addr;
dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
+ struct amdgpu_retryfault_hashtable *faults;
};
#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
@@ -109,5 +119,7 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
bool use_bus_addr);
void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
int amdgpu_ih_process(struct amdgpu_device *adev);
+int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key);
+void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 4510627..0cfc68d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -65,6 +65,7 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
amdgpu_sync_create(&(*job)->sync);
amdgpu_sync_create(&(*job)->dep_sync);
amdgpu_sync_create(&(*job)->sched_sync);
+ (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
return 0;
}
@@ -103,6 +104,7 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job)
{
struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
+ amdgpu_ring_priority_put(job->ring, amd_sched_get_job_priority(s_job));
dma_fence_put(job->fence);
amdgpu_sync_free(&job->sync);
amdgpu_sync_free(&job->dep_sync);
@@ -139,6 +141,8 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
job->fence_ctx = entity->fence_context;
*f = dma_fence_get(&job->base.s_fence->finished);
amdgpu_job_free_resources(job);
+ amdgpu_ring_priority_get(job->ring,
+ amd_sched_get_job_priority(&job->base));
amd_sched_entity_push_job(&job->base);
return 0;
@@ -177,8 +181,8 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job)
{
struct dma_fence *fence = NULL;
+ struct amdgpu_device *adev;
struct amdgpu_job *job;
- struct amdgpu_fpriv *fpriv = NULL;
int r;
if (!sched_job) {
@@ -186,23 +190,25 @@ static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job)
return NULL;
}
job = to_amdgpu_job(sched_job);
+ adev = job->adev;
BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
trace_amdgpu_sched_run_job(job);
- if (job->vm)
- fpriv = container_of(job->vm, struct amdgpu_fpriv, vm);
/* skip ib schedule when vram is lost */
- if (fpriv && amdgpu_kms_vram_lost(job->adev, fpriv))
+ if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) {
+ dma_fence_set_error(&job->base.s_fence->finished, -ECANCELED);
DRM_ERROR("Skip scheduling IBs!\n");
- else {
- r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence);
+ } else {
+ r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job,
+ &fence);
if (r)
DRM_ERROR("Error scheduling IBs (%d)\n", r);
}
/* if gpu reset, hw fence will be replaced here */
dma_fence_put(job->fence);
job->fence = dma_fence_get(fence);
+
amdgpu_job_free_resources(job);
return fence;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e162290..6f0b26d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -28,6 +28,7 @@
#include <drm/drmP.h>
#include "amdgpu.h"
#include <drm/amdgpu_drm.h>
+#include "amdgpu_sched.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
@@ -269,7 +270,6 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
struct amdgpu_device *adev = dev->dev_private;
- struct amdgpu_fpriv *fpriv = filp->driver_priv;
struct drm_amdgpu_info *info = data;
struct amdgpu_mode_info *minfo = &adev->mode_info;
void __user *out = (void __user *)(uintptr_t)info->return_pointer;
@@ -282,8 +282,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
if (!info->return_size || !info->return_pointer)
return -EINVAL;
- if (amdgpu_kms_vram_lost(adev, fpriv))
- return -ENODEV;
switch (info->query) {
case AMDGPU_INFO_ACCEL_WORKING:
@@ -765,6 +763,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
}
return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
}
+ case AMDGPU_INFO_VRAM_LOST_COUNTER:
+ ui32 = atomic_read(&adev->vram_lost_counter);
+ return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->query);
return -EINVAL;
@@ -791,12 +792,6 @@ void amdgpu_driver_lastclose_kms(struct drm_device *dev)
vga_switcheroo_process_delayed_switch();
}
-bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
- struct amdgpu_fpriv *fpriv)
-{
- return fpriv->vram_lost_counter != atomic_read(&adev->vram_lost_counter);
-}
-
/**
* amdgpu_driver_open_kms - drm callback for open
*
@@ -825,7 +820,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
}
r = amdgpu_vm_init(adev, &fpriv->vm,
- AMDGPU_VM_CONTEXT_GFX);
+ AMDGPU_VM_CONTEXT_GFX, 0);
if (r) {
kfree(fpriv);
goto out_suspend;
@@ -841,8 +836,11 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
- if (r)
+ if (r) {
+ amdgpu_vm_fini(adev, &fpriv->vm);
+ kfree(fpriv);
goto out_suspend;
+ }
}
mutex_init(&fpriv->bo_list_lock);
@@ -850,7 +848,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
- fpriv->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
file_priv->driver_priv = fpriv;
out_suspend:
@@ -1020,7 +1017,9 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
/* KMS */
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 3b0f2ec..bd67f4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -50,8 +50,10 @@ struct amdgpu_mn {
struct hlist_node node;
/* objects protected by lock */
- struct mutex lock;
+ struct rw_semaphore lock;
struct rb_root_cached objects;
+ struct mutex read_lock;
+ atomic_t recursion;
};
struct amdgpu_mn_node {
@@ -74,7 +76,7 @@ static void amdgpu_mn_destroy(struct work_struct *work)
struct amdgpu_bo *bo, *next_bo;
mutex_lock(&adev->mn_lock);
- mutex_lock(&rmn->lock);
+ down_write(&rmn->lock);
hash_del(&rmn->node);
rbtree_postorder_for_each_entry_safe(node, next_node,
&rmn->objects.rb_root, it.rb) {
@@ -84,7 +86,7 @@ static void amdgpu_mn_destroy(struct work_struct *work)
}
kfree(node);
}
- mutex_unlock(&rmn->lock);
+ up_write(&rmn->lock);
mutex_unlock(&adev->mn_lock);
mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm);
kfree(rmn);
@@ -106,6 +108,53 @@ static void amdgpu_mn_release(struct mmu_notifier *mn,
schedule_work(&rmn->work);
}
+
+/**
+ * amdgpu_mn_lock - take the write side lock for this mn
+ */
+void amdgpu_mn_lock(struct amdgpu_mn *mn)
+{
+ if (mn)
+ down_write(&mn->lock);
+}
+
+/**
+ * amdgpu_mn_unlock - drop the write side lock for this mn
+ */
+void amdgpu_mn_unlock(struct amdgpu_mn *mn)
+{
+ if (mn)
+ up_write(&mn->lock);
+}
+
+/**
+ * amdgpu_mn_read_lock - take the rmn read lock
+ *
+ * @rmn: our notifier
+ *
+ * Take the rmn read side lock.
+ */
+static void amdgpu_mn_read_lock(struct amdgpu_mn *rmn)
+{
+ mutex_lock(&rmn->read_lock);
+ if (atomic_inc_return(&rmn->recursion) == 1)
+ down_read_non_owner(&rmn->lock);
+ mutex_unlock(&rmn->read_lock);
+}
+
+/**
+ * amdgpu_mn_read_unlock - drop the rmn read lock
+ *
+ * @rmn: our notifier
+ *
+ * Drop the rmn read side lock.
+ */
+static void amdgpu_mn_read_unlock(struct amdgpu_mn *rmn)
+{
+ if (atomic_dec_return(&rmn->recursion) == 0)
+ up_read_non_owner(&rmn->lock);
+}
+
/**
* amdgpu_mn_invalidate_node - unmap all BOs of a node
*
@@ -126,23 +175,12 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
continue;
- r = amdgpu_bo_reserve(bo, true);
- if (r) {
- DRM_ERROR("(%ld) failed to reserve user bo\n", r);
- continue;
- }
-
r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
true, false, MAX_SCHEDULE_TIMEOUT);
if (r <= 0)
DRM_ERROR("(%ld) failed to wait for user bo\n", r);
- amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
- if (r)
- DRM_ERROR("(%ld) failed to validate user bo\n", r);
-
- amdgpu_bo_unreserve(bo);
+ amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm);
}
}
@@ -168,7 +206,7 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
/* notification is exclusive, but interval is inclusive */
end -= 1;
- mutex_lock(&rmn->lock);
+ amdgpu_mn_read_lock(rmn);
it = interval_tree_iter_first(&rmn->objects, start, end);
while (it) {
@@ -179,13 +217,32 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
amdgpu_mn_invalidate_node(node, start, end);
}
+}
- mutex_unlock(&rmn->lock);
+/**
+ * amdgpu_mn_invalidate_range_end - callback to notify about mm change
+ *
+ * @mn: our notifier
+ * @mn: the mm this callback is about
+ * @start: start of updated range
+ * @end: end of updated range
+ *
+ * Release the lock again to allow new command submissions.
+ */
+static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn,
+ struct mm_struct *mm,
+ unsigned long start,
+ unsigned long end)
+{
+ struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
+
+ amdgpu_mn_read_unlock(rmn);
}
static const struct mmu_notifier_ops amdgpu_mn_ops = {
.release = amdgpu_mn_release,
.invalidate_range_start = amdgpu_mn_invalidate_range_start,
+ .invalidate_range_end = amdgpu_mn_invalidate_range_end,
};
/**
@@ -195,7 +252,7 @@ static const struct mmu_notifier_ops amdgpu_mn_ops = {
*
* Creates a notifier context for current->mm.
*/
-static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
+struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
{
struct mm_struct *mm = current->mm;
struct amdgpu_mn *rmn;
@@ -220,8 +277,10 @@ static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
rmn->adev = adev;
rmn->mm = mm;
rmn->mn.ops = &amdgpu_mn_ops;
- mutex_init(&rmn->lock);
+ init_rwsem(&rmn->lock);
rmn->objects = RB_ROOT_CACHED;
+ mutex_init(&rmn->read_lock);
+ atomic_set(&rmn->recursion, 0);
r = __mmu_notifier_register(&rmn->mn, mm);
if (r)
@@ -267,7 +326,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
INIT_LIST_HEAD(&bos);
- mutex_lock(&rmn->lock);
+ down_write(&rmn->lock);
while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) {
kfree(node);
@@ -281,7 +340,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
if (!node) {
node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
if (!node) {
- mutex_unlock(&rmn->lock);
+ up_write(&rmn->lock);
return -ENOMEM;
}
}
@@ -296,7 +355,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
interval_tree_insert(&node->it, &rmn->objects);
- mutex_unlock(&rmn->lock);
+ up_write(&rmn->lock);
return 0;
}
@@ -322,7 +381,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
return;
}
- mutex_lock(&rmn->lock);
+ down_write(&rmn->lock);
/* save the next list entry for later */
head = bo->mn_list.next;
@@ -337,6 +396,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
kfree(node);
}
- mutex_unlock(&rmn->lock);
+ up_write(&rmn->lock);
mutex_unlock(&adev->mn_lock);
}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
new file mode 100644
index 0000000..d0095a3
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Christian König
+ */
+#ifndef __AMDGPU_MN_H__
+#define __AMDGPU_MN_H__
+
+/*
+ * MMU Notifier
+ */
+struct amdgpu_mn;
+
+#if defined(CONFIG_MMU_NOTIFIER)
+void amdgpu_mn_lock(struct amdgpu_mn *mn);
+void amdgpu_mn_unlock(struct amdgpu_mn *mn);
+struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev);
+int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
+void amdgpu_mn_unregister(struct amdgpu_bo *bo);
+#else
+static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {}
+static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {}
+static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
+{
+ return NULL;
+}
+static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
+{
+ return -ENODEV;
+}
+static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9e495da..ea25164 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -40,9 +40,7 @@
static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
- struct amdgpu_bo *bo;
-
- bo = container_of(tbo, struct amdgpu_bo, tbo);
+ struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
amdgpu_bo_kunmap(bo);
@@ -64,11 +62,12 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
return false;
}
-static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
- struct ttm_placement *placement,
- struct ttm_place *places,
- u32 domain, u64 flags)
+void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
+ struct ttm_placement *placement = &abo->placement;
+ struct ttm_place *places = abo->placements;
+ u64 flags = abo->flags;
u32 c = 0;
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
@@ -151,27 +150,6 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
placement->busy_placement = places;
}
-void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
-{
- struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
-
- amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements,
- domain, abo->flags);
-}
-
-static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
- struct ttm_placement *placement)
-{
- BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
-
- memcpy(bo->placements, placement->placement,
- placement->num_placement * sizeof(struct ttm_place));
- bo->placement.num_placement = placement->num_placement;
- bo->placement.num_busy_placement = placement->num_busy_placement;
- bo->placement.placement = bo->placements;
- bo->placement.busy_placement = bo->placements;
-}
-
/**
* amdgpu_bo_create_reserved - create reserved BO for kernel use
*
@@ -303,14 +281,13 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
*cpu_addr = NULL;
}
-int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
- unsigned long size, int byte_align,
- bool kernel, u32 domain, u64 flags,
- struct sg_table *sg,
- struct ttm_placement *placement,
- struct reservation_object *resv,
- uint64_t init_value,
- struct amdgpu_bo **bo_ptr)
+static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ unsigned long size, int byte_align,
+ bool kernel, u32 domain, u64 flags,
+ struct sg_table *sg,
+ struct reservation_object *resv,
+ uint64_t init_value,
+ struct amdgpu_bo **bo_ptr)
{
struct amdgpu_bo *bo;
enum ttm_bo_type type;
@@ -384,13 +361,17 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
#endif
- amdgpu_fill_placement_to_bo(bo, placement);
- /* Kernel allocation are uninterruptible */
+ bo->tbo.bdev = &adev->mman.bdev;
+ amdgpu_ttm_placement_from_domain(bo, domain);
initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
+ /* Kernel allocation are uninterruptible */
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
&bo->placement, page_align, !kernel, NULL,
acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
+ if (unlikely(r != 0))
+ return r;
+
bytes_moved = atomic64_read(&adev->num_bytes_moved) -
initial_bytes_moved;
if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
@@ -400,9 +381,6 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
else
amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0);
- if (unlikely(r != 0))
- return r;
-
if (kernel)
bo->tbo.priority = 1;
@@ -442,27 +420,17 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
unsigned long size, int byte_align,
struct amdgpu_bo *bo)
{
- struct ttm_placement placement = {0};
- struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
int r;
if (bo->shadow)
return 0;
- memset(&placements, 0, sizeof(placements));
- amdgpu_ttm_placement_init(adev, &placement, placements,
- AMDGPU_GEM_DOMAIN_GTT,
- AMDGPU_GEM_CREATE_CPU_GTT_USWC |
- AMDGPU_GEM_CREATE_SHADOW);
-
- r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
- AMDGPU_GEM_DOMAIN_GTT,
- AMDGPU_GEM_CREATE_CPU_GTT_USWC |
- AMDGPU_GEM_CREATE_SHADOW,
- NULL, &placement,
- bo->tbo.resv,
- 0,
- &bo->shadow);
+ r = amdgpu_bo_do_create(adev, size, byte_align, true,
+ AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_GEM_CREATE_CPU_GTT_USWC |
+ AMDGPU_GEM_CREATE_SHADOW,
+ NULL, bo->tbo.resv, 0,
+ &bo->shadow);
if (!r) {
bo->shadow->parent = amdgpu_bo_ref(bo);
mutex_lock(&adev->shadow_list_lock);
@@ -484,18 +452,11 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
uint64_t init_value,
struct amdgpu_bo **bo_ptr)
{
- struct ttm_placement placement = {0};
- struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
int r;
- memset(&placements, 0, sizeof(placements));
- amdgpu_ttm_placement_init(adev, &placement, placements,
- domain, parent_flags);
-
- r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, domain,
- parent_flags, sg, &placement, resv,
- init_value, bo_ptr);
+ r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain,
+ parent_flags, sg, resv, init_value, bo_ptr);
if (r)
return r;
@@ -672,7 +633,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
int r, i;
- unsigned fpfn, lpfn;
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
return -EPERM;
@@ -704,22 +664,16 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
}
bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ /* force to pin into visible video ram */
+ if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
+ bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
amdgpu_ttm_placement_from_domain(bo, domain);
for (i = 0; i < bo->placement.num_placement; i++) {
- /* force to pin into visible video ram */
- if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
- !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
- (!max_offset || max_offset >
- adev->mc.visible_vram_size)) {
- if (WARN_ON_ONCE(min_offset >
- adev->mc.visible_vram_size))
- return -EINVAL;
- fpfn = min_offset >> PAGE_SHIFT;
- lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
- } else {
- fpfn = min_offset >> PAGE_SHIFT;
- lpfn = max_offset >> PAGE_SHIFT;
- }
+ unsigned fpfn, lpfn;
+
+ fpfn = min_offset >> PAGE_SHIFT;
+ lpfn = max_offset >> PAGE_SHIFT;
+
if (fpfn > bo->placements[i].fpfn)
bo->placements[i].fpfn = fpfn;
if (!bo->placements[i].lpfn ||
@@ -928,8 +882,8 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
return;
- abo = container_of(bo, struct amdgpu_bo, tbo);
- amdgpu_vm_bo_invalidate(adev, abo);
+ abo = ttm_to_amdgpu_bo(bo);
+ amdgpu_vm_bo_invalidate(adev, abo, evict);
amdgpu_bo_kunmap(abo);
@@ -955,7 +909,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
return 0;
- abo = container_of(bo, struct amdgpu_bo, tbo);
+ abo = ttm_to_amdgpu_bo(bo);
/* Remember that this BO was accessed by the CPU */
abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index a288fa6..428aae0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -35,6 +35,7 @@
/* bo virtual addresses in a vm */
struct amdgpu_bo_va_mapping {
+ struct amdgpu_bo_va *bo_va;
struct list_head list;
struct rb_node rb;
uint64_t start;
@@ -49,12 +50,17 @@ struct amdgpu_bo_va {
struct amdgpu_vm_bo_base base;
/* protected by bo being reserved */
- struct dma_fence *last_pt_update;
unsigned ref_count;
+ /* all other members protected by the VM PD being reserved */
+ struct dma_fence *last_pt_update;
+
/* mappings for this bo_va */
struct list_head invalids;
struct list_head valids;
+
+ /* If the mappings are cleared or filled */
+ bool cleared;
};
struct amdgpu_bo {
@@ -88,6 +94,11 @@ struct amdgpu_bo {
};
};
+static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
+{
+ return container_of(tbo, struct amdgpu_bo, tbo);
+}
+
/**
* amdgpu_mem_type_to_domain - return domain corresponding to mem_type
* @mem_type: ttm memory type
@@ -182,6 +193,14 @@ static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
}
}
+/**
+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
+ */
+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+{
+ return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+}
+
int amdgpu_bo_create(struct amdgpu_device *adev,
unsigned long size, int byte_align,
bool kernel, u32 domain, u64 flags,
@@ -189,14 +208,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
struct reservation_object *resv,
uint64_t init_value,
struct amdgpu_bo **bo_ptr);
-int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
- unsigned long size, int byte_align,
- bool kernel, u32 domain, u64 flags,
- struct sg_table *sg,
- struct ttm_placement *placement,
- struct reservation_object *resv,
- uint64_t init_value,
- struct amdgpu_bo **bo_ptr);
int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
unsigned long size, int align,
u32 domain, struct amdgpu_bo **bo_ptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7df503a..a59e04f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -64,17 +64,13 @@ static const struct cg_flag_name clocks[] = {
void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
{
- if (adev->pp_enabled)
- /* TODO */
- return;
-
if (adev->pm.dpm_enabled) {
mutex_lock(&adev->pm.mutex);
if (power_supply_is_system_supplied() > 0)
adev->pm.dpm.ac_power = true;
else
adev->pm.dpm.ac_power = false;
- if (adev->pm.funcs->enable_bapm)
+ if (adev->powerplay.pp_funcs->enable_bapm)
amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
mutex_unlock(&adev->pm.mutex);
}
@@ -88,9 +84,9 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
enum amd_pm_state_type pm;
- if (adev->pp_enabled) {
+ if (adev->powerplay.pp_funcs->get_current_power_state)
pm = amdgpu_dpm_get_current_power_state(adev);
- } else
+ else
pm = adev->pm.dpm.user_state;
return snprintf(buf, PAGE_SIZE, "%s\n",
@@ -118,8 +114,8 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
goto fail;
}
- if (adev->pp_enabled) {
- amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
} else {
mutex_lock(&adev->pm.mutex);
adev->pm.dpm.user_state = state;
@@ -140,13 +136,17 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- enum amd_dpm_forced_level level;
+ enum amd_dpm_forced_level level = 0xff;
if ((adev->flags & AMD_IS_PX) &&
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return snprintf(buf, PAGE_SIZE, "off\n");
- level = amdgpu_dpm_get_performance_level(adev);
+ if (adev->powerplay.pp_funcs->get_performance_level)
+ level = amdgpu_dpm_get_performance_level(adev);
+ else
+ level = adev->pm.dpm.forced_level;
+
return snprintf(buf, PAGE_SIZE, "%s\n",
(level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
(level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
@@ -167,7 +167,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
enum amd_dpm_forced_level level;
- enum amd_dpm_forced_level current_level;
+ enum amd_dpm_forced_level current_level = 0xff;
int ret = 0;
/* Can't force performance level when the card is off */
@@ -175,7 +175,8 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- current_level = amdgpu_dpm_get_performance_level(adev);
+ if (adev->powerplay.pp_funcs->get_performance_level)
+ current_level = amdgpu_dpm_get_performance_level(adev);
if (strncmp("low", buf, strlen("low")) == 0) {
level = AMD_DPM_FORCED_LEVEL_LOW;
@@ -203,9 +204,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
if (current_level == level)
return count;
- if (adev->pp_enabled)
- amdgpu_dpm_force_performance_level(adev, level);
- else {
+ if (adev->powerplay.pp_funcs->force_performance_level) {
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
count = -EINVAL;
@@ -233,7 +232,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
struct pp_states_info data;
int i, buf_len;
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->get_pp_num_states)
amdgpu_dpm_get_pp_num_states(adev, &data);
buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
@@ -257,8 +256,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
enum amd_pm_state_type pm = 0;
int i = 0;
- if (adev->pp_enabled) {
-
+ if (adev->powerplay.pp_funcs->get_current_power_state
+ && adev->powerplay.pp_funcs->get_pp_num_states) {
pm = amdgpu_dpm_get_current_power_state(adev);
amdgpu_dpm_get_pp_num_states(adev, &data);
@@ -280,25 +279,10 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- struct pp_states_info data;
- enum amd_pm_state_type pm = 0;
- int i;
- if (adev->pp_force_state_enabled && adev->pp_enabled) {
- pm = amdgpu_dpm_get_current_power_state(adev);
- amdgpu_dpm_get_pp_num_states(adev, &data);
-
- for (i = 0; i < data.nums; i++) {
- if (pm == data.states[i])
- break;
- }
-
- if (i == data.nums)
- i = -EINVAL;
-
- return snprintf(buf, PAGE_SIZE, "%d\n", i);
-
- } else
+ if (adev->pp_force_state_enabled)
+ return amdgpu_get_pp_cur_state(dev, attr, buf);
+ else
return snprintf(buf, PAGE_SIZE, "\n");
}
@@ -315,7 +299,8 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
if (strlen(buf) == 1)
adev->pp_force_state_enabled = false;
- else if (adev->pp_enabled) {
+ else if (adev->powerplay.pp_funcs->dispatch_tasks &&
+ adev->powerplay.pp_funcs->get_pp_num_states) {
struct pp_states_info data;
ret = kstrtoul(buf, 0, &idx);
@@ -330,7 +315,7 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
state != POWER_STATE_TYPE_DEFAULT) {
amdgpu_dpm_dispatch_task(adev,
- AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
+ AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
adev->pp_force_state_enabled = true;
}
}
@@ -347,7 +332,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
char *table = NULL;
int size;
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->get_pp_table)
size = amdgpu_dpm_get_pp_table(adev, &table);
else
return 0;
@@ -368,7 +353,7 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->set_pp_table)
amdgpu_dpm_set_pp_table(adev, buf, count);
return count;
@@ -380,14 +365,11 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- ssize_t size = 0;
- if (adev->pp_enabled)
- size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
- else if (adev->pm.funcs->print_clock_levels)
- size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
-
- return size;
+ if (adev->powerplay.pp_funcs->print_clock_levels)
+ return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
+ else
+ return snprintf(buf, PAGE_SIZE, "\n");
}
static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
@@ -416,10 +398,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
mask |= 1 << level;
}
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->force_clock_level)
amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
- else if (adev->pm.funcs->force_clock_level)
- adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
+
fail:
return count;
}
@@ -430,14 +411,11 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- ssize_t size = 0;
- if (adev->pp_enabled)
- size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
- else if (adev->pm.funcs->print_clock_levels)
- size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
-
- return size;
+ if (adev->powerplay.pp_funcs->print_clock_levels)
+ return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
+ else
+ return snprintf(buf, PAGE_SIZE, "\n");
}
static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
@@ -465,11 +443,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
}
mask |= 1 << level;
}
-
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->force_clock_level)
amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
- else if (adev->pm.funcs->force_clock_level)
- adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
+
fail:
return count;
}
@@ -480,14 +456,11 @@ static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- ssize_t size = 0;
- if (adev->pp_enabled)
- size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
- else if (adev->pm.funcs->print_clock_levels)
- size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
-
- return size;
+ if (adev->powerplay.pp_funcs->print_clock_levels)
+ return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
+ else
+ return snprintf(buf, PAGE_SIZE, "\n");
}
static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
@@ -515,11 +488,9 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
}
mask |= 1 << level;
}
-
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->force_clock_level)
amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
- else if (adev->pm.funcs->force_clock_level)
- adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
+
fail:
return count;
}
@@ -532,10 +503,8 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
uint32_t value = 0;
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->get_sclk_od)
value = amdgpu_dpm_get_sclk_od(adev);
- else if (adev->pm.funcs->get_sclk_od)
- value = adev->pm.funcs->get_sclk_od(adev);
return snprintf(buf, PAGE_SIZE, "%d\n", value);
}
@@ -556,12 +525,12 @@ static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
count = -EINVAL;
goto fail;
}
-
- if (adev->pp_enabled) {
+ if (adev->powerplay.pp_funcs->set_sclk_od)
amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
- amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
- } else if (adev->pm.funcs->set_sclk_od) {
- adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
+
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
+ } else {
adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
amdgpu_pm_compute_clocks(adev);
}
@@ -578,10 +547,8 @@ static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
uint32_t value = 0;
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->get_mclk_od)
value = amdgpu_dpm_get_mclk_od(adev);
- else if (adev->pm.funcs->get_mclk_od)
- value = adev->pm.funcs->get_mclk_od(adev);
return snprintf(buf, PAGE_SIZE, "%d\n", value);
}
@@ -602,12 +569,12 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
count = -EINVAL;
goto fail;
}
-
- if (adev->pp_enabled) {
+ if (adev->powerplay.pp_funcs->set_mclk_od)
amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
- amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
- } else if (adev->pm.funcs->set_mclk_od) {
- adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
+
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
+ } else {
adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
amdgpu_pm_compute_clocks(adev);
}
@@ -621,14 +588,11 @@ static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- int ret = 0;
+ int ret = 0xff;
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->get_power_profile_state)
ret = amdgpu_dpm_get_power_profile_state(
adev, query);
- else if (adev->pm.funcs->get_power_profile_state)
- ret = adev->pm.funcs->get_power_profile_state(
- adev, query);
if (ret)
return ret;
@@ -675,15 +639,12 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
char *sub_str, buf_cpy[128], *tmp_str;
const char delimiter[3] = {' ', '\n', '\0'};
long int value;
- int ret = 0;
+ int ret = 0xff;
if (strncmp("reset", buf, strlen("reset")) == 0) {
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->reset_power_profile_state)
ret = amdgpu_dpm_reset_power_profile_state(
adev, request);
- else if (adev->pm.funcs->reset_power_profile_state)
- ret = adev->pm.funcs->reset_power_profile_state(
- adev, request);
if (ret) {
count = -EINVAL;
goto fail;
@@ -692,12 +653,10 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
}
if (strncmp("set", buf, strlen("set")) == 0) {
- if (adev->pp_enabled)
+ if (adev->powerplay.pp_funcs->set_power_profile_state)
ret = amdgpu_dpm_set_power_profile_state(
adev, request);
- else if (adev->pm.funcs->set_power_profile_state)
- ret = adev->pm.funcs->set_power_profile_state(
- adev, request);
+
if (ret) {
count = -EINVAL;
goto fail;
@@ -745,13 +704,8 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
loop++;
}
-
- if (adev->pp_enabled)
- ret = amdgpu_dpm_set_power_profile_state(
- adev, request);
- else if (adev->pm.funcs->set_power_profile_state)
- ret = adev->pm.funcs->set_power_profile_state(
- adev, request);
+ if (adev->powerplay.pp_funcs->set_power_profile_state)
+ ret = amdgpu_dpm_set_power_profile_state(adev, request);
if (ret)
count = -EINVAL;
@@ -831,7 +785,7 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
+ if (!adev->powerplay.pp_funcs->get_temperature)
temp = 0;
else
temp = amdgpu_dpm_get_temperature(adev);
@@ -862,7 +816,7 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
struct amdgpu_device *adev = dev_get_drvdata(dev);
u32 pwm_mode = 0;
- if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
+ if (!adev->powerplay.pp_funcs->get_fan_control_mode)
return -EINVAL;
pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
@@ -879,7 +833,7 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
int err;
int value;
- if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
+ if (!adev->powerplay.pp_funcs->set_fan_control_mode)
return -EINVAL;
err = kstrtoint(buf, 10, &value);
@@ -919,9 +873,11 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
value = (value * 100) / 255;
- err = amdgpu_dpm_set_fan_speed_percent(adev, value);
- if (err)
- return err;
+ if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
+ err = amdgpu_dpm_set_fan_speed_percent(adev, value);
+ if (err)
+ return err;
+ }
return count;
}
@@ -932,11 +888,13 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
int err;
- u32 speed;
+ u32 speed = 0;
- err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
- if (err)
- return err;
+ if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
+ err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
+ if (err)
+ return err;
+ }
speed = (speed * 255) / 100;
@@ -949,11 +907,13 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
int err;
- u32 speed;
+ u32 speed = 0;
- err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
- if (err)
- return err;
+ if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
+ err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
+ if (err)
+ return err;
+ }
return sprintf(buf, "%i\n", speed);
}
@@ -996,9 +956,6 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
return 0;
- if (adev->pp_enabled)
- return effective_mode;
-
/* Skip fan attributes if fan is not present */
if (adev->pm.no_fan &&
(attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
@@ -1008,21 +965,21 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
return 0;
/* mask fan attributes if we have no bindings for this asic to expose */
- if ((!adev->pm.funcs->get_fan_speed_percent &&
+ if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
- (!adev->pm.funcs->get_fan_control_mode &&
+ (!adev->powerplay.pp_funcs->get_fan_control_mode &&
attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
effective_mode &= ~S_IRUGO;
- if ((!adev->pm.funcs->set_fan_speed_percent &&
+ if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
- (!adev->pm.funcs->set_fan_control_mode &&
+ (!adev->powerplay.pp_funcs->set_fan_control_mode &&
attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
effective_mode &= ~S_IWUSR;
/* hide max/min values if we can't both query and manage the fan */
- if ((!adev->pm.funcs->set_fan_speed_percent &&
- !adev->pm.funcs->get_fan_speed_percent) &&
+ if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
+ !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
(attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
return 0;
@@ -1055,7 +1012,7 @@ void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
if (!adev->pm.dpm_enabled)
return;
- if (adev->pm.funcs->get_temperature) {
+ if (adev->powerplay.pp_funcs->get_temperature) {
int temp = amdgpu_dpm_get_temperature(adev);
if (temp < adev->pm.dpm.thermal.min_temp)
@@ -1087,7 +1044,7 @@ static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
true : false;
/* check if the vblank period is too short to adjust the mclk */
- if (single_display && adev->pm.funcs->vblank_too_short) {
+ if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
if (amdgpu_dpm_vblank_too_short(adev))
single_display = false;
}
@@ -1216,7 +1173,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
struct amdgpu_ps *ps;
enum amd_pm_state_type dpm_state;
int ret;
- bool equal;
+ bool equal = false;
/* if dpm init failed */
if (!adev->pm.dpm_enabled)
@@ -1236,7 +1193,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
else
return;
- if (amdgpu_dpm == 1) {
+ if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
printk("switching from power state:\n");
amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
printk("switching to power state:\n");
@@ -1245,15 +1202,17 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
/* update whether vce is active */
ps->vce_active = adev->pm.dpm.vce_active;
-
- amdgpu_dpm_display_configuration_changed(adev);
+ if (adev->powerplay.pp_funcs->display_configuration_changed)
+ amdgpu_dpm_display_configuration_changed(adev);
ret = amdgpu_dpm_pre_set_power_state(adev);
if (ret)
return;
- if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)))
- equal = false;
+ if (adev->powerplay.pp_funcs->check_state_equal) {
+ if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
+ equal = false;
+ }
if (equal)
return;
@@ -1264,7 +1223,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
- if (adev->pm.funcs->force_performance_level) {
+ if (adev->powerplay.pp_funcs->force_performance_level) {
if (adev->pm.dpm.thermal_active) {
enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
/* force low perf level for thermal */
@@ -1280,7 +1239,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
{
- if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
+ if (adev->powerplay.pp_funcs->powergate_uvd) {
/* enable/disable UVD */
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_powergate_uvd(adev, !enable);
@@ -1302,7 +1261,7 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
{
- if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
+ if (adev->powerplay.pp_funcs->powergate_vce) {
/* enable/disable VCE */
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_powergate_vce(adev, !enable);
@@ -1337,8 +1296,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
{
int i;
- if (adev->pp_enabled)
- /* TO DO */
+ if (adev->powerplay.pp_funcs->print_power_state == NULL)
return;
for (i = 0; i < adev->pm.dpm.num_ps; i++)
@@ -1353,10 +1311,11 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
if (adev->pm.sysfs_initialized)
return 0;
- if (!adev->pp_enabled) {
- if (adev->pm.funcs->get_temperature == NULL)
- return 0;
- }
+ if (adev->pm.dpm_enabled == 0)
+ return 0;
+
+ if (adev->powerplay.pp_funcs->get_temperature == NULL)
+ return 0;
adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
DRIVER_NAME, adev,
@@ -1379,27 +1338,26 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
return ret;
}
- if (adev->pp_enabled) {
- ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
- if (ret) {
- DRM_ERROR("failed to create device file pp_num_states\n");
- return ret;
- }
- ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
- if (ret) {
- DRM_ERROR("failed to create device file pp_cur_state\n");
- return ret;
- }
- ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
- if (ret) {
- DRM_ERROR("failed to create device file pp_force_state\n");
- return ret;
- }
- ret = device_create_file(adev->dev, &dev_attr_pp_table);
- if (ret) {
- DRM_ERROR("failed to create device file pp_table\n");
- return ret;
- }
+
+ ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_num_states\n");
+ return ret;
+ }
+ ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_cur_state\n");
+ return ret;
+ }
+ ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_force_state\n");
+ return ret;
+ }
+ ret = device_create_file(adev->dev, &dev_attr_pp_table);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_table\n");
+ return ret;
}
ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
@@ -1455,16 +1413,19 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
{
+ if (adev->pm.dpm_enabled == 0)
+ return;
+
if (adev->pm.int_hwmon_dev)
hwmon_device_unregister(adev->pm.int_hwmon_dev);
device_remove_file(adev->dev, &dev_attr_power_dpm_state);
device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
- if (adev->pp_enabled) {
- device_remove_file(adev->dev, &dev_attr_pp_num_states);
- device_remove_file(adev->dev, &dev_attr_pp_cur_state);
- device_remove_file(adev->dev, &dev_attr_pp_force_state);
- device_remove_file(adev->dev, &dev_attr_pp_table);
- }
+
+ device_remove_file(adev->dev, &dev_attr_pp_num_states);
+ device_remove_file(adev->dev, &dev_attr_pp_cur_state);
+ device_remove_file(adev->dev, &dev_attr_pp_force_state);
+ device_remove_file(adev->dev, &dev_attr_pp_table);
+
device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
@@ -1495,8 +1456,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
amdgpu_fence_wait_empty(ring);
}
- if (adev->pp_enabled) {
- amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL);
} else {
mutex_lock(&adev->pm.mutex);
adev->pm.dpm.new_active_crtcs = 0;
@@ -1630,15 +1591,15 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
if ((adev->flags & AMD_IS_PX) &&
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
seq_printf(m, "PX asic powered off\n");
- } else if (adev->pp_enabled) {
- return amdgpu_debugfs_pm_info_pp(m, adev);
- } else {
+ } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
mutex_lock(&adev->pm.mutex);
- if (adev->pm.funcs->debugfs_print_current_performance_level)
- adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
+ if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
+ adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
else
seq_printf(m, "Debugfs support not implemented for this asic\n");
mutex_unlock(&adev->pm.mutex);
+ } else {
+ return amdgpu_debugfs_pm_info_pp(m, adev);
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index b7e1c02..5f5aa5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -34,24 +34,6 @@
#include "cik_dpm.h"
#include "vi_dpm.h"
-static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
-{
- struct amd_pp_init pp_init;
- struct amd_powerplay *amd_pp;
- int ret;
-
- amd_pp = &(adev->powerplay);
- pp_init.chip_family = adev->family;
- pp_init.chip_id = adev->asic_type;
- pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
- pp_init.feature_mask = amdgpu_pp_feature_mask;
- pp_init.device = amdgpu_cgs_create_device(adev);
- ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
- if (ret)
- return -EINVAL;
- return 0;
-}
-
static int amdgpu_pp_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -59,7 +41,6 @@ static int amdgpu_pp_early_init(void *handle)
int ret = 0;
amd_pp = &(adev->powerplay);
- adev->pp_enabled = false;
amd_pp->pp_handle = (void *)adev;
switch (adev->asic_type) {
@@ -73,9 +54,7 @@ static int amdgpu_pp_early_init(void *handle)
case CHIP_STONEY:
case CHIP_VEGA10:
case CHIP_RAVEN:
- adev->pp_enabled = true;
- if (amdgpu_create_pp_handle(adev))
- return -EINVAL;
+ amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
amd_pp->ip_funcs = &pp_ip_funcs;
amd_pp->pp_funcs = &pp_dpm_funcs;
break;
@@ -87,17 +66,26 @@ static int amdgpu_pp_early_init(void *handle)
case CHIP_OLAND:
case CHIP_HAINAN:
amd_pp->ip_funcs = &si_dpm_ip_funcs;
+ amd_pp->pp_funcs = &si_dpm_funcs;
break;
#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
case CHIP_BONAIRE:
case CHIP_HAWAII:
- amd_pp->ip_funcs = &ci_dpm_ip_funcs;
+ if (amdgpu_dpm == -1) {
+ amd_pp->ip_funcs = &ci_dpm_ip_funcs;
+ amd_pp->pp_funcs = &ci_dpm_funcs;
+ } else {
+ amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
+ amd_pp->ip_funcs = &pp_ip_funcs;
+ amd_pp->pp_funcs = &pp_dpm_funcs;
+ }
break;
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_KAVERI:
amd_pp->ip_funcs = &kv_dpm_ip_funcs;
+ amd_pp->pp_funcs = &kv_dpm_funcs;
break;
#endif
default:
@@ -107,12 +95,9 @@ static int amdgpu_pp_early_init(void *handle)
if (adev->powerplay.ip_funcs->early_init)
ret = adev->powerplay.ip_funcs->early_init(
- adev->powerplay.pp_handle);
+ amd_pp->cgs_device ? amd_pp->cgs_device :
+ amd_pp->pp_handle);
- if (ret == PP_DPM_DISABLED) {
- adev->pm.dpm_enabled = false;
- return 0;
- }
return ret;
}
@@ -126,11 +111,6 @@ static int amdgpu_pp_late_init(void *handle)
ret = adev->powerplay.ip_funcs->late_init(
adev->powerplay.pp_handle);
- if (adev->pp_enabled && adev->pm.dpm_enabled) {
- amdgpu_pm_sysfs_init(adev);
- amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
- }
-
return ret;
}
@@ -165,21 +145,13 @@ static int amdgpu_pp_hw_init(void *handle)
int ret = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
amdgpu_ucode_init_bo(adev);
if (adev->powerplay.ip_funcs->hw_init)
ret = adev->powerplay.ip_funcs->hw_init(
adev->powerplay.pp_handle);
- if (ret == PP_DPM_DISABLED) {
- adev->pm.dpm_enabled = false;
- return 0;
- }
-
- if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
- adev->pm.dpm_enabled = true;
-
return ret;
}
@@ -188,14 +160,11 @@ static int amdgpu_pp_hw_fini(void *handle)
int ret = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->pp_enabled && adev->pm.dpm_enabled)
- amdgpu_pm_sysfs_fini(adev);
-
if (adev->powerplay.ip_funcs->hw_fini)
ret = adev->powerplay.ip_funcs->hw_fini(
adev->powerplay.pp_handle);
- if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
amdgpu_ucode_fini_bo(adev);
return ret;
@@ -209,9 +178,8 @@ static void amdgpu_pp_late_fini(void *handle)
adev->powerplay.ip_funcs->late_fini(
adev->powerplay.pp_handle);
-
- if (adev->pp_enabled)
- amd_powerplay_destroy(adev->powerplay.pp_handle);
+ if (adev->powerplay.cgs_device)
+ amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
}
static int amdgpu_pp_suspend(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 5b3f928..90af8e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -57,6 +57,40 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
ttm_bo_kunmap(&bo->dma_buf_vmap);
}
+int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
+{
+ struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ unsigned asize = amdgpu_bo_size(bo);
+ int ret;
+
+ if (!vma->vm_file)
+ return -ENODEV;
+
+ if (adev == NULL)
+ return -ENODEV;
+
+ /* Check for valid size. */
+ if (asize < vma->vm_end - vma->vm_start)
+ return -EINVAL;
+
+ if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
+ (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
+ return -EPERM;
+ }
+ vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
+
+ /* prime mmap does not need to check access, so allow here */
+ ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
+ if (ret)
+ return ret;
+
+ ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
+ drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
+
+ return ret;
+}
+
struct drm_gem_object *
amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
struct dma_buf_attachment *attach,
@@ -136,7 +170,8 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
{
struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
- if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
+ if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
+ bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
return ERR_PTR(-EPERM);
return drm_gem_prime_export(dev, gobj, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8c2204c..447d446 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -57,21 +57,23 @@ static int psp_sw_init(void *handle)
psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
psp->ring_init = psp_v3_1_ring_init;
psp->ring_create = psp_v3_1_ring_create;
+ psp->ring_stop = psp_v3_1_ring_stop;
psp->ring_destroy = psp_v3_1_ring_destroy;
psp->cmd_submit = psp_v3_1_cmd_submit;
psp->compare_sram_data = psp_v3_1_compare_sram_data;
psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
+ psp->mode1_reset = psp_v3_1_mode1_reset;
break;
case CHIP_RAVEN:
-#if 0
psp->init_microcode = psp_v10_0_init_microcode;
-#endif
psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
psp->ring_init = psp_v10_0_ring_init;
psp->ring_create = psp_v10_0_ring_create;
+ psp->ring_stop = psp_v10_0_ring_stop;
psp->ring_destroy = psp_v10_0_ring_destroy;
psp->cmd_submit = psp_v10_0_cmd_submit;
psp->compare_sram_data = psp_v10_0_compare_sram_data;
+ psp->mode1_reset = psp_v10_0_mode1_reset;
break;
default:
return -EINVAL;
@@ -90,6 +92,12 @@ static int psp_sw_init(void *handle)
static int psp_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ release_firmware(adev->psp.sos_fw);
+ adev->psp.sos_fw = NULL;
+ release_firmware(adev->psp.asd_fw);
+ adev->psp.asd_fw = NULL;
return 0;
}
@@ -253,15 +261,18 @@ static int psp_asd_load(struct psp_context *psp)
static int psp_hw_start(struct psp_context *psp)
{
+ struct amdgpu_device *adev = psp->adev;
int ret;
- ret = psp_bootloader_load_sysdrv(psp);
- if (ret)
- return ret;
+ if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
+ ret = psp_bootloader_load_sysdrv(psp);
+ if (ret)
+ return ret;
- ret = psp_bootloader_load_sos(psp);
- if (ret)
- return ret;
+ ret = psp_bootloader_load_sos(psp);
+ if (ret)
+ return ret;
+ }
ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
if (ret)
@@ -453,6 +464,16 @@ static int psp_hw_fini(void *handle)
static int psp_suspend(void *handle)
{
+ int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct psp_context *psp = &adev->psp;
+
+ ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
+ if (ret) {
+ DRM_ERROR("PSP ring stop failed\n");
+ return ret;
+ }
+
return 0;
}
@@ -487,6 +508,22 @@ static int psp_resume(void *handle)
return ret;
}
+static bool psp_check_reset(void* handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (adev->flags & AMD_IS_APU)
+ return true;
+
+ return false;
+}
+
+static int psp_reset(void* handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ return psp_mode1_reset(&adev->psp);
+}
+
static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
enum AMDGPU_UCODE_ID ucode_type)
{
@@ -530,8 +567,9 @@ const struct amd_ip_funcs psp_ip_funcs = {
.suspend = psp_suspend,
.resume = psp_resume,
.is_idle = NULL,
+ .check_soft_reset = psp_check_reset,
.wait_for_idle = NULL,
- .soft_reset = NULL,
+ .soft_reset = psp_reset,
.set_clockgating_state = psp_set_clockgating_state,
.set_powergating_state = psp_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 538fa9d..ce465455 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -66,6 +66,8 @@ struct psp_context
struct psp_gfx_cmd_resp *cmd);
int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
+ int (*ring_stop)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
@@ -74,6 +76,7 @@ struct psp_context
struct amdgpu_firmware_info *ucode,
enum AMDGPU_UCODE_ID ucode_type);
bool (*smu_reload_quirk)(struct psp_context *psp);
+ int (*mode1_reset)(struct psp_context *psp);
/* fence buffer */
struct amdgpu_bo *fw_pri_bo;
@@ -123,6 +126,7 @@ struct amdgpu_psp_funcs {
#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
#define psp_ring_create(psp, type) (psp)->ring_create((psp), (type))
+#define psp_ring_stop(psp, type) (psp)->ring_stop((psp), (type))
#define psp_ring_destroy(psp, type) ((psp)->ring_destroy((psp), (type)))
#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
(psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
@@ -136,6 +140,8 @@ struct amdgpu_psp_funcs {
((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
#define psp_smu_reload_quirk(psp) \
((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
+#define psp_mode1_reset(psp) \
+ ((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false)
extern const struct amd_ip_funcs psp_ip_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index befc09b..190e28c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -121,7 +121,7 @@ static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip)
static int amdgpu_lru_map(struct amdgpu_device *adev,
struct amdgpu_queue_mapper *mapper,
- int user_ring,
+ int user_ring, bool lru_pipe_order,
struct amdgpu_ring **out_ring)
{
int r, i, j;
@@ -139,7 +139,7 @@ static int amdgpu_lru_map(struct amdgpu_device *adev,
}
r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist,
- j, out_ring);
+ j, lru_pipe_order, out_ring);
if (r)
return r;
@@ -284,8 +284,10 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
r = amdgpu_identity_map(adev, mapper, ring, out_ring);
break;
case AMDGPU_HW_IP_DMA:
+ r = amdgpu_lru_map(adev, mapper, ring, false, out_ring);
+ break;
case AMDGPU_HW_IP_COMPUTE:
- r = amdgpu_lru_map(adev, mapper, ring, out_ring);
+ r = amdgpu_lru_map(adev, mapper, ring, true, out_ring);
break;
default:
*out_ring = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 5ce6528..a98fbbb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -136,7 +136,8 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)
if (ring->funcs->end_use)
ring->funcs->end_use(ring);
- amdgpu_ring_lru_touch(ring->adev, ring);
+ if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)
+ amdgpu_ring_lru_touch(ring->adev, ring);
}
/**
@@ -155,6 +156,75 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring)
}
/**
+ * amdgpu_ring_priority_put - restore a ring's priority
+ *
+ * @ring: amdgpu_ring structure holding the information
+ * @priority: target priority
+ *
+ * Release a request for executing at @priority
+ */
+void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
+ enum amd_sched_priority priority)
+{
+ int i;
+
+ if (!ring->funcs->set_priority)
+ return;
+
+ if (atomic_dec_return(&ring->num_jobs[priority]) > 0)
+ return;
+
+ /* no need to restore if the job is already at the lowest priority */
+ if (priority == AMD_SCHED_PRIORITY_NORMAL)
+ return;
+
+ mutex_lock(&ring->priority_mutex);
+ /* something higher prio is executing, no need to decay */
+ if (ring->priority > priority)
+ goto out_unlock;
+
+ /* decay priority to the next level with a job available */
+ for (i = priority; i >= AMD_SCHED_PRIORITY_MIN; i--) {
+ if (i == AMD_SCHED_PRIORITY_NORMAL
+ || atomic_read(&ring->num_jobs[i])) {
+ ring->priority = i;
+ ring->funcs->set_priority(ring, i);
+ break;
+ }
+ }
+
+out_unlock:
+ mutex_unlock(&ring->priority_mutex);
+}
+
+/**
+ * amdgpu_ring_priority_get - change the ring's priority
+ *
+ * @ring: amdgpu_ring structure holding the information
+ * @priority: target priority
+ *
+ * Request a ring's priority to be raised to @priority (refcounted).
+ */
+void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
+ enum amd_sched_priority priority)
+{
+ if (!ring->funcs->set_priority)
+ return;
+
+ atomic_inc(&ring->num_jobs[priority]);
+
+ mutex_lock(&ring->priority_mutex);
+ if (priority <= ring->priority)
+ goto out_unlock;
+
+ ring->priority = priority;
+ ring->funcs->set_priority(ring, priority);
+
+out_unlock:
+ mutex_unlock(&ring->priority_mutex);
+}
+
+/**
* amdgpu_ring_init - init driver ring struct.
*
* @adev: amdgpu_device pointer
@@ -169,7 +239,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
unsigned max_dw, struct amdgpu_irq_src *irq_src,
unsigned irq_type)
{
- int r;
+ int r, i;
int sched_hw_submission = amdgpu_sched_hw_submission;
/* Set the hw submission limit higher for KIQ because
@@ -247,9 +317,14 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
}
ring->max_dw = max_dw;
+ ring->priority = AMD_SCHED_PRIORITY_NORMAL;
+ mutex_init(&ring->priority_mutex);
INIT_LIST_HEAD(&ring->lru_list);
amdgpu_ring_lru_touch(adev, ring);
+ for (i = 0; i < AMD_SCHED_PRIORITY_MAX; ++i)
+ atomic_set(&ring->num_jobs[i], 0);
+
if (amdgpu_debugfs_ring_init(adev, ring)) {
DRM_ERROR("Failed to register debugfs file for rings !\n");
}
@@ -315,14 +390,16 @@ static bool amdgpu_ring_is_blacklisted(struct amdgpu_ring *ring,
* @type: amdgpu_ring_type enum
* @blacklist: blacklisted ring ids array
* @num_blacklist: number of entries in @blacklist
+ * @lru_pipe_order: find a ring from the least recently used pipe
* @ring: output ring
*
* Retrieve the amdgpu_ring structure for the least recently used ring of
* a specific IP block (all asics).
* Returns 0 on success, error on failure.
*/
-int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
- int num_blacklist, struct amdgpu_ring **ring)
+int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
+ int *blacklist, int num_blacklist,
+ bool lru_pipe_order, struct amdgpu_ring **ring)
{
struct amdgpu_ring *entry;
@@ -337,10 +414,23 @@ int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist))
continue;
- *ring = entry;
- amdgpu_ring_lru_touch_locked(adev, *ring);
- break;
+ if (!*ring) {
+ *ring = entry;
+
+ /* We are done for ring LRU */
+ if (!lru_pipe_order)
+ break;
+ }
+
+ /* Move all rings on the same pipe to the end of the list */
+ if (entry->pipe == (*ring)->pipe)
+ amdgpu_ring_lru_touch_locked(adev, entry);
}
+
+ /* Move the ring we found to the end of the list */
+ if (*ring)
+ amdgpu_ring_lru_touch_locked(adev, *ring);
+
spin_unlock(&adev->ring_lru_list_lock);
if (!*ring) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 322d2529..b18c2b96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -24,6 +24,7 @@
#ifndef __AMDGPU_RING_H__
#define __AMDGPU_RING_H__
+#include <drm/amdgpu_drm.h>
#include "gpu_scheduler.h"
/* max number of rings */
@@ -56,6 +57,7 @@ struct amdgpu_device;
struct amdgpu_ring;
struct amdgpu_ib;
struct amdgpu_cs_parser;
+struct amdgpu_job;
/*
* Fences.
@@ -88,8 +90,12 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
void amdgpu_fence_process(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
+signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
+ uint32_t wait_seq,
+ signed long timeout);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
/*
@@ -147,6 +153,9 @@ struct amdgpu_ring_funcs {
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
+ /* priority functions */
+ void (*set_priority) (struct amdgpu_ring *ring,
+ enum amd_sched_priority priority);
};
struct amdgpu_ring {
@@ -187,6 +196,12 @@ struct amdgpu_ring {
volatile u32 *cond_exe_cpu_addr;
unsigned vm_inv_eng;
bool has_compute_vm_bug;
+
+ atomic_t num_jobs[AMD_SCHED_PRIORITY_MAX];
+ struct mutex priority_mutex;
+ /* protected by priority_mutex */
+ int priority;
+
#if defined(CONFIG_DEBUG_FS)
struct dentry *ent;
#endif
@@ -197,12 +212,17 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
+void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
+ enum amd_sched_priority priority);
+void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
+ enum amd_sched_priority priority);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
unsigned ring_size, struct amdgpu_irq_src *irq_src,
unsigned irq_type);
void amdgpu_ring_fini(struct amdgpu_ring *ring);
-int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
- int num_blacklist, struct amdgpu_ring **ring);
+int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
+ int *blacklist, int num_blacklist,
+ bool lru_pipe_order, struct amdgpu_ring **ring);
void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
new file mode 100644
index 0000000..290cc3f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2017 Valve Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Andres Rodriguez <andresx7@gmail.com>
+ */
+
+#include <linux/fdtable.h>
+#include <linux/pid.h>
+#include <drm/amdgpu_drm.h>
+#include "amdgpu.h"
+
+#include "amdgpu_vm.h"
+
+enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
+{
+ switch (amdgpu_priority) {
+ case AMDGPU_CTX_PRIORITY_VERY_HIGH:
+ return AMD_SCHED_PRIORITY_HIGH_HW;
+ case AMDGPU_CTX_PRIORITY_HIGH:
+ return AMD_SCHED_PRIORITY_HIGH_SW;
+ case AMDGPU_CTX_PRIORITY_NORMAL:
+ return AMD_SCHED_PRIORITY_NORMAL;
+ case AMDGPU_CTX_PRIORITY_LOW:
+ case AMDGPU_CTX_PRIORITY_VERY_LOW:
+ return AMD_SCHED_PRIORITY_LOW;
+ case AMDGPU_CTX_PRIORITY_UNSET:
+ return AMD_SCHED_PRIORITY_UNSET;
+ default:
+ WARN(1, "Invalid context priority %d\n", amdgpu_priority);
+ return AMD_SCHED_PRIORITY_INVALID;
+ }
+}
+
+static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
+ int fd,
+ enum amd_sched_priority priority)
+{
+ struct file *filp = fcheck(fd);
+ struct drm_file *file;
+ struct pid *pid;
+ struct amdgpu_fpriv *fpriv;
+ struct amdgpu_ctx *ctx;
+ uint32_t id;
+
+ if (!filp)
+ return -EINVAL;
+
+ pid = get_pid(((struct drm_file *)filp->private_data)->pid);
+
+ mutex_lock(&adev->ddev->filelist_mutex);
+ list_for_each_entry(file, &adev->ddev->filelist, lhead) {
+ if (file->pid != pid)
+ continue;
+
+ fpriv = file->driver_priv;
+ idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
+ amdgpu_ctx_priority_override(ctx, priority);
+ }
+ mutex_unlock(&adev->ddev->filelist_mutex);
+
+ put_pid(pid);
+
+ return 0;
+}
+
+int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ union drm_amdgpu_sched *args = data;
+ struct amdgpu_device *adev = dev->dev_private;
+ enum amd_sched_priority priority;
+ int r;
+
+ priority = amdgpu_to_sched_priority(args->in.priority);
+ if (args->in.flags || priority == AMD_SCHED_PRIORITY_INVALID)
+ return -EINVAL;
+
+ switch (args->in.op) {
+ case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
+ r = amdgpu_sched_process_priority_override(adev,
+ args->in.fd,
+ priority);
+ break;
+ default:
+ DRM_ERROR("Invalid sched op specified: %d\n", args->in.op);
+ r = -EINVAL;
+ break;
+ }
+
+ return r;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
similarity index 72%
rename from drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h
rename to drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
index 9ef96aa..b28c067 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2017 Valve Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,16 +19,16 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
+ * Authors: Andres Rodriguez <andresx7@gmail.com>
*/
-#ifndef _EVENTINIT_H_
-#define _EVENTINIT_H_
+#ifndef __AMDGPU_SCHED_H__
+#define __AMDGPU_SCHED_H__
-#define PEM_CURRENT_POWERPLAY_FEATURE_VERSION 4
+#include <drm/drmP.h>
-void pem_init_feature_info(struct pp_eventmgr *eventmgr);
-void pem_uninit_featureInfo(struct pp_eventmgr *eventmgr);
-int pem_register_interrupts(struct pp_eventmgr *eventmgr);
-int pem_unregister_interrupts(struct pp_eventmgr *eventmgr);
+enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority);
+int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
-#endif /* _EVENTINIT_H_ */
+#endif // __AMDGPU_SCHED_H__
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index c586f44..a4bf21f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
*
* @sync: sync object to add fences from reservation object to
* @resv: reservation object with embedded fence
- * @shared: true if we should only sync to the exclusive fence
+ * @explicit_sync: true if we should only sync to the exclusive fence
*
* Sync to the fence
*/
int amdgpu_sync_resv(struct amdgpu_device *adev,
struct amdgpu_sync *sync,
struct reservation_object *resv,
- void *owner)
+ void *owner, bool explicit_sync)
{
struct reservation_object_list *flist;
struct dma_fence *f;
@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
f = reservation_object_get_excl(resv);
r = amdgpu_sync_fence(adev, sync, f);
+ if (explicit_sync)
+ return r;
+
flist = reservation_object_get_list(resv);
if (!flist || r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
index dc76879..70d7e3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
int amdgpu_sync_resv(struct amdgpu_device *adev,
struct amdgpu_sync *sync,
struct reservation_object *resv,
- void *owner);
+ void *owner,
+ bool explicit_sync);
struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
struct amdgpu_ring *ring);
struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 34c99a3..f337c316 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -15,62 +15,6 @@
#define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)
-TRACE_EVENT(amdgpu_ttm_tt_populate,
- TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address),
- TP_ARGS(adev, dma_address, phys_address),
- TP_STRUCT__entry(
- __field(uint16_t, domain)
- __field(uint8_t, bus)
- __field(uint8_t, slot)
- __field(uint8_t, func)
- __field(uint64_t, dma)
- __field(uint64_t, phys)
- ),
- TP_fast_assign(
- __entry->domain = pci_domain_nr(adev->pdev->bus);
- __entry->bus = adev->pdev->bus->number;
- __entry->slot = PCI_SLOT(adev->pdev->devfn);
- __entry->func = PCI_FUNC(adev->pdev->devfn);
- __entry->dma = dma_address;
- __entry->phys = phys_address;
- ),
- TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx",
- (unsigned)__entry->domain,
- (unsigned)__entry->bus,
- (unsigned)__entry->slot,
- (unsigned)__entry->func,
- (unsigned long long)__entry->dma,
- (unsigned long long)__entry->phys)
-);
-
-TRACE_EVENT(amdgpu_ttm_tt_unpopulate,
- TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address),
- TP_ARGS(adev, dma_address, phys_address),
- TP_STRUCT__entry(
- __field(uint16_t, domain)
- __field(uint8_t, bus)
- __field(uint8_t, slot)
- __field(uint8_t, func)
- __field(uint64_t, dma)
- __field(uint64_t, phys)
- ),
- TP_fast_assign(
- __entry->domain = pci_domain_nr(adev->pdev->bus);
- __entry->bus = adev->pdev->bus->number;
- __entry->slot = PCI_SLOT(adev->pdev->devfn);
- __entry->func = PCI_FUNC(adev->pdev->devfn);
- __entry->dma = dma_address;
- __entry->phys = phys_address;
- ),
- TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx",
- (unsigned)__entry->domain,
- (unsigned)__entry->bus,
- (unsigned)__entry->slot,
- (unsigned)__entry->func,
- (unsigned long long)__entry->dma,
- (unsigned long long)__entry->phys)
-);
-
TRACE_EVENT(amdgpu_mm_rreg,
TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
TP_ARGS(did, reg, value),
@@ -474,5 +418,5 @@ TRACE_EVENT(amdgpu_ttm_bo_move,
/* This part must be outside protection */
#undef TRACE_INCLUDE_PATH
-#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu
#include <trace/define_trace.h>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
index 89680d5..b160b95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
@@ -1,5 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright Red Hat Inc 2010.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
* Author : Dave Airlie <airlied@redhat.com>
*/
#include <drm/drmP.h>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d792959..ad5bf86 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -42,7 +42,9 @@
#include <linux/swap.h>
#include <linux/pagemap.h>
#include <linux/debugfs.h>
+#include <linux/iommu.h>
#include "amdgpu.h"
+#include "amdgpu_object.h"
#include "amdgpu_trace.h"
#include "bif/bif_4_1_d.h"
@@ -208,7 +210,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
placement->num_busy_placement = 1;
return;
}
- abo = container_of(bo, struct amdgpu_bo, tbo);
+ abo = ttm_to_amdgpu_bo(bo);
switch (bo->mem.mem_type) {
case TTM_PL_VRAM:
if (adev->mman.buffer_funcs &&
@@ -256,7 +258,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
{
- struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
+ struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
if (amdgpu_ttm_tt_get_usermm(bo->ttm))
return -EPERM;
@@ -288,97 +290,177 @@ static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
return addr;
}
-static int amdgpu_move_blit(struct ttm_buffer_object *bo,
- bool evict, bool no_wait_gpu,
- struct ttm_mem_reg *new_mem,
- struct ttm_mem_reg *old_mem)
+/**
+ * amdgpu_find_mm_node - Helper function finds the drm_mm_node
+ * corresponding to @offset. It also modifies the offset to be
+ * within the drm_mm_node returned
+ */
+static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
+ unsigned long *offset)
{
- struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
+ struct drm_mm_node *mm_node = mem->mm_node;
+
+ while (*offset >= (mm_node->size << PAGE_SHIFT)) {
+ *offset -= (mm_node->size << PAGE_SHIFT);
+ ++mm_node;
+ }
+ return mm_node;
+}
+
+/**
+ * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
+ *
+ * The function copies @size bytes from {src->mem + src->offset} to
+ * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
+ * move and different for a BO to BO copy.
+ *
+ * @f: Returns the last fence if multiple jobs are submitted.
+ */
+int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+ struct amdgpu_copy_mem *src,
+ struct amdgpu_copy_mem *dst,
+ uint64_t size,
+ struct reservation_object *resv,
+ struct dma_fence **f)
+{
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
-
- struct drm_mm_node *old_mm, *new_mm;
- uint64_t old_start, old_size, new_start, new_size;
- unsigned long num_pages;
+ struct drm_mm_node *src_mm, *dst_mm;
+ uint64_t src_node_start, dst_node_start, src_node_size,
+ dst_node_size, src_page_offset, dst_page_offset;
struct dma_fence *fence = NULL;
- int r;
-
- BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
+ int r = 0;
+ const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
+ AMDGPU_GPU_PAGE_SIZE);
if (!ring->ready) {
DRM_ERROR("Trying to move memory with ring turned off.\n");
return -EINVAL;
}
- old_mm = old_mem->mm_node;
- old_size = old_mm->size;
- old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
+ src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
+ src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
+ src->offset;
+ src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
+ src_page_offset = src_node_start & (PAGE_SIZE - 1);
- new_mm = new_mem->mm_node;
- new_size = new_mm->size;
- new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
+ dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
+ dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
+ dst->offset;
+ dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
+ dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
- num_pages = new_mem->num_pages;
mutex_lock(&adev->mman.gtt_window_lock);
- while (num_pages) {
- unsigned long cur_pages = min(min(old_size, new_size),
- (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
- uint64_t from = old_start, to = new_start;
+
+ while (size) {
+ unsigned long cur_size;
+ uint64_t from = src_node_start, to = dst_node_start;
struct dma_fence *next;
- if (old_mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_is_allocated(old_mem)) {
- r = amdgpu_map_buffer(bo, old_mem, cur_pages,
- old_start, 0, ring, &from);
+ /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
+ * begins at an offset, then adjust the size accordingly
+ */
+ cur_size = min3(min(src_node_size, dst_node_size), size,
+ GTT_MAX_BYTES);
+ if (cur_size + src_page_offset > GTT_MAX_BYTES ||
+ cur_size + dst_page_offset > GTT_MAX_BYTES)
+ cur_size -= max(src_page_offset, dst_page_offset);
+
+ /* Map only what needs to be accessed. Map src to window 0 and
+ * dst to window 1
+ */
+ if (src->mem->mem_type == TTM_PL_TT &&
+ !amdgpu_gtt_mgr_is_allocated(src->mem)) {
+ r = amdgpu_map_buffer(src->bo, src->mem,
+ PFN_UP(cur_size + src_page_offset),
+ src_node_start, 0, ring,
+ &from);
if (r)
goto error;
+ /* Adjust the offset because amdgpu_map_buffer returns
+ * start of mapped page
+ */
+ from += src_page_offset;
}
- if (new_mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_is_allocated(new_mem)) {
- r = amdgpu_map_buffer(bo, new_mem, cur_pages,
- new_start, 1, ring, &to);
+ if (dst->mem->mem_type == TTM_PL_TT &&
+ !amdgpu_gtt_mgr_is_allocated(dst->mem)) {
+ r = amdgpu_map_buffer(dst->bo, dst->mem,
+ PFN_UP(cur_size + dst_page_offset),
+ dst_node_start, 1, ring,
+ &to);
if (r)
goto error;
+ to += dst_page_offset;
}
- r = amdgpu_copy_buffer(ring, from, to,
- cur_pages * PAGE_SIZE,
- bo->resv, &next, false, true);
+ r = amdgpu_copy_buffer(ring, from, to, cur_size,
+ resv, &next, false, true);
if (r)
goto error;
dma_fence_put(fence);
fence = next;
- num_pages -= cur_pages;
- if (!num_pages)
+ size -= cur_size;
+ if (!size)
break;
- old_size -= cur_pages;
- if (!old_size) {
- old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
- old_size = old_mm->size;
+ src_node_size -= cur_size;
+ if (!src_node_size) {
+ src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
+ src->mem);
+ src_node_size = (src_mm->size << PAGE_SHIFT);
} else {
- old_start += cur_pages * PAGE_SIZE;
+ src_node_start += cur_size;
+ src_page_offset = src_node_start & (PAGE_SIZE - 1);
}
-
- new_size -= cur_pages;
- if (!new_size) {
- new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
- new_size = new_mm->size;
+ dst_node_size -= cur_size;
+ if (!dst_node_size) {
+ dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
+ dst->mem);
+ dst_node_size = (dst_mm->size << PAGE_SHIFT);
} else {
- new_start += cur_pages * PAGE_SIZE;
+ dst_node_start += cur_size;
+ dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
}
}
+error:
mutex_unlock(&adev->mman.gtt_window_lock);
+ if (f)
+ *f = dma_fence_get(fence);
+ dma_fence_put(fence);
+ return r;
+}
+
+
+static int amdgpu_move_blit(struct ttm_buffer_object *bo,
+ bool evict, bool no_wait_gpu,
+ struct ttm_mem_reg *new_mem,
+ struct ttm_mem_reg *old_mem)
+{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
+ struct amdgpu_copy_mem src, dst;
+ struct dma_fence *fence = NULL;
+ int r;
+
+ src.bo = bo;
+ dst.bo = bo;
+ src.mem = old_mem;
+ dst.mem = new_mem;
+ src.offset = 0;
+ dst.offset = 0;
+
+ r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
+ new_mem->num_pages << PAGE_SHIFT,
+ bo->resv, &fence);
+ if (r)
+ goto error;
r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
dma_fence_put(fence);
return r;
error:
- mutex_unlock(&adev->mman.gtt_window_lock);
-
if (fence)
dma_fence_wait(fence, false);
dma_fence_put(fence);
@@ -483,7 +565,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo,
int r;
/* Can't move a pinned BO */
- abo = container_of(bo, struct amdgpu_bo, tbo);
+ abo = ttm_to_amdgpu_bo(bo);
if (WARN_ON_ONCE(abo->pin_count > 0))
return -EINVAL;
@@ -581,13 +663,12 @@ static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_re
static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
unsigned long page_offset)
{
- struct drm_mm_node *mm = bo->mem.mm_node;
- uint64_t size = mm->size;
- uint64_t offset = page_offset;
+ struct drm_mm_node *mm;
+ unsigned long offset = (page_offset << PAGE_SHIFT);
- page_offset = do_div(offset, size);
- mm += offset;
- return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
+ mm = amdgpu_find_mm_node(&bo->mem, &offset);
+ return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
+ (offset >> PAGE_SHIFT);
}
/*
@@ -608,6 +689,7 @@ struct amdgpu_ttm_tt {
spinlock_t guptasklock;
struct list_head guptasks;
atomic_t mmu_invalidations;
+ uint32_t last_set_pages;
struct list_head list;
};
@@ -621,6 +703,8 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
flags |= FOLL_WRITE;
+ down_read(¤t->mm->mmap_sem);
+
if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
/* check that we only use anonymous memory
to prevent problems with writeback */
@@ -628,8 +712,10 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
struct vm_area_struct *vma;
vma = find_vma(gtt->usermm, gtt->userptr);
- if (!vma || vma->vm_file || vma->vm_end < end)
+ if (!vma || vma->vm_file || vma->vm_end < end) {
+ up_read(¤t->mm->mmap_sem);
return -EPERM;
+ }
}
do {
@@ -656,42 +742,44 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
} while (pinned < ttm->num_pages);
+ up_read(¤t->mm->mmap_sem);
return 0;
release_pages:
release_pages(pages, pinned);
+ up_read(¤t->mm->mmap_sem);
return r;
}
-static void amdgpu_trace_dma_map(struct ttm_tt *ttm)
+void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
{
- struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;
unsigned i;
- if (unlikely(trace_amdgpu_ttm_tt_populate_enabled())) {
- for (i = 0; i < ttm->num_pages; i++) {
- trace_amdgpu_ttm_tt_populate(
- adev,
- gtt->ttm.dma_address[i],
- page_to_phys(ttm->pages[i]));
- }
+ gtt->last_set_pages = atomic_read(>t->mmu_invalidations);
+ for (i = 0; i < ttm->num_pages; ++i) {
+ if (ttm->pages[i])
+ put_page(ttm->pages[i]);
+
+ ttm->pages[i] = pages ? pages[i] : NULL;
}
}
-static void amdgpu_trace_dma_unmap(struct ttm_tt *ttm)
+void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
{
- struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;
unsigned i;
- if (unlikely(trace_amdgpu_ttm_tt_unpopulate_enabled())) {
- for (i = 0; i < ttm->num_pages; i++) {
- trace_amdgpu_ttm_tt_unpopulate(
- adev,
- gtt->ttm.dma_address[i],
- page_to_phys(ttm->pages[i]));
- }
+ for (i = 0; i < ttm->num_pages; ++i) {
+ struct page *page = ttm->pages[i];
+
+ if (!page)
+ continue;
+
+ if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
+ set_page_dirty(page);
+
+ mark_page_accessed(page);
}
}
@@ -721,8 +809,6 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
gtt->ttm.dma_address, ttm->num_pages);
- amdgpu_trace_dma_map(ttm);
-
return 0;
release_sg:
@@ -734,7 +820,6 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;
- struct sg_page_iter sg_iter;
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
@@ -747,16 +832,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
/* free the sg table and pages again */
dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
- for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
- struct page *page = sg_page_iter_page(&sg_iter);
- if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
- set_page_dirty(page);
-
- mark_page_accessed(page);
- put_page(page);
- }
-
- amdgpu_trace_dma_unmap(ttm);
+ amdgpu_ttm_tt_mark_user_pages(ttm);
sg_free_table(ttm->sg);
}
@@ -818,7 +894,6 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_tt *ttm = bo->ttm;
struct ttm_mem_reg tmp;
-
struct ttm_placement placement;
struct ttm_place placements;
int r;
@@ -834,7 +909,8 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
placement.busy_placement = &placements;
placements.fpfn = 0;
placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
- placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
+ placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
+ TTM_PL_FLAG_TT;
r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
if (unlikely(r))
@@ -941,8 +1017,6 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
struct amdgpu_ttm_tt *gtt = (void *)ttm;
- unsigned i;
- int r;
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
if (ttm->state != tt_unpopulated)
@@ -962,52 +1036,26 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
gtt->ttm.dma_address, ttm->num_pages);
ttm->state = tt_unbound;
- r = 0;
- goto trace_mappings;
+ return 0;
}
#ifdef CONFIG_SWIOTLB
if (swiotlb_nr_tbl()) {
- r = ttm_dma_populate(>t->ttm, adev->dev);
- goto trace_mappings;
+ return ttm_dma_populate(>t->ttm, adev->dev);
}
#endif
- r = ttm_pool_populate(ttm);
- if (r) {
- return r;
- }
-
- for (i = 0; i < ttm->num_pages; i++) {
- gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
- 0, PAGE_SIZE,
- PCI_DMA_BIDIRECTIONAL);
- if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
- while (i--) {
- pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
- PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- gtt->ttm.dma_address[i] = 0;
- }
- ttm_pool_unpopulate(ttm);
- return -EFAULT;
- }
- }
-
- r = 0;
-trace_mappings:
- if (likely(!r))
- amdgpu_trace_dma_map(ttm);
- return r;
+ return ttm_populate_and_map_pages(adev->dev, >t->ttm);
}
static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
{
struct amdgpu_device *adev;
struct amdgpu_ttm_tt *gtt = (void *)ttm;
- unsigned i;
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
if (gtt && gtt->userptr) {
+ amdgpu_ttm_tt_set_user_pages(ttm, NULL);
kfree(ttm->sg);
ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
return;
@@ -1018,8 +1066,6 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
adev = amdgpu_ttm_adev(ttm->bdev);
- amdgpu_trace_dma_unmap(ttm);
-
#ifdef CONFIG_SWIOTLB
if (swiotlb_nr_tbl()) {
ttm_dma_unpopulate(>t->ttm, adev->dev);
@@ -1027,14 +1073,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
}
#endif
- for (i = 0; i < ttm->num_pages; i++) {
- if (gtt->ttm.dma_address[i]) {
- pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
- PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- }
- }
-
- ttm_pool_unpopulate(ttm);
+ ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
}
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
@@ -1051,6 +1090,7 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
spin_lock_init(>t->guptasklock);
INIT_LIST_HEAD(>t->guptasks);
atomic_set(>t->mmu_invalidations, 0);
+ gtt->last_set_pages = 0;
return 0;
}
@@ -1103,6 +1143,16 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
return prev_invalidated != *last_invalidated;
}
+bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
+{
+ struct amdgpu_ttm_tt *gtt = (void *)ttm;
+
+ if (gtt == NULL || !gtt->userptr)
+ return false;
+
+ return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages;
+}
+
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
{
struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -1143,9 +1193,6 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
unsigned long num_pages = bo->mem.num_pages;
struct drm_mm_node *node = bo->mem.mm_node;
- if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
- return ttm_bo_eviction_valuable(bo, place);
-
switch (bo->mem.mem_type) {
case TTM_PL_TT:
return true;
@@ -1160,7 +1207,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
num_pages -= node->size;
++node;
}
- break;
+ return false;
default:
break;
@@ -1173,9 +1220,9 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
unsigned long offset,
void *buf, int len, int write)
{
- struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
+ struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
- struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
+ struct drm_mm_node *nodes;
uint32_t value = 0;
int ret = 0;
uint64_t pos;
@@ -1184,10 +1231,7 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
if (bo->mem.mem_type != TTM_PL_VRAM)
return -EIO;
- while (offset >= (nodes->size << PAGE_SHIFT)) {
- offset -= nodes->size << PAGE_SHIFT;
- ++nodes;
- }
+ nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
pos = (nodes->start << PAGE_SHIFT) + offset;
while (len && pos < adev->mc.mc_vram_size) {
@@ -1202,14 +1246,14 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
}
spin_lock_irqsave(&adev->mmio_idx_lock, flags);
- WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
- WREG32(mmMM_INDEX_HI, aligned_pos >> 31);
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
+ WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
if (!write || mask != 0xffffffff)
- value = RREG32(mmMM_DATA);
+ value = RREG32_NO_KIQ(mmMM_DATA);
if (write) {
value &= ~mask;
value |= (*(uint32_t *)buf << shift) & mask;
- WREG32(mmMM_DATA, value);
+ WREG32_NO_KIQ(mmMM_DATA, value);
}
spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
if (!write) {
@@ -1286,6 +1330,15 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
/* Change the size here instead of the init above so only lpfn is affected */
amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
+ /*
+ *The reserved vram for firmware must be pinned to the specified
+ *place on the VRAM, so reserve it early.
+ */
+ r = amdgpu_fw_reserve_vram_init(adev);
+ if (r) {
+ return r;
+ }
+
r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&adev->stolen_vga_memory,
@@ -1510,7 +1563,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
job->vm_needs_flush = vm_needs_flush;
if (resv) {
r = amdgpu_sync_resv(adev, &job->sync, resv,
- AMDGPU_FENCE_OWNER_UNDEFINED);
+ AMDGPU_FENCE_OWNER_UNDEFINED,
+ false);
if (r) {
DRM_ERROR("sync failed (%d).\n", r);
goto error_free;
@@ -1557,8 +1611,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
struct dma_fence **fence)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/
- uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
+ uint32_t max_bytes = 8 *
+ adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
struct drm_mm_node *mm_node;
@@ -1590,8 +1644,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
++mm_node;
}
- /* 10 double words for each SDMA_OP_PTEPDE cmd */
- num_dw = num_loops * 10;
+ /* num of dwords for each SDMA_OP_PTEPDE cmd */
+ num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
/* for IB padding */
num_dw += 64;
@@ -1602,7 +1656,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
if (resv) {
r = amdgpu_sync_resv(adev, &job->sync, resv,
- AMDGPU_FENCE_OWNER_UNDEFINED);
+ AMDGPU_FENCE_OWNER_UNDEFINED, false);
if (r) {
DRM_ERROR("sync failed (%d).\n", r);
goto error_free;
@@ -1697,9 +1751,9 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
return result;
spin_lock_irqsave(&adev->mmio_idx_lock, flags);
- WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
- WREG32(mmMM_INDEX_HI, *pos >> 31);
- value = RREG32(mmMM_DATA);
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
+ WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
+ value = RREG32_NO_KIQ(mmMM_DATA);
spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
r = put_user(value, (uint32_t *)buf);
@@ -1715,10 +1769,50 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
return result;
}
+static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ if (*pos >= adev->mc.mc_vram_size)
+ return -ENXIO;
+
+ while (size) {
+ unsigned long flags;
+ uint32_t value;
+
+ if (*pos >= adev->mc.mc_vram_size)
+ return result;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
+ WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
+ WREG32_NO_KIQ(mmMM_DATA, value);
+ spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
static const struct file_operations amdgpu_ttm_vram_fops = {
.owner = THIS_MODULE,
.read = amdgpu_ttm_vram_read,
- .llseek = default_llseek
+ .write = amdgpu_ttm_vram_write,
+ .llseek = default_llseek,
};
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
@@ -1770,6 +1864,53 @@ static const struct file_operations amdgpu_ttm_gtt_fops = {
#endif
+static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ int r;
+ uint64_t phys;
+ struct iommu_domain *dom;
+
+ // always return 8 bytes
+ if (size != 8)
+ return -EINVAL;
+
+ // only accept page addresses
+ if (*pos & 0xFFF)
+ return -EINVAL;
+
+ dom = iommu_get_domain_for_dev(adev->dev);
+ if (dom)
+ phys = iommu_iova_to_phys(dom, *pos);
+ else
+ phys = *pos;
+
+ r = copy_to_user(buf, &phys, 8);
+ if (r)
+ return -EFAULT;
+
+ return 8;
+}
+
+static const struct file_operations amdgpu_ttm_iova_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_iova_to_phys_read,
+ .llseek = default_llseek
+};
+
+static const struct {
+ char *name;
+ const struct file_operations *fops;
+ int domain;
+} ttm_debugfs_entries[] = {
+ { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
+ { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
+#endif
+ { "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM },
+};
+
#endif
static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
@@ -1780,22 +1921,21 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
struct drm_minor *minor = adev->ddev->primary;
struct dentry *ent, *root = minor->debugfs_root;
- ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
- adev, &amdgpu_ttm_vram_fops);
- if (IS_ERR(ent))
- return PTR_ERR(ent);
- i_size_write(ent->d_inode, adev->mc.mc_vram_size);
- adev->mman.vram = ent;
+ for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
+ ent = debugfs_create_file(
+ ttm_debugfs_entries[count].name,
+ S_IFREG | S_IRUGO, root,
+ adev,
+ ttm_debugfs_entries[count].fops);
+ if (IS_ERR(ent))
+ return PTR_ERR(ent);
+ if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
+ i_size_write(ent->d_inode, adev->mc.mc_vram_size);
+ else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
+ i_size_write(ent->d_inode, adev->mc.gart_size);
+ adev->mman.debugfs_entries[count] = ent;
+ }
-#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
- ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
- adev, &amdgpu_ttm_gtt_fops);
- if (IS_ERR(ent))
- return PTR_ERR(ent);
- i_size_write(ent->d_inode, adev->mc.gart_size);
- adev->mman.gtt = ent;
-
-#endif
count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
#ifdef CONFIG_SWIOTLB
@@ -1805,7 +1945,6 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
#else
-
return 0;
#endif
}
@@ -1813,14 +1952,9 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
+ unsigned i;
- debugfs_remove(adev->mman.vram);
- adev->mman.vram = NULL;
-
-#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
- debugfs_remove(adev->mman.gtt);
- adev->mman.gtt = NULL;
-#endif
-
+ for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
+ debugfs_remove(adev->mman.debugfs_entries[i]);
#endif
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 43093bf..abd4084 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -24,6 +24,7 @@
#ifndef __AMDGPU_TTM_H__
#define __AMDGPU_TTM_H__
+#include "amdgpu.h"
#include "gpu_scheduler.h"
#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
@@ -45,8 +46,7 @@ struct amdgpu_mman {
bool initialized;
#if defined(CONFIG_DEBUG_FS)
- struct dentry *vram;
- struct dentry *gtt;
+ struct dentry *debugfs_entries[8];
#endif
/* buffer handling */
@@ -58,6 +58,12 @@ struct amdgpu_mman {
struct amd_sched_entity entity;
};
+struct amdgpu_copy_mem {
+ struct ttm_buffer_object *bo;
+ struct ttm_mem_reg *mem;
+ unsigned long offset;
+};
+
extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
@@ -72,6 +78,12 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
struct reservation_object *resv,
struct dma_fence **fence, bool direct_submit,
bool vm_needs_flush);
+int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+ struct amdgpu_copy_mem *src,
+ struct amdgpu_copy_mem *dst,
+ uint64_t size,
+ struct reservation_object *resv,
+ struct dma_fence **f);
int amdgpu_fill_buffer(struct amdgpu_bo *bo,
uint64_t src_data,
struct reservation_object *resv,
@@ -82,4 +94,20 @@ bool amdgpu_ttm_is_bound(struct ttm_tt *ttm);
int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem);
int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
+int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
+void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
+void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm);
+int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
+ uint32_t flags);
+bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
+struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
+bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
+ unsigned long end);
+bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
+ int *last_invalidated);
+bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
+bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
+ struct ttm_mem_reg *mem);
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 36c7633..6564902 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -270,12 +270,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
else
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
- if (!load_type)
- return AMDGPU_FW_LOAD_DIRECT;
- else
- return AMDGPU_FW_LOAD_PSP;
case CHIP_RAVEN:
- if (load_type != 2)
+ if (!load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
@@ -364,8 +360,6 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
struct amdgpu_bo **bo = &adev->firmware.fw_buf;
- uint64_t fw_mc_addr;
- void *fw_buf_ptr = NULL;
uint64_t fw_offset = 0;
int i, err;
struct amdgpu_firmware_info *ucode = NULL;
@@ -376,37 +370,39 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
return 0;
}
- err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
- amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
- NULL, NULL, 0, bo);
- if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
- goto failed;
+ if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) {
+ err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
+ amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
+ NULL, NULL, 0, bo);
+ if (err) {
+ dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
+ goto failed;
+ }
+
+ err = amdgpu_bo_reserve(*bo, false);
+ if (err) {
+ dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
+ goto failed_reserve;
+ }
+
+ err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
+ &adev->firmware.fw_buf_mc);
+ if (err) {
+ dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
+ goto failed_pin;
+ }
+
+ err = amdgpu_bo_kmap(*bo, &adev->firmware.fw_buf_ptr);
+ if (err) {
+ dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
+ goto failed_kmap;
+ }
+
+ amdgpu_bo_unreserve(*bo);
}
- err = amdgpu_bo_reserve(*bo, false);
- if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
- goto failed_reserve;
- }
-
- err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- &fw_mc_addr);
- if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
- goto failed_pin;
- }
-
- err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
- if (err) {
- dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
- goto failed_kmap;
- }
-
- amdgpu_bo_unreserve(*bo);
-
- memset(fw_buf_ptr, 0, adev->firmware.fw_size);
+ memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
/*
* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
@@ -425,14 +421,14 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
ucode = &adev->firmware.ucode[i];
if (ucode->fw) {
header = (const struct common_firmware_header *)ucode->fw->data;
- amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset,
- (void *)((uint8_t *)fw_buf_ptr + fw_offset));
+ amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
+ adev->firmware.fw_buf_ptr + fw_offset);
if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
const struct gfx_firmware_header_v1_0 *cp_hdr;
cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
- amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
- fw_buf_ptr + fw_offset);
+ amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
+ adev->firmware.fw_buf_ptr + fw_offset);
fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
}
fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e19928d..e8bd50c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -269,6 +269,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
{
+ int i;
kfree(adev->uvd.saved_bo);
amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
@@ -279,6 +280,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
amdgpu_ring_fini(&adev->uvd.ring);
+ for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
+ amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
+
release_firmware(adev->uvd.fw);
return 0;
@@ -410,10 +414,10 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
int r = 0;
- mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
- if (mapping == NULL) {
+ r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
+ if (r) {
DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
- return -EINVAL;
+ return r;
}
if (!ctx->parser->adev->uvd.address_64_bit) {
@@ -737,10 +741,10 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
int r;
- mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
- if (mapping == NULL) {
+ r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
+ if (r) {
DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
- return -EINVAL;
+ return r;
}
start = amdgpu_bo_gpu_offset(bo);
@@ -917,10 +921,6 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
return -EINVAL;
}
- r = amdgpu_cs_sysvm_access_required(parser);
- if (r)
- return r;
-
ctx.parser = parser;
ctx.buf_sizes = buf_sizes;
ctx.ib_idx = ib_idx;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index c855366..2918de2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -559,6 +559,7 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
struct amdgpu_bo_va_mapping *mapping;
struct amdgpu_bo *bo;
uint64_t addr;
+ int r;
if (index == 0xffffffff)
index = 0;
@@ -567,11 +568,11 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
addr += ((uint64_t)size) * ((uint64_t)index);
- mapping = amdgpu_cs_find_mapping(p, addr, &bo);
- if (mapping == NULL) {
+ r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
+ if (r) {
DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
addr, lo, hi, size, index);
- return -EINVAL;
+ return r;
}
if ((addr + (uint64_t)size) >
@@ -647,15 +648,11 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
uint32_t allocated = 0;
uint32_t tmp, handle = 0;
uint32_t *size = &tmp;
- int i, r, idx = 0;
+ int i, r = 0, idx = 0;
p->job->vm = NULL;
ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
- r = amdgpu_cs_sysvm_access_required(p);
- if (r)
- return r;
-
while (idx < ib->length_dw) {
uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
index 45ac918..7f70979 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
@@ -25,30 +25,26 @@
#include "amdgpu_vf_error.h"
#include "mxgpu_ai.h"
-#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
-
-/* struct error_entry - amdgpu VF error information. */
-struct amdgpu_vf_error_buffer {
- int read_count;
- int write_count;
- uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
- uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
- uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
-};
-
-struct amdgpu_vf_error_buffer admgpu_vf_errors;
-
-
-void amdgpu_vf_error_put(uint16_t sub_error_code, uint16_t error_flags, uint64_t error_data)
+void amdgpu_vf_error_put(struct amdgpu_device *adev,
+ uint16_t sub_error_code,
+ uint16_t error_flags,
+ uint64_t error_data)
{
int index;
- uint16_t error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, sub_error_code);
+ uint16_t error_code;
- index = admgpu_vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
- admgpu_vf_errors.code [index] = error_code;
- admgpu_vf_errors.flags [index] = error_flags;
- admgpu_vf_errors.data [index] = error_data;
- admgpu_vf_errors.write_count ++;
+ if (!amdgpu_sriov_vf(adev))
+ return;
+
+ error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, sub_error_code);
+
+ mutex_lock(&adev->virt.vf_errors.lock);
+ index = adev->virt.vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
+ adev->virt.vf_errors.code [index] = error_code;
+ adev->virt.vf_errors.flags [index] = error_flags;
+ adev->virt.vf_errors.data [index] = error_data;
+ adev->virt.vf_errors.write_count ++;
+ mutex_unlock(&adev->virt.vf_errors.lock);
}
@@ -58,7 +54,8 @@ void amdgpu_vf_error_trans_all(struct amdgpu_device *adev)
u32 data1, data2, data3;
int index;
- if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || (!adev->virt.ops) || (!adev->virt.ops->trans_msg)) {
+ if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) ||
+ (!adev->virt.ops) || (!adev->virt.ops->trans_msg)) {
return;
}
/*
@@ -68,18 +65,22 @@ void amdgpu_vf_error_trans_all(struct amdgpu_device *adev)
return;
}
*/
+
+ mutex_lock(&adev->virt.vf_errors.lock);
/* The errors are overlay of array, correct read_count as full. */
- if (admgpu_vf_errors.write_count - admgpu_vf_errors.read_count > AMDGPU_VF_ERROR_ENTRY_SIZE) {
- admgpu_vf_errors.read_count = admgpu_vf_errors.write_count - AMDGPU_VF_ERROR_ENTRY_SIZE;
+ if (adev->virt.vf_errors.write_count - adev->virt.vf_errors.read_count > AMDGPU_VF_ERROR_ENTRY_SIZE) {
+ adev->virt.vf_errors.read_count = adev->virt.vf_errors.write_count - AMDGPU_VF_ERROR_ENTRY_SIZE;
}
- while (admgpu_vf_errors.read_count < admgpu_vf_errors.write_count) {
- index =admgpu_vf_errors.read_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
- data1 = AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX (admgpu_vf_errors.code[index], admgpu_vf_errors.flags[index]);
- data2 = admgpu_vf_errors.data[index] & 0xFFFFFFFF;
- data3 = (admgpu_vf_errors.data[index] >> 32) & 0xFFFFFFFF;
+ while (adev->virt.vf_errors.read_count < adev->virt.vf_errors.write_count) {
+ index =adev->virt.vf_errors.read_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
+ data1 = AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX(adev->virt.vf_errors.code[index],
+ adev->virt.vf_errors.flags[index]);
+ data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF;
+ data3 = (adev->virt.vf_errors.data[index] >> 32) & 0xFFFFFFFF;
adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
- admgpu_vf_errors.read_count ++;
+ adev->virt.vf_errors.read_count ++;
}
+ mutex_unlock(&adev->virt.vf_errors.lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.h
index 2a3278e..6436bd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.h
@@ -56,7 +56,10 @@ enum AMDGIM_ERROR_CATEGORY {
AMDGIM_ERROR_CATEGORY_MAX
};
-void amdgpu_vf_error_put(uint16_t sub_error_code, uint16_t error_flags, uint64_t error_data);
+void amdgpu_vf_error_put(struct amdgpu_device *adev,
+ uint16_t sub_error_code,
+ uint16_t error_flags,
+ uint64_t error_data);
void amdgpu_vf_error_trans_all (struct amdgpu_device *adev);
#endif /* __VF_ERROR_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index ab05121..6738df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,7 +22,7 @@
*/
#include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT 100000
+#define MAX_KIQ_REG_WAIT 100000000 /* in usecs */
int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
{
@@ -114,27 +114,25 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
{
signed long r;
- uint32_t val;
- struct dma_fence *f;
+ unsigned long flags;
+ uint32_t val, seq;
struct amdgpu_kiq *kiq = &adev->gfx.kiq;
struct amdgpu_ring *ring = &kiq->ring;
BUG_ON(!ring->funcs->emit_rreg);
- mutex_lock(&kiq->ring_mutex);
+ spin_lock_irqsave(&kiq->ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_rreg(ring, reg);
- amdgpu_fence_emit(ring, &f);
+ amdgpu_fence_emit_polling(ring, &seq);
amdgpu_ring_commit(ring);
- mutex_unlock(&kiq->ring_mutex);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
- r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
- dma_fence_put(f);
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
if (r < 1) {
- DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+ DRM_ERROR("wait for kiq fence error: %ld\n", r);
return ~0;
}
-
val = adev->wb.wb[adev->virt.reg_val_offs];
return val;
@@ -143,23 +141,23 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
{
signed long r;
- struct dma_fence *f;
+ unsigned long flags;
+ uint32_t seq;
struct amdgpu_kiq *kiq = &adev->gfx.kiq;
struct amdgpu_ring *ring = &kiq->ring;
BUG_ON(!ring->funcs->emit_wreg);
- mutex_lock(&kiq->ring_mutex);
+ spin_lock_irqsave(&kiq->ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_wreg(ring, reg, v);
- amdgpu_fence_emit(ring, &f);
+ amdgpu_fence_emit_polling(ring, &seq);
amdgpu_ring_commit(ring);
- mutex_unlock(&kiq->ring_mutex);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
- r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
if (r < 1)
- DRM_ERROR("wait for kiq fence error: %ld.\n", r);
- dma_fence_put(f);
+ DRM_ERROR("wait for kiq fence error: %ld\n", r);
}
/**
@@ -274,3 +272,80 @@ void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
(void *)&adev->virt.mm_table.cpu_addr);
adev->virt.mm_table.gpu_addr = 0;
}
+
+
+int amdgpu_virt_fw_reserve_get_checksum(void *obj,
+ unsigned long obj_size,
+ unsigned int key,
+ unsigned int chksum)
+{
+ unsigned int ret = key;
+ unsigned long i = 0;
+ unsigned char *pos;
+
+ pos = (char *)obj;
+ /* calculate checksum */
+ for (i = 0; i < obj_size; ++i)
+ ret += *(pos + i);
+ /* minus the chksum itself */
+ pos = (char *)&chksum;
+ for (i = 0; i < sizeof(chksum); ++i)
+ ret -= *(pos + i);
+ return ret;
+}
+
+void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
+{
+ uint32_t pf2vf_ver = 0;
+ uint32_t pf2vf_size = 0;
+ uint32_t checksum = 0;
+ uint32_t checkval;
+ char *str;
+
+ adev->virt.fw_reserve.p_pf2vf = NULL;
+ adev->virt.fw_reserve.p_vf2pf = NULL;
+
+ if (adev->fw_vram_usage.va != NULL) {
+ adev->virt.fw_reserve.p_pf2vf =
+ (struct amdgim_pf2vf_info_header *)(
+ adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
+ pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version;
+ AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
+ AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
+
+ /* pf2vf message must be in 4K */
+ if (pf2vf_size > 0 && pf2vf_size < 4096) {
+ checkval = amdgpu_virt_fw_reserve_get_checksum(
+ adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
+ adev->virt.fw_reserve.checksum_key, checksum);
+ if (checkval == checksum) {
+ adev->virt.fw_reserve.p_vf2pf =
+ ((void *)adev->virt.fw_reserve.p_pf2vf +
+ pf2vf_size);
+ memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
+ sizeof(amdgim_vf2pf_info));
+ AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
+ AMDGPU_FW_VRAM_VF2PF_VER);
+ AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
+ sizeof(amdgim_vf2pf_info));
+ AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
+ &str);
+#ifdef MODULE
+ if (THIS_MODULE->version != NULL)
+ strcpy(str, THIS_MODULE->version);
+ else
+#endif
+ strcpy(str, "N/A");
+ AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
+ 0);
+ AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
+ amdgpu_virt_fw_reserve_get_checksum(
+ adev->virt.fw_reserve.p_vf2pf,
+ pf2vf_size,
+ adev->virt.fw_reserve.checksum_key, 0));
+ }
+ }
+ }
+}
+
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index afcfb8b..b89d37f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -36,6 +36,18 @@ struct amdgpu_mm_table {
uint64_t gpu_addr;
};
+#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
+
+/* struct error_entry - amdgpu VF error information. */
+struct amdgpu_vf_error_buffer {
+ struct mutex lock;
+ int read_count;
+ int write_count;
+ uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
+ uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
+ uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
+};
+
/**
* struct amdgpu_virt_ops - amdgpu device virt operations
*/
@@ -46,6 +58,179 @@ struct amdgpu_virt_ops {
void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
};
+/*
+ * Firmware Reserve Frame buffer
+ */
+struct amdgpu_virt_fw_reserve {
+ struct amdgim_pf2vf_info_header *p_pf2vf;
+ struct amdgim_vf2pf_info_header *p_vf2pf;
+ unsigned int checksum_key;
+};
+/*
+ * Defination between PF and VF
+ * Structures forcibly aligned to 4 to keep the same style as PF.
+ */
+#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
+
+#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
+ (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
+
+enum AMDGIM_FEATURE_FLAG {
+ /* GIM supports feature of Error log collecting */
+ AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
+ /* GIM supports feature of loading uCodes */
+ AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
+};
+
+struct amdgim_pf2vf_info_header {
+ /* the total structure size in byte. */
+ uint32_t size;
+ /* version of this structure, written by the GIM */
+ uint32_t version;
+} __aligned(4);
+struct amdgim_pf2vf_info_v1 {
+ /* header contains size and version */
+ struct amdgim_pf2vf_info_header header;
+ /* max_width * max_height */
+ unsigned int uvd_enc_max_pixels_count;
+ /* 16x16 pixels/sec, codec independent */
+ unsigned int uvd_enc_max_bandwidth;
+ /* max_width * max_height */
+ unsigned int vce_enc_max_pixels_count;
+ /* 16x16 pixels/sec, codec independent */
+ unsigned int vce_enc_max_bandwidth;
+ /* MEC FW position in kb from the start of visible frame buffer */
+ unsigned int mecfw_kboffset;
+ /* The features flags of the GIM driver supports. */
+ unsigned int feature_flags;
+ /* use private key from mailbox 2 to create chueksum */
+ unsigned int checksum;
+} __aligned(4);
+
+struct amdgim_pf2vf_info_v2 {
+ /* header contains size and version */
+ struct amdgim_pf2vf_info_header header;
+ /* use private key from mailbox 2 to create chueksum */
+ uint32_t checksum;
+ /* The features flags of the GIM driver supports. */
+ uint32_t feature_flags;
+ /* max_width * max_height */
+ uint32_t uvd_enc_max_pixels_count;
+ /* 16x16 pixels/sec, codec independent */
+ uint32_t uvd_enc_max_bandwidth;
+ /* max_width * max_height */
+ uint32_t vce_enc_max_pixels_count;
+ /* 16x16 pixels/sec, codec independent */
+ uint32_t vce_enc_max_bandwidth;
+ /* MEC FW position in kb from the start of VF visible frame buffer */
+ uint64_t mecfw_kboffset;
+ /* MEC FW size in KB */
+ uint32_t mecfw_ksize;
+ /* UVD FW position in kb from the start of VF visible frame buffer */
+ uint64_t uvdfw_kboffset;
+ /* UVD FW size in KB */
+ uint32_t uvdfw_ksize;
+ /* VCE FW position in kb from the start of VF visible frame buffer */
+ uint64_t vcefw_kboffset;
+ /* VCE FW size in KB */
+ uint32_t vcefw_ksize;
+ uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amdgim_pf2vf_info_header)/sizeof(uint32_t)), 3)];
+} __aligned(4);
+
+
+struct amdgim_vf2pf_info_header {
+ /* the total structure size in byte. */
+ uint32_t size;
+ /*version of this structure, written by the guest */
+ uint32_t version;
+} __aligned(4);
+
+struct amdgim_vf2pf_info_v1 {
+ /* header contains size and version */
+ struct amdgim_vf2pf_info_header header;
+ /* driver version */
+ char driver_version[64];
+ /* driver certification, 1=WHQL, 0=None */
+ unsigned int driver_cert;
+ /* guest OS type and version: need a define */
+ unsigned int os_info;
+ /* in the unit of 1M */
+ unsigned int fb_usage;
+ /* guest gfx engine usage percentage */
+ unsigned int gfx_usage;
+ /* guest gfx engine health percentage */
+ unsigned int gfx_health;
+ /* guest compute engine usage percentage */
+ unsigned int compute_usage;
+ /* guest compute engine health percentage */
+ unsigned int compute_health;
+ /* guest vce engine usage percentage. 0xffff means N/A. */
+ unsigned int vce_enc_usage;
+ /* guest vce engine health percentage. 0xffff means N/A. */
+ unsigned int vce_enc_health;
+ /* guest uvd engine usage percentage. 0xffff means N/A. */
+ unsigned int uvd_enc_usage;
+ /* guest uvd engine usage percentage. 0xffff means N/A. */
+ unsigned int uvd_enc_health;
+ unsigned int checksum;
+} __aligned(4);
+
+struct amdgim_vf2pf_info_v2 {
+ /* header contains size and version */
+ struct amdgim_vf2pf_info_header header;
+ uint32_t checksum;
+ /* driver version */
+ uint8_t driver_version[64];
+ /* driver certification, 1=WHQL, 0=None */
+ uint32_t driver_cert;
+ /* guest OS type and version: need a define */
+ uint32_t os_info;
+ /* in the unit of 1M */
+ uint32_t fb_usage;
+ /* guest gfx engine usage percentage */
+ uint32_t gfx_usage;
+ /* guest gfx engine health percentage */
+ uint32_t gfx_health;
+ /* guest compute engine usage percentage */
+ uint32_t compute_usage;
+ /* guest compute engine health percentage */
+ uint32_t compute_health;
+ /* guest vce engine usage percentage. 0xffff means N/A. */
+ uint32_t vce_enc_usage;
+ /* guest vce engine health percentage. 0xffff means N/A. */
+ uint32_t vce_enc_health;
+ /* guest uvd engine usage percentage. 0xffff means N/A. */
+ uint32_t uvd_enc_usage;
+ /* guest uvd engine usage percentage. 0xffff means N/A. */
+ uint32_t uvd_enc_health;
+ uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amdgim_vf2pf_info_header)/sizeof(uint32_t)), 0)];
+} __aligned(4);
+
+#define AMDGPU_FW_VRAM_VF2PF_VER 2
+typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
+
+#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
+ do { \
+ ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
+ } while (0)
+
+#define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \
+ do { \
+ (*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
+ } while (0)
+
+#define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \
+ do { \
+ if (!adev->virt.fw_reserve.p_pf2vf) \
+ *(val) = 0; \
+ else { \
+ if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
+ *(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
+ if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
+ *(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
+ } \
+ } while (0)
+
/* GPU virtualization */
struct amdgpu_virt {
uint32_t caps;
@@ -59,6 +244,8 @@ struct amdgpu_virt {
struct work_struct flr_work;
struct amdgpu_mm_table mm_table;
const struct amdgpu_virt_ops *ops;
+ struct amdgpu_vf_error_buffer vf_errors;
+ struct amdgpu_virt_fw_reserve fw_reserve;
};
#define AMDGPU_CSA_SIZE (8 * 1024)
@@ -101,5 +288,9 @@ int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job);
int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
+int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
+ unsigned int key,
+ unsigned int chksum);
+void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index bd20ff0..c8c26f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -27,12 +27,59 @@
*/
#include <linux/dma-fence-array.h>
#include <linux/interval_tree_generic.h>
+#include <linux/idr.h>
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"
/*
+ * PASID manager
+ *
+ * PASIDs are global address space identifiers that can be shared
+ * between the GPU, an IOMMU and the driver. VMs on different devices
+ * may use the same PASID if they share the same address
+ * space. Therefore PASIDs are allocated using a global IDA. VMs are
+ * looked up from the PASID per amdgpu_device.
+ */
+static DEFINE_IDA(amdgpu_vm_pasid_ida);
+
+/**
+ * amdgpu_vm_alloc_pasid - Allocate a PASID
+ * @bits: Maximum width of the PASID in bits, must be at least 1
+ *
+ * Allocates a PASID of the given width while keeping smaller PASIDs
+ * available if possible.
+ *
+ * Returns a positive integer on success. Returns %-EINVAL if bits==0.
+ * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
+ * memory allocation failure.
+ */
+int amdgpu_vm_alloc_pasid(unsigned int bits)
+{
+ int pasid = -EINVAL;
+
+ for (bits = min(bits, 31U); bits > 0; bits--) {
+ pasid = ida_simple_get(&amdgpu_vm_pasid_ida,
+ 1U << (bits - 1), 1U << bits,
+ GFP_KERNEL);
+ if (pasid != -ENOSPC)
+ break;
+ }
+
+ return pasid;
+}
+
+/**
+ * amdgpu_vm_free_pasid - Free a PASID
+ * @pasid: PASID to free
+ */
+void amdgpu_vm_free_pasid(unsigned int pasid)
+{
+ ida_simple_remove(&amdgpu_vm_pasid_ida, pasid);
+}
+
+/*
* GPUVM
* GPUVM is similar to the legacy gart on older asics, however
* rather than there being a single global gart table
@@ -140,7 +187,7 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
struct list_head *validated,
struct amdgpu_bo_list_entry *entry)
{
- entry->robj = vm->root.bo;
+ entry->robj = vm->root.base.bo;
entry->priority = 0;
entry->tv.bo = &entry->robj->tbo;
entry->tv.shared = true;
@@ -149,61 +196,6 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
}
/**
- * amdgpu_vm_validate_layer - validate a single page table level
- *
- * @parent: parent page table level
- * @validate: callback to do the validation
- * @param: parameter for the validation callback
- *
- * Validate the page table BOs on command submission if neccessary.
- */
-static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
- int (*validate)(void *, struct amdgpu_bo *),
- void *param, bool use_cpu_for_update,
- struct ttm_bo_global *glob)
-{
- unsigned i;
- int r;
-
- if (use_cpu_for_update) {
- r = amdgpu_bo_kmap(parent->bo, NULL);
- if (r)
- return r;
- }
-
- if (!parent->entries)
- return 0;
-
- for (i = 0; i <= parent->last_entry_used; ++i) {
- struct amdgpu_vm_pt *entry = &parent->entries[i];
-
- if (!entry->bo)
- continue;
-
- r = validate(param, entry->bo);
- if (r)
- return r;
-
- spin_lock(&glob->lru_lock);
- ttm_bo_move_to_lru_tail(&entry->bo->tbo);
- if (entry->bo->shadow)
- ttm_bo_move_to_lru_tail(&entry->bo->shadow->tbo);
- spin_unlock(&glob->lru_lock);
-
- /*
- * Recurse into the sub directory. This is harmless because we
- * have only a maximum of 5 layers.
- */
- r = amdgpu_vm_validate_level(entry, validate, param,
- use_cpu_for_update, glob);
- if (r)
- return r;
- }
-
- return r;
-}
-
-/**
* amdgpu_vm_validate_pt_bos - validate the page table BOs
*
* @adev: amdgpu device pointer
@@ -217,18 +209,67 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
int (*validate)(void *p, struct amdgpu_bo *bo),
void *param)
{
- uint64_t num_evictions;
+ struct ttm_bo_global *glob = adev->mman.bdev.glob;
+ int r;
- /* We only need to validate the page tables
- * if they aren't already valid.
- */
- num_evictions = atomic64_read(&adev->num_evictions);
- if (num_evictions == vm->last_eviction_counter)
- return 0;
+ spin_lock(&vm->status_lock);
+ while (!list_empty(&vm->evicted)) {
+ struct amdgpu_vm_bo_base *bo_base;
+ struct amdgpu_bo *bo;
- return amdgpu_vm_validate_level(&vm->root, validate, param,
- vm->use_cpu_for_update,
- adev->mman.bdev.glob);
+ bo_base = list_first_entry(&vm->evicted,
+ struct amdgpu_vm_bo_base,
+ vm_status);
+ spin_unlock(&vm->status_lock);
+
+ bo = bo_base->bo;
+ BUG_ON(!bo);
+ if (bo->parent) {
+ r = validate(param, bo);
+ if (r)
+ return r;
+
+ spin_lock(&glob->lru_lock);
+ ttm_bo_move_to_lru_tail(&bo->tbo);
+ if (bo->shadow)
+ ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
+ spin_unlock(&glob->lru_lock);
+ }
+
+ if (bo->tbo.type == ttm_bo_type_kernel &&
+ vm->use_cpu_for_update) {
+ r = amdgpu_bo_kmap(bo, NULL);
+ if (r)
+ return r;
+ }
+
+ spin_lock(&vm->status_lock);
+ if (bo->tbo.type != ttm_bo_type_kernel)
+ list_move(&bo_base->vm_status, &vm->moved);
+ else
+ list_move(&bo_base->vm_status, &vm->relocated);
+ }
+ spin_unlock(&vm->status_lock);
+
+ return 0;
+}
+
+/**
+ * amdgpu_vm_ready - check VM is ready for updates
+ *
+ * @vm: VM to check
+ *
+ * Check if all VM PDs/PTs are ready for updates
+ */
+bool amdgpu_vm_ready(struct amdgpu_vm *vm)
+{
+ bool ready;
+
+ spin_lock(&vm->status_lock);
+ ready = list_empty(&vm->evicted);
+ spin_unlock(&vm->status_lock);
+
+ return ready;
}
/**
@@ -287,18 +328,19 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
AMDGPU_GEM_CREATE_SHADOW);
if (vm->pte_support_ats) {
- init_value = AMDGPU_PTE_SYSTEM;
+ init_value = AMDGPU_PTE_DEFAULT_ATC;
if (level != adev->vm_manager.num_level - 1)
init_value |= AMDGPU_PDE_PTE;
+
}
/* walk over the address space and allocate the page tables */
for (pt_idx = from; pt_idx <= to; ++pt_idx) {
- struct reservation_object *resv = vm->root.bo->tbo.resv;
+ struct reservation_object *resv = vm->root.base.bo->tbo.resv;
struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
struct amdgpu_bo *pt;
- if (!entry->bo) {
+ if (!entry->base.bo) {
r = amdgpu_bo_create(adev,
amdgpu_vm_bo_size(adev, level),
AMDGPU_GPU_PAGE_SIZE, true,
@@ -319,9 +361,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
/* Keep a reference to the root directory to avoid
* freeing them up in the wrong order.
*/
- pt->parent = amdgpu_bo_ref(vm->root.bo);
+ pt->parent = amdgpu_bo_ref(parent->base.bo);
- entry->bo = pt;
+ entry->base.vm = vm;
+ entry->base.bo = pt;
+ list_add_tail(&entry->base.bo_list, &pt->va);
+ spin_lock(&vm->status_lock);
+ list_add(&entry->base.vm_status, &vm->relocated);
+ spin_unlock(&vm->status_lock);
entry->addr = 0;
}
@@ -988,7 +1035,7 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
int r;
amdgpu_sync_create(&sync);
- amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.resv, owner);
+ amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
r = amdgpu_sync_wait(&sync, true);
amdgpu_sync_free(&sync);
@@ -1007,18 +1054,17 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
*/
static int amdgpu_vm_update_level(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
- struct amdgpu_vm_pt *parent,
- unsigned level)
+ struct amdgpu_vm_pt *parent)
{
struct amdgpu_bo *shadow;
struct amdgpu_ring *ring = NULL;
uint64_t pd_addr, shadow_addr = 0;
- uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
unsigned count = 0, pt_idx, ndw = 0;
struct amdgpu_job *job;
struct amdgpu_pte_update_params params;
struct dma_fence *fence = NULL;
+ uint32_t incr;
int r;
@@ -1027,10 +1073,10 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
memset(¶ms, 0, sizeof(params));
params.adev = adev;
- shadow = parent->bo->shadow;
+ shadow = parent->base.bo->shadow;
if (vm->use_cpu_for_update) {
- pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo);
+ pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
if (unlikely(r))
return r;
@@ -1046,7 +1092,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
/* assume the worst case */
ndw += parent->last_entry_used * 6;
- pd_addr = amdgpu_bo_gpu_offset(parent->bo);
+ pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
if (shadow) {
shadow_addr = amdgpu_bo_gpu_offset(shadow);
@@ -1066,12 +1112,17 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
/* walk over the address space and update the directory */
for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
- struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
+ struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
+ struct amdgpu_bo *bo = entry->base.bo;
uint64_t pde, pt;
if (bo == NULL)
continue;
+ spin_lock(&vm->status_lock);
+ list_del_init(&entry->base.vm_status);
+ spin_unlock(&vm->status_lock);
+
pt = amdgpu_bo_gpu_offset(bo);
pt = amdgpu_gart_get_vm_pde(adev, pt);
/* Don't update huge pages here */
@@ -1082,6 +1133,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID;
pde = pd_addr + pt_idx * 8;
+ incr = amdgpu_bo_size(bo);
if (((last_pde + 8 * count) != pde) ||
((last_pt + incr * count) != pt) ||
(count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
@@ -1109,7 +1161,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
}
if (count) {
- if (vm->root.bo->shadow)
+ if (vm->root.base.bo->shadow)
params.func(¶ms, last_shadow, last_pt,
count, incr, AMDGPU_PTE_VALID);
@@ -1122,12 +1174,13 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
amdgpu_job_free(job);
} else {
amdgpu_ring_pad_ib(ring, params.ib);
- amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
- AMDGPU_FENCE_OWNER_VM);
+ amdgpu_sync_resv(adev, &job->sync,
+ parent->base.bo->tbo.resv,
+ AMDGPU_FENCE_OWNER_VM, false);
if (shadow)
amdgpu_sync_resv(adev, &job->sync,
shadow->tbo.resv,
- AMDGPU_FENCE_OWNER_VM);
+ AMDGPU_FENCE_OWNER_VM, false);
WARN_ON(params.ib->length_dw > ndw);
r = amdgpu_job_submit(job, ring, &vm->entity,
@@ -1135,26 +1188,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
if (r)
goto error_free;
- amdgpu_bo_fence(parent->bo, fence, true);
- dma_fence_put(vm->last_dir_update);
- vm->last_dir_update = dma_fence_get(fence);
- dma_fence_put(fence);
+ amdgpu_bo_fence(parent->base.bo, fence, true);
+ dma_fence_put(vm->last_update);
+ vm->last_update = fence;
}
}
- /*
- * Recurse into the subdirectories. This recursion is harmless because
- * we only have a maximum of 5 layers.
- */
- for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
- struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
-
- if (!entry->bo)
- continue;
-
- r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
- if (r)
- return r;
- }
return 0;
@@ -1170,7 +1208,8 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
*
* Mark all PD level as invalid after an error.
*/
-static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent)
+static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm,
+ struct amdgpu_vm_pt *parent)
{
unsigned pt_idx;
@@ -1181,11 +1220,15 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent)
for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
- if (!entry->bo)
+ if (!entry->base.bo)
continue;
entry->addr = ~0ULL;
- amdgpu_vm_invalidate_level(entry);
+ spin_lock(&vm->status_lock);
+ if (list_empty(&entry->base.vm_status))
+ list_add(&entry->base.vm_status, &vm->relocated);
+ spin_unlock(&vm->status_lock);
+ amdgpu_vm_invalidate_level(vm, entry);
}
}
@@ -1201,11 +1244,40 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent)
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
{
- int r;
+ int r = 0;
- r = amdgpu_vm_update_level(adev, vm, &vm->root, 0);
- if (r)
- amdgpu_vm_invalidate_level(&vm->root);
+ spin_lock(&vm->status_lock);
+ while (!list_empty(&vm->relocated)) {
+ struct amdgpu_vm_bo_base *bo_base;
+ struct amdgpu_bo *bo;
+
+ bo_base = list_first_entry(&vm->relocated,
+ struct amdgpu_vm_bo_base,
+ vm_status);
+ spin_unlock(&vm->status_lock);
+
+ bo = bo_base->bo->parent;
+ if (bo) {
+ struct amdgpu_vm_bo_base *parent;
+ struct amdgpu_vm_pt *pt;
+
+ parent = list_first_entry(&bo->va,
+ struct amdgpu_vm_bo_base,
+ bo_list);
+ pt = container_of(parent, struct amdgpu_vm_pt, base);
+
+ r = amdgpu_vm_update_level(adev, vm, pt);
+ if (r) {
+ amdgpu_vm_invalidate_level(vm, &vm->root);
+ return r;
+ }
+ spin_lock(&vm->status_lock);
+ } else {
+ spin_lock(&vm->status_lock);
+ list_del_init(&bo_base->vm_status);
+ }
+ }
+ spin_unlock(&vm->status_lock);
if (vm->use_cpu_for_update) {
/* Flush HDP */
@@ -1236,7 +1308,7 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
*entry = &p->vm->root;
while ((*entry)->entries) {
idx = addr >> (p->adev->vm_manager.block_size * level--);
- idx %= amdgpu_bo_size((*entry)->bo) / 8;
+ idx %= amdgpu_bo_size((*entry)->base.bo) / 8;
*parent = *entry;
*entry = &(*entry)->entries[idx];
}
@@ -1272,7 +1344,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
p->src ||
!(flags & AMDGPU_PTE_VALID)) {
- dst = amdgpu_bo_gpu_offset(entry->bo);
+ dst = amdgpu_bo_gpu_offset(entry->base.bo);
dst = amdgpu_gart_get_vm_pde(p->adev, dst);
flags = AMDGPU_PTE_VALID;
} else {
@@ -1298,18 +1370,18 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
tmp = p->pages_addr;
p->pages_addr = NULL;
- pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo);
+ pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
pde = pd_addr + (entry - parent->entries) * 8;
amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
p->pages_addr = tmp;
} else {
- if (parent->bo->shadow) {
- pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow);
+ if (parent->base.bo->shadow) {
+ pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
pde = pd_addr + (entry - parent->entries) * 8;
amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
}
- pd_addr = amdgpu_bo_gpu_offset(parent->bo);
+ pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
pde = pd_addr + (entry - parent->entries) * 8;
amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
}
@@ -1360,7 +1432,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
if (entry->addr & AMDGPU_PDE_PTE)
continue;
- pt = entry->bo;
+ pt = entry->base.bo;
if (use_cpu_update) {
pe_start = (unsigned long)amdgpu_bo_kptr(pt);
} else {
@@ -1396,8 +1468,6 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags)
{
- int r;
-
/**
* The MC L1 TLB supports variable sized pages, based on a fragment
* field in the PTE. When this field is set to a non-zero value, page
@@ -1416,39 +1486,38 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
* Userspace can support this by aligning virtual base address and
* allocation size to the fragment size.
*/
- unsigned pages_per_frag = params->adev->vm_manager.fragment_size;
- uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag);
- uint64_t frag_align = 1 << pages_per_frag;
-
- uint64_t frag_start = ALIGN(start, frag_align);
- uint64_t frag_end = end & ~(frag_align - 1);
+ unsigned max_frag = params->adev->vm_manager.fragment_size;
+ int r;
/* system pages are non continuously */
- if (params->src || !(flags & AMDGPU_PTE_VALID) ||
- (frag_start >= frag_end))
+ if (params->src || !(flags & AMDGPU_PTE_VALID))
return amdgpu_vm_update_ptes(params, start, end, dst, flags);
- /* handle the 4K area at the beginning */
- if (start != frag_start) {
- r = amdgpu_vm_update_ptes(params, start, frag_start,
- dst, flags);
+ while (start != end) {
+ uint64_t frag_flags, frag_end;
+ unsigned frag;
+
+ /* This intentionally wraps around if no bit is set */
+ frag = min((unsigned)ffs(start) - 1,
+ (unsigned)fls64(end - start) - 1);
+ if (frag >= max_frag) {
+ frag_flags = AMDGPU_PTE_FRAG(max_frag);
+ frag_end = end & ~((1ULL << max_frag) - 1);
+ } else {
+ frag_flags = AMDGPU_PTE_FRAG(frag);
+ frag_end = start + (1 << frag);
+ }
+
+ r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
+ flags | frag_flags);
if (r)
return r;
- dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
+
+ dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
+ start = frag_end;
}
- /* handle the area in the middle */
- r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
- flags | frag_flags);
- if (r)
- return r;
-
- /* handle the 4K area at the end */
- if (frag_end != end) {
- dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
- r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
- }
- return r;
+ return 0;
}
/**
@@ -1456,7 +1525,6 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
*
* @adev: amdgpu_device pointer
* @exclusive: fence we need to sync to
- * @src: address where to copy page table entries from
* @pages_addr: DMA addresses to use for mapping
* @vm: requested vm
* @start: start of mapped range
@@ -1470,7 +1538,6 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
*/
static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
struct dma_fence *exclusive,
- uint64_t src,
dma_addr_t *pages_addr,
struct amdgpu_vm *vm,
uint64_t start, uint64_t last,
@@ -1488,7 +1555,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
memset(¶ms, 0, sizeof(params));
params.adev = adev;
params.vm = vm;
- params.src = src;
/* sync to everything on unmapping */
if (!(flags & AMDGPU_PTE_VALID))
@@ -1517,10 +1583,12 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
nptes = last - start + 1;
/*
- * reserve space for one command every (1 << BLOCK_SIZE)
+ * reserve space for two commands every (1 << BLOCK_SIZE)
* entries or 2k dwords (whatever is smaller)
+ *
+ * The second command is for the shadow pagetables.
*/
- ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1;
+ ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
/* padding, etc. */
ndw = 64;
@@ -1528,15 +1596,9 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
/* one PDE write for each huge page */
ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6;
- if (src) {
- /* only copy commands needed */
- ndw += ncmds * 7;
-
- params.func = amdgpu_vm_do_copy_ptes;
-
- } else if (pages_addr) {
+ if (pages_addr) {
/* copy commands needed */
- ndw += ncmds * 7;
+ ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
/* and also PTEs */
ndw += nptes * 2;
@@ -1545,10 +1607,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
} else {
/* set page commands needed */
- ndw += ncmds * 10;
+ ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
- /* two extra commands for begin/end of fragment */
- ndw += 2 * 10;
+ /* extra commands for begin/end fragments */
+ ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw
+ * adev->vm_manager.fragment_size;
params.func = amdgpu_vm_do_set_ptes;
}
@@ -1559,7 +1622,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
params.ib = &job->ibs[0];
- if (!src && pages_addr) {
+ if (pages_addr) {
uint64_t *pte;
unsigned i;
@@ -1580,12 +1643,12 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
if (r)
goto error_free;
- r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
- owner);
+ r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
+ owner, false);
if (r)
goto error_free;
- r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
+ r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
if (r)
goto error_free;
@@ -1600,14 +1663,14 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
if (r)
goto error_free;
- amdgpu_bo_fence(vm->root.bo, f, true);
+ amdgpu_bo_fence(vm->root.base.bo, f, true);
dma_fence_put(*fence);
*fence = f;
return 0;
error_free:
amdgpu_job_free(job);
- amdgpu_vm_invalidate_level(&vm->root);
+ amdgpu_vm_invalidate_level(vm, &vm->root);
return r;
}
@@ -1636,7 +1699,8 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
struct drm_mm_node *nodes,
struct dma_fence **fence)
{
- uint64_t pfn, src = 0, start = mapping->start;
+ unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
+ uint64_t pfn, start = mapping->start;
int r;
/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
@@ -1670,6 +1734,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
}
do {
+ dma_addr_t *dma_addr = NULL;
uint64_t max_entries;
uint64_t addr, last;
@@ -1683,16 +1748,32 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
}
if (pages_addr) {
+ uint64_t count;
+
max_entries = min(max_entries, 16ull * 1024ull);
- addr = 0;
+ for (count = 1; count < max_entries; ++count) {
+ uint64_t idx = pfn + count;
+
+ if (pages_addr[idx] !=
+ (pages_addr[idx - 1] + PAGE_SIZE))
+ break;
+ }
+
+ if (count < min_linear_pages) {
+ addr = pfn << PAGE_SHIFT;
+ dma_addr = pages_addr;
+ } else {
+ addr = pages_addr[pfn];
+ max_entries = count;
+ }
+
} else if (flags & AMDGPU_PTE_VALID) {
addr += adev->vm_manager.vram_base_offset;
+ addr += pfn << PAGE_SHIFT;
}
- addr += pfn << PAGE_SHIFT;
last = min((uint64_t)mapping->last, start + max_entries - 1);
- r = amdgpu_vm_bo_update_mapping(adev, exclusive,
- src, pages_addr, vm,
+ r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
start, last, flags, addr,
fence);
if (r)
@@ -1730,7 +1811,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
dma_addr_t *pages_addr = NULL;
struct ttm_mem_reg *mem;
struct drm_mm_node *nodes;
- struct dma_fence *exclusive;
+ struct dma_fence *exclusive, **last_update;
uint64_t flags;
int r;
@@ -1756,40 +1837,45 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
else
flags = 0x0;
- spin_lock(&vm->status_lock);
- if (!list_empty(&bo_va->base.vm_status))
+ if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
+ last_update = &vm->last_update;
+ else
+ last_update = &bo_va->last_pt_update;
+
+ if (!clear && bo_va->base.moved) {
+ bo_va->base.moved = false;
list_splice_init(&bo_va->valids, &bo_va->invalids);
- spin_unlock(&vm->status_lock);
+
+ } else if (bo_va->cleared != clear) {
+ list_splice_init(&bo_va->valids, &bo_va->invalids);
+ }
list_for_each_entry(mapping, &bo_va->invalids, list) {
r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
mapping, flags, nodes,
- &bo_va->last_pt_update);
+ last_update);
if (r)
return r;
}
- if (trace_amdgpu_vm_bo_mapping_enabled()) {
- list_for_each_entry(mapping, &bo_va->valids, list)
- trace_amdgpu_vm_bo_mapping(mapping);
-
- list_for_each_entry(mapping, &bo_va->invalids, list)
- trace_amdgpu_vm_bo_mapping(mapping);
- }
-
- spin_lock(&vm->status_lock);
- list_splice_init(&bo_va->invalids, &bo_va->valids);
- list_del_init(&bo_va->base.vm_status);
- if (clear)
- list_add(&bo_va->base.vm_status, &vm->cleared);
- spin_unlock(&vm->status_lock);
-
if (vm->use_cpu_for_update) {
/* Flush HDP */
mb();
amdgpu_gart_flush_gpu_tlb(adev, 0);
}
+ spin_lock(&vm->status_lock);
+ list_del_init(&bo_va->base.vm_status);
+ spin_unlock(&vm->status_lock);
+
+ list_splice_init(&bo_va->invalids, &bo_va->valids);
+ bo_va->cleared = clear;
+
+ if (trace_amdgpu_vm_bo_mapping_enabled()) {
+ list_for_each_entry(mapping, &bo_va->valids, list)
+ trace_amdgpu_vm_bo_mapping(mapping);
+ }
+
return 0;
}
@@ -1895,7 +1981,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
*/
static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
- struct reservation_object *resv = vm->root.bo->tbo.resv;
+ struct reservation_object *resv = vm->root.base.bo->tbo.resv;
struct dma_fence *excl, **shared;
unsigned i, shared_count;
int r;
@@ -1951,9 +2037,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
list_del(&mapping->list);
if (vm->pte_support_ats)
- init_pte_value = AMDGPU_PTE_SYSTEM;
+ init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
- r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm,
+ r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
mapping->start, mapping->last,
init_pte_value, 0, &f);
amdgpu_vm_free_mapping(adev, vm, mapping, f);
@@ -1975,29 +2061,35 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
}
/**
- * amdgpu_vm_clear_moved - clear moved BOs in the PT
+ * amdgpu_vm_handle_moved - handle moved BOs in the PT
*
* @adev: amdgpu_device pointer
* @vm: requested vm
+ * @sync: sync object to add fences to
*
- * Make sure all moved BOs are cleared in the PT.
+ * Make sure all BOs which are moved are updated in the PTs.
* Returns 0 for success.
*
- * PTs have to be reserved and mutex must be locked!
+ * PTs have to be reserved!
*/
-int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- struct amdgpu_sync *sync)
+int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm)
{
- struct amdgpu_bo_va *bo_va = NULL;
+ bool clear;
int r = 0;
spin_lock(&vm->status_lock);
while (!list_empty(&vm->moved)) {
+ struct amdgpu_bo_va *bo_va;
+
bo_va = list_first_entry(&vm->moved,
struct amdgpu_bo_va, base.vm_status);
spin_unlock(&vm->status_lock);
- r = amdgpu_vm_bo_update(adev, bo_va, true);
+ /* Per VM BOs never need to bo cleared in the page tables */
+ clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv;
+
+ r = amdgpu_vm_bo_update(adev, bo_va, clear);
if (r)
return r;
@@ -2005,9 +2097,6 @@ int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm,
}
spin_unlock(&vm->status_lock);
- if (bo_va)
- r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
-
return r;
}
@@ -2049,6 +2138,39 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
return bo_va;
}
+
+/**
+ * amdgpu_vm_bo_insert_mapping - insert a new mapping
+ *
+ * @adev: amdgpu_device pointer
+ * @bo_va: bo_va to store the address
+ * @mapping: the mapping to insert
+ *
+ * Insert a new mapping into all structures.
+ */
+static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
+ struct amdgpu_bo_va *bo_va,
+ struct amdgpu_bo_va_mapping *mapping)
+{
+ struct amdgpu_vm *vm = bo_va->base.vm;
+ struct amdgpu_bo *bo = bo_va->base.bo;
+
+ mapping->bo_va = bo_va;
+ list_add(&mapping->list, &bo_va->invalids);
+ amdgpu_vm_it_insert(mapping, &vm->va);
+
+ if (mapping->flags & AMDGPU_PTE_PRT)
+ amdgpu_vm_prt_get(adev);
+
+ if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
+ spin_lock(&vm->status_lock);
+ if (list_empty(&bo_va->base.vm_status))
+ list_add(&bo_va->base.vm_status, &vm->moved);
+ spin_unlock(&vm->status_lock);
+ }
+ trace_amdgpu_vm_bo_map(bo_va, mapping);
+}
+
/**
* amdgpu_vm_bo_map - map bo inside a vm
*
@@ -2100,17 +2222,12 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
if (!mapping)
return -ENOMEM;
- INIT_LIST_HEAD(&mapping->list);
mapping->start = saddr;
mapping->last = eaddr;
mapping->offset = offset;
mapping->flags = flags;
- list_add(&mapping->list, &bo_va->invalids);
- amdgpu_vm_it_insert(mapping, &vm->va);
-
- if (flags & AMDGPU_PTE_PRT)
- amdgpu_vm_prt_get(adev);
+ amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
return 0;
}
@@ -2137,7 +2254,6 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
{
struct amdgpu_bo_va_mapping *mapping;
struct amdgpu_bo *bo = bo_va->base.bo;
- struct amdgpu_vm *vm = bo_va->base.vm;
uint64_t eaddr;
int r;
@@ -2171,11 +2287,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
mapping->offset = offset;
mapping->flags = flags;
- list_add(&mapping->list, &bo_va->invalids);
- amdgpu_vm_it_insert(mapping, &vm->va);
-
- if (flags & AMDGPU_PTE_PRT)
- amdgpu_vm_prt_get(adev);
+ amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
return 0;
}
@@ -2221,6 +2333,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
list_del(&mapping->list);
amdgpu_vm_it_remove(mapping, &vm->va);
+ mapping->bo_va = NULL;
trace_amdgpu_vm_bo_unmap(bo_va, mapping);
if (valid)
@@ -2306,6 +2419,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
if (tmp->last > eaddr)
tmp->last = eaddr;
+ tmp->bo_va = NULL;
list_add(&tmp->list, &vm->freed);
trace_amdgpu_vm_bo_unmap(NULL, tmp);
}
@@ -2332,6 +2446,19 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
}
/**
+ * amdgpu_vm_bo_lookup_mapping - find mapping by address
+ *
+ * @vm: the requested VM
+ *
+ * Find a mapping by it's address.
+ */
+struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
+ uint64_t addr)
+{
+ return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
+}
+
+/**
* amdgpu_vm_bo_rmv - remove a bo to a specific vm
*
* @adev: amdgpu_device pointer
@@ -2356,6 +2483,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
list_del(&mapping->list);
amdgpu_vm_it_remove(mapping, &vm->va);
+ mapping->bo_va = NULL;
trace_amdgpu_vm_bo_unmap(bo_va, mapping);
list_add(&mapping->list, &vm->freed);
}
@@ -2380,15 +2508,36 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
* Mark @bo as invalid.
*/
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
- struct amdgpu_bo *bo)
+ struct amdgpu_bo *bo, bool evicted)
{
struct amdgpu_vm_bo_base *bo_base;
list_for_each_entry(bo_base, &bo->va, bo_list) {
+ struct amdgpu_vm *vm = bo_base->vm;
+
+ bo_base->moved = true;
+ if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
+ spin_lock(&bo_base->vm->status_lock);
+ if (bo->tbo.type == ttm_bo_type_kernel)
+ list_move(&bo_base->vm_status, &vm->evicted);
+ else
+ list_move_tail(&bo_base->vm_status,
+ &vm->evicted);
+ spin_unlock(&bo_base->vm->status_lock);
+ continue;
+ }
+
+ if (bo->tbo.type == ttm_bo_type_kernel) {
+ spin_lock(&bo_base->vm->status_lock);
+ if (list_empty(&bo_base->vm_status))
+ list_add(&bo_base->vm_status, &vm->relocated);
+ spin_unlock(&bo_base->vm->status_lock);
+ continue;
+ }
+
spin_lock(&bo_base->vm->status_lock);
if (list_empty(&bo_base->vm_status))
- list_add(&bo_base->vm_status,
- &bo_base->vm->moved);
+ list_add(&bo_base->vm_status, &vm->moved);
spin_unlock(&bo_base->vm->status_lock);
}
}
@@ -2412,7 +2561,8 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
* @adev: amdgpu_device pointer
* @fragment_size_default: the default fragment size if it's set auto
*/
-void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_size_default)
+void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
+ uint32_t fragment_size_default)
{
if (amdgpu_vm_fragment_size == -1)
adev->vm_manager.fragment_size = fragment_size_default;
@@ -2426,7 +2576,8 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_s
* @adev: amdgpu_device pointer
* @vm_size: the default vm size if it's set auto
*/
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_t fragment_size_default)
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
+ uint32_t fragment_size_default)
{
/* adjust vm size firstly */
if (amdgpu_vm_size == -1)
@@ -2458,7 +2609,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_
* Init @vm fields.
*/
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- int vm_context)
+ int vm_context, unsigned int pasid)
{
const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
AMDGPU_VM_PTE_COUNT(adev) * 8);
@@ -2474,8 +2625,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
vm->reserved_vmid[i] = NULL;
spin_lock_init(&vm->status_lock);
+ INIT_LIST_HEAD(&vm->evicted);
+ INIT_LIST_HEAD(&vm->relocated);
INIT_LIST_HEAD(&vm->moved);
- INIT_LIST_HEAD(&vm->cleared);
INIT_LIST_HEAD(&vm->freed);
/* create scheduler entity for page table updates */
@@ -2497,7 +2649,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
if (adev->asic_type == CHIP_RAVEN) {
vm->pte_support_ats = true;
- init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE;
+ init_pde_value = AMDGPU_PTE_DEFAULT_ATC
+ | AMDGPU_PDE_PTE;
+
}
} else
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
@@ -2506,7 +2660,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
vm->use_cpu_for_update ? "CPU" : "SDMA");
WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
"CPU update of VM recommended only for large BAR system\n");
- vm->last_dir_update = NULL;
+ vm->last_update = NULL;
flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_VRAM_CLEARED;
@@ -2519,30 +2673,47 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
AMDGPU_GEM_DOMAIN_VRAM,
flags,
- NULL, NULL, init_pde_value, &vm->root.bo);
+ NULL, NULL, init_pde_value, &vm->root.base.bo);
if (r)
goto error_free_sched_entity;
- r = amdgpu_bo_reserve(vm->root.bo, false);
- if (r)
- goto error_free_root;
-
- vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
+ vm->root.base.vm = vm;
+ list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
+ INIT_LIST_HEAD(&vm->root.base.vm_status);
if (vm->use_cpu_for_update) {
- r = amdgpu_bo_kmap(vm->root.bo, NULL);
+ r = amdgpu_bo_reserve(vm->root.base.bo, false);
+ if (r)
+ goto error_free_root;
+
+ r = amdgpu_bo_kmap(vm->root.base.bo, NULL);
+ amdgpu_bo_unreserve(vm->root.base.bo);
if (r)
goto error_free_root;
}
- amdgpu_bo_unreserve(vm->root.bo);
+ if (pasid) {
+ unsigned long flags;
+
+ spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
+ r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
+ GFP_ATOMIC);
+ spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
+ if (r < 0)
+ goto error_free_root;
+
+ vm->pasid = pasid;
+ }
+
+ INIT_KFIFO(vm->faults);
+ vm->fault_credit = 16;
return 0;
error_free_root:
- amdgpu_bo_unref(&vm->root.bo->shadow);
- amdgpu_bo_unref(&vm->root.bo);
- vm->root.bo = NULL;
+ amdgpu_bo_unref(&vm->root.base.bo->shadow);
+ amdgpu_bo_unref(&vm->root.base.bo);
+ vm->root.base.bo = NULL;
error_free_sched_entity:
amd_sched_entity_fini(&ring->sched, &vm->entity);
@@ -2561,9 +2732,11 @@ static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
{
unsigned i;
- if (level->bo) {
- amdgpu_bo_unref(&level->bo->shadow);
- amdgpu_bo_unref(&level->bo);
+ if (level->base.bo) {
+ list_del(&level->base.bo_list);
+ list_del(&level->base.vm_status);
+ amdgpu_bo_unref(&level->base.bo->shadow);
+ amdgpu_bo_unref(&level->base.bo);
}
if (level->entries)
@@ -2586,7 +2759,21 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
struct amdgpu_bo_va_mapping *mapping, *tmp;
bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
- int i;
+ struct amdgpu_bo *root;
+ u64 fault;
+ int i, r;
+
+ /* Clear pending page faults from IH when the VM is destroyed */
+ while (kfifo_get(&vm->faults, &fault))
+ amdgpu_ih_clear_fault(adev, fault);
+
+ if (vm->pasid) {
+ unsigned long flags;
+
+ spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
+ idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
+ spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
+ }
amd_sched_entity_fini(vm->entity.sched, &vm->entity);
@@ -2609,13 +2796,51 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
}
- amdgpu_vm_free_levels(&vm->root);
- dma_fence_put(vm->last_dir_update);
+ root = amdgpu_bo_ref(vm->root.base.bo);
+ r = amdgpu_bo_reserve(root, true);
+ if (r) {
+ dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
+ } else {
+ amdgpu_vm_free_levels(&vm->root);
+ amdgpu_bo_unreserve(root);
+ }
+ amdgpu_bo_unref(&root);
+ dma_fence_put(vm->last_update);
for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
amdgpu_vm_free_reserved_vmid(adev, vm, i);
}
/**
+ * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: PASID do identify the VM
+ *
+ * This function is expected to be called in interrupt context. Returns
+ * true if there was fault credit, false otherwise
+ */
+bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
+ unsigned int pasid)
+{
+ struct amdgpu_vm *vm;
+
+ spin_lock(&adev->vm_manager.pasid_lock);
+ vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
+ spin_unlock(&adev->vm_manager.pasid_lock);
+ if (!vm)
+ /* VM not found, can't track fault credit */
+ return true;
+
+ /* No lock needed. only accessed by IRQ handler */
+ if (!vm->fault_credit)
+ /* Too many faults in this VM */
+ return false;
+
+ vm->fault_credit--;
+ return true;
+}
+
+/**
* amdgpu_vm_manager_init - init the VM manager
*
* @adev: amdgpu_device pointer
@@ -2668,6 +2893,8 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
adev->vm_manager.vm_update_mode = 0;
#endif
+ idr_init(&adev->vm_manager.pasid_idr);
+ spin_lock_init(&adev->vm_manager.pasid_lock);
}
/**
@@ -2681,6 +2908,9 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
{
unsigned i, j;
+ WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
+ idr_destroy(&adev->vm_manager.pasid_idr);
+
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
struct amdgpu_vm_id_manager *id_mgr =
&adev->vm_manager.id_mgr[i];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 6716355..aa91425 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -25,6 +25,7 @@
#define __AMDGPU_VM_H__
#include <linux/rbtree.h>
+#include <linux/idr.h>
#include "gpu_scheduler.h"
#include "amdgpu_sync.h"
@@ -72,6 +73,16 @@ struct amdgpu_bo_list_entry;
#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
+/* For Raven */
+#define AMDGPU_MTYPE_CC 2
+
+#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
+ | AMDGPU_PTE_SNOOPED \
+ | AMDGPU_PTE_EXECUTABLE \
+ | AMDGPU_PTE_READABLE \
+ | AMDGPU_PTE_WRITEABLE \
+ | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
+
/* How to programm VM fault handling */
#define AMDGPU_VM_FAULT_STOP_NEVER 0
#define AMDGPU_VM_FAULT_STOP_FIRST 1
@@ -105,17 +116,24 @@ struct amdgpu_vm_bo_base {
/* protected by spinlock */
struct list_head vm_status;
+
+ /* protected by the BO being reserved */
+ bool moved;
};
struct amdgpu_vm_pt {
- struct amdgpu_bo *bo;
- uint64_t addr;
+ struct amdgpu_vm_bo_base base;
+ uint64_t addr;
/* array of page tables, one for each directory entry */
- struct amdgpu_vm_pt *entries;
- unsigned last_entry_used;
+ struct amdgpu_vm_pt *entries;
+ unsigned last_entry_used;
};
+#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
+#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
+#define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
+
struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached va;
@@ -123,19 +141,21 @@ struct amdgpu_vm {
/* protecting invalidated */
spinlock_t status_lock;
+ /* BOs who needs a validation */
+ struct list_head evicted;
+
+ /* PT BOs which relocated and their parent need an update */
+ struct list_head relocated;
+
/* BOs moved, but not yet updated in the PT */
struct list_head moved;
- /* BOs cleared in the PT because of a move */
- struct list_head cleared;
-
/* BO mappings freed, but not yet updated in the PT */
struct list_head freed;
/* contains the page directory */
struct amdgpu_vm_pt root;
- struct dma_fence *last_dir_update;
- uint64_t last_eviction_counter;
+ struct dma_fence *last_update;
/* protecting freed */
spinlock_t freed_lock;
@@ -143,8 +163,9 @@ struct amdgpu_vm {
/* Scheduler entity for page table updates */
struct amd_sched_entity entity;
- /* client id */
+ /* client id and PASID (TODO: replace client_id with PASID) */
u64 client_id;
+ unsigned int pasid;
/* dedicated to vm */
struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS];
@@ -153,6 +174,12 @@ struct amdgpu_vm {
/* Flag to indicate ATS support from PTE for GFX9 */
bool pte_support_ats;
+
+ /* Up to 128 pending retry page faults */
+ DECLARE_KFIFO(faults, u64, 128);
+
+ /* Limit non-retry fault storms */
+ unsigned int fault_credit;
};
struct amdgpu_vm_id {
@@ -215,16 +242,27 @@ struct amdgpu_vm_manager {
* BIT1[= 0] Compute updated by SDMA [= 1] by CPU
*/
int vm_update_mode;
+
+ /* PASID to VM mapping, will be used in interrupt context to
+ * look up VM of a page fault
+ */
+ struct idr pasid_idr;
+ spinlock_t pasid_lock;
};
+int amdgpu_vm_alloc_pasid(unsigned int bits);
+void amdgpu_vm_free_pasid(unsigned int pasid);
void amdgpu_vm_manager_init(struct amdgpu_device *adev);
void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- int vm_context);
+ int vm_context, unsigned int pasid);
void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
+bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
+ unsigned int pasid);
void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
struct list_head *validated,
struct amdgpu_bo_list_entry *entry);
+bool amdgpu_vm_ready(struct amdgpu_vm *vm);
int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
int (*callback)(void *p, struct amdgpu_bo *bo),
void *param);
@@ -243,13 +281,13 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
struct dma_fence **fence);
-int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- struct amdgpu_sync *sync);
+int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm);
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
bool clear);
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
- struct amdgpu_bo *bo);
+ struct amdgpu_bo *bo, bool evicted);
struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
struct amdgpu_bo *bo);
struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
@@ -269,6 +307,8 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
uint64_t saddr, uint64_t size);
+struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
+ uint64_t addr);
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va);
void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
index d69aa2e..69500a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1343,8 +1343,11 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
idx = 0x80;
str = CSTR(idx);
- if (*str != '\0')
+ if (*str != '\0') {
pr_info("ATOM BIOS: %s\n", str);
+ strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
+ }
+
return ctx;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h
index ddd8045..a3917099 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -140,6 +140,7 @@ struct atom_context {
int io_mode;
uint32_t *scratch;
int scratch_size_bytes;
+ char vbios_version[20];
};
extern int amdgpu_atom_debug;
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index cb508a2..68b505c 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -307,7 +307,6 @@ static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
u32 target_tdp);
static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
-static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
@@ -883,8 +882,9 @@ static int ci_power_control_set_level(struct amdgpu_device *adev)
return ret;
}
-static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
+static void ci_dpm_powergate_uvd(void *handle, bool gate)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
pi->uvd_power_gated = gate;
@@ -901,8 +901,9 @@ static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
}
}
-static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
+static bool ci_dpm_vblank_too_short(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
@@ -1210,11 +1211,12 @@ static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
}
}
-static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
+static int ci_dpm_get_fan_speed_percent(void *handle,
u32 *speed)
{
u32 duty, duty100;
u64 tmp64;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->pm.no_fan)
return -ENOENT;
@@ -1237,12 +1239,13 @@ static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
return 0;
}
-static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
+static int ci_dpm_set_fan_speed_percent(void *handle,
u32 speed)
{
u32 tmp;
u32 duty, duty100;
u64 tmp64;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
if (adev->pm.no_fan)
@@ -1271,8 +1274,10 @@ static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
return 0;
}
-static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
+static void ci_dpm_set_fan_control_mode(void *handle, u32 mode)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
switch (mode) {
case AMD_FAN_CTRL_NONE:
if (adev->pm.dpm.fan.ucode_fan_control)
@@ -1292,8 +1297,9 @@ static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
}
}
-static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
+static u32 ci_dpm_get_fan_control_mode(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
if (pi->fan_is_controlled_by_smc)
@@ -4378,9 +4384,10 @@ static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
}
-static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
+static int ci_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
u32 tmp, levels, i;
int ret;
@@ -5291,8 +5298,9 @@ static void ci_update_requested_ps(struct amdgpu_device *adev,
adev->pm.dpm.requested_ps = &pi->requested_rps;
}
-static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
+static int ci_dpm_pre_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
struct amdgpu_ps *new_ps = &requested_ps;
@@ -5304,8 +5312,9 @@ static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
return 0;
}
-static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
+static void ci_dpm_post_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct amdgpu_ps *new_ps = &pi->requested_rps;
@@ -5479,8 +5488,9 @@ static void ci_dpm_disable(struct amdgpu_device *adev)
ci_update_current_ps(adev, boot_ps);
}
-static int ci_dpm_set_power_state(struct amdgpu_device *adev)
+static int ci_dpm_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct amdgpu_ps *new_ps = &pi->requested_rps;
struct amdgpu_ps *old_ps = &pi->current_rps;
@@ -5551,8 +5561,10 @@ static void ci_dpm_reset_asic(struct amdgpu_device *adev)
}
#endif
-static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
+static void ci_dpm_display_configuration_changed(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
ci_program_display_gap(adev);
}
@@ -6105,9 +6117,10 @@ static int ci_dpm_init(struct amdgpu_device *adev)
}
static void
-ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
+ci_dpm_debugfs_print_current_performance_level(void *handle,
struct seq_file *m)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct amdgpu_ps *rps = &pi->current_rps;
u32 sclk = ci_get_average_sclk_freq(adev);
@@ -6131,12 +6144,13 @@ ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
seq_printf(m, "GPU load: %u %%\n", activity_percent);
}
-static void ci_dpm_print_power_state(struct amdgpu_device *adev,
- struct amdgpu_ps *rps)
+static void ci_dpm_print_power_state(void *handle, void *current_ps)
{
+ struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
struct ci_ps *ps = ci_get_ps(rps);
struct ci_pl *pl;
int i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_dpm_print_class_info(rps->class, rps->class2);
amdgpu_dpm_print_cap_info(rps->caps);
@@ -6158,20 +6172,23 @@ static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1,
(ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));
}
-static int ci_check_state_equal(struct amdgpu_device *adev,
- struct amdgpu_ps *cps,
- struct amdgpu_ps *rps,
+static int ci_check_state_equal(void *handle,
+ void *current_ps,
+ void *request_ps,
bool *equal)
{
struct ci_ps *ci_cps;
struct ci_ps *ci_rps;
int i;
+ struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
+ struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
return -EINVAL;
- ci_cps = ci_get_ps(cps);
- ci_rps = ci_get_ps(rps);
+ ci_cps = ci_get_ps((struct amdgpu_ps *)cps);
+ ci_rps = ci_get_ps((struct amdgpu_ps *)rps);
if (ci_cps == NULL) {
*equal = false;
@@ -6199,8 +6216,9 @@ static int ci_check_state_equal(struct amdgpu_device *adev,
return 0;
}
-static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
+static u32 ci_dpm_get_sclk(void *handle, bool low)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
@@ -6210,8 +6228,9 @@ static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
}
-static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
+static u32 ci_dpm_get_mclk(void *handle, bool low)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
@@ -6222,10 +6241,11 @@ static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
}
/* get temperature in millidegrees */
-static int ci_dpm_get_temp(struct amdgpu_device *adev)
+static int ci_dpm_get_temp(void *handle)
{
u32 temp;
int actual_temp = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
@@ -6261,7 +6281,6 @@ static int ci_dpm_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- ci_dpm_set_dpm_funcs(adev);
ci_dpm_set_irq_funcs(adev);
return 0;
@@ -6346,7 +6365,6 @@ static int ci_dpm_sw_fini(void *handle)
flush_work(&adev->pm.dpm.thermal.work);
mutex_lock(&adev->pm.mutex);
- amdgpu_pm_sysfs_fini(adev);
ci_dpm_fini(adev);
mutex_unlock(&adev->pm.mutex);
@@ -6551,9 +6569,10 @@ static int ci_dpm_set_powergating_state(void *handle,
return 0;
}
-static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
+static int ci_dpm_print_clock_levels(void *handle,
enum pp_clock_type type, char *buf)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
@@ -6618,9 +6637,10 @@ static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
return size;
}
-static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
+static int ci_dpm_force_clock_level(void *handle,
enum pp_clock_type type, uint32_t mask)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |
@@ -6664,8 +6684,9 @@ static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
return 0;
}
-static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
+static int ci_dpm_get_sclk_od(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
struct ci_single_dpm_table *golden_sclk_table =
@@ -6680,8 +6701,9 @@ static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
return value;
}
-static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
+static int ci_dpm_set_sclk_od(void *handle, uint32_t value)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
struct ci_single_dpm_table *golden_sclk_table =
@@ -6698,8 +6720,9 @@ static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
return 0;
}
-static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
+static int ci_dpm_get_mclk_od(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
struct ci_single_dpm_table *golden_mclk_table =
@@ -6714,8 +6737,9 @@ static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
return value;
}
-static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
+static int ci_dpm_set_mclk_od(void *handle, uint32_t value)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
struct ci_single_dpm_table *golden_mclk_table =
@@ -6732,9 +6756,10 @@ static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
return 0;
}
-static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev,
+static int ci_dpm_get_power_profile_state(void *handle,
struct amd_pp_profile *query)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
if (!pi || !query)
@@ -6851,9 +6876,10 @@ static int ci_set_power_profile_state(struct amdgpu_device *adev,
return result;
}
-static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev,
+static int ci_dpm_set_power_profile_state(void *handle,
struct amd_pp_profile *request)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
int ret = -1;
@@ -6906,9 +6932,10 @@ static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev,
return 0;
}
-static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev,
+static int ci_dpm_reset_power_profile_state(void *handle,
struct amd_pp_profile *request)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
if (!pi || !request)
@@ -6927,9 +6954,10 @@ static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev,
return -EINVAL;
}
-static int ci_dpm_switch_power_profile(struct amdgpu_device *adev,
+static int ci_dpm_switch_power_profile(void *handle,
enum amd_pp_profile_type type)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ci_power_info *pi = ci_get_pi(adev);
struct amd_pp_profile request = {0};
@@ -6944,11 +6972,12 @@ static int ci_dpm_switch_power_profile(struct amdgpu_device *adev,
return 0;
}
-static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+static int ci_dpm_read_sensor(void *handle, int idx,
void *value, int *size)
{
u32 activity_percent = 50;
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* size must be at least 4 bytes for all sensors */
if (*size < 4)
@@ -7003,7 +7032,7 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = {
.set_powergating_state = ci_dpm_set_powergating_state,
};
-static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
+const struct amd_pm_funcs ci_dpm_funcs = {
.get_temperature = &ci_dpm_get_temp,
.pre_set_power_state = &ci_dpm_pre_set_power_state,
.set_power_state = &ci_dpm_set_power_state,
@@ -7035,12 +7064,6 @@ static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
.read_sensor = ci_dpm_read_sensor,
};
-static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
-{
- if (adev->pm.funcs == NULL)
- adev->pm.funcs = &ci_dpm_funcs;
-}
-
static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
.set = ci_dpm_set_interrupt_state,
.process = ci_dpm_process_interrupt,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
index b1c8e7b..c7b4349 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
@@ -26,5 +26,6 @@
extern const struct amd_ip_funcs ci_dpm_ip_funcs;
extern const struct amd_ip_funcs kv_dpm_ip_funcs;
-
+extern const struct amd_pm_funcs ci_dpm_funcs;
+extern const struct amd_pm_funcs kv_dpm_funcs;
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index b891843..a870b35 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -228,6 +228,34 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
* [127:96] - reserved
*/
+/**
+ * cik_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool cik_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ u32 ring_index = adev->irq.ih.rptr >> 2;
+ u16 pasid;
+
+ switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
+ case 146:
+ case 147:
+ pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
+ if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
+ return true;
+ break;
+ default:
+ /* Not a VM fault */
+ return true;
+ }
+
+ adev->irq.ih.rptr += 16;
+ return false;
+}
+
/**
* cik_ih_decode_iv - decode an interrupt vector
*
@@ -433,6 +461,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
static const struct amdgpu_ih_funcs cik_ih_funcs = {
.get_wptr = cik_ih_get_wptr,
+ .prescreen_iv = cik_ih_prescreen_iv,
.decode_iv = cik_ih_decode_iv,
.set_rptr = cik_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index f508f4d..60cecd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1387,8 +1387,13 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
}
static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
+ .copy_pte_num_dw = 7,
.copy_pte = cik_sdma_vm_copy_pte,
+
.write_pte = cik_sdma_vm_write_pte,
+
+ .set_max_nums_pte_pde = 0x1fffff >> 3,
+ .set_pte_pde_num_dw = 10,
.set_pte_pde = cik_sdma_vm_set_pte_pde,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 0c1209c..fa61d64 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -208,6 +208,34 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
}
/**
+ * cz_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool cz_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ u32 ring_index = adev->irq.ih.rptr >> 2;
+ u16 pasid;
+
+ switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
+ case 146:
+ case 147:
+ pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
+ if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
+ return true;
+ break;
+ default:
+ /* Not a VM fault */
+ return true;
+ }
+
+ adev->irq.ih.rptr += 16;
+ return false;
+}
+
+/**
* cz_ih_decode_iv - decode an interrupt vector
*
* @adev: amdgpu_device pointer
@@ -414,6 +442,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
static const struct amdgpu_ih_funcs cz_ih_funcs = {
.get_wptr = cz_ih_get_wptr,
+ .prescreen_iv = cz_ih_prescreen_iv,
.decode_iv = cz_ih_decode_iv,
.set_rptr = cz_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index b9ee907..a8829af 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -288,7 +288,7 @@ dce_virtual_encoder(struct drm_connector *connector)
if (connector->encoder_ids[i] == 0)
break;
- encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+ encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
if (!encoder)
continue;
@@ -298,7 +298,7 @@ dce_virtual_encoder(struct drm_connector *connector)
/* pick the first one */
if (enc_id)
- return drm_encoder_find(connector->dev, enc_id);
+ return drm_encoder_find(connector->dev, NULL, enc_id);
return NULL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index fc260c1..b8002ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
+#include <linux/kernel.h>
#include <linux/firmware.h>
#include <drm/drmP.h>
#include "amdgpu.h"
@@ -125,24 +126,39 @@ MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
+MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
+MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
+MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
+MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
+MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
@@ -918,8 +934,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
BUG();
}
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
- err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
+ if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
+ err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
+ if (err == -ENOENT) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
+ err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
+ }
+ } else {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
+ err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
+ }
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
@@ -929,8 +954,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
- err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
+ if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
+ err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
+ if (err == -ENOENT) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
+ err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
+ }
+ } else {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
+ err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
+ }
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.me_fw);
@@ -941,8 +975,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
- err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
+ if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
+ err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
+ if (err == -ENOENT) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
+ err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
+ }
+ } else {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
+ err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
+ }
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.ce_fw);
@@ -1012,8 +1055,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
- err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+ if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+ if (err == -ENOENT) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+ }
+ } else {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+ }
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.mec_fw);
@@ -1025,8 +1077,17 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
if ((adev->asic_type != CHIP_STONEY) &&
(adev->asic_type != CHIP_TOPAZ)) {
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
- err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+ if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+ if (err == -ENOENT) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+ }
+ } else {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+ }
if (!err) {
err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
if (err)
@@ -2053,6 +2114,7 @@ static int gfx_v8_0_sw_fini(void *handle)
amdgpu_gfx_compute_mqd_sw_fini(adev);
amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
amdgpu_gfx_kiq_fini(adev);
+ amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
gfx_v8_0_mec_fini(adev);
gfx_v8_0_rlc_fini(adev);
@@ -3891,10 +3953,10 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
adev->gfx.rlc.reg_list_format_size_bytes >> 2,
unique_indices,
&indices_count,
- sizeof(unique_indices) / sizeof(int),
+ ARRAY_SIZE(unique_indices),
indirect_start_offsets,
&offset_count,
- sizeof(indirect_start_offsets)/sizeof(int));
+ ARRAY_SIZE(indirect_start_offsets));
/* save and restore list */
WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
@@ -3916,14 +3978,14 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
/* starting offsets starts */
WREG32(mmRLC_GPM_SCRATCH_ADDR,
adev->gfx.rlc.starting_offsets_start);
- for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
+ for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
WREG32(mmRLC_GPM_SCRATCH_DATA,
indirect_start_offsets[i]);
/* unique indices */
temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
data = mmRLC_SRM_INDEX_CNTL_DATA_0;
- for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
+ for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
if (unique_indices[i] != 0) {
WREG32(temp + i, unique_indices[i] & 0x3FFFF);
WREG32(data + i, unique_indices[i] >> 20);
@@ -4071,18 +4133,12 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
gfx_v8_0_rlc_reset(adev);
gfx_v8_0_init_pg(adev);
- if (!adev->pp_enabled) {
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
- /* legacy rlc firmware loading */
- r = gfx_v8_0_rlc_load_microcode(adev);
- if (r)
- return r;
- } else {
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- AMDGPU_UCODE_ID_RLC_G);
- if (r)
- return -EINVAL;
- }
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ /* legacy rlc firmware loading */
+ r = gfx_v8_0_rlc_load_microcode(adev);
+ if (r)
+ return r;
}
gfx_v8_0_rlc_start(adev);
@@ -4577,12 +4633,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
mqd->compute_misc_reserved = 0x00000003;
- if (!(adev->flags & AMD_IS_APU)) {
- mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
- + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
- mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
- + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
- }
+ mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
+ + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
+ mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
+ + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
eop_base_addr = ring->eop_gpu_addr >> 8;
mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
@@ -4753,7 +4807,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
gfx_v8_0_kiq_setting(ring);
- if (adev->gfx.in_reset) { /* for GPU_RESET case */
+ if (adev->in_sriov_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
@@ -4790,7 +4844,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
struct vi_mqd *mqd = ring->mqd_ptr;
int mqd_idx = ring - &adev->gfx.compute_ring[0];
- if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
+ if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
@@ -4802,7 +4856,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
- } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
+ } else if (adev->in_sriov_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
@@ -4900,43 +4954,15 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
if (!(adev->flags & AMD_IS_APU))
gfx_v8_0_enable_gui_idle_interrupt(adev, false);
- if (!adev->pp_enabled) {
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
/* legacy firmware loading */
- r = gfx_v8_0_cp_gfx_load_microcode(adev);
- if (r)
- return r;
+ r = gfx_v8_0_cp_gfx_load_microcode(adev);
+ if (r)
+ return r;
- r = gfx_v8_0_cp_compute_load_microcode(adev);
- if (r)
- return r;
- } else {
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- AMDGPU_UCODE_ID_CP_CE);
- if (r)
- return -EINVAL;
-
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- AMDGPU_UCODE_ID_CP_PFP);
- if (r)
- return -EINVAL;
-
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- AMDGPU_UCODE_ID_CP_ME);
- if (r)
- return -EINVAL;
-
- if (adev->asic_type == CHIP_TOPAZ) {
- r = gfx_v8_0_cp_compute_load_microcode(adev);
- if (r)
- return r;
- } else {
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- AMDGPU_UCODE_ID_CP_MEC1);
- if (r)
- return -EINVAL;
- }
- }
+ r = gfx_v8_0_cp_compute_load_microcode(adev);
+ if (r)
+ return r;
}
r = gfx_v8_0_cp_gfx_resume(adev);
@@ -4975,12 +5001,69 @@ static int gfx_v8_0_hw_init(void *handle)
return r;
}
+static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = kiq_ring->adev;
+ uint32_t scratch, tmp = 0;
+ int r, i;
+
+ r = amdgpu_gfx_scratch_get(adev, &scratch);
+ if (r) {
+ DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+
+ r = amdgpu_ring_alloc(kiq_ring, 10);
+ if (r) {
+ DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+ amdgpu_gfx_scratch_free(adev, scratch);
+ return r;
+ }
+
+ /* unmap queues */
+ amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
+ amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
+ PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
+ PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
+ PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
+ PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
+ amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
+ amdgpu_ring_write(kiq_ring, 0);
+ amdgpu_ring_write(kiq_ring, 0);
+ amdgpu_ring_write(kiq_ring, 0);
+ /* write to scratch for completion */
+ amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
+ amdgpu_ring_commit(kiq_ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+ if (i >= adev->usec_timeout) {
+ DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
+ r = -EINVAL;
+ }
+ amdgpu_gfx_scratch_free(adev, scratch);
+ return r;
+}
+
static int gfx_v8_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i;
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+
+ /* disable KCQ to avoid CPC touch memory not valid anymore */
+ for (i = 0; i < adev->gfx.num_compute_rings; i++)
+ gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
+
if (amdgpu_sriov_vf(adev)) {
pr_debug("For SRIOV client, shouldn't do anything.\n");
return 0;
@@ -5902,7 +5985,6 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
{
uint32_t msg_id, pp_state = 0;
uint32_t pp_support_state = 0;
- void *pp_handle = adev->powerplay.pp_handle;
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@@ -5920,7 +6002,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
PP_BLOCK_GFX_CG,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
@@ -5941,7 +6024,8 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
PP_BLOCK_GFX_MG,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
return 0;
@@ -5953,7 +6037,6 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
uint32_t msg_id, pp_state = 0;
uint32_t pp_support_state = 0;
- void *pp_handle = adev->powerplay.pp_handle;
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@@ -5971,7 +6054,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
PP_BLOCK_GFX_CG,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
@@ -5990,7 +6074,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
PP_BLOCK_GFX_3D,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
@@ -6011,7 +6096,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
PP_BLOCK_GFX_MG,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
@@ -6026,7 +6112,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
PP_BLOCK_GFX_RLC,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
@@ -6040,7 +6127,8 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
PP_BLOCK_GFX_CP,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
return 0;
@@ -6307,6 +6395,104 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
}
+static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
+ bool acquire)
+{
+ struct amdgpu_device *adev = ring->adev;
+ int pipe_num, tmp, reg;
+ int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
+
+ pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
+
+ /* first me only has 2 entries, GFX and HP3D */
+ if (ring->me > 0)
+ pipe_num -= 2;
+
+ reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;
+ tmp = RREG32(reg);
+ tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
+ WREG32(reg, tmp);
+}
+
+static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring,
+ bool acquire)
+{
+ int i, pipe;
+ bool reserve;
+ struct amdgpu_ring *iring;
+
+ mutex_lock(&adev->gfx.pipe_reserve_mutex);
+ pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
+ if (acquire)
+ set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
+ else
+ clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
+
+ if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
+ /* Clear all reservations - everyone reacquires all resources */
+ for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
+ gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
+ true);
+
+ for (i = 0; i < adev->gfx.num_compute_rings; ++i)
+ gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
+ true);
+ } else {
+ /* Lower all pipes without a current reservation */
+ for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
+ iring = &adev->gfx.gfx_ring[i];
+ pipe = amdgpu_gfx_queue_to_bit(adev,
+ iring->me,
+ iring->pipe,
+ 0);
+ reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
+ gfx_v8_0_ring_set_pipe_percent(iring, reserve);
+ }
+
+ for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
+ iring = &adev->gfx.compute_ring[i];
+ pipe = amdgpu_gfx_queue_to_bit(adev,
+ iring->me,
+ iring->pipe,
+ 0);
+ reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
+ gfx_v8_0_ring_set_pipe_percent(iring, reserve);
+ }
+ }
+
+ mutex_unlock(&adev->gfx.pipe_reserve_mutex);
+}
+
+static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring,
+ bool acquire)
+{
+ uint32_t pipe_priority = acquire ? 0x2 : 0x0;
+ uint32_t queue_priority = acquire ? 0xf : 0x0;
+
+ mutex_lock(&adev->srbm_mutex);
+ vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+
+ WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);
+ WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);
+
+ vi_srbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
+}
+static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
+ enum amd_sched_priority priority)
+{
+ struct amdgpu_device *adev = ring->adev;
+ bool acquire = priority == AMD_SCHED_PRIORITY_HIGH_HW;
+
+ if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
+ return;
+
+ gfx_v8_0_hqd_set_priority(adev, ring, acquire);
+ gfx_v8_0_pipe_reserve_resources(adev, ring, acquire);
+}
+
static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
u64 addr, u64 seq,
unsigned flags)
@@ -6752,6 +6938,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
.test_ib = gfx_v8_0_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
+ .set_priority = gfx_v8_0_ring_set_priority_compute,
};
static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
@@ -6960,7 +7147,7 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
{
uint64_t ce_payload_addr;
int cnt_ce;
- static union {
+ union {
struct vi_ce_ib_state regular;
struct vi_ce_ib_state_chained_ib chained;
} ce_payload = {};
@@ -6989,7 +7176,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
{
uint64_t de_payload_addr, gds_addr, csa_addr;
int cnt_de;
- static union {
+ union {
struct vi_de_ib_state regular;
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 69182ee..7f15bb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
+#include <linux/kernel.h>
#include <linux/firmware.h>
#include <drm/drmP.h>
#include "amdgpu.h"
@@ -66,38 +67,70 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
{
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
- {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
+ { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
+ SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
};
static const u32 golden_settings_gc_9_0[] =
@@ -352,6 +385,25 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
return r;
}
+
+static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
+{
+ release_firmware(adev->gfx.pfp_fw);
+ adev->gfx.pfp_fw = NULL;
+ release_firmware(adev->gfx.me_fw);
+ adev->gfx.me_fw = NULL;
+ release_firmware(adev->gfx.ce_fw);
+ adev->gfx.ce_fw = NULL;
+ release_firmware(adev->gfx.rlc_fw);
+ adev->gfx.rlc_fw = NULL;
+ release_firmware(adev->gfx.mec_fw);
+ adev->gfx.mec_fw = NULL;
+ release_firmware(adev->gfx.mec2_fw);
+ adev->gfx.mec2_fw = NULL;
+
+ kfree(adev->gfx.rlc.register_list_format);
+}
+
static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
{
const char *chip_name;
@@ -1120,30 +1172,22 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
int r;
- u32 data;
- u32 size;
- u32 base;
+ u32 data, base;
if (!amdgpu_ngg)
return 0;
/* Program buffer size */
- data = 0;
- size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
- data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
-
- size = adev->gfx.ngg.buf[NGG_POS].size / 256;
- data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
-
+ data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
+ adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
+ data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
+ adev->gfx.ngg.buf[NGG_POS].size >> 8);
WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
- data = 0;
- size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
- data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
-
- size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
- data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
-
+ data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
+ adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
+ data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
+ adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
/* Program buffer base address */
@@ -1306,7 +1350,10 @@ static int gfx_v9_0_sw_init(void *handle)
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
ring->ring_obj = NULL;
- sprintf(ring->name, "gfx");
+ if (!i)
+ sprintf(ring->name, "gfx");
+ else
+ sprintf(ring->name, "gfx_%d", i);
ring->use_doorbell = true;
ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
r = amdgpu_ring_init(adev, ring, 1024,
@@ -1346,7 +1393,7 @@ static int gfx_v9_0_sw_init(void *handle)
return r;
/* create MQD for all compute queues as wel as KIQ for SRIOV case */
- r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd));
+ r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
if (r)
return r;
@@ -1398,9 +1445,11 @@ static int gfx_v9_0_sw_fini(void *handle)
amdgpu_gfx_compute_mqd_sw_fini(adev);
amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
amdgpu_gfx_kiq_fini(adev);
+ amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
gfx_v9_0_mec_fini(adev);
gfx_v9_0_ngg_fini(adev);
+ gfx_v9_0_free_microcode(adev);
return 0;
}
@@ -1682,10 +1731,10 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
adev->gfx.rlc.reg_list_format_size_bytes >> 2,
unique_indirect_regs,
&unique_indirect_reg_count,
- sizeof(unique_indirect_regs)/sizeof(int),
+ ARRAY_SIZE(unique_indirect_regs),
indirect_start_offsets,
&indirect_start_offsets_count,
- sizeof(indirect_start_offsets)/sizeof(int));
+ ARRAY_SIZE(indirect_start_offsets));
/* enable auto inc in case it is disabled */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
@@ -1722,12 +1771,12 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
/* write the starting offsets to RLC scratch ram */
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
adev->gfx.rlc.starting_offsets_start);
- for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
+ for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
indirect_start_offsets[i]);
/* load unique indirect regs*/
- for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
+ for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
unique_indirect_regs[i] & 0x3FFFF);
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
@@ -1740,11 +1789,7 @@ static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
{
- u32 tmp = 0;
-
- tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
- tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
+ WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
}
static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
@@ -1822,16 +1867,11 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev
uint32_t default_data = 0;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
-
- if (enable == true) {
- data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
- if (default_data != data)
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- } else {
- data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
- if(default_data != data)
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
+ enable ? 1 : 0);
+ if (default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
}
static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
@@ -1841,16 +1881,11 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *ad
uint32_t default_data = 0;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
-
- if (enable == true) {
- data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
- if(default_data != data)
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- } else {
- data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
- if(default_data != data)
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
+ enable ? 1 : 0);
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
}
static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
@@ -1860,16 +1895,11 @@ static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
uint32_t default_data = 0;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
-
- if (enable == true) {
- data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
- if(default_data != data)
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- } else {
- data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
- if(default_data != data)
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ CP_PG_DISABLE,
+ enable ? 0 : 1);
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
}
static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
@@ -1878,10 +1908,9 @@ static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
uint32_t data, default_data;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
- if (enable == true)
- data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
- else
- data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ GFX_POWER_GATING_ENABLE,
+ enable ? 1 : 0);
if(default_data != data)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
}
@@ -1892,10 +1921,9 @@ static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
uint32_t data, default_data;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
- if (enable == true)
- data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
- else
- data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ GFX_PIPELINE_PG_ENABLE,
+ enable ? 1 : 0);
if(default_data != data)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
@@ -1910,10 +1938,9 @@ static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade
uint32_t data, default_data;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
- if (enable == true)
- data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
- else
- data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ STATIC_PER_CU_PG_ENABLE,
+ enable ? 1 : 0);
if(default_data != data)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
}
@@ -1924,10 +1951,9 @@ static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad
uint32_t data, default_data;
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
- if (enable == true)
- data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
- else
- data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+ data = REG_SET_FIELD(data, RLC_PG_CNTL,
+ DYN_PER_CU_PG_ENABLE,
+ enable ? 1 : 0);
if(default_data != data)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
}
@@ -1967,13 +1993,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
-
- tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
- WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
-
+ WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
gfx_v9_0_enable_gui_idle_interrupt(adev, false);
-
gfx_v9_0_wait_for_rlc_serdes(adev);
}
@@ -2045,8 +2066,10 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
{
int r;
- if (amdgpu_sriov_vf(adev))
+ if (amdgpu_sriov_vf(adev)) {
+ gfx_v9_0_init_csb(adev);
return 0;
+ }
gfx_v9_0_rlc_stop(adev);
@@ -2463,6 +2486,13 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
mqd->compute_misc_reserved = 0x00000003;
+ mqd->dynamic_cu_mask_addr_lo =
+ lower_32_bits(ring->mqd_gpu_addr
+ + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
+ mqd->dynamic_cu_mask_addr_hi =
+ upper_32_bits(ring->mqd_gpu_addr
+ + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
+
eop_base_addr = ring->eop_gpu_addr >> 8;
mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
@@ -2486,10 +2516,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
DOORBELL_SOURCE, 0);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_HIT, 0);
- }
- else
+ } else {
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_EN, 0);
+ }
mqd->cp_hqd_pq_doorbell_control = tmp;
@@ -2692,10 +2722,10 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
gfx_v9_0_kiq_setting(ring);
- if (adev->gfx.in_reset) { /* for GPU_RESET case */
+ if (adev->in_sriov_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
- memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
+ memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
/* reset ring buffer */
ring->wptr = 0;
@@ -2707,7 +2737,9 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
soc15_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
} else {
- memset((void *)mqd, 0, sizeof(*mqd));
+ memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
+ ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
+ ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
mutex_lock(&adev->srbm_mutex);
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v9_0_mqd_init(ring);
@@ -2716,7 +2748,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
mutex_unlock(&adev->srbm_mutex);
if (adev->gfx.mec.mqd_backup[mqd_idx])
- memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
+ memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
}
return 0;
@@ -2728,8 +2760,10 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
struct v9_mqd *mqd = ring->mqd_ptr;
int mqd_idx = ring - &adev->gfx.compute_ring[0];
- if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
- memset((void *)mqd, 0, sizeof(*mqd));
+ if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
+ memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
+ ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
+ ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
mutex_lock(&adev->srbm_mutex);
soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
gfx_v9_0_mqd_init(ring);
@@ -2737,11 +2771,11 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
mutex_unlock(&adev->srbm_mutex);
if (adev->gfx.mec.mqd_backup[mqd_idx])
- memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
- } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
+ memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
+ } else if (adev->in_sriov_reset) { /* for GPU_RESET case */
/* reset MQD to a clean status */
if (adev->gfx.mec.mqd_backup[mqd_idx])
- memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
+ memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
/* reset ring buffer */
ring->wptr = 0;
@@ -2882,12 +2916,70 @@ static int gfx_v9_0_hw_init(void *handle)
return r;
}
+static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = kiq_ring->adev;
+ uint32_t scratch, tmp = 0;
+ int r, i;
+
+ r = amdgpu_gfx_scratch_get(adev, &scratch);
+ if (r) {
+ DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+
+ r = amdgpu_ring_alloc(kiq_ring, 10);
+ if (r) {
+ DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+ amdgpu_gfx_scratch_free(adev, scratch);
+ return r;
+ }
+
+ /* unmap queues */
+ amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
+ amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
+ PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
+ PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
+ PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
+ PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
+ amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
+ amdgpu_ring_write(kiq_ring, 0);
+ amdgpu_ring_write(kiq_ring, 0);
+ amdgpu_ring_write(kiq_ring, 0);
+ /* write to scratch for completion */
+ amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+ amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
+ amdgpu_ring_commit(kiq_ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+ if (i >= adev->usec_timeout) {
+ DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
+ r = -EINVAL;
+ }
+ amdgpu_gfx_scratch_free(adev, scratch);
+ return r;
+}
+
+
static int gfx_v9_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i;
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+
+ /* disable KCQ to avoid CPC touch memory not valid anymore */
+ for (i = 0; i < adev->gfx.num_compute_rings; i++)
+ gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
+
if (amdgpu_sriov_vf(adev)) {
pr_debug("For SRIOV client, shouldn't do anything.\n");
return 0;
@@ -2930,15 +3022,10 @@ static bool gfx_v9_0_is_idle(void *handle)
static int gfx_v9_0_wait_for_idle(void *handle)
{
unsigned i;
- u32 tmp;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
- /* read MC_STATUS */
- tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
- GRBM_STATUS__GUI_ACTIVE_MASK;
-
- if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
+ if (gfx_v9_0_is_idle(handle))
return 0;
udelay(1);
}
@@ -3497,9 +3584,11 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
u32 ref_and_mask, reg_mem_engine;
- struct nbio_hdp_flush_reg *nbio_hf_reg;
+ const struct nbio_hdp_flush_reg *nbio_hf_reg;
- if (ring->adev->asic_type == CHIP_VEGA10)
+ if (ring->adev->flags & AMD_IS_APU)
+ nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
+ else
nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
@@ -3528,7 +3617,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
gfx_v9_0_write_data_to_reg(ring, 0, true,
- SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
+ SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
}
static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
@@ -3718,7 +3807,7 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
{
- static struct v9_ce_ib_state ce_payload = {0};
+ struct v9_ce_ib_state ce_payload = {0};
uint64_t csa_addr;
int cnt;
@@ -3737,7 +3826,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
{
- static struct v9_de_ib_state de_payload = {0};
+ struct v9_de_ib_state de_payload = {0};
uint64_t csa_addr, gds_addr;
int cnt;
@@ -3757,6 +3846,12 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
}
+static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
+{
+ amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
+ amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
+}
+
static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
{
uint32_t dw2 = 0;
@@ -3764,6 +3859,8 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
if (amdgpu_sriov_vf(ring->adev))
gfx_v9_0_ring_emit_ce_meta(ring);
+ gfx_v9_0_ring_emit_tmz(ring, true);
+
dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
/* set load_global_config & load_global_uconfig */
@@ -3814,12 +3911,6 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
}
-static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
-{
- amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
- amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
-}
-
static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
{
struct amdgpu_device *adev = ring->adev;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 6c8040e..c17996e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -319,6 +319,12 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ if (!value) {
+ tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_NO_RETRY_FAULT, 1);
+ tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_RETRY_FAULT, 1);
+ }
WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 5be9c83..f4603a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -831,7 +831,7 @@ static int gmc_v6_0_sw_init(void *handle)
if (r)
return r;
- amdgpu_vm_adjust_size(adev, 64, 4);
+ amdgpu_vm_adjust_size(adev, 64, 9);
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
adev->mc.mc_mask = 0xffffffffffULL;
@@ -901,6 +901,8 @@ static int gmc_v6_0_sw_fini(void *handle)
gmc_v6_0_gart_fini(adev);
amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
+ release_firmware(adev->mc.fw);
+ adev->mc.fw = NULL;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index eace9e7..b0528ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -970,7 +970,7 @@ static int gmc_v7_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits.
*/
- amdgpu_vm_adjust_size(adev, 64, 4);
+ amdgpu_vm_adjust_size(adev, 64, 9);
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
/* Set the internal MC address mask
@@ -1050,6 +1050,8 @@ static int gmc_v7_0_sw_fini(void *handle)
gmc_v7_0_gart_fini(adev);
amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
+ release_firmware(adev->mc.fw);
+ adev->mc.fw = NULL;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 3b3326d..f368cfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1067,7 +1067,7 @@ static int gmc_v8_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits.
*/
- amdgpu_vm_adjust_size(adev, 64, 4);
+ amdgpu_vm_adjust_size(adev, 64, 9);
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
/* Set the internal MC address mask
@@ -1147,6 +1147,8 @@ static int gmc_v8_0_sw_fini(void *handle)
gmc_v8_0_gart_fini(adev);
amdgpu_gem_force_release(adev);
amdgpu_bo_fini(adev);
+ release_firmware(adev->mc.fw);
+ adev->mc.fw = NULL;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index d04d0b1..6216993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -32,6 +32,8 @@
#include "vega10/DC/dce_12_0_offset.h"
#include "vega10/DC/dce_12_0_sh_mask.h"
#include "vega10/vega10_enum.h"
+#include "vega10/MMHUB/mmhub_1_0_offset.h"
+#include "vega10/ATHUB/athub_1_0_offset.h"
#include "soc15_common.h"
@@ -71,13 +73,25 @@ static const u32 golden_settings_vega10_hdp[] =
0xf6e, 0x0fffffff, 0x00000000,
};
+static const u32 golden_settings_mmhub_1_0_0[] =
+{
+ SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
+};
+
+static const u32 golden_settings_athub_1_0_0[] =
+{
+ SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
+ SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
+};
+
static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned type,
enum amdgpu_interrupt_state state)
{
struct amdgpu_vmhub *hub;
- u32 tmp, reg, bits, i;
+ u32 tmp, reg, bits, i, j;
bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
@@ -89,43 +103,26 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
- /* MM HUB */
- hub = &adev->vmhub[AMDGPU_MMHUB];
- for (i = 0; i< 16; i++) {
- reg = hub->vm_context0_cntl + i;
- tmp = RREG32(reg);
- tmp &= ~bits;
- WREG32(reg, tmp);
- }
-
- /* GFX HUB */
- hub = &adev->vmhub[AMDGPU_GFXHUB];
- for (i = 0; i < 16; i++) {
- reg = hub->vm_context0_cntl + i;
- tmp = RREG32(reg);
- tmp &= ~bits;
- WREG32(reg, tmp);
+ for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
+ hub = &adev->vmhub[j];
+ for (i = 0; i < 16; i++) {
+ reg = hub->vm_context0_cntl + i;
+ tmp = RREG32(reg);
+ tmp &= ~bits;
+ WREG32(reg, tmp);
+ }
}
break;
case AMDGPU_IRQ_STATE_ENABLE:
- /* MM HUB */
- hub = &adev->vmhub[AMDGPU_MMHUB];
- for (i = 0; i< 16; i++) {
- reg = hub->vm_context0_cntl + i;
- tmp = RREG32(reg);
- tmp |= bits;
- WREG32(reg, tmp);
+ for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
+ hub = &adev->vmhub[j];
+ for (i = 0; i < 16; i++) {
+ reg = hub->vm_context0_cntl + i;
+ tmp = RREG32(reg);
+ tmp |= bits;
+ WREG32(reg, tmp);
+ }
}
-
- /* GFX HUB */
- hub = &adev->vmhub[AMDGPU_GFXHUB];
- for (i = 0; i < 16; i++) {
- reg = hub->vm_context0_cntl + i;
- tmp = RREG32(reg);
- tmp |= bits;
- WREG32(reg, tmp);
- }
- break;
default:
break;
}
@@ -682,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_VEGA10:
+ amdgpu_program_register_sequence(adev,
+ golden_settings_mmhub_1_0_0,
+ (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+ amdgpu_program_register_sequence(adev,
+ golden_settings_athub_1_0_0,
+ (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
case CHIP_RAVEN:
+ amdgpu_program_register_sequence(adev,
+ golden_settings_athub_1_0_0,
+ (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
default:
break;
@@ -713,12 +719,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
if (r)
return r;
- /* After HDP is initialized, flush HDP.*/
- if (adev->flags & AMD_IS_APU)
- nbio_v7_0_hdp_flush(adev);
- else
- nbio_v6_1_hdp_flush(adev);
-
switch (adev->asic_type) {
case CHIP_RAVEN:
mmhub_v1_0_initialize_power_gating(adev);
@@ -736,13 +736,16 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
if (r)
return r;
- tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
- tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
- WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
+ WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
+ /* After HDP is initialized, flush HDP.*/
+ if (adev->flags & AMD_IS_APU)
+ nbio_v7_0_hdp_flush(adev);
+ else
+ nbio_v6_1_hdp_flush(adev);
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
value = false;
@@ -751,7 +754,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
gfxhub_v1_0_set_fault_enable_default(adev, value);
mmhub_v1_0_set_fault_enable_default(adev, value);
-
gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
@@ -770,17 +772,11 @@ static int gmc_v9_0_hw_init(void *handle)
gmc_v9_0_init_golden_registers(adev);
if (adev->mode_info.num_crtc) {
- u32 tmp;
-
/* Lockout access through VGA aperture*/
- tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL);
- tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
- WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp);
+ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
/* disable VGA render */
- tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL);
- tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
- WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp);
+ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
}
r = gmc_v9_0_gart_enable(adev);
@@ -822,9 +818,7 @@ static int gmc_v9_0_suspend(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- gmc_v9_0_hw_fini(adev);
-
- return 0;
+ return gmc_v9_0_hw_fini(adev);
}
static int gmc_v9_0_resume(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 7a0ea27..bd592cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -208,6 +208,34 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
}
/**
+ * iceland_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool iceland_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ u32 ring_index = adev->irq.ih.rptr >> 2;
+ u16 pasid;
+
+ switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
+ case 146:
+ case 147:
+ pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
+ if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
+ return true;
+ break;
+ default:
+ /* Not a VM fault */
+ return true;
+ }
+
+ adev->irq.ih.rptr += 16;
+ return false;
+}
+
+/**
* iceland_ih_decode_iv - decode an interrupt vector
*
* @adev: amdgpu_device pointer
@@ -412,6 +440,7 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
static const struct amdgpu_ih_funcs iceland_ih_funcs = {
.get_wptr = iceland_ih_get_wptr,
+ .prescreen_iv = iceland_ih_prescreen_iv,
.decode_iv = iceland_ih_decode_iv,
.set_rptr = iceland_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 3bbf2cc..f33d1ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -42,7 +42,6 @@
#define KV_MINIMUM_ENGINE_CLOCK 800
#define SMC_RAM_END 0x40000
-static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
static int kv_enable_nb_dpm(struct amdgpu_device *adev,
bool enable);
@@ -64,7 +63,7 @@ static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
int min_temp, int max_temp);
static int kv_init_fps_limits(struct amdgpu_device *adev);
-static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
+static void kv_dpm_powergate_uvd(void *handle, bool gate);
static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
@@ -1245,8 +1244,9 @@ static void kv_update_requested_ps(struct amdgpu_device *adev,
adev->pm.dpm.requested_ps = &pi->requested_rps;
}
-static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
+static void kv_dpm_enable_bapm(void *handle, bool enable)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
int ret;
@@ -1672,8 +1672,9 @@ static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
return kv_enable_acp_dpm(adev, !gate);
}
-static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
+static void kv_dpm_powergate_uvd(void *handle, bool gate)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
int ret;
@@ -1868,10 +1869,11 @@ static int kv_enable_nb_dpm(struct amdgpu_device *adev,
return ret;
}
-static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
+static int kv_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
ret = kv_force_dpm_highest(adev);
@@ -1892,8 +1894,9 @@ static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
return 0;
}
-static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
+static int kv_dpm_pre_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
struct amdgpu_ps *new_ps = &requested_ps;
@@ -1907,8 +1910,9 @@ static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
return 0;
}
-static int kv_dpm_set_power_state(struct amdgpu_device *adev)
+static int kv_dpm_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
struct amdgpu_ps *new_ps = &pi->requested_rps;
struct amdgpu_ps *old_ps = &pi->current_rps;
@@ -1981,8 +1985,9 @@ static int kv_dpm_set_power_state(struct amdgpu_device *adev)
return 0;
}
-static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)
+static void kv_dpm_post_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
struct amdgpu_ps *new_ps = &pi->requested_rps;
@@ -2848,9 +2853,10 @@ static int kv_dpm_init(struct amdgpu_device *adev)
}
static void
-kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
+kv_dpm_debugfs_print_current_performance_level(void *handle,
struct seq_file *m)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
u32 current_index =
(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
@@ -2875,11 +2881,12 @@ kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
}
static void
-kv_dpm_print_power_state(struct amdgpu_device *adev,
- struct amdgpu_ps *rps)
+kv_dpm_print_power_state(void *handle, void *request_ps)
{
int i;
+ struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
struct kv_ps *ps = kv_get_ps(rps);
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_dpm_print_class_info(rps->class, rps->class2);
amdgpu_dpm_print_cap_info(rps->caps);
@@ -2905,13 +2912,14 @@ static void kv_dpm_fini(struct amdgpu_device *adev)
amdgpu_free_extended_power_table(adev);
}
-static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev)
+static void kv_dpm_display_configuration_changed(void *handle)
{
}
-static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
+static u32 kv_dpm_get_sclk(void *handle, bool low)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
@@ -2921,18 +2929,20 @@ static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
return requested_state->levels[requested_state->num_levels - 1].sclk;
}
-static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low)
+static u32 kv_dpm_get_mclk(void *handle, bool low)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
return pi->sys_info.bootup_uma_clk;
}
/* get temperature in millidegrees */
-static int kv_dpm_get_temp(struct amdgpu_device *adev)
+static int kv_dpm_get_temp(void *handle)
{
u32 temp;
int actual_temp = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
temp = RREG32_SMC(0xC0300E0C);
@@ -2950,7 +2960,6 @@ static int kv_dpm_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- kv_dpm_set_dpm_funcs(adev);
kv_dpm_set_irq_funcs(adev);
return 0;
@@ -2960,16 +2969,10 @@ static int kv_dpm_late_init(void *handle)
{
/* powerdown unused blocks for now */
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- int ret;
if (!amdgpu_dpm)
return 0;
- /* init the sysfs and debugfs files late */
- ret = amdgpu_pm_sysfs_init(adev);
- if (ret)
- return ret;
-
kv_dpm_powergate_acp(adev, true);
kv_dpm_powergate_samu(adev, true);
@@ -3031,7 +3034,6 @@ static int kv_dpm_sw_fini(void *handle)
flush_work(&adev->pm.dpm.thermal.work);
mutex_lock(&adev->pm.mutex);
- amdgpu_pm_sysfs_fini(adev);
kv_dpm_fini(adev);
mutex_unlock(&adev->pm.mutex);
@@ -3222,14 +3224,17 @@ static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
(kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
}
-static int kv_check_state_equal(struct amdgpu_device *adev,
- struct amdgpu_ps *cps,
- struct amdgpu_ps *rps,
+static int kv_check_state_equal(void *handle,
+ void *current_ps,
+ void *request_ps,
bool *equal)
{
struct kv_ps *kv_cps;
struct kv_ps *kv_rps;
int i;
+ struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
+ struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
return -EINVAL;
@@ -3262,9 +3267,10 @@ static int kv_check_state_equal(struct amdgpu_device *adev,
return 0;
}
-static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+static int kv_dpm_read_sensor(void *handle, int idx,
void *value, int *size)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct kv_power_info *pi = kv_get_pi(adev);
uint32_t sclk;
u32 pl_index =
@@ -3312,7 +3318,7 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = {
.set_powergating_state = kv_dpm_set_powergating_state,
};
-static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
+const struct amd_pm_funcs kv_dpm_funcs = {
.get_temperature = &kv_dpm_get_temp,
.pre_set_power_state = &kv_dpm_pre_set_power_state,
.set_power_state = &kv_dpm_set_power_state,
@@ -3330,12 +3336,6 @@ static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
.read_sensor = &kv_dpm_read_sensor,
};
-static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
-{
- if (adev->pm.funcs == NULL)
- adev->pm.funcs = &kv_dpm_funcs;
-}
-
static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
.set = kv_dpm_set_interrupt_state,
.process = kv_dpm_process_interrupt,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 74cb647..cc21c4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -273,7 +273,7 @@ static const struct pctl_data pctl0_data[] = {
{0x135, 0x12a810},
{0x149, 0x7a82c}
};
-#define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0]))
+#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
#define PCTL0_RENG_EXEC_END_PTR 0x151
#define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640
@@ -309,7 +309,7 @@ static const struct pctl_data pctl1_data[] = {
{0x1f0, 0x5000a7f6},
{0x1f1, 0x5000a7e4}
};
-#define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0]))
+#define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data))
#define PCTL1_RENG_EXEC_END_PTR 0x1f1
#define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000
@@ -561,6 +561,13 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ if (!value) {
+ tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_NO_RETRY_FAULT, 1);
+ tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_RETRY_FAULT, 1);
+ }
+
WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 2812d88..b4906d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -183,6 +183,12 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
return r;
}
+ /* Retrieve checksum from mailbox2 */
+ if (req == IDH_REQ_GPU_INIT_ACCESS) {
+ adev->virt.fw_reserve.checksum_key =
+ RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+ mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
+ }
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
index 1e91b9a..67e7857 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
@@ -24,7 +24,7 @@
#ifndef __MXGPU_AI_H__
#define __MXGPU_AI_H__
-#define AI_MAILBOX_TIMEDOUT 5000
+#define AI_MAILBOX_TIMEDOUT 12000
enum idh_request {
IDH_REQ_GPU_INIT_ACCESS = 1,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h
index c791d73..f13dc6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h
@@ -23,7 +23,7 @@
#ifndef __MXGPU_VI_H__
#define __MXGPU_VI_H__
-#define VI_MAILBOX_TIMEDOUT 5000
+#define VI_MAILBOX_TIMEDOUT 12000
#define VI_MAILBOX_RESET_TIME 12
/* VI mailbox messages request */
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 045988b..904a1ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -215,31 +215,27 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
*flags |= AMD_CG_SUPPORT_BIF_LS;
}
-struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
-struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
+const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
+ .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ),
+ .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE),
+ .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
+ .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
+ .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
+ .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
+ .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
+ .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
+ .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
+ .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
+ .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
+ .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
+ .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
+ .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
+};
-int nbio_v6_1_init(struct amdgpu_device *adev)
-{
- nbio_v6_1_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
- nbio_v6_1_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK;
- nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK;
-
- nbio_v6_1_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
- nbio_v6_1_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
-
- return 0;
-}
+const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
+ .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
+ .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
+};
void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index 686e4b4..14ca8d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -26,8 +26,8 @@
#include "soc15_common.h"
-extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
-extern struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
+extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
+extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
int nbio_v6_1_init(struct amdgpu_device *adev);
u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
uint32_t idx);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 11b70d6..f802b97 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -185,28 +185,24 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev)
WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
}
-struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
-struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
+const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
+ .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ),
+ .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE),
+ .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
+ .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
+ .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
+ .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
+ .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
+ .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
+ .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
+ .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
+ .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
+ .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
+ .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
+ .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
+};
-int nbio_v7_0_init(struct amdgpu_device *adev)
-{
- nbio_v7_0_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
- nbio_v7_0_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
- nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
-
- nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
- nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
-
- return 0;
-}
+const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data = {
+ .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2),
+ .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
index 054ff49..df8fa90 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
@@ -26,8 +26,8 @@
#include "soc15_common.h"
-extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
-extern struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
+extern const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
+extern const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
int nbio_v7_0_init(struct amdgpu_device *adev);
u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
uint32_t idx);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index f7cf994..4e20d91 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -35,6 +35,8 @@
#include "raven1/GC/gc_9_1_offset.h"
#include "raven1/SDMA0/sdma0_4_1_offset.h"
+MODULE_FIRMWARE("amdgpu/raven_asd.bin");
+
static int
psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
{
@@ -136,15 +138,13 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
{
int ret;
uint64_t fw_mem_mc_addr = ucode->mc_addr;
- struct common_firmware_header *header;
memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
- header = (struct common_firmware_header *)ucode->fw;
cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
+ cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
if (ret)
@@ -209,7 +209,7 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
return ret;
}
-int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
+int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
{
int ret = 0;
struct psp_ring *ring;
@@ -229,6 +229,19 @@ int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x80000000, false);
+ return ret;
+}
+
+int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ struct psp_ring *ring = &psp->km_ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ ret = psp_v10_0_ring_stop(psp, ring_type);
+ if (ret)
+ DRM_ERROR("Fail to stop psp ring\n");
+
amdgpu_bo_free_kernel(&adev->firmware.rbuf,
&ring->ring_mem_mc_addr,
(void **)&ring->ring_mem);
@@ -244,16 +257,31 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
unsigned int psp_write_ptr_reg = 0;
struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
struct psp_ring *ring = &psp->km_ring;
+ struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+ struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+ ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
struct amdgpu_device *adev = psp->adev;
+ uint32_t ring_size_dw = ring->ring_size / 4;
+ uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
/* KM (GPCOM) prepare write pointer */
psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
/* Update KM RB frame pointer to new frame */
- if ((psp_write_ptr_reg % ring->ring_size) == 0)
- write_frame = ring->ring_mem;
+ if ((psp_write_ptr_reg % ring_size_dw) == 0)
+ write_frame = ring_buffer_start;
else
- write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
+ write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+ /* Check invalid write_frame ptr address */
+ if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+ DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+ ring_buffer_start, ring_buffer_end, write_frame);
+ DRM_ERROR("write_frame is pointing to address out of bounds\n");
+ return -EINVAL;
+ }
+
+ /* Initialize KM RB frame */
+ memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
/* Update KM RB frame */
write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
@@ -263,8 +291,7 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
write_frame->fence_value = index;
/* Update the write Pointer in DWORDs */
- psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
- psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
+ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
return 0;
@@ -390,3 +417,10 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp,
return true;
}
+
+
+int psp_v10_0_mode1_reset(struct psp_context *psp)
+{
+ DRM_INFO("psp mode 1 reset not supported now! \n");
+ return -EINVAL;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index e76cde2..451e830 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v10_0_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type);
+extern int psp_v10_0_ring_stop(struct psp_context *psp,
+ enum psp_ring_type ring_type);
extern int psp_v10_0_ring_destroy(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v10_0_cmd_submit(struct psp_context *psp,
@@ -43,4 +45,6 @@ extern int psp_v10_0_cmd_submit(struct psp_context *psp,
extern bool psp_v10_0_compare_sram_data(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
enum AMDGPU_UCODE_ID ucode_type);
+
+extern int psp_v10_0_mode1_reset(struct psp_context *psp);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 2a535a4..c7bcfe8 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -319,7 +319,7 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
return ret;
}
-int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
+int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
{
int ret = 0;
struct psp_ring *ring;
@@ -339,6 +339,19 @@ int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x80000000, false);
+ return ret;
+}
+
+int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ struct psp_ring *ring = &psp->km_ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ ret = psp_v3_1_ring_stop(psp, ring_type);
+ if (ret)
+ DRM_ERROR("Fail to stop psp ring\n");
+
amdgpu_bo_free_kernel(&adev->firmware.rbuf,
&ring->ring_mem_mc_addr,
(void **)&ring->ring_mem);
@@ -354,6 +367,9 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
unsigned int psp_write_ptr_reg = 0;
struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
struct psp_ring *ring = &psp->km_ring;
+ struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+ struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+ ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
struct amdgpu_device *adev = psp->adev;
uint32_t ring_size_dw = ring->ring_size / 4;
uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
@@ -365,9 +381,16 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
/* write_frame ptr increments by size of rb_frame in bytes */
/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
if ((psp_write_ptr_reg % ring_size_dw) == 0)
- write_frame = ring->ring_mem;
+ write_frame = ring_buffer_start;
else
- write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
+ write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+ /* Check invalid write_frame ptr address */
+ if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+ DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+ ring_buffer_start, ring_buffer_end, write_frame);
+ DRM_ERROR("write_frame is pointing to address out of bounds\n");
+ return -EINVAL;
+ }
/* Initialize KM RB frame */
memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
@@ -517,3 +540,37 @@ bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);
return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
}
+
+int psp_v3_1_mode1_reset(struct psp_context *psp)
+{
+ int ret;
+ uint32_t offset;
+ struct amdgpu_device *adev = psp->adev;
+
+ offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
+
+ ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
+
+ if (ret) {
+ DRM_INFO("psp is not working correctly before mode1 reset!\n");
+ return -EINVAL;
+ }
+
+ /*send the mode 1 reset command*/
+ WREG32(offset, 0x70000);
+
+ mdelay(1000);
+
+ offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
+
+ ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
+
+ if (ret) {
+ DRM_INFO("psp mode 1 reset failed!\n");
+ return -EINVAL;
+ }
+
+ DRM_INFO("psp mode1 reset succeed \n");
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
index 9dcd0b2..b05dbad 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
@@ -41,6 +41,8 @@ extern int psp_v3_1_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v3_1_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type);
+extern int psp_v3_1_ring_stop(struct psp_context *psp,
+ enum psp_ring_type ring_type);
extern int psp_v3_1_ring_destroy(struct psp_context *psp,
enum psp_ring_type ring_type);
extern int psp_v3_1_cmd_submit(struct psp_context *psp,
@@ -51,4 +53,5 @@ extern bool psp_v3_1_compare_sram_data(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
enum AMDGPU_UCODE_ID ucode_type);
extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp);
+extern int psp_v3_1_mode1_reset(struct psp_context *psp);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index f2d0710..67f375b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -561,21 +561,11 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
{
int r;
- if (!adev->pp_enabled) {
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
- r = sdma_v2_4_load_microcode(adev);
- if (r)
- return r;
- } else {
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- AMDGPU_UCODE_ID_SDMA0);
- if (r)
- return -EINVAL;
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- AMDGPU_UCODE_ID_SDMA1);
- if (r)
- return -EINVAL;
- }
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ r = sdma_v2_4_load_microcode(adev);
+ if (r)
+ return r;
}
/* halt the engine before programing */
@@ -1324,8 +1314,13 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
}
static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
+ .copy_pte_num_dw = 7,
.copy_pte = sdma_v2_4_vm_copy_pte,
+
.write_pte = sdma_v2_4_vm_write_pte,
+
+ .set_max_nums_pte_pde = 0x1fffff >> 3,
+ .set_pte_pde_num_dw = 10,
.set_pte_pde = sdma_v2_4_vm_set_pte_pde,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index b1de44f..6d06f8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -379,8 +379,10 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
if (ring->use_doorbell) {
+ u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
+
/* XXX check if swapping is necessary on BE */
- adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2;
+ WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
} else {
int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
@@ -641,10 +643,11 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- u32 rb_cntl, ib_cntl;
+ u32 rb_cntl, ib_cntl, wptr_poll_cntl;
u32 rb_bufsz;
u32 wb_offset;
u32 doorbell;
+ u64 wptr_gpu_addr;
int i, j, r;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -707,6 +710,20 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
}
WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
+ /* setup the wptr shadow polling */
+ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+
+ WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
+ lower_32_bits(wptr_gpu_addr));
+ WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
+ upper_32_bits(wptr_gpu_addr));
+ wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
+ if (amdgpu_sriov_vf(adev))
+ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
+ else
+ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
+ WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
+
/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
@@ -802,23 +819,12 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
*/
static int sdma_v3_0_start(struct amdgpu_device *adev)
{
- int r, i;
+ int r;
- if (!adev->pp_enabled) {
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
- r = sdma_v3_0_load_microcode(adev);
- if (r)
- return r;
- } else {
- for (i = 0; i < adev->sdma.num_instances; i++) {
- r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
- (i == 0) ?
- AMDGPU_UCODE_ID_SDMA0 :
- AMDGPU_UCODE_ID_SDMA1);
- if (r)
- return -EINVAL;
- }
- }
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ r = sdma_v3_0_load_microcode(adev);
+ if (r)
+ return r;
}
/* disable sdma engine before programing it */
@@ -1713,11 +1719,11 @@ static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
}
static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
- .copy_max_bytes = 0x1fffff,
+ .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
.copy_num_dw = 7,
.emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
- .fill_max_bytes = 0x1fffff,
+ .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
.fill_num_dw = 5,
.emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
};
@@ -1731,8 +1737,14 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
}
static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
+ .copy_pte_num_dw = 7,
.copy_pte = sdma_v3_0_vm_copy_pte,
+
.write_pte = sdma_v3_0_vm_write_pte,
+
+ /* not 0x3fffff due to HW limitation */
+ .set_max_nums_pte_pde = 0x3fffe0 >> 3,
+ .set_pte_pde_num_dw = 10,
.set_pte_pde = sdma_v3_0_vm_set_pte_pde,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fd7c72a..46009db 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -54,7 +54,7 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
static const u32 golden_settings_sdma_4[] = {
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
@@ -89,7 +89,7 @@ static const u32 golden_settings_sdma_vg10[] = {
static const u32 golden_settings_sdma_4_1[] =
{
- SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
@@ -371,7 +371,7 @@ static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
u32 ref_and_mask = 0;
- struct nbio_hdp_flush_reg *nbio_hf_reg;
+ const struct nbio_hdp_flush_reg *nbio_hf_reg;
if (ring->adev->flags & AMD_IS_APU)
nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
@@ -398,7 +398,7 @@ static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0));
+ amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE));
amdgpu_ring_write(ring, 1);
}
@@ -1264,6 +1264,11 @@ static int sdma_v4_0_sw_fini(void *handle)
for (i = 0; i < adev->sdma.num_instances; i++)
amdgpu_ring_fini(&adev->sdma.instance[i].ring);
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ release_firmware(adev->sdma.instance[i].fw);
+ adev->sdma.instance[i].fw = NULL;
+ }
+
return 0;
}
@@ -1714,8 +1719,13 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
}
static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
+ .copy_pte_num_dw = 7,
.copy_pte = sdma_v4_0_vm_copy_pte,
+
.write_pte = sdma_v4_0_vm_write_pte,
+
+ .set_max_nums_pte_pde = 0x400000 >> 3,
+ .set_pte_pde_num_dw = 10,
.set_pte_pde = sdma_v4_0_vm_set_pte_pde,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 112969f..3fa2fbf 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -887,8 +887,13 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev)
}
static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
+ .copy_pte_num_dw = 5,
.copy_pte = si_dma_vm_copy_pte,
+
.write_pte = si_dma_vm_write_pte,
+
+ .set_max_nums_pte_pde = 0xffff8 >> 3,
+ .set_pte_pde_num_dw = 9,
.set_pte_pde = si_dma_vm_set_pte_pde,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index d63873f..51fd0c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -1847,7 +1847,6 @@ static int si_calculate_sclk_params(struct amdgpu_device *adev,
static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
-static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
@@ -3060,9 +3059,9 @@ static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
return ret;
}
-static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
+static bool si_dpm_vblank_too_short(void *handle)
{
-
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
/* we never hit the non-gddr5 limit so disable it */
u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
@@ -3871,9 +3870,10 @@ static int si_restrict_performance_levels_before_switch(struct amdgpu_device *ad
0 : -EINVAL;
}
-static int si_dpm_force_performance_level(struct amdgpu_device *adev,
+static int si_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
struct si_ps *ps = si_get_ps(rps);
u32 levels = ps->performance_level_count;
@@ -6575,11 +6575,12 @@ static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
}
}
-static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
+static int si_dpm_get_fan_speed_percent(void *handle,
u32 *speed)
{
u32 duty, duty100;
u64 tmp64;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->pm.no_fan)
return -ENOENT;
@@ -6600,9 +6601,10 @@ static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
return 0;
}
-static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
+static int si_dpm_set_fan_speed_percent(void *handle,
u32 speed)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct si_power_info *si_pi = si_get_pi(adev);
u32 tmp;
u32 duty, duty100;
@@ -6633,8 +6635,10 @@ static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
return 0;
}
-static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
+static void si_dpm_set_fan_control_mode(void *handle, u32 mode)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
if (mode) {
/* stop auto-manage */
if (adev->pm.dpm.fan.ucode_fan_control)
@@ -6649,8 +6653,9 @@ static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
}
}
-static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
+static u32 si_dpm_get_fan_control_mode(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct si_power_info *si_pi = si_get_pi(adev);
u32 tmp;
@@ -6946,8 +6951,9 @@ static void si_dpm_disable(struct amdgpu_device *adev)
ni_update_current_ps(adev, boot_ps);
}
-static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
+static int si_dpm_pre_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
struct amdgpu_ps *new_ps = &requested_ps;
@@ -6984,8 +6990,9 @@ static int si_power_control_set_level(struct amdgpu_device *adev)
return 0;
}
-static int si_dpm_set_power_state(struct amdgpu_device *adev)
+static int si_dpm_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
struct amdgpu_ps *old_ps = &eg_pi->current_rps;
@@ -7086,8 +7093,9 @@ static int si_dpm_set_power_state(struct amdgpu_device *adev)
return 0;
}
-static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
+static void si_dpm_post_set_power_state(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
@@ -7103,8 +7111,10 @@ void si_dpm_reset_asic(struct amdgpu_device *adev)
}
#endif
-static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
+static void si_dpm_display_configuration_changed(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
si_program_display_gap(adev);
}
@@ -7486,9 +7496,10 @@ static void si_dpm_fini(struct amdgpu_device *adev)
amdgpu_free_extended_power_table(adev);
}
-static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
+static void si_dpm_debugfs_print_current_performance_level(void *handle,
struct seq_file *m)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct amdgpu_ps *rps = &eg_pi->current_rps;
struct si_ps *ps = si_get_ps(rps);
@@ -7593,11 +7604,6 @@ static int si_dpm_late_init(void *handle)
if (!amdgpu_dpm)
return 0;
- /* init the sysfs and debugfs files late */
- ret = amdgpu_pm_sysfs_init(adev);
- if (ret)
- return ret;
-
ret = si_set_temperature_range(adev);
if (ret)
return ret;
@@ -7753,7 +7759,6 @@ static int si_dpm_sw_fini(void *handle)
flush_work(&adev->pm.dpm.thermal.work);
mutex_lock(&adev->pm.mutex);
- amdgpu_pm_sysfs_fini(adev);
si_dpm_fini(adev);
mutex_unlock(&adev->pm.mutex);
@@ -7860,10 +7865,11 @@ static int si_dpm_set_powergating_state(void *handle,
}
/* get temperature in millidegrees */
-static int si_dpm_get_temp(struct amdgpu_device *adev)
+static int si_dpm_get_temp(void *handle)
{
u32 temp;
int actual_temp = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
CTF_TEMP_SHIFT;
@@ -7878,8 +7884,9 @@ static int si_dpm_get_temp(struct amdgpu_device *adev)
return actual_temp;
}
-static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
+static u32 si_dpm_get_sclk(void *handle, bool low)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
@@ -7889,8 +7896,9 @@ static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
}
-static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
+static u32 si_dpm_get_mclk(void *handle, bool low)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
@@ -7900,9 +7908,11 @@ static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
}
-static void si_dpm_print_power_state(struct amdgpu_device *adev,
- struct amdgpu_ps *rps)
+static void si_dpm_print_power_state(void *handle,
+ void *current_ps)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
struct si_ps *ps = si_get_ps(rps);
struct rv7xx_pl *pl;
int i;
@@ -7927,7 +7937,6 @@ static int si_dpm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- si_dpm_set_dpm_funcs(adev);
si_dpm_set_irq_funcs(adev);
return 0;
}
@@ -7942,20 +7951,23 @@ static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
(si_cpl1->vddci == si_cpl2->vddci));
}
-static int si_check_state_equal(struct amdgpu_device *adev,
- struct amdgpu_ps *cps,
- struct amdgpu_ps *rps,
+static int si_check_state_equal(void *handle,
+ void *current_ps,
+ void *request_ps,
bool *equal)
{
struct si_ps *si_cps;
struct si_ps *si_rps;
int i;
+ struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
+ struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
return -EINVAL;
- si_cps = si_get_ps(cps);
- si_rps = si_get_ps(rps);
+ si_cps = si_get_ps((struct amdgpu_ps *)cps);
+ si_rps = si_get_ps((struct amdgpu_ps *)rps);
if (si_cps == NULL) {
printk("si_cps is NULL\n");
@@ -7983,9 +7995,10 @@ static int si_check_state_equal(struct amdgpu_device *adev,
return 0;
}
-static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+static int si_dpm_read_sensor(void *handle, int idx,
void *value, int *size)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
struct amdgpu_ps *rps = &eg_pi->current_rps;
struct si_ps *ps = si_get_ps(rps);
@@ -8041,7 +8054,7 @@ const struct amd_ip_funcs si_dpm_ip_funcs = {
.set_powergating_state = si_dpm_set_powergating_state,
};
-static const struct amdgpu_dpm_funcs si_dpm_funcs = {
+const struct amd_pm_funcs si_dpm_funcs = {
.get_temperature = &si_dpm_get_temp,
.pre_set_power_state = &si_dpm_pre_set_power_state,
.set_power_state = &si_dpm_set_power_state,
@@ -8062,12 +8075,6 @@ static const struct amdgpu_dpm_funcs si_dpm_funcs = {
.read_sensor = &si_dpm_read_sensor,
};
-static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
-{
- if (adev->pm.funcs == NULL)
- adev->pm.funcs = &si_dpm_funcs;
-}
-
static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
.set = si_dpm_set_interrupt_state,
.process = si_dpm_process_interrupt,
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.h b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
index 51ce21c..9fe343d 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
@@ -246,6 +246,7 @@ enum si_display_gap
};
extern const struct amd_ip_funcs si_dpm_ip_funcs;
+extern const struct amd_pm_funcs si_dpm_funcs;
struct ni_leakage_coeffients
{
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index ce25e03..d2c6b80 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -118,6 +118,19 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev)
return (wptr & adev->irq.ih.ptr_mask);
}
+/**
+ * si_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool si_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ /* Process all interrupts */
+ return true;
+}
+
static void si_ih_decode_iv(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry)
{
@@ -288,6 +301,7 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
static const struct amdgpu_ih_funcs si_ih_funcs = {
.get_wptr = si_ih_get_wptr,
+ .prescreen_iv = si_ih_prescreen_iv,
.decode_iv = si_ih_decode_iv,
.set_rptr = si_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f2c3a49..3ca9d11 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -101,7 +101,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
{
unsigned long flags, address, data;
u32 r;
- struct nbio_pcie_index_data *nbio_pcie_id;
+ const struct nbio_pcie_index_data *nbio_pcie_id;
if (adev->flags & AMD_IS_APU)
nbio_pcie_id = &nbio_v7_0_pcie_index_data;
@@ -122,7 +122,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{
unsigned long flags, address, data;
- struct nbio_pcie_index_data *nbio_pcie_id;
+ const struct nbio_pcie_index_data *nbio_pcie_id;
if (adev->flags & AMD_IS_APU)
nbio_pcie_id = &nbio_v7_0_pcie_index_data;
@@ -279,10 +279,7 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
}
static u32 soc15_get_xclk(struct amdgpu_device *adev)
{
- if (adev->asic_type == CHIP_VEGA10)
- return adev->clock.spll.reference_freq/4;
- else
- return adev->clock.spll.reference_freq;
+ return adev->clock.spll.reference_freq;
}
@@ -407,18 +404,27 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
return -EINVAL;
}
-static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
+static int soc15_asic_reset(struct amdgpu_device *adev)
{
u32 i;
- dev_info(adev->dev, "GPU pci config reset\n");
+ amdgpu_atombios_scratch_regs_engine_hung(adev, true);
+
+ dev_info(adev->dev, "GPU reset\n");
/* disable BM */
pci_clear_master(adev->pdev);
- /* reset */
- amdgpu_pci_config_reset(adev);
- udelay(100);
+ pci_save_state(adev->pdev);
+
+ for (i = 0; i < AMDGPU_MAX_IP_NUM; i++) {
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP){
+ adev->ip_blocks[i].version->funcs->soft_reset((void *)adev);
+ break;
+ }
+ }
+
+ pci_restore_state(adev->pdev);
/* wait for asic to come out of reset */
for (i = 0; i < adev->usec_timeout; i++) {
@@ -430,14 +436,6 @@ static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
udelay(1);
}
-}
-
-static int soc15_asic_reset(struct amdgpu_device *adev)
-{
- amdgpu_atombios_scratch_regs_engine_hung(adev, true);
-
- soc15_gpu_pci_config_reset(adev);
-
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
return 0;
@@ -603,21 +601,6 @@ static int soc15_common_early_init(void *handle)
(amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
psp_enabled = true;
- /*
- * nbio need be used for both sdma and gfx9, but only
- * initializes once
- */
- switch(adev->asic_type) {
- case CHIP_VEGA10:
- nbio_v6_1_init(adev);
- break;
- case CHIP_RAVEN:
- nbio_v7_0_init(adev);
- break;
- default:
- return -EINVAL;
- }
-
adev->rev_id = soc15_get_rev_id(adev);
adev->external_rev_id = 0xFF;
switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 923df2c..aa4e320 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -219,6 +219,34 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
}
/**
+ * tonga_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool tonga_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ u32 ring_index = adev->irq.ih.rptr >> 2;
+ u16 pasid;
+
+ switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
+ case 146:
+ case 147:
+ pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
+ if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
+ return true;
+ break;
+ default:
+ /* Not a VM fault */
+ return true;
+ }
+
+ adev->irq.ih.rptr += 16;
+ return false;
+}
+
+/**
* tonga_ih_decode_iv - decode an interrupt vector
*
* @adev: amdgpu_device pointer
@@ -478,6 +506,7 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
static const struct amdgpu_ih_funcs tonga_ih_funcs = {
.get_wptr = tonga_ih_get_wptr,
+ .prescreen_iv = tonga_ih_prescreen_iv,
.decode_iv = tonga_ih_decode_iv,
.set_rptr = tonga_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 62cd16a..920910a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -38,6 +38,8 @@
#include "vi.h"
static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
+static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+
static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static int uvd_v6_0_start(struct amdgpu_device *adev);
static void uvd_v6_0_stop(struct amdgpu_device *adev);
@@ -48,6 +50,18 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
bool enable);
/**
+* uvd_v6_0_enc_support - get encode support status
+*
+* @adev: amdgpu_device pointer
+*
+* Returns the current hardware encode support status
+*/
+static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
+{
+ return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
+}
+
+/**
* uvd_v6_0_ring_get_rptr - get read pointer
*
* @ring: amdgpu_ring pointer
@@ -62,6 +76,22 @@ static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
}
/**
+ * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc read pointer
+ */
+static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->uvd.ring_enc[0])
+ return RREG32(mmUVD_RB_RPTR);
+ else
+ return RREG32(mmUVD_RB_RPTR2);
+}
+/**
* uvd_v6_0_ring_get_wptr - get write pointer
*
* @ring: amdgpu_ring pointer
@@ -76,6 +106,23 @@ static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
}
/**
+ * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc write pointer
+ */
+static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->uvd.ring_enc[0])
+ return RREG32(mmUVD_RB_WPTR);
+ else
+ return RREG32(mmUVD_RB_WPTR2);
+}
+
+/**
* uvd_v6_0_ring_set_wptr - set write pointer
*
* @ring: amdgpu_ring pointer
@@ -89,6 +136,237 @@ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
}
+/**
+ * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the enc write pointer to the hardware
+ */
+static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->uvd.ring_enc[0])
+ WREG32(mmUVD_RB_WPTR,
+ lower_32_bits(ring->wptr));
+ else
+ WREG32(mmUVD_RB_WPTR2,
+ lower_32_bits(ring->wptr));
+}
+
+/**
+ * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
+ *
+ * @ring: the engine to test on
+ *
+ */
+static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t rptr = amdgpu_ring_get_rptr(ring);
+ unsigned i;
+ int r;
+
+ r = amdgpu_ring_alloc(ring, 16);
+ if (r) {
+ DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
+ ring->idx, r);
+ return r;
+ }
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (amdgpu_ring_get_rptr(ring) != rptr)
+ break;
+ DRM_UDELAY(1);
+ }
+
+ if (i < adev->usec_timeout) {
+ DRM_INFO("ring test on %d succeeded in %d usecs\n",
+ ring->idx, i);
+ } else {
+ DRM_ERROR("amdgpu: ring %d test failed\n",
+ ring->idx);
+ r = -ETIMEDOUT;
+ }
+
+ return r;
+}
+
+/**
+ * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
+ *
+ * @adev: amdgpu_device pointer
+ * @ring: ring we should submit the msg to
+ * @handle: session handle to use
+ * @fence: optional fence to return
+ *
+ * Open up a stream for HW test
+ */
+static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+ struct dma_fence **fence)
+{
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+ uint64_t dummy;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+ if (r)
+ return r;
+
+ ib = &job->ibs[0];
+ dummy = ib->gpu_addr + 1024;
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = 0x00010000;
+ ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+ ib->ptr[ib->length_dw++] = dummy;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+ ib->ptr[ib->length_dw++] = 0x0000001c;
+ ib->ptr[ib->length_dw++] = 0x00000001;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+
+ ib->ptr[ib->length_dw++] = 0x00000008;
+ ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
+
+ for (i = ib->length_dw; i < ib_size_dw; ++i)
+ ib->ptr[i] = 0x0;
+
+ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ job->fence = dma_fence_get(f);
+ if (r)
+ goto err;
+
+ amdgpu_job_free(job);
+ if (fence)
+ *fence = dma_fence_get(f);
+ dma_fence_put(f);
+ return 0;
+
+err:
+ amdgpu_job_free(job);
+ return r;
+}
+
+/**
+ * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
+ *
+ * @adev: amdgpu_device pointer
+ * @ring: ring we should submit the msg to
+ * @handle: session handle to use
+ * @fence: optional fence to return
+ *
+ * Close up a stream for HW test or if userspace failed to do so
+ */
+static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+ uint32_t handle,
+ bool direct, struct dma_fence **fence)
+{
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+ uint64_t dummy;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+ if (r)
+ return r;
+
+ ib = &job->ibs[0];
+ dummy = ib->gpu_addr + 1024;
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = 0x00010000;
+ ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+ ib->ptr[ib->length_dw++] = dummy;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+ ib->ptr[ib->length_dw++] = 0x0000001c;
+ ib->ptr[ib->length_dw++] = 0x00000001;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+
+ ib->ptr[ib->length_dw++] = 0x00000008;
+ ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
+
+ for (i = ib->length_dw; i < ib_size_dw; ++i)
+ ib->ptr[i] = 0x0;
+
+ if (direct) {
+ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ job->fence = dma_fence_get(f);
+ if (r)
+ goto err;
+
+ amdgpu_job_free(job);
+ } else {
+ r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
+ AMDGPU_FENCE_OWNER_UNDEFINED, &f);
+ if (r)
+ goto err;
+ }
+
+ if (fence)
+ *fence = dma_fence_get(f);
+ dma_fence_put(f);
+ return 0;
+
+err:
+ amdgpu_job_free(job);
+ return r;
+}
+
+/**
+ * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
+ *
+ * @ring: the engine to test on
+ *
+ */
+static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+ struct dma_fence *fence = NULL;
+ long r;
+
+ r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
+ goto error;
+ }
+
+ r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
+ goto error;
+ }
+
+ r = dma_fence_wait_timeout(fence, false, timeout);
+ if (r == 0) {
+ DRM_ERROR("amdgpu: IB test timed out.\n");
+ r = -ETIMEDOUT;
+ } else if (r < 0) {
+ DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+ } else {
+ DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
+ r = 0;
+ }
+error:
+ dma_fence_put(fence);
+ return r;
+}
static int uvd_v6_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -98,6 +376,12 @@ static int uvd_v6_0_early_init(void *handle)
return -ENOENT;
uvd_v6_0_set_ring_funcs(adev);
+
+ if (uvd_v6_0_enc_support(adev)) {
+ adev->uvd.num_enc_rings = 2;
+ uvd_v6_0_set_enc_ring_funcs(adev);
+ }
+
uvd_v6_0_set_irq_funcs(adev);
return 0;
@@ -106,7 +390,7 @@ static int uvd_v6_0_early_init(void *handle)
static int uvd_v6_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
- int r;
+ int i, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* UVD TRAP */
@@ -114,10 +398,31 @@ static int uvd_v6_0_sw_init(void *handle)
if (r)
return r;
+ /* UVD ENC TRAP */
+ if (uvd_v6_0_enc_support(adev)) {
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
+ if (r)
+ return r;
+ }
+ }
+
r = amdgpu_uvd_sw_init(adev);
if (r)
return r;
+ if (uvd_v6_0_enc_support(adev)) {
+ struct amd_sched_rq *rq;
+ ring = &adev->uvd.ring_enc[0];
+ rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
+ r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
+ rq, amdgpu_sched_jobs);
+ if (r) {
+ DRM_ERROR("Failed setting up UVD ENC run queue.\n");
+ return r;
+ }
+ }
+
r = amdgpu_uvd_resume(adev);
if (r)
return r;
@@ -125,19 +430,38 @@ static int uvd_v6_0_sw_init(void *handle)
ring = &adev->uvd.ring;
sprintf(ring->name, "uvd");
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+ if (r)
+ return r;
+
+ if (uvd_v6_0_enc_support(adev)) {
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+ ring = &adev->uvd.ring_enc[i];
+ sprintf(ring->name, "uvd_enc%d", i);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+ if (r)
+ return r;
+ }
+ }
return r;
}
static int uvd_v6_0_sw_fini(void *handle)
{
- int r;
+ int i, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_uvd_suspend(adev);
if (r)
return r;
+ if (uvd_v6_0_enc_support(adev)) {
+ amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
+
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+ amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
+ }
+
return amdgpu_uvd_sw_fini(adev);
}
@@ -153,7 +477,7 @@ static int uvd_v6_0_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->uvd.ring;
uint32_t tmp;
- int r;
+ int i, r;
amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
@@ -193,9 +517,25 @@ static int uvd_v6_0_hw_init(void *handle)
amdgpu_ring_commit(ring);
+ if (uvd_v6_0_enc_support(adev)) {
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+ ring = &adev->uvd.ring_enc[i];
+ ring->ready = true;
+ r = amdgpu_ring_test_ring(ring);
+ if (r) {
+ ring->ready = false;
+ goto done;
+ }
+ }
+ }
+
done:
- if (!r)
- DRM_INFO("UVD initialized successfully.\n");
+ if (!r) {
+ if (uvd_v6_0_enc_support(adev))
+ DRM_INFO("UVD and UVD ENC initialized successfully.\n");
+ else
+ DRM_INFO("UVD initialized successfully.\n");
+ }
return r;
}
@@ -512,6 +852,22 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
+ if (uvd_v6_0_enc_support(adev)) {
+ ring = &adev->uvd.ring_enc[0];
+ WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
+
+ ring = &adev->uvd.ring_enc[1];
+ WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
+ }
+
return 0;
}
@@ -575,6 +931,26 @@ static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
}
/**
+ * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
+ *
+ * @ring: amdgpu_ring pointer
+ * @fence: fence to emit
+ *
+ * Write enc a fence and a trap command to the ring.
+ */
+static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+ u64 seq, unsigned flags)
+{
+ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
+ amdgpu_ring_write(ring, addr);
+ amdgpu_ring_write(ring, upper_32_bits(addr));
+ amdgpu_ring_write(ring, seq);
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
+}
+
+/**
* uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
*
* @ring: amdgpu_ring pointer
@@ -665,6 +1041,24 @@ static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, ib->length_dw);
}
+/**
+ * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
+ *
+ * @ring: amdgpu_ring pointer
+ * @ib: indirect buffer to execute
+ *
+ * Write enc ring commands to execute the indirect buffer
+ */
+static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+{
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
+ amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring, ib->length_dw);
+}
+
static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vm_id, uint64_t pd_addr)
{
@@ -716,6 +1110,33 @@ static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0xE);
}
+static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+{
+ uint32_t seq = ring->fence_drv.sync_seq;
+ uint64_t addr = ring->fence_drv.gpu_addr;
+
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
+ amdgpu_ring_write(ring, lower_32_bits(addr));
+ amdgpu_ring_write(ring, upper_32_bits(addr));
+ amdgpu_ring_write(ring, seq);
+}
+
+static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
+}
+
+static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ unsigned int vm_id, uint64_t pd_addr)
+{
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
+ amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, pd_addr >> 12);
+
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
+ amdgpu_ring_write(ring, vm_id);
+}
+
static bool uvd_v6_0_is_idle(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -823,8 +1244,31 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
+ bool int_handled = true;
DRM_DEBUG("IH: UVD TRAP\n");
- amdgpu_fence_process(&adev->uvd.ring);
+
+ switch (entry->src_id) {
+ case 124:
+ amdgpu_fence_process(&adev->uvd.ring);
+ break;
+ case 119:
+ if (likely(uvd_v6_0_enc_support(adev)))
+ amdgpu_fence_process(&adev->uvd.ring_enc[0]);
+ else
+ int_handled = false;
+ break;
+ case 120:
+ if (likely(uvd_v6_0_enc_support(adev)))
+ amdgpu_fence_process(&adev->uvd.ring_enc[1]);
+ else
+ int_handled = false;
+ break;
+ }
+
+ if (false == int_handled)
+ DRM_ERROR("Unhandled interrupt: %d %d\n",
+ entry->src_id, entry->src_data[0]);
+
return 0;
}
@@ -1151,6 +1595,33 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
.end_use = amdgpu_uvd_ring_end_use,
};
+static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_UVD_ENC,
+ .align_mask = 0x3f,
+ .nop = HEVC_ENC_CMD_NO_OP,
+ .support_64bit_ptrs = false,
+ .get_rptr = uvd_v6_0_enc_ring_get_rptr,
+ .get_wptr = uvd_v6_0_enc_ring_get_wptr,
+ .set_wptr = uvd_v6_0_enc_ring_set_wptr,
+ .emit_frame_size =
+ 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
+ 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
+ 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
+ 1, /* uvd_v6_0_enc_ring_insert_end */
+ .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
+ .emit_ib = uvd_v6_0_enc_ring_emit_ib,
+ .emit_fence = uvd_v6_0_enc_ring_emit_fence,
+ .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
+ .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
+ .test_ring = uvd_v6_0_enc_ring_test_ring,
+ .test_ib = uvd_v6_0_enc_ring_test_ib,
+ .insert_nop = amdgpu_ring_insert_nop,
+ .insert_end = uvd_v6_0_enc_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_uvd_ring_begin_use,
+ .end_use = amdgpu_uvd_ring_end_use,
+};
+
static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
{
if (adev->asic_type >= CHIP_POLARIS10) {
@@ -1162,6 +1633,16 @@ static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
}
}
+static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+{
+ int i;
+
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+ adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
+
+ DRM_INFO("UVD ENC is enabled in VM mode\n");
+}
+
static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
.set = uvd_v6_0_set_interrupt_state,
.process = uvd_v6_0_process_interrupt,
@@ -1169,7 +1650,11 @@ static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->uvd.irq.num_types = 1;
+ if (uvd_v6_0_enc_support(adev))
+ adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
+ else
+ adev->uvd.irq.num_types = 1;
+
adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 23a8575..6634545 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -592,11 +592,7 @@ static int uvd_v7_0_suspend(void *handle)
if (r)
return r;
- /* Skip this for APU for now */
- if (!(adev->flags & AMD_IS_APU))
- r = amdgpu_uvd_suspend(adev);
-
- return r;
+ return amdgpu_uvd_suspend(adev);
}
static int uvd_v7_0_resume(void *handle)
@@ -604,12 +600,10 @@ static int uvd_v7_0_resume(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- /* Skip this for APU for now */
- if (!(adev->flags & AMD_IS_APU)) {
- r = amdgpu_uvd_resume(adev);
- if (r)
- return r;
- }
+ r = amdgpu_uvd_resume(adev);
+ if (r)
+ return r;
+
return uvd_v7_0_hw_init(adev);
}
@@ -1161,7 +1155,7 @@ static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
*/
static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
- amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
+ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
amdgpu_ring_write(ring, 1);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 11134d5..7574554 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -1011,10 +1011,6 @@ static int vce_v4_0_process_interrupt(struct amdgpu_device *adev,
{
DRM_DEBUG("IH: VCE\n");
- WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_STATUS),
- VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK,
- ~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK);
-
switch (entry->src_data[0]) {
case 0:
case 1:
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 21e7b88..1eb4d79 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -812,7 +812,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
*/
static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
{
- amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
+ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
amdgpu_ring_write(ring, 1);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 56150e8..6973257 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -219,14 +219,95 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
wptr, adev->irq.ih.rptr, tmp);
adev->irq.ih.rptr = tmp;
- tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+ tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
- WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
+ WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
}
return (wptr & adev->irq.ih.ptr_mask);
}
/**
+ * vega10_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
+{
+ u32 ring_index = adev->irq.ih.rptr >> 2;
+ u32 dw0, dw3, dw4, dw5;
+ u16 pasid;
+ u64 addr, key;
+ struct amdgpu_vm *vm;
+ int r;
+
+ dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
+ dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
+ dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
+ dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
+
+ /* Filter retry page faults, let only the first one pass. If
+ * there are too many outstanding faults, ignore them until
+ * some faults get cleared.
+ */
+ switch (dw0 & 0xff) {
+ case AMDGPU_IH_CLIENTID_VMC:
+ case AMDGPU_IH_CLIENTID_UTCL2:
+ break;
+ default:
+ /* Not a VM fault */
+ return true;
+ }
+
+ pasid = dw3 & 0xffff;
+ /* No PASID, can't identify faulting process */
+ if (!pasid)
+ return true;
+
+ /* Not a retry fault, check fault credit */
+ if (!(dw5 & 0x80)) {
+ if (!amdgpu_vm_pasid_fault_credit(adev, pasid))
+ goto ignore_iv;
+ return true;
+ }
+
+ addr = ((u64)(dw5 & 0xf) << 44) | ((u64)dw4 << 12);
+ key = AMDGPU_VM_FAULT(pasid, addr);
+ r = amdgpu_ih_add_fault(adev, key);
+
+ /* Hash table is full or the fault is already being processed,
+ * ignore further page faults
+ */
+ if (r != 0)
+ goto ignore_iv;
+
+ /* Track retry faults in per-VM fault FIFO. */
+ spin_lock(&adev->vm_manager.pasid_lock);
+ vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
+ spin_unlock(&adev->vm_manager.pasid_lock);
+ if (WARN_ON_ONCE(!vm)) {
+ /* VM not found, process it normally */
+ amdgpu_ih_clear_fault(adev, key);
+ return true;
+ }
+ /* No locking required with single writer and single reader */
+ r = kfifo_put(&vm->faults, key);
+ if (!r) {
+ /* FIFO is full. Ignore it until there is space */
+ amdgpu_ih_clear_fault(adev, key);
+ goto ignore_iv;
+ }
+
+ /* It's the first fault for this address, process it normally */
+ return true;
+
+ignore_iv:
+ adev->irq.ih.rptr += 32;
+ return false;
+}
+
+/**
* vega10_ih_decode_iv - decode an interrupt vector
*
* @adev: amdgpu_device pointer
@@ -310,6 +391,14 @@ static int vega10_ih_sw_init(void *handle)
adev->irq.ih.use_doorbell = true;
adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;
+ adev->irq.ih.faults = kmalloc(sizeof(*adev->irq.ih.faults), GFP_KERNEL);
+ if (!adev->irq.ih.faults)
+ return -ENOMEM;
+ INIT_CHASH_TABLE(adev->irq.ih.faults->hash,
+ AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
+ spin_lock_init(&adev->irq.ih.faults->lock);
+ adev->irq.ih.faults->count = 0;
+
r = amdgpu_irq_init(adev);
return r;
@@ -322,6 +411,9 @@ static int vega10_ih_sw_fini(void *handle)
amdgpu_irq_fini(adev);
amdgpu_ih_ring_fini(adev);
+ kfree(adev->irq.ih.faults);
+ adev->irq.ih.faults = NULL;
+
return 0;
}
@@ -410,6 +502,7 @@ const struct amd_ip_funcs vega10_ih_ip_funcs = {
static const struct amdgpu_ih_funcs vega10_ih_funcs = {
.get_wptr = vega10_ih_get_wptr,
+ .prescreen_iv = vega10_ih_prescreen_iv,
.decode_iv = vega10_ih_decode_iv,
.set_rptr = vega10_ih_set_rptr
};
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 9ff69b9..f3cfef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1254,7 +1254,6 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
uint32_t msg_id, pp_state = 0;
uint32_t pp_support_state = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- void *pp_handle = adev->powerplay.pp_handle;
if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
@@ -1271,7 +1270,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
PP_BLOCK_SYS_MC,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
@@ -1289,7 +1289,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
PP_BLOCK_SYS_SDMA,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
@@ -1307,7 +1308,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
PP_BLOCK_SYS_HDP,
pp_support_state,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
@@ -1321,7 +1323,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
PP_BLOCK_SYS_BIF,
PP_STATE_SUPPORT_LS,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
if (state == AMD_CG_STATE_UNGATE)
@@ -1333,7 +1336,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
PP_BLOCK_SYS_BIF,
PP_STATE_SUPPORT_CG,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
@@ -1347,7 +1351,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
PP_BLOCK_SYS_DRM,
PP_STATE_SUPPORT_LS,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
@@ -1361,7 +1366,8 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
PP_BLOCK_SYS_ROM,
PP_STATE_SUPPORT_CG,
pp_state);
- amd_set_clockgating_by_smu(pp_handle, msg_id);
+ if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
+ amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
}
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index a648525..dbf3703 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -465,6 +465,16 @@
#define VCE_CMD_UPDATE_PTB 0x00000107
#define VCE_CMD_FLUSH_TLB 0x00000108
+/* HEVC ENC */
+#define HEVC_ENC_CMD_NO_OP 0x00000000
+#define HEVC_ENC_CMD_END 0x00000001
+#define HEVC_ENC_CMD_FENCE 0x00000003
+#define HEVC_ENC_CMD_TRAP 0x00000004
+#define HEVC_ENC_CMD_IB_VM 0x00000102
+#define HEVC_ENC_CMD_WAIT_GE 0x00000106
+#define HEVC_ENC_CMD_UPDATE_PTB 0x00000107
+#define HEVC_ENC_CMD_FLUSH_TLB 0x00000108
+
/* mmPA_SC_RASTER_CONFIG mask */
#define RB_MAP_PKR0(x) ((x) << 0)
#define RB_MAP_PKR0_MASK (0x3 << 0)
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig
index e13c67c..bc5a294 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -4,6 +4,6 @@
config HSA_AMD
tristate "HSA kernel driver for AMD GPU devices"
- depends on (DRM_RADEON || DRM_AMDGPU) && AMD_IOMMU_V2 && X86_64
+ depends on DRM_AMDGPU && AMD_IOMMU_V2 && X86_64
help
Enable this if you want to use HSA features on AMD GPU devices.
diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
index 211fc48..3d5ccb3 100644
--- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
@@ -36,6 +36,7 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
/* Do not process in ISR, just request it to be forwarded to WQ. */
return (pasid != 0) &&
(ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE ||
+ ihre->source_id == CIK_INTSRC_SDMA_TRAP ||
ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG ||
ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE);
}
@@ -46,6 +47,7 @@ static void cik_event_interrupt_wq(struct kfd_dev *dev,
unsigned int pasid;
const struct cik_ih_ring_entry *ihre =
(const struct cik_ih_ring_entry *)ih_ring_entry;
+ uint32_t context_id = ihre->data & 0xfffffff;
pasid = (ihre->ring_id & 0xffff0000) >> 16;
@@ -53,9 +55,11 @@ static void cik_event_interrupt_wq(struct kfd_dev *dev,
return;
if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE)
- kfd_signal_event_interrupt(pasid, 0, 0);
+ kfd_signal_event_interrupt(pasid, context_id, 28);
+ else if (ihre->source_id == CIK_INTSRC_SDMA_TRAP)
+ kfd_signal_event_interrupt(pasid, context_id, 28);
else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG)
- kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8);
+ kfd_signal_event_interrupt(pasid, context_id & 0xff, 8);
else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE)
kfd_signal_hw_exception_event(pasid);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h b/drivers/gpu/drm/amd/amdkfd/cik_int.h
index 79a16d2..109298b 100644
--- a/drivers/gpu/drm/amd/amdkfd/cik_int.h
+++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h
@@ -32,9 +32,10 @@ struct cik_ih_ring_entry {
uint32_t reserved;
};
-#define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6
#define CIK_INTSRC_CP_END_OF_PIPE 0xB5
#define CIK_INTSRC_CP_BAD_OPCODE 0xB7
+#define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6
+#define CIK_INTSRC_SDMA_TRAP 0xE0
#define CIK_INTSRC_SQ_INTERRUPT_MSG 0xEF
#endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 660b3fb..505d391 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -282,8 +282,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
p->pasid,
dev->id);
- err = pqm_create_queue(&p->pqm, dev, filep, &q_properties,
- 0, q_properties.type, &queue_id);
+ err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id);
if (err != 0)
goto err_create_queue;
@@ -451,8 +450,8 @@ static int kfd_ioctl_dbg_register(struct file *filep,
return -EINVAL;
}
- mutex_lock(kfd_get_dbgmgr_mutex());
mutex_lock(&p->mutex);
+ mutex_lock(kfd_get_dbgmgr_mutex());
/*
* make sure that we have pdd, if this the first queue created for
@@ -480,8 +479,8 @@ static int kfd_ioctl_dbg_register(struct file *filep,
}
out:
- mutex_unlock(&p->mutex);
mutex_unlock(kfd_get_dbgmgr_mutex());
+ mutex_unlock(&p->mutex);
return status;
}
@@ -836,15 +835,12 @@ static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
void *data)
{
struct kfd_ioctl_wait_events_args *args = data;
- enum kfd_event_wait_result wait_result;
int err;
err = kfd_wait_on_events(p, args->num_events,
(void __user *)args->events_ptr,
(args->wait_for_all != 0),
- args->timeout, &wait_result);
-
- args->wait_result = wait_result;
+ args->timeout, &args->wait_result);
return err;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
index 0aa021a..c407f6b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
@@ -184,9 +184,10 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev)
struct kernel_queue *kq = NULL;
int status;
+ properties.type = KFD_QUEUE_TYPE_DIQ;
+
status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL,
- &properties, 0, KFD_QUEUE_TYPE_DIQ,
- &qid);
+ &properties, &qid);
if (status) {
pr_err("Failed to create DIQ\n");
@@ -769,13 +770,8 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
union GRBM_GFX_INDEX_BITS reg_gfx_index;
struct kfd_process_device *pdd;
struct dbg_wave_control_info wac_info;
- int temp;
- int first_vmid_to_scan = 8;
- int last_vmid_to_scan = 15;
-
- first_vmid_to_scan = ffs(dev->shared_resources.compute_vmid_bitmap) - 1;
- temp = dev->shared_resources.compute_vmid_bitmap >> first_vmid_to_scan;
- last_vmid_to_scan = first_vmid_to_scan + ffz(temp);
+ int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
+ int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
reg_sq_cmd.u32All = 0;
status = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 61fff25..621a3b5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -92,6 +92,8 @@ static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
unsigned int chunk_size);
static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
+static int kfd_resume(struct kfd_dev *kfd);
+
static const struct kfd_device_info *lookup_device_info(unsigned short did)
{
size_t i;
@@ -168,23 +170,9 @@ static bool device_iommu_pasid_init(struct kfd_dev *kfd)
pasid_limit = min_t(unsigned int,
(unsigned int)(1 << kfd->device_info->max_pasid_bits),
iommu_info.max_pasids);
- /*
- * last pasid is used for kernel queues doorbells
- * in the future the last pasid might be used for a kernel thread.
- */
- pasid_limit = min_t(unsigned int,
- pasid_limit,
- kfd->doorbell_process_limit - 1);
-
- err = amd_iommu_init_device(kfd->pdev, pasid_limit);
- if (err < 0) {
- dev_err(kfd_device, "error initializing iommu device\n");
- return false;
- }
if (!kfd_set_pasid_limit(pasid_limit)) {
dev_err(kfd_device, "error setting pasid limit\n");
- amd_iommu_free_device(kfd->pdev);
return false;
}
@@ -196,7 +184,7 @@ static void iommu_pasid_shutdown_callback(struct pci_dev *pdev, int pasid)
struct kfd_dev *dev = kfd_device_by_pci_dev(pdev);
if (dev)
- kfd_unbind_process_from_device(dev, pasid);
+ kfd_process_iommu_unbind_callback(dev, pasid);
}
/*
@@ -231,6 +219,11 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
kfd->shared_resources = *gpu_resources;
+ kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
+ kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
+ kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
+ - kfd->vm_info.first_vmid_kfd + 1;
+
/* calculate max size of mqds needed for queues */
size = max_num_of_queues_per_device *
kfd->device_info->mqd_size_aligned;
@@ -280,29 +273,22 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
goto kfd_interrupt_error;
}
- if (!device_iommu_pasid_init(kfd)) {
- dev_err(kfd_device,
- "Error initializing iommuv2 for device %x:%x\n",
- kfd->pdev->vendor, kfd->pdev->device);
- goto device_iommu_pasid_error;
- }
- amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
- iommu_pasid_shutdown_callback);
- amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
-
kfd->dqm = device_queue_manager_init(kfd);
if (!kfd->dqm) {
dev_err(kfd_device, "Error initializing queue manager\n");
goto device_queue_manager_error;
}
- if (kfd->dqm->ops.start(kfd->dqm)) {
+ if (!device_iommu_pasid_init(kfd)) {
dev_err(kfd_device,
- "Error starting queue manager for device %x:%x\n",
+ "Error initializing iommuv2 for device %x:%x\n",
kfd->pdev->vendor, kfd->pdev->device);
- goto dqm_start_error;
+ goto device_iommu_pasid_error;
}
+ if (kfd_resume(kfd))
+ goto kfd_resume_error;
+
kfd->dbgmgr = NULL;
kfd->init_complete = true;
@@ -314,11 +300,10 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
goto out;
-dqm_start_error:
+kfd_resume_error:
+device_iommu_pasid_error:
device_queue_manager_uninit(kfd->dqm);
device_queue_manager_error:
- amd_iommu_free_device(kfd->pdev);
-device_iommu_pasid_error:
kfd_interrupt_exit(kfd);
kfd_interrupt_error:
kfd_topology_remove_device(kfd);
@@ -338,8 +323,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
void kgd2kfd_device_exit(struct kfd_dev *kfd)
{
if (kfd->init_complete) {
+ kgd2kfd_suspend(kfd);
device_queue_manager_uninit(kfd->dqm);
- amd_iommu_free_device(kfd->pdev);
kfd_interrupt_exit(kfd);
kfd_topology_remove_device(kfd);
kfd_doorbell_fini(kfd);
@@ -352,35 +337,59 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd)
void kgd2kfd_suspend(struct kfd_dev *kfd)
{
- if (kfd->init_complete) {
- kfd->dqm->ops.stop(kfd->dqm);
- amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL);
- amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL);
- amd_iommu_free_device(kfd->pdev);
- }
+ if (!kfd->init_complete)
+ return;
+
+ kfd->dqm->ops.stop(kfd->dqm);
+
+ kfd_unbind_processes_from_device(kfd);
+
+ amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL);
+ amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL);
+ amd_iommu_free_device(kfd->pdev);
}
int kgd2kfd_resume(struct kfd_dev *kfd)
{
- unsigned int pasid_limit;
- int err;
+ if (!kfd->init_complete)
+ return 0;
- pasid_limit = kfd_get_pasid_limit();
+ return kfd_resume(kfd);
- if (kfd->init_complete) {
- err = amd_iommu_init_device(kfd->pdev, pasid_limit);
- if (err < 0) {
- dev_err(kfd_device, "failed to initialize iommu\n");
- return -ENXIO;
- }
+}
- amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
- iommu_pasid_shutdown_callback);
- amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
- kfd->dqm->ops.start(kfd->dqm);
+static int kfd_resume(struct kfd_dev *kfd)
+{
+ int err = 0;
+ unsigned int pasid_limit = kfd_get_pasid_limit();
+
+ err = amd_iommu_init_device(kfd->pdev, pasid_limit);
+ if (err)
+ return -ENXIO;
+ amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
+ iommu_pasid_shutdown_callback);
+ amd_iommu_set_invalid_ppr_cb(kfd->pdev,
+ iommu_invalid_ppr_cb);
+
+ err = kfd_bind_processes_to_device(kfd);
+ if (err)
+ goto processes_bind_error;
+
+ err = kfd->dqm->ops.start(kfd->dqm);
+ if (err) {
+ dev_err(kfd_device,
+ "Error starting queue manager for device %x:%x\n",
+ kfd->pdev->vendor, kfd->pdev->device);
+ goto dqm_start_error;
}
- return 0;
+ return err;
+
+dqm_start_error:
+processes_bind_error:
+ amd_iommu_free_device(kfd->pdev);
+
+ return err;
}
/* This is called directly from KGD at ISR. */
@@ -394,7 +403,7 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
if (kfd->interrupts_active
&& interrupt_is_wanted(kfd, ih_ring_entry)
&& enqueue_ih_ring_entry(kfd, ih_ring_entry))
- schedule_work(&kfd->interrupt_work);
+ queue_work(kfd->ih_wq, &kfd->interrupt_work);
spin_unlock(&kfd->interrupt_lock);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 53a66e8..e202921 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -44,9 +44,14 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
struct queue *q,
struct qcm_process_device *qpd);
-static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock);
-static int destroy_queues_cpsch(struct device_queue_manager *dqm,
- bool preempt_static_queues, bool lock);
+static int execute_queues_cpsch(struct device_queue_manager *dqm,
+ enum kfd_unmap_queues_filter filter,
+ uint32_t filter_param);
+static int unmap_queues_cpsch(struct device_queue_manager *dqm,
+ enum kfd_unmap_queues_filter filter,
+ uint32_t filter_param);
+
+static int map_queues_cpsch(struct device_queue_manager *dqm);
static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
struct queue *q,
@@ -113,11 +118,11 @@ static int allocate_vmid(struct device_queue_manager *dqm,
if (dqm->vmid_bitmap == 0)
return -ENOMEM;
- bit = find_first_bit((unsigned long *)&dqm->vmid_bitmap, CIK_VMID_NUM);
+ bit = find_first_bit((unsigned long *)&dqm->vmid_bitmap,
+ dqm->dev->vm_info.vmid_num_kfd);
clear_bit(bit, (unsigned long *)&dqm->vmid_bitmap);
- /* Kaveri kfd vmid's starts from vmid 8 */
- allocated_vmid = bit + KFD_VMID_START_OFFSET;
+ allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
pr_debug("vmid allocation %d\n", allocated_vmid);
qpd->vmid = allocated_vmid;
q->properties.vmid = allocated_vmid;
@@ -132,7 +137,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
struct qcm_process_device *qpd,
struct queue *q)
{
- int bit = qpd->vmid - KFD_VMID_START_OFFSET;
+ int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
/* Release the vmid mapping */
set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
@@ -184,6 +189,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm,
}
list_add(&q->list, &qpd->queues_list);
+ qpd->queue_count++;
if (q->properties.is_active)
dqm->queue_count++;
@@ -273,6 +279,9 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
dqm->dev->kfd2kgd->set_scratch_backing_va(
dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
+ if (!q->properties.is_active)
+ return 0;
+
retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue, &q->properties,
q->process->mm);
if (retval)
@@ -288,65 +297,74 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
return retval;
}
-static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
+/* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
+ * to avoid asynchronized access
+ */
+static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
struct qcm_process_device *qpd,
struct queue *q)
{
int retval;
struct mqd_manager *mqd;
- retval = 0;
-
- mutex_lock(&dqm->lock);
+ mqd = dqm->ops.get_mqd_manager(dqm,
+ get_mqd_type_from_queue_type(q->properties.type));
+ if (!mqd)
+ return -ENOMEM;
if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
- mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
- if (mqd == NULL) {
- retval = -ENOMEM;
- goto out;
- }
deallocate_hqd(dqm, q);
} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
- mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
- if (mqd == NULL) {
- retval = -ENOMEM;
- goto out;
- }
dqm->sdma_queue_count--;
deallocate_sdma_queue(dqm, q->sdma_id);
} else {
pr_debug("q->properties.type %d is invalid\n",
q->properties.type);
- retval = -EINVAL;
- goto out;
+ return -EINVAL;
}
+ dqm->total_queue_count--;
retval = mqd->destroy_mqd(mqd, q->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
- QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
+ KFD_UNMAP_LATENCY_MS,
q->pipe, q->queue);
-
- if (retval)
- goto out;
+ if (retval == -ETIME)
+ qpd->reset_wavefronts = true;
mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
list_del(&q->list);
- if (list_empty(&qpd->queues_list))
+ if (list_empty(&qpd->queues_list)) {
+ if (qpd->reset_wavefronts) {
+ pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
+ dqm->dev);
+ /* dbgdev_wave_reset_wavefronts has to be called before
+ * deallocate_vmid(), i.e. when vmid is still in use.
+ */
+ dbgdev_wave_reset_wavefronts(dqm->dev,
+ qpd->pqm->process);
+ qpd->reset_wavefronts = false;
+ }
+
deallocate_vmid(dqm, qpd, q);
+ }
+ qpd->queue_count--;
if (q->properties.is_active)
dqm->queue_count--;
- /*
- * Unconditionally decrement this counter, regardless of the queue's
- * type
- */
- dqm->total_queue_count--;
- pr_debug("Total of %d queues are accountable so far\n",
- dqm->total_queue_count);
+ return retval;
+}
-out:
+static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
+ struct qcm_process_device *qpd,
+ struct queue *q)
+{
+ int retval;
+
+ mutex_lock(&dqm->lock);
+ retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
mutex_unlock(&dqm->lock);
+
return retval;
}
@@ -364,29 +382,56 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
goto out_unlock;
}
- if (q->properties.is_active)
- prev_active = true;
+ /* Save previous activity state for counters */
+ prev_active = q->properties.is_active;
+
+ /* Make sure the queue is unmapped before updating the MQD */
+ if (sched_policy != KFD_SCHED_POLICY_NO_HWS) {
+ retval = unmap_queues_cpsch(dqm,
+ KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
+ if (retval) {
+ pr_err("unmap queue failed\n");
+ goto out_unlock;
+ }
+ } else if (prev_active &&
+ (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
+ q->properties.type == KFD_QUEUE_TYPE_SDMA)) {
+ retval = mqd->destroy_mqd(mqd, q->mqd,
+ KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
+ KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
+ if (retval) {
+ pr_err("destroy mqd failed\n");
+ goto out_unlock;
+ }
+ }
+
+ retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
/*
- *
- * check active state vs. the previous state
- * and modify counter accordingly
+ * check active state vs. the previous state and modify
+ * counter accordingly. map_queues_cpsch uses the
+ * dqm->queue_count to determine whether a new runlist must be
+ * uploaded.
*/
- retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
- if ((q->properties.is_active) && (!prev_active))
+ if (q->properties.is_active && !prev_active)
dqm->queue_count++;
else if (!q->properties.is_active && prev_active)
dqm->queue_count--;
if (sched_policy != KFD_SCHED_POLICY_NO_HWS)
- retval = execute_queues_cpsch(dqm, false);
+ retval = map_queues_cpsch(dqm);
+ else if (q->properties.is_active &&
+ (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
+ q->properties.type == KFD_QUEUE_TYPE_SDMA))
+ retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue,
+ &q->properties, q->process->mm);
out_unlock:
mutex_unlock(&dqm->lock);
return retval;
}
-static struct mqd_manager *get_mqd_manager_nocpsch(
+static struct mqd_manager *get_mqd_manager(
struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
{
struct mqd_manager *mqd;
@@ -407,7 +452,7 @@ static struct mqd_manager *get_mqd_manager_nocpsch(
return mqd;
}
-static int register_process_nocpsch(struct device_queue_manager *dqm,
+static int register_process(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
struct device_process_node *n;
@@ -422,7 +467,7 @@ static int register_process_nocpsch(struct device_queue_manager *dqm,
mutex_lock(&dqm->lock);
list_add(&n->list, &dqm->queues);
- retval = dqm->ops_asic_specific.register_process(dqm, qpd);
+ retval = dqm->asic_ops.update_qpd(dqm, qpd);
dqm->processes_count++;
@@ -431,7 +476,7 @@ static int register_process_nocpsch(struct device_queue_manager *dqm,
return retval;
}
-static int unregister_process_nocpsch(struct device_queue_manager *dqm,
+static int unregister_process(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
int retval;
@@ -507,13 +552,13 @@ static int initialize_nocpsch(struct device_queue_manager *dqm)
dqm->allocated_queues[pipe] |= 1 << queue;
}
- dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1;
+ dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
return 0;
}
-static void uninitialize_nocpsch(struct device_queue_manager *dqm)
+static void uninitialize(struct device_queue_manager *dqm)
{
int i;
@@ -577,14 +622,14 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
if (retval)
return retval;
- q->properties.sdma_queue_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
- q->properties.sdma_engine_id = q->sdma_id / CIK_SDMA_ENGINE_NUM;
+ q->properties.sdma_queue_id = q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
+ q->properties.sdma_engine_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
pr_debug("SDMA id is: %d\n", q->sdma_id);
pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
- dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd);
+ dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
&q->gart_mqd_addr, &q->properties);
if (retval)
@@ -613,8 +658,7 @@ static int set_sched_resources(struct device_queue_manager *dqm)
int i, mec;
struct scheduling_resources res;
- res.vmid_mask = (1 << VMID_PER_DEVICE) - 1;
- res.vmid_mask <<= KFD_VMID_START_OFFSET;
+ res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
res.queue_mask = 0;
for (i = 0; i < KGD_MAX_QUEUES; ++i) {
@@ -652,8 +696,6 @@ static int set_sched_resources(struct device_queue_manager *dqm)
static int initialize_cpsch(struct device_queue_manager *dqm)
{
- int retval;
-
pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
mutex_init(&dqm->lock);
@@ -661,16 +703,13 @@ static int initialize_cpsch(struct device_queue_manager *dqm)
dqm->queue_count = dqm->processes_count = 0;
dqm->sdma_queue_count = 0;
dqm->active_runlist = false;
- retval = dqm->ops_asic_specific.initialize(dqm);
- if (retval)
- mutex_destroy(&dqm->lock);
+ dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
- return retval;
+ return 0;
}
static int start_cpsch(struct device_queue_manager *dqm)
{
- struct device_process_node *node;
int retval;
retval = 0;
@@ -697,12 +736,9 @@ static int start_cpsch(struct device_queue_manager *dqm)
init_interrupts(dqm);
- list_for_each_entry(node, &dqm->queues, list)
- if (node->qpd->pqm->process && dqm->dev)
- kfd_bind_process_to_device(dqm->dev,
- node->qpd->pqm->process);
-
- execute_queues_cpsch(dqm, true);
+ mutex_lock(&dqm->lock);
+ execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
+ mutex_unlock(&dqm->lock);
return 0;
fail_allocate_vidmem:
@@ -714,15 +750,10 @@ static int start_cpsch(struct device_queue_manager *dqm)
static int stop_cpsch(struct device_queue_manager *dqm)
{
- struct device_process_node *node;
- struct kfd_process_device *pdd;
+ mutex_lock(&dqm->lock);
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ mutex_unlock(&dqm->lock);
- destroy_queues_cpsch(dqm, true, true);
-
- list_for_each_entry(node, &dqm->queues, list) {
- pdd = qpd_to_pdd(node->qpd);
- pdd->bound = false;
- }
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
pm_uninit(&dqm->packets);
@@ -752,7 +783,7 @@ static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
list_add(&kq->list, &qpd->priv_queue_list);
dqm->queue_count++;
qpd->is_debug = true;
- execute_queues_cpsch(dqm, false);
+ execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
mutex_unlock(&dqm->lock);
return 0;
@@ -763,12 +794,10 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
mutex_lock(&dqm->lock);
- /* here we actually preempt the DIQ */
- destroy_queues_cpsch(dqm, true, false);
list_del(&kq->list);
dqm->queue_count--;
qpd->is_debug = false;
- execute_queues_cpsch(dqm, false);
+ execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
/*
* Unconditionally decrement this counter, regardless of the queue's
* type.
@@ -779,14 +808,6 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
mutex_unlock(&dqm->lock);
}
-static void select_sdma_engine_id(struct queue *q)
-{
- static int sdma_id;
-
- q->sdma_id = sdma_id;
- sdma_id = (sdma_id + 1) % 2;
-}
-
static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
struct qcm_process_device *qpd, int *allocate_vmid)
{
@@ -807,9 +828,15 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
goto out;
}
- if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
- select_sdma_engine_id(q);
-
+ if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
+ retval = allocate_sdma_queue(dqm, &q->sdma_id);
+ if (retval)
+ goto out;
+ q->properties.sdma_queue_id =
+ q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
+ q->properties.sdma_engine_id =
+ q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
+ }
mqd = dqm->ops.get_mqd_manager(dqm,
get_mqd_type_from_queue_type(q->properties.type));
@@ -818,16 +845,18 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
goto out;
}
- dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd);
+ dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
&q->gart_mqd_addr, &q->properties);
if (retval)
goto out;
list_add(&q->list, &qpd->queues_list);
+ qpd->queue_count++;
if (q->properties.is_active) {
dqm->queue_count++;
- retval = execute_queues_cpsch(dqm, false);
+ retval = execute_queues_cpsch(dqm,
+ KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
}
if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
@@ -848,12 +877,12 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
unsigned int fence_value,
- unsigned long timeout)
+ unsigned int timeout_ms)
{
- timeout += jiffies;
+ unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
while (*fence_addr != fence_value) {
- if (time_after(jiffies, timeout)) {
+ if (time_after(jiffies, end_jiffies)) {
pr_err("qcm fence wait loop timeout expired\n");
return -ETIME;
}
@@ -863,44 +892,57 @@ int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
return 0;
}
-static int destroy_sdma_queues(struct device_queue_manager *dqm,
+static int unmap_sdma_queues(struct device_queue_manager *dqm,
unsigned int sdma_engine)
{
return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
- KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES, 0, false,
+ KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
sdma_engine);
}
-static int destroy_queues_cpsch(struct device_queue_manager *dqm,
- bool preempt_static_queues, bool lock)
+/* dqm->lock mutex has to be locked before calling this function */
+static int map_queues_cpsch(struct device_queue_manager *dqm)
{
int retval;
- enum kfd_preempt_type_filter preempt_type;
- struct kfd_process_device *pdd;
- retval = 0;
+ if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
+ return 0;
- if (lock)
- mutex_lock(&dqm->lock);
+ if (dqm->active_runlist)
+ return 0;
+
+ retval = pm_send_runlist(&dqm->packets, &dqm->queues);
+ if (retval) {
+ pr_err("failed to execute runlist\n");
+ return retval;
+ }
+ dqm->active_runlist = true;
+
+ return retval;
+}
+
+/* dqm->lock mutex has to be locked before calling this function */
+static int unmap_queues_cpsch(struct device_queue_manager *dqm,
+ enum kfd_unmap_queues_filter filter,
+ uint32_t filter_param)
+{
+ int retval = 0;
+
if (!dqm->active_runlist)
- goto out;
+ return retval;
pr_debug("Before destroying queues, sdma queue count is : %u\n",
dqm->sdma_queue_count);
if (dqm->sdma_queue_count > 0) {
- destroy_sdma_queues(dqm, 0);
- destroy_sdma_queues(dqm, 1);
+ unmap_sdma_queues(dqm, 0);
+ unmap_sdma_queues(dqm, 1);
}
- preempt_type = preempt_static_queues ?
- KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES :
- KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES;
-
retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
- preempt_type, 0, false, 0);
+ filter, filter_param, false, 0);
if (retval)
- goto out;
+ return retval;
*dqm->fence_addr = KFD_FENCE_INIT;
pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
@@ -908,55 +950,29 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm,
/* should be timed out */
retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS);
- if (retval) {
- pdd = kfd_get_process_device_data(dqm->dev,
- kfd_get_process(current));
- pdd->reset_wavefronts = true;
- goto out;
- }
+ if (retval)
+ return retval;
+
pm_release_ib(&dqm->packets);
dqm->active_runlist = false;
-out:
- if (lock)
- mutex_unlock(&dqm->lock);
return retval;
}
-static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock)
+/* dqm->lock mutex has to be locked before calling this function */
+static int execute_queues_cpsch(struct device_queue_manager *dqm,
+ enum kfd_unmap_queues_filter filter,
+ uint32_t filter_param)
{
int retval;
- if (lock)
- mutex_lock(&dqm->lock);
-
- retval = destroy_queues_cpsch(dqm, false, false);
+ retval = unmap_queues_cpsch(dqm, filter, filter_param);
if (retval) {
- pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption");
- goto out;
+ pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
+ return retval;
}
- if (dqm->queue_count <= 0 || dqm->processes_count <= 0) {
- retval = 0;
- goto out;
- }
-
- if (dqm->active_runlist) {
- retval = 0;
- goto out;
- }
-
- retval = pm_send_runlist(&dqm->packets, &dqm->queues);
- if (retval) {
- pr_err("failed to execute runlist");
- goto out;
- }
- dqm->active_runlist = true;
-
-out:
- if (lock)
- mutex_unlock(&dqm->lock);
- return retval;
+ return map_queues_cpsch(dqm);
}
static int destroy_queue_cpsch(struct device_queue_manager *dqm,
@@ -991,14 +1007,20 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
goto failed;
}
- if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
+ if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
dqm->sdma_queue_count--;
+ deallocate_sdma_queue(dqm, q->sdma_id);
+ }
list_del(&q->list);
+ qpd->queue_count--;
if (q->properties.is_active)
dqm->queue_count--;
- execute_queues_cpsch(dqm, false);
+ retval = execute_queues_cpsch(dqm,
+ KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
+ if (retval == -ETIME)
+ qpd->reset_wavefronts = true;
mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
@@ -1068,7 +1090,7 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm,
qpd->sh_mem_ape1_limit = limit >> 16;
}
- retval = dqm->ops_asic_specific.set_cache_memory_policy(
+ retval = dqm->asic_ops.set_cache_memory_policy(
dqm,
qpd,
default_policy,
@@ -1088,6 +1110,109 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm,
return retval;
}
+static int process_termination_nocpsch(struct device_queue_manager *dqm,
+ struct qcm_process_device *qpd)
+{
+ struct queue *q, *next;
+ struct device_process_node *cur, *next_dpn;
+ int retval = 0;
+
+ mutex_lock(&dqm->lock);
+
+ /* Clear all user mode queues */
+ list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
+ int ret;
+
+ ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
+ if (ret)
+ retval = ret;
+ }
+
+ /* Unregister process */
+ list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
+ if (qpd == cur->qpd) {
+ list_del(&cur->list);
+ kfree(cur);
+ dqm->processes_count--;
+ break;
+ }
+ }
+
+ mutex_unlock(&dqm->lock);
+ return retval;
+}
+
+
+static int process_termination_cpsch(struct device_queue_manager *dqm,
+ struct qcm_process_device *qpd)
+{
+ int retval;
+ struct queue *q, *next;
+ struct kernel_queue *kq, *kq_next;
+ struct mqd_manager *mqd;
+ struct device_process_node *cur, *next_dpn;
+ enum kfd_unmap_queues_filter filter =
+ KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
+
+ retval = 0;
+
+ mutex_lock(&dqm->lock);
+
+ /* Clean all kernel queues */
+ list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
+ list_del(&kq->list);
+ dqm->queue_count--;
+ qpd->is_debug = false;
+ dqm->total_queue_count--;
+ filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
+ }
+
+ /* Clear all user mode queues */
+ list_for_each_entry(q, &qpd->queues_list, list) {
+ if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
+ dqm->sdma_queue_count--;
+
+ if (q->properties.is_active)
+ dqm->queue_count--;
+
+ dqm->total_queue_count--;
+ }
+
+ /* Unregister process */
+ list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
+ if (qpd == cur->qpd) {
+ list_del(&cur->list);
+ kfree(cur);
+ dqm->processes_count--;
+ break;
+ }
+ }
+
+ retval = execute_queues_cpsch(dqm, filter, 0);
+ if (retval || qpd->reset_wavefronts) {
+ pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
+ dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
+ qpd->reset_wavefronts = false;
+ }
+
+ /* lastly, free mqd resources */
+ list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
+ mqd = dqm->ops.get_mqd_manager(dqm,
+ get_mqd_type_from_queue_type(q->properties.type));
+ if (!mqd) {
+ retval = -ENOMEM;
+ goto out;
+ }
+ list_del(&q->list);
+ qpd->queue_count--;
+ mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
+ }
+
+out:
+ mutex_unlock(&dqm->lock);
+ return retval;
+}
+
struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
{
struct device_queue_manager *dqm;
@@ -1109,13 +1234,14 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.stop = stop_cpsch;
dqm->ops.destroy_queue = destroy_queue_cpsch;
dqm->ops.update_queue = update_queue;
- dqm->ops.get_mqd_manager = get_mqd_manager_nocpsch;
- dqm->ops.register_process = register_process_nocpsch;
- dqm->ops.unregister_process = unregister_process_nocpsch;
- dqm->ops.uninitialize = uninitialize_nocpsch;
+ dqm->ops.get_mqd_manager = get_mqd_manager;
+ dqm->ops.register_process = register_process;
+ dqm->ops.unregister_process = unregister_process;
+ dqm->ops.uninitialize = uninitialize;
dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
+ dqm->ops.process_termination = process_termination_cpsch;
break;
case KFD_SCHED_POLICY_NO_HWS:
/* initialize dqm for no cp scheduling */
@@ -1124,12 +1250,13 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.create_queue = create_queue_nocpsch;
dqm->ops.destroy_queue = destroy_queue_nocpsch;
dqm->ops.update_queue = update_queue;
- dqm->ops.get_mqd_manager = get_mqd_manager_nocpsch;
- dqm->ops.register_process = register_process_nocpsch;
- dqm->ops.unregister_process = unregister_process_nocpsch;
+ dqm->ops.get_mqd_manager = get_mqd_manager;
+ dqm->ops.register_process = register_process;
+ dqm->ops.unregister_process = unregister_process;
dqm->ops.initialize = initialize_nocpsch;
- dqm->ops.uninitialize = uninitialize_nocpsch;
+ dqm->ops.uninitialize = uninitialize;
dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
+ dqm->ops.process_termination = process_termination_nocpsch;
break;
default:
pr_err("Invalid scheduling policy %d\n", sched_policy);
@@ -1138,12 +1265,16 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
switch (dev->device_info->asic_family) {
case CHIP_CARRIZO:
- device_queue_manager_init_vi(&dqm->ops_asic_specific);
+ device_queue_manager_init_vi(&dqm->asic_ops);
break;
case CHIP_KAVERI:
- device_queue_manager_init_cik(&dqm->ops_asic_specific);
+ device_queue_manager_init_cik(&dqm->asic_ops);
break;
+ default:
+ WARN(1, "Unexpected ASIC family %u",
+ dev->device_info->asic_family);
+ goto out_free;
}
if (!dqm->ops.initialize(dqm))
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index faf820a..5b77cb6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -29,11 +29,9 @@
#include "kfd_priv.h"
#include "kfd_mqd_manager.h"
-#define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS (500)
-#define CIK_VMID_NUM (8)
-#define KFD_VMID_START_OFFSET (8)
-#define VMID_PER_DEVICE CIK_VMID_NUM
-#define KFD_DQM_FIRST_PIPE (0)
+#define KFD_UNMAP_LATENCY_MS (4000)
+#define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS (2 * KFD_UNMAP_LATENCY_MS + 1000)
+
#define CIK_SDMA_QUEUES (4)
#define CIK_SDMA_QUEUES_PER_ENGINE (2)
#define CIK_SDMA_ENGINE_NUM (2)
@@ -79,6 +77,8 @@ struct device_process_node {
* @set_cache_memory_policy: Sets memory policy (cached/ non cached) for the
* memory apertures.
*
+ * @process_termination: Clears all process queues belongs to that device.
+ *
*/
struct device_queue_manager_ops {
@@ -122,12 +122,14 @@ struct device_queue_manager_ops {
enum cache_policy alternate_policy,
void __user *alternate_aperture_base,
uint64_t alternate_aperture_size);
+
+ int (*process_termination)(struct device_queue_manager *dqm,
+ struct qcm_process_device *qpd);
};
struct device_queue_manager_asic_ops {
- int (*register_process)(struct device_queue_manager *dqm,
+ int (*update_qpd)(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
- int (*initialize)(struct device_queue_manager *dqm);
bool (*set_cache_memory_policy)(struct device_queue_manager *dqm,
struct qcm_process_device *qpd,
enum cache_policy default_policy,
@@ -153,7 +155,7 @@ struct device_queue_manager_asic_ops {
struct device_queue_manager {
struct device_queue_manager_ops ops;
- struct device_queue_manager_asic_ops ops_asic_specific;
+ struct device_queue_manager_asic_ops asic_ops;
struct mqd_manager *mqds[KFD_MQD_TYPE_MAX];
struct packet_manager packets;
@@ -176,8 +178,10 @@ struct device_queue_manager {
bool active_runlist;
};
-void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops);
-void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops);
+void device_queue_manager_init_cik(
+ struct device_queue_manager_asic_ops *asic_ops);
+void device_queue_manager_init_vi(
+ struct device_queue_manager_asic_ops *asic_ops);
void program_sh_mem_settings(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
unsigned int get_queues_num(struct device_queue_manager *dqm);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
index 72c3cba..28e48c9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
@@ -32,18 +32,17 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
enum cache_policy alternate_policy,
void __user *alternate_aperture_base,
uint64_t alternate_aperture_size);
-static int register_process_cik(struct device_queue_manager *dqm,
+static int update_qpd_cik(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
-static int initialize_cpsch_cik(struct device_queue_manager *dqm);
static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
struct qcm_process_device *qpd);
-void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)
+void device_queue_manager_init_cik(
+ struct device_queue_manager_asic_ops *asic_ops)
{
- ops->set_cache_memory_policy = set_cache_memory_policy_cik;
- ops->register_process = register_process_cik;
- ops->initialize = initialize_cpsch_cik;
- ops->init_sdma_vm = init_sdma_vm;
+ asic_ops->set_cache_memory_policy = set_cache_memory_policy_cik;
+ asic_ops->update_qpd = update_qpd_cik;
+ asic_ops->init_sdma_vm = init_sdma_vm;
}
static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
@@ -99,7 +98,7 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
return true;
}
-static int register_process_cik(struct device_queue_manager *dqm,
+static int update_qpd_cik(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
struct kfd_process_device *pdd;
@@ -148,8 +147,3 @@ static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
q->properties.sdma_vm_addr = value;
}
-
-static int initialize_cpsch_cik(struct device_queue_manager *dqm)
-{
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
index 40e9ddd..2fbce57 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
@@ -33,18 +33,17 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
enum cache_policy alternate_policy,
void __user *alternate_aperture_base,
uint64_t alternate_aperture_size);
-static int register_process_vi(struct device_queue_manager *dqm,
+static int update_qpd_vi(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
-static int initialize_cpsch_vi(struct device_queue_manager *dqm);
static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
struct qcm_process_device *qpd);
-void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)
+void device_queue_manager_init_vi(
+ struct device_queue_manager_asic_ops *asic_ops)
{
- ops->set_cache_memory_policy = set_cache_memory_policy_vi;
- ops->register_process = register_process_vi;
- ops->initialize = initialize_cpsch_vi;
- ops->init_sdma_vm = init_sdma_vm;
+ asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi;
+ asic_ops->update_qpd = update_qpd_vi;
+ asic_ops->init_sdma_vm = init_sdma_vm;
}
static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
@@ -104,7 +103,7 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
return true;
}
-static int register_process_vi(struct device_queue_manager *dqm,
+static int update_qpd_vi(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
{
struct kfd_process_device *pdd;
@@ -160,8 +159,3 @@ static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
q->properties.sdma_vm_addr = value;
}
-
-static int initialize_cpsch_vi(struct device_queue_manager *dqm)
-{
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
index acf4d2a..feb76c2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
@@ -24,16 +24,15 @@
#include <linux/mman.h>
#include <linux/slab.h>
#include <linux/io.h>
+#include <linux/idr.h>
/*
- * This extension supports a kernel level doorbells management for
- * the kernel queues.
- * Basically the last doorbells page is devoted to kernel queues
- * and that's assures that any user process won't get access to the
- * kernel doorbells page
+ * This extension supports a kernel level doorbells management for the
+ * kernel queues using the first doorbell page reserved for the kernel.
*/
-#define KERNEL_DOORBELL_PASID 1
+static DEFINE_IDA(doorbell_ida);
+static unsigned int max_doorbell_slices;
#define KFD_SIZE_OF_DOORBELL_IN_BYTES 4
/*
@@ -84,13 +83,16 @@ int kfd_doorbell_init(struct kfd_dev *kfd)
(doorbell_aperture_size - doorbell_start_offset) /
doorbell_process_allocation();
else
- doorbell_process_limit = 0;
+ return -ENOSPC;
+
+ if (!max_doorbell_slices ||
+ doorbell_process_limit < max_doorbell_slices)
+ max_doorbell_slices = doorbell_process_limit;
kfd->doorbell_base = kfd->shared_resources.doorbell_physical_address +
doorbell_start_offset;
kfd->doorbell_id_offset = doorbell_start_offset / sizeof(u32);
- kfd->doorbell_process_limit = doorbell_process_limit - 1;
kfd->doorbell_kernel_ptr = ioremap(kfd->doorbell_base,
doorbell_process_allocation());
@@ -185,11 +187,10 @@ u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
return NULL;
/*
- * Calculating the kernel doorbell offset using "faked" kernel
- * pasid that allocated for kernel queues only
+ * Calculating the kernel doorbell offset using the first
+ * doorbell page.
*/
- *doorbell_off = KERNEL_DOORBELL_PASID * (doorbell_process_allocation() /
- sizeof(u32)) + inx;
+ *doorbell_off = kfd->doorbell_id_offset + inx;
pr_debug("Get kernel queue doorbell\n"
" doorbell offset == 0x%08X\n"
@@ -228,11 +229,12 @@ unsigned int kfd_queue_id_to_doorbell(struct kfd_dev *kfd,
{
/*
* doorbell_id_offset accounts for doorbells taken by KGD.
- * pasid * doorbell_process_allocation/sizeof(u32) adjusts
- * to the process's doorbells
+ * index * doorbell_process_allocation/sizeof(u32) adjusts to
+ * the process's doorbells.
*/
return kfd->doorbell_id_offset +
- process->pasid * (doorbell_process_allocation()/sizeof(u32)) +
+ process->doorbell_index
+ * doorbell_process_allocation() / sizeof(u32) +
queue_id;
}
@@ -250,5 +252,21 @@ phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
struct kfd_process *process)
{
return dev->doorbell_base +
- process->pasid * doorbell_process_allocation();
+ process->doorbell_index * doorbell_process_allocation();
+}
+
+int kfd_alloc_process_doorbells(struct kfd_process *process)
+{
+ int r = ida_simple_get(&doorbell_ida, 1, max_doorbell_slices,
+ GFP_KERNEL);
+ if (r > 0)
+ process->doorbell_index = r;
+
+ return r;
+}
+
+void kfd_free_process_doorbells(struct kfd_process *process)
+{
+ if (process->doorbell_index)
+ ida_simple_remove(&doorbell_ida, process->doorbell_index);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 944abfa..cb92d4b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -24,8 +24,8 @@
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/sched/signal.h>
+#include <linux/sched/mm.h>
#include <linux/uaccess.h>
-#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/memory.h>
#include "kfd_priv.h"
@@ -33,185 +33,89 @@
#include <linux/device.h>
/*
- * A task can only be on a single wait_queue at a time, but we need to support
- * waiting on multiple events (any/all).
- * Instead of each event simply having a wait_queue with sleeping tasks, it
- * has a singly-linked list of tasks.
- * A thread that wants to sleep creates an array of these, one for each event
- * and adds one to each event's waiter chain.
+ * Wrapper around wait_queue_entry_t
*/
struct kfd_event_waiter {
- struct list_head waiters;
- struct task_struct *sleeping_task;
-
- /* Transitions to true when the event this belongs to is signaled. */
- bool activated;
-
- /* Event */
- struct kfd_event *event;
- uint32_t input_index;
+ wait_queue_entry_t wait;
+ struct kfd_event *event; /* Event to wait for */
+ bool activated; /* Becomes true when event is signaled */
};
/*
- * Over-complicated pooled allocator for event notification slots.
- *
* Each signal event needs a 64-bit signal slot where the signaler will write
- * a 1 before sending an interrupt.l (This is needed because some interrupts
+ * a 1 before sending an interrupt. (This is needed because some interrupts
* do not contain enough spare data bits to identify an event.)
- * We get whole pages from vmalloc and map them to the process VA.
- * Individual signal events are then allocated a slot in a page.
+ * We get whole pages and map them to the process VA.
+ * Individual signal events use their event_id as slot index.
*/
-
-struct signal_page {
- struct list_head event_pages; /* kfd_process.signal_event_pages */
+struct kfd_signal_page {
uint64_t *kernel_address;
uint64_t __user *user_address;
- uint32_t page_index; /* Index into the mmap aperture. */
- unsigned int free_slots;
- unsigned long used_slot_bitmap[0];
};
-#define SLOTS_PER_PAGE KFD_SIGNAL_EVENT_LIMIT
-#define SLOT_BITMAP_SIZE BITS_TO_LONGS(SLOTS_PER_PAGE)
-#define BITS_PER_PAGE (ilog2(SLOTS_PER_PAGE)+1)
-#define SIGNAL_PAGE_SIZE (sizeof(struct signal_page) + \
- SLOT_BITMAP_SIZE * sizeof(long))
-/*
- * For signal events, the event ID is used as the interrupt user data.
- * For SQ s_sendmsg interrupts, this is limited to 8 bits.
- */
-
-#define INTERRUPT_DATA_BITS 8
-#define SIGNAL_EVENT_ID_SLOT_SHIFT 0
-
-static uint64_t *page_slots(struct signal_page *page)
+static uint64_t *page_slots(struct kfd_signal_page *page)
{
return page->kernel_address;
}
-static bool allocate_free_slot(struct kfd_process *process,
- struct signal_page **out_page,
- unsigned int *out_slot_index)
-{
- struct signal_page *page;
-
- list_for_each_entry(page, &process->signal_event_pages, event_pages) {
- if (page->free_slots > 0) {
- unsigned int slot =
- find_first_zero_bit(page->used_slot_bitmap,
- SLOTS_PER_PAGE);
-
- __set_bit(slot, page->used_slot_bitmap);
- page->free_slots--;
-
- page_slots(page)[slot] = UNSIGNALED_EVENT_SLOT;
-
- *out_page = page;
- *out_slot_index = slot;
-
- pr_debug("Allocated event signal slot in page %p, slot %d\n",
- page, slot);
-
- return true;
- }
- }
-
- pr_debug("No free event signal slots were found for process %p\n",
- process);
-
- return false;
-}
-
-#define list_tail_entry(head, type, member) \
- list_entry((head)->prev, type, member)
-
-static bool allocate_signal_page(struct file *devkfd, struct kfd_process *p)
+static struct kfd_signal_page *allocate_signal_page(struct kfd_process *p)
{
void *backing_store;
- struct signal_page *page;
+ struct kfd_signal_page *page;
- page = kzalloc(SIGNAL_PAGE_SIZE, GFP_KERNEL);
+ page = kzalloc(sizeof(*page), GFP_KERNEL);
if (!page)
- goto fail_alloc_signal_page;
+ return NULL;
- page->free_slots = SLOTS_PER_PAGE;
-
- backing_store = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
+ backing_store = (void *) __get_free_pages(GFP_KERNEL,
get_order(KFD_SIGNAL_EVENT_LIMIT * 8));
if (!backing_store)
goto fail_alloc_signal_store;
- /* prevent user-mode info leaks */
+ /* Initialize all events to unsignaled */
memset(backing_store, (uint8_t) UNSIGNALED_EVENT_SLOT,
- KFD_SIGNAL_EVENT_LIMIT * 8);
+ KFD_SIGNAL_EVENT_LIMIT * 8);
page->kernel_address = backing_store;
-
- if (list_empty(&p->signal_event_pages))
- page->page_index = 0;
- else
- page->page_index = list_tail_entry(&p->signal_event_pages,
- struct signal_page,
- event_pages)->page_index + 1;
-
pr_debug("Allocated new event signal page at %p, for process %p\n",
page, p);
- pr_debug("Page index is %d\n", page->page_index);
- list_add(&page->event_pages, &p->signal_event_pages);
-
- return true;
+ return page;
fail_alloc_signal_store:
kfree(page);
-fail_alloc_signal_page:
- return false;
+ return NULL;
}
-static bool allocate_event_notification_slot(struct file *devkfd,
- struct kfd_process *p,
- struct signal_page **page,
- unsigned int *signal_slot_index)
+static int allocate_event_notification_slot(struct kfd_process *p,
+ struct kfd_event *ev)
{
- bool ret;
+ int id;
- ret = allocate_free_slot(p, page, signal_slot_index);
- if (!ret) {
- ret = allocate_signal_page(devkfd, p);
- if (ret)
- ret = allocate_free_slot(p, page, signal_slot_index);
+ if (!p->signal_page) {
+ p->signal_page = allocate_signal_page(p);
+ if (!p->signal_page)
+ return -ENOMEM;
+ /* Oldest user mode expects 256 event slots */
+ p->signal_mapped_size = 256*8;
}
- return ret;
-}
-
-/* Assumes that the process's event_mutex is locked. */
-static void release_event_notification_slot(struct signal_page *page,
- size_t slot_index)
-{
- __clear_bit(slot_index, page->used_slot_bitmap);
- page->free_slots++;
-
- /* We don't free signal pages, they are retained by the process
- * and reused until it exits.
- */
-}
-
-static struct signal_page *lookup_signal_page_by_index(struct kfd_process *p,
- unsigned int page_index)
-{
- struct signal_page *page;
-
/*
- * This is safe because we don't delete signal pages until the
- * process exits.
+ * Compatibility with old user mode: Only use signal slots
+ * user mode has mapped, may be less than
+ * KFD_SIGNAL_EVENT_LIMIT. This also allows future increase
+ * of the event limit without breaking user mode.
*/
- list_for_each_entry(page, &p->signal_event_pages, event_pages)
- if (page->page_index == page_index)
- return page;
+ id = idr_alloc(&p->event_idr, ev, 0, p->signal_mapped_size / 8,
+ GFP_KERNEL);
+ if (id < 0)
+ return id;
- return NULL;
+ ev->event_id = id;
+ page_slots(p->signal_page)[id] = UNSIGNALED_EVENT_SLOT;
+
+ return 0;
}
/*
@@ -220,99 +124,81 @@ static struct signal_page *lookup_signal_page_by_index(struct kfd_process *p,
*/
static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id)
{
+ return idr_find(&p->event_idr, id);
+}
+
+/**
+ * lookup_signaled_event_by_partial_id - Lookup signaled event from partial ID
+ * @p: Pointer to struct kfd_process
+ * @id: ID to look up
+ * @bits: Number of valid bits in @id
+ *
+ * Finds the first signaled event with a matching partial ID. If no
+ * matching signaled event is found, returns NULL. In that case the
+ * caller should assume that the partial ID is invalid and do an
+ * exhaustive search of all siglaned events.
+ *
+ * If multiple events with the same partial ID signal at the same
+ * time, they will be found one interrupt at a time, not necessarily
+ * in the same order the interrupts occurred. As long as the number of
+ * interrupts is correct, all signaled events will be seen by the
+ * driver.
+ */
+static struct kfd_event *lookup_signaled_event_by_partial_id(
+ struct kfd_process *p, uint32_t id, uint32_t bits)
+{
struct kfd_event *ev;
- hash_for_each_possible(p->events, ev, events, id)
- if (ev->event_id == id)
- return ev;
+ if (!p->signal_page || id >= KFD_SIGNAL_EVENT_LIMIT)
+ return NULL;
- return NULL;
-}
+ /* Fast path for the common case that @id is not a partial ID
+ * and we only need a single lookup.
+ */
+ if (bits > 31 || (1U << bits) >= KFD_SIGNAL_EVENT_LIMIT) {
+ if (page_slots(p->signal_page)[id] == UNSIGNALED_EVENT_SLOT)
+ return NULL;
-static u32 make_signal_event_id(struct signal_page *page,
- unsigned int signal_slot_index)
-{
- return page->page_index |
- (signal_slot_index << SIGNAL_EVENT_ID_SLOT_SHIFT);
-}
-
-/*
- * Produce a kfd event id for a nonsignal event.
- * These are arbitrary numbers, so we do a sequential search through
- * the hash table for an unused number.
- */
-static u32 make_nonsignal_event_id(struct kfd_process *p)
-{
- u32 id;
-
- for (id = p->next_nonsignal_event_id;
- id < KFD_LAST_NONSIGNAL_EVENT_ID &&
- lookup_event_by_id(p, id);
- id++)
- ;
-
- if (id < KFD_LAST_NONSIGNAL_EVENT_ID) {
-
- /*
- * What if id == LAST_NONSIGNAL_EVENT_ID - 1?
- * Then next_nonsignal_event_id = LAST_NONSIGNAL_EVENT_ID so
- * the first loop fails immediately and we proceed with the
- * wraparound loop below.
- */
- p->next_nonsignal_event_id = id + 1;
-
- return id;
+ return idr_find(&p->event_idr, id);
}
- for (id = KFD_FIRST_NONSIGNAL_EVENT_ID;
- id < KFD_LAST_NONSIGNAL_EVENT_ID &&
- lookup_event_by_id(p, id);
- id++)
- ;
+ /* General case for partial IDs: Iterate over all matching IDs
+ * and find the first one that has signaled.
+ */
+ for (ev = NULL; id < KFD_SIGNAL_EVENT_LIMIT && !ev; id += 1U << bits) {
+ if (page_slots(p->signal_page)[id] == UNSIGNALED_EVENT_SLOT)
+ continue;
-
- if (id < KFD_LAST_NONSIGNAL_EVENT_ID) {
- p->next_nonsignal_event_id = id + 1;
- return id;
+ ev = idr_find(&p->event_idr, id);
}
- p->next_nonsignal_event_id = KFD_FIRST_NONSIGNAL_EVENT_ID;
- return 0;
-}
-
-static struct kfd_event *lookup_event_by_page_slot(struct kfd_process *p,
- struct signal_page *page,
- unsigned int signal_slot)
-{
- return lookup_event_by_id(p, make_signal_event_id(page, signal_slot));
+ return ev;
}
static int create_signal_event(struct file *devkfd,
struct kfd_process *p,
struct kfd_event *ev)
{
- if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) {
+ int ret;
+
+ if (p->signal_mapped_size &&
+ p->signal_event_count == p->signal_mapped_size / 8) {
if (!p->signal_event_limit_reached) {
pr_warn("Signal event wasn't created because limit was reached\n");
p->signal_event_limit_reached = true;
}
- return -ENOMEM;
+ return -ENOSPC;
}
- if (!allocate_event_notification_slot(devkfd, p, &ev->signal_page,
- &ev->signal_slot_index)) {
+ ret = allocate_event_notification_slot(p, ev);
+ if (ret) {
pr_warn("Signal event wasn't created because out of kernel memory\n");
- return -ENOMEM;
+ return ret;
}
p->signal_event_count++;
- ev->user_signal_address =
- &ev->signal_page->user_address[ev->signal_slot_index];
-
- ev->event_id = make_signal_event_id(ev->signal_page,
- ev->signal_slot_index);
-
+ ev->user_signal_address = &p->signal_page->user_address[ev->event_id];
pr_debug("Signal event number %zu created with id %d, address %p\n",
p->signal_event_count, ev->event_id,
ev->user_signal_address);
@@ -320,16 +206,20 @@ static int create_signal_event(struct file *devkfd,
return 0;
}
-/*
- * No non-signal events are supported yet.
- * We create them as events that never signal.
- * Set event calls from user-mode are failed.
- */
static int create_other_event(struct kfd_process *p, struct kfd_event *ev)
{
- ev->event_id = make_nonsignal_event_id(p);
- if (ev->event_id == 0)
- return -ENOMEM;
+ /* Cast KFD_LAST_NONSIGNAL_EVENT to uint32_t. This allows an
+ * intentional integer overflow to -1 without a compiler
+ * warning. idr_alloc treats a negative value as "maximum
+ * signed integer".
+ */
+ int id = idr_alloc(&p->event_idr, ev, KFD_FIRST_NONSIGNAL_EVENT_ID,
+ (uint32_t)KFD_LAST_NONSIGNAL_EVENT_ID + 1,
+ GFP_KERNEL);
+
+ if (id < 0)
+ return id;
+ ev->event_id = id;
return 0;
}
@@ -337,50 +227,47 @@ static int create_other_event(struct kfd_process *p, struct kfd_event *ev)
void kfd_event_init_process(struct kfd_process *p)
{
mutex_init(&p->event_mutex);
- hash_init(p->events);
- INIT_LIST_HEAD(&p->signal_event_pages);
- p->next_nonsignal_event_id = KFD_FIRST_NONSIGNAL_EVENT_ID;
+ idr_init(&p->event_idr);
+ p->signal_page = NULL;
p->signal_event_count = 0;
}
static void destroy_event(struct kfd_process *p, struct kfd_event *ev)
{
- if (ev->signal_page) {
- release_event_notification_slot(ev->signal_page,
- ev->signal_slot_index);
+ struct kfd_event_waiter *waiter;
+
+ /* Wake up pending waiters. They will return failure */
+ list_for_each_entry(waiter, &ev->wq.head, wait.entry)
+ waiter->event = NULL;
+ wake_up_all(&ev->wq);
+
+ if (ev->type == KFD_EVENT_TYPE_SIGNAL ||
+ ev->type == KFD_EVENT_TYPE_DEBUG)
p->signal_event_count--;
- }
- /*
- * Abandon the list of waiters. Individual waiting threads will
- * clean up their own data.
- */
- list_del(&ev->waiters);
-
- hash_del(&ev->events);
+ idr_remove(&p->event_idr, ev->event_id);
kfree(ev);
}
static void destroy_events(struct kfd_process *p)
{
struct kfd_event *ev;
- struct hlist_node *tmp;
- unsigned int hash_bkt;
+ uint32_t id;
- hash_for_each_safe(p->events, hash_bkt, tmp, ev, events)
+ idr_for_each_entry(&p->event_idr, ev, id)
destroy_event(p, ev);
+ idr_destroy(&p->event_idr);
}
/*
* We assume that the process is being destroyed and there is no need to
* unmap the pages or keep bookkeeping data in order.
*/
-static void shutdown_signal_pages(struct kfd_process *p)
+static void shutdown_signal_page(struct kfd_process *p)
{
- struct signal_page *page, *tmp;
+ struct kfd_signal_page *page = p->signal_page;
- list_for_each_entry_safe(page, tmp, &p->signal_event_pages,
- event_pages) {
+ if (page) {
free_pages((unsigned long)page->kernel_address,
get_order(KFD_SIGNAL_EVENT_LIMIT * 8));
kfree(page);
@@ -390,7 +277,7 @@ static void shutdown_signal_pages(struct kfd_process *p)
void kfd_event_free_process(struct kfd_process *p)
{
destroy_events(p);
- shutdown_signal_pages(p);
+ shutdown_signal_page(p);
}
static bool event_can_be_gpu_signaled(const struct kfd_event *ev)
@@ -419,7 +306,7 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p,
ev->auto_reset = auto_reset;
ev->signaled = false;
- INIT_LIST_HEAD(&ev->waiters);
+ init_waitqueue_head(&ev->wq);
*event_page_offset = 0;
@@ -430,10 +317,9 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p,
case KFD_EVENT_TYPE_DEBUG:
ret = create_signal_event(devkfd, p, ev);
if (!ret) {
- *event_page_offset = (ev->signal_page->page_index |
- KFD_MMAP_EVENTS_MASK);
+ *event_page_offset = KFD_MMAP_EVENTS_MASK;
*event_page_offset <<= PAGE_SHIFT;
- *event_slot_index = ev->signal_slot_index;
+ *event_slot_index = ev->event_id;
}
break;
default:
@@ -442,8 +328,6 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p,
}
if (!ret) {
- hash_add(p->events, &ev->events, ev->event_id);
-
*event_id = ev->event_id;
*event_trigger_data = ev->event_id;
} else {
@@ -477,19 +361,18 @@ int kfd_event_destroy(struct kfd_process *p, uint32_t event_id)
static void set_event(struct kfd_event *ev)
{
struct kfd_event_waiter *waiter;
- struct kfd_event_waiter *next;
- /* Auto reset if the list is non-empty and we're waking someone. */
- ev->signaled = !ev->auto_reset || list_empty(&ev->waiters);
+ /* Auto reset if the list is non-empty and we're waking
+ * someone. waitqueue_active is safe here because we're
+ * protected by the p->event_mutex, which is also held when
+ * updating the wait queues in kfd_wait_on_events.
+ */
+ ev->signaled = !ev->auto_reset || !waitqueue_active(&ev->wq);
- list_for_each_entry_safe(waiter, next, &ev->waiters, waiters) {
+ list_for_each_entry(waiter, &ev->wq.head, wait.entry)
waiter->activated = true;
- /* _init because free_waiters will call list_del */
- list_del_init(&waiter->waiters);
-
- wake_up_process(waiter->sleeping_task);
- }
+ wake_up_all(&ev->wq);
}
/* Assumes that p is current. */
@@ -538,13 +421,7 @@ int kfd_reset_event(struct kfd_process *p, uint32_t event_id)
static void acknowledge_signal(struct kfd_process *p, struct kfd_event *ev)
{
- page_slots(ev->signal_page)[ev->signal_slot_index] =
- UNSIGNALED_EVENT_SLOT;
-}
-
-static bool is_slot_signaled(struct signal_page *page, unsigned int index)
-{
- return page_slots(page)[index] != UNSIGNALED_EVENT_SLOT;
+ page_slots(p->signal_page)[ev->event_id] = UNSIGNALED_EVENT_SLOT;
}
static void set_event_from_interrupt(struct kfd_process *p,
@@ -559,7 +436,7 @@ static void set_event_from_interrupt(struct kfd_process *p,
void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
uint32_t valid_id_bits)
{
- struct kfd_event *ev;
+ struct kfd_event *ev = NULL;
/*
* Because we are called from arbitrary context (workqueue) as opposed
@@ -573,26 +450,46 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
mutex_lock(&p->event_mutex);
- if (valid_id_bits >= INTERRUPT_DATA_BITS) {
- /* Partial ID is a full ID. */
- ev = lookup_event_by_id(p, partial_id);
+ if (valid_id_bits)
+ ev = lookup_signaled_event_by_partial_id(p, partial_id,
+ valid_id_bits);
+ if (ev) {
set_event_from_interrupt(p, ev);
- } else {
+ } else if (p->signal_page) {
/*
- * Partial ID is in fact partial. For now we completely
- * ignore it, but we could use any bits we did receive to
- * search faster.
+ * Partial ID lookup failed. Assume that the event ID
+ * in the interrupt payload was invalid and do an
+ * exhaustive search of signaled events.
*/
- struct signal_page *page;
- unsigned int i;
+ uint64_t *slots = page_slots(p->signal_page);
+ uint32_t id;
- list_for_each_entry(page, &p->signal_event_pages, event_pages)
- for (i = 0; i < SLOTS_PER_PAGE; i++)
- if (is_slot_signaled(page, i)) {
- ev = lookup_event_by_page_slot(p,
- page, i);
+ if (valid_id_bits)
+ pr_debug_ratelimited("Partial ID invalid: %u (%u valid bits)\n",
+ partial_id, valid_id_bits);
+
+ if (p->signal_event_count < KFD_SIGNAL_EVENT_LIMIT/2) {
+ /* With relatively few events, it's faster to
+ * iterate over the event IDR
+ */
+ idr_for_each_entry(&p->event_idr, ev, id) {
+ if (id >= KFD_SIGNAL_EVENT_LIMIT)
+ break;
+
+ if (slots[id] != UNSIGNALED_EVENT_SLOT)
+ set_event_from_interrupt(p, ev);
+ }
+ } else {
+ /* With relatively many events, it's faster to
+ * iterate over the signal slots and lookup
+ * only signaled events from the IDR.
+ */
+ for (id = 0; id < KFD_SIGNAL_EVENT_LIMIT; id++)
+ if (slots[id] != UNSIGNALED_EVENT_SLOT) {
+ ev = lookup_event_by_id(p, id);
set_event_from_interrupt(p, ev);
}
+ }
}
mutex_unlock(&p->event_mutex);
@@ -609,18 +506,16 @@ static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events)
GFP_KERNEL);
for (i = 0; (event_waiters) && (i < num_events) ; i++) {
- INIT_LIST_HEAD(&event_waiters[i].waiters);
- event_waiters[i].sleeping_task = current;
+ init_wait(&event_waiters[i].wait);
event_waiters[i].activated = false;
}
return event_waiters;
}
-static int init_event_waiter(struct kfd_process *p,
+static int init_event_waiter_get_status(struct kfd_process *p,
struct kfd_event_waiter *waiter,
- uint32_t event_id,
- uint32_t input_index)
+ uint32_t event_id)
{
struct kfd_event *ev = lookup_event_by_id(p, event_id);
@@ -628,38 +523,60 @@ static int init_event_waiter(struct kfd_process *p,
return -EINVAL;
waiter->event = ev;
- waiter->input_index = input_index;
waiter->activated = ev->signaled;
ev->signaled = ev->signaled && !ev->auto_reset;
- list_add(&waiter->waiters, &ev->waiters);
-
return 0;
}
-static bool test_event_condition(bool all, uint32_t num_events,
+static void init_event_waiter_add_to_waitlist(struct kfd_event_waiter *waiter)
+{
+ struct kfd_event *ev = waiter->event;
+
+ /* Only add to the wait list if we actually need to
+ * wait on this event.
+ */
+ if (!waiter->activated)
+ add_wait_queue(&ev->wq, &waiter->wait);
+}
+
+/* test_event_condition - Test condition of events being waited for
+ * @all: Return completion only if all events have signaled
+ * @num_events: Number of events to wait for
+ * @event_waiters: Array of event waiters, one per event
+ *
+ * Returns KFD_IOC_WAIT_RESULT_COMPLETE if all (or one) event(s) have
+ * signaled. Returns KFD_IOC_WAIT_RESULT_TIMEOUT if no (or not all)
+ * events have signaled. Returns KFD_IOC_WAIT_RESULT_FAIL if any of
+ * the events have been destroyed.
+ */
+static uint32_t test_event_condition(bool all, uint32_t num_events,
struct kfd_event_waiter *event_waiters)
{
uint32_t i;
uint32_t activated_count = 0;
for (i = 0; i < num_events; i++) {
+ if (!event_waiters[i].event)
+ return KFD_IOC_WAIT_RESULT_FAIL;
+
if (event_waiters[i].activated) {
if (!all)
- return true;
+ return KFD_IOC_WAIT_RESULT_COMPLETE;
activated_count++;
}
}
- return activated_count == num_events;
+ return activated_count == num_events ?
+ KFD_IOC_WAIT_RESULT_COMPLETE : KFD_IOC_WAIT_RESULT_TIMEOUT;
}
/*
* Copy event specific data, if defined.
* Currently only memory exception events have additional data to copy to user
*/
-static bool copy_signaled_event_data(uint32_t num_events,
+static int copy_signaled_event_data(uint32_t num_events,
struct kfd_event_waiter *event_waiters,
struct kfd_event_data __user *data)
{
@@ -673,15 +590,15 @@ static bool copy_signaled_event_data(uint32_t num_events,
waiter = &event_waiters[i];
event = waiter->event;
if (waiter->activated && event->type == KFD_EVENT_TYPE_MEMORY) {
- dst = &data[waiter->input_index].memory_exception_data;
+ dst = &data[i].memory_exception_data;
src = &event->memory_exception_data;
if (copy_to_user(dst, src,
sizeof(struct kfd_hsa_memory_exception_data)))
- return false;
+ return -EFAULT;
}
}
- return true;
+ return 0;
}
@@ -710,7 +627,9 @@ static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters)
uint32_t i;
for (i = 0; i < num_events; i++)
- list_del(&waiters[i].waiters);
+ if (waiters[i].event)
+ remove_wait_queue(&waiters[i].event->wq,
+ &waiters[i].wait);
kfree(waiters);
}
@@ -718,38 +637,56 @@ static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters)
int kfd_wait_on_events(struct kfd_process *p,
uint32_t num_events, void __user *data,
bool all, uint32_t user_timeout_ms,
- enum kfd_event_wait_result *wait_result)
+ uint32_t *wait_result)
{
struct kfd_event_data __user *events =
(struct kfd_event_data __user *) data;
uint32_t i;
int ret = 0;
+
struct kfd_event_waiter *event_waiters = NULL;
long timeout = user_timeout_to_jiffies(user_timeout_ms);
- mutex_lock(&p->event_mutex);
-
event_waiters = alloc_event_waiters(num_events);
if (!event_waiters) {
ret = -ENOMEM;
- goto fail;
+ goto out;
}
+ mutex_lock(&p->event_mutex);
+
for (i = 0; i < num_events; i++) {
struct kfd_event_data event_data;
if (copy_from_user(&event_data, &events[i],
sizeof(struct kfd_event_data))) {
ret = -EFAULT;
- goto fail;
+ goto out_unlock;
}
- ret = init_event_waiter(p, &event_waiters[i],
- event_data.event_id, i);
+ ret = init_event_waiter_get_status(p, &event_waiters[i],
+ event_data.event_id);
if (ret)
- goto fail;
+ goto out_unlock;
}
+ /* Check condition once. */
+ *wait_result = test_event_condition(all, num_events, event_waiters);
+ if (*wait_result == KFD_IOC_WAIT_RESULT_COMPLETE) {
+ ret = copy_signaled_event_data(num_events,
+ event_waiters, events);
+ goto out_unlock;
+ } else if (WARN_ON(*wait_result == KFD_IOC_WAIT_RESULT_FAIL)) {
+ /* This should not happen. Events shouldn't be
+ * destroyed while we're holding the event_mutex
+ */
+ goto out_unlock;
+ }
+
+ /* Add to wait lists if we need to wait. */
+ for (i = 0; i < num_events; i++)
+ init_event_waiter_add_to_waitlist(&event_waiters[i]);
+
mutex_unlock(&p->event_mutex);
while (true) {
@@ -771,62 +708,66 @@ int kfd_wait_on_events(struct kfd_process *p,
break;
}
- if (test_event_condition(all, num_events, event_waiters)) {
- if (copy_signaled_event_data(num_events,
- event_waiters, events))
- *wait_result = KFD_WAIT_COMPLETE;
- else
- *wait_result = KFD_WAIT_ERROR;
- break;
- }
+ /* Set task state to interruptible sleep before
+ * checking wake-up conditions. A concurrent wake-up
+ * will put the task back into runnable state. In that
+ * case schedule_timeout will not put the task to
+ * sleep and we'll get a chance to re-check the
+ * updated conditions almost immediately. Otherwise,
+ * this race condition would lead to a soft hang or a
+ * very long sleep.
+ */
+ set_current_state(TASK_INTERRUPTIBLE);
- if (timeout <= 0) {
- *wait_result = KFD_WAIT_TIMEOUT;
+ *wait_result = test_event_condition(all, num_events,
+ event_waiters);
+ if (*wait_result != KFD_IOC_WAIT_RESULT_TIMEOUT)
break;
- }
- timeout = schedule_timeout_interruptible(timeout);
+ if (timeout <= 0)
+ break;
+
+ timeout = schedule_timeout(timeout);
}
__set_current_state(TASK_RUNNING);
+ /* copy_signaled_event_data may sleep. So this has to happen
+ * after the task state is set back to RUNNING.
+ */
+ if (!ret && *wait_result == KFD_IOC_WAIT_RESULT_COMPLETE)
+ ret = copy_signaled_event_data(num_events,
+ event_waiters, events);
+
mutex_lock(&p->event_mutex);
+out_unlock:
free_waiters(num_events, event_waiters);
mutex_unlock(&p->event_mutex);
-
- return ret;
-
-fail:
- if (event_waiters)
- free_waiters(num_events, event_waiters);
-
- mutex_unlock(&p->event_mutex);
-
- *wait_result = KFD_WAIT_ERROR;
+out:
+ if (ret)
+ *wait_result = KFD_IOC_WAIT_RESULT_FAIL;
+ else if (*wait_result == KFD_IOC_WAIT_RESULT_FAIL)
+ ret = -EIO;
return ret;
}
int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma)
{
-
- unsigned int page_index;
unsigned long pfn;
- struct signal_page *page;
+ struct kfd_signal_page *page;
+ int ret;
- /* check required size is logical */
- if (get_order(KFD_SIGNAL_EVENT_LIMIT * 8) !=
+ /* check required size doesn't exceed the allocated size */
+ if (get_order(KFD_SIGNAL_EVENT_LIMIT * 8) <
get_order(vma->vm_end - vma->vm_start)) {
pr_err("Event page mmap requested illegal size\n");
return -EINVAL;
}
- page_index = vma->vm_pgoff;
-
- page = lookup_signal_page_by_index(p, page_index);
+ page = p->signal_page;
if (!page) {
/* Probably KFD bug, but mmap is user-accessible. */
- pr_debug("Signal page could not be found for page_index %u\n",
- page_index);
+ pr_debug("Signal page could not be found\n");
return -EINVAL;
}
@@ -847,8 +788,12 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma)
page->user_address = (uint64_t __user *)vma->vm_start;
/* mapping the page to user process */
- return remap_pfn_range(vma, vma->vm_start, pfn,
+ ret = remap_pfn_range(vma, vma->vm_start, pfn,
vma->vm_end - vma->vm_start, vma->vm_page_prot);
+ if (!ret)
+ p->signal_mapped_size = vma->vm_end - vma->vm_start;
+
+ return ret;
}
/*
@@ -860,12 +805,13 @@ static void lookup_events_by_type_and_signal(struct kfd_process *p,
{
struct kfd_hsa_memory_exception_data *ev_data;
struct kfd_event *ev;
- int bkt;
+ uint32_t id;
bool send_signal = true;
ev_data = (struct kfd_hsa_memory_exception_data *) event_data;
- hash_for_each(p->events, bkt, ev, events)
+ id = KFD_FIRST_NONSIGNAL_EVENT_ID;
+ idr_for_each_entry_continue(&p->event_idr, ev, id)
if (ev->type == type) {
send_signal = false;
dev_dbg(kfd_device,
@@ -904,14 +850,24 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid,
* running so the lookup function returns a locked process.
*/
struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
+ struct mm_struct *mm;
if (!p)
return; /* Presumably process exited. */
+ /* Take a safe reference to the mm_struct, which may otherwise
+ * disappear even while the kfd_process is still referenced.
+ */
+ mm = get_task_mm(p->lead_thread);
+ if (!mm) {
+ mutex_unlock(&p->mutex);
+ return; /* Process is exiting */
+ }
+
memset(&memory_exception_data, 0, sizeof(memory_exception_data));
- down_read(&p->mm->mmap_sem);
- vma = find_vma(p->mm, address);
+ down_read(&mm->mmap_sem);
+ vma = find_vma(mm, address);
memory_exception_data.gpu_id = dev->id;
memory_exception_data.va = address;
@@ -937,7 +893,8 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid,
}
}
- up_read(&p->mm->mmap_sem);
+ up_read(&mm->mmap_sem);
+ mmput(mm);
mutex_lock(&p->event_mutex);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_events.h
index 28f6838..abca5bf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.h
@@ -27,12 +27,17 @@
#include <linux/hashtable.h>
#include <linux/types.h>
#include <linux/list.h>
+#include <linux/wait.h>
#include "kfd_priv.h"
#include <uapi/linux/kfd_ioctl.h>
-#define KFD_EVENT_ID_NONSIGNAL_MASK 0x80000000U
-#define KFD_FIRST_NONSIGNAL_EVENT_ID KFD_EVENT_ID_NONSIGNAL_MASK
-#define KFD_LAST_NONSIGNAL_EVENT_ID UINT_MAX
+/*
+ * IDR supports non-negative integer IDs. Small IDs are used for
+ * signal events to match their signal slot. Use the upper half of the
+ * ID space for non-signal events.
+ */
+#define KFD_FIRST_NONSIGNAL_EVENT_ID ((INT_MAX >> 1) + 1)
+#define KFD_LAST_NONSIGNAL_EVENT_ID INT_MAX
/*
* Written into kfd_signal_slot_t to indicate that the event is not signaled.
@@ -46,9 +51,6 @@ struct kfd_event_waiter;
struct signal_page;
struct kfd_event {
- /* All events in process, rooted at kfd_process.events. */
- struct hlist_node events;
-
u32 event_id;
bool signaled;
@@ -56,11 +58,9 @@ struct kfd_event {
int type;
- struct list_head waiters; /* List of kfd_event_waiter by waiters. */
+ wait_queue_head_t wq; /* List of event waiters. */
/* Only for signal events. */
- struct signal_page *signal_page;
- unsigned int signal_slot_index;
uint64_t __user *user_signal_address;
/* type specific data */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index 70b3a99c..035c351 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -42,26 +42,26 @@
#include <linux/slab.h>
#include <linux/device.h>
+#include <linux/kfifo.h>
#include "kfd_priv.h"
-#define KFD_INTERRUPT_RING_SIZE 1024
+#define KFD_IH_NUM_ENTRIES 8192
static void interrupt_wq(struct work_struct *);
int kfd_interrupt_init(struct kfd_dev *kfd)
{
- void *interrupt_ring = kmalloc_array(KFD_INTERRUPT_RING_SIZE,
- kfd->device_info->ih_ring_entry_size,
- GFP_KERNEL);
- if (!interrupt_ring)
- return -ENOMEM;
+ int r;
- kfd->interrupt_ring = interrupt_ring;
- kfd->interrupt_ring_size =
- KFD_INTERRUPT_RING_SIZE * kfd->device_info->ih_ring_entry_size;
- atomic_set(&kfd->interrupt_ring_wptr, 0);
- atomic_set(&kfd->interrupt_ring_rptr, 0);
+ r = kfifo_alloc(&kfd->ih_fifo,
+ KFD_IH_NUM_ENTRIES * kfd->device_info->ih_ring_entry_size,
+ GFP_KERNEL);
+ if (r) {
+ dev_err(kfd_chardev(), "Failed to allocate IH fifo\n");
+ return r;
+ }
+ kfd->ih_wq = alloc_workqueue("KFD IH", WQ_HIGHPRI, 1);
spin_lock_init(&kfd->interrupt_lock);
INIT_WORK(&kfd->interrupt_work, interrupt_wq);
@@ -92,74 +92,47 @@ void kfd_interrupt_exit(struct kfd_dev *kfd)
spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
/*
- * Flush_scheduled_work ensures that there are no outstanding
+ * flush_work ensures that there are no outstanding
* work-queue items that will access interrupt_ring. New work items
* can't be created because we stopped interrupt handling above.
*/
- flush_scheduled_work();
+ flush_workqueue(kfd->ih_wq);
- kfree(kfd->interrupt_ring);
+ kfifo_free(&kfd->ih_fifo);
}
/*
- * This assumes that it can't be called concurrently with itself
- * but only with dequeue_ih_ring_entry.
+ * Assumption: single reader/writer. This function is not re-entrant
*/
bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry)
{
- unsigned int rptr = atomic_read(&kfd->interrupt_ring_rptr);
- unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr);
+ int count;
- if ((rptr - wptr) % kfd->interrupt_ring_size ==
- kfd->device_info->ih_ring_entry_size) {
- /* This is very bad, the system is likely to hang. */
+ count = kfifo_in(&kfd->ih_fifo, ih_ring_entry,
+ kfd->device_info->ih_ring_entry_size);
+ if (count != kfd->device_info->ih_ring_entry_size) {
dev_err_ratelimited(kfd_chardev(),
- "Interrupt ring overflow, dropping interrupt.\n");
+ "Interrupt ring overflow, dropping interrupt %d\n",
+ count);
return false;
}
- memcpy(kfd->interrupt_ring + wptr, ih_ring_entry,
- kfd->device_info->ih_ring_entry_size);
-
- wptr = (wptr + kfd->device_info->ih_ring_entry_size) %
- kfd->interrupt_ring_size;
- smp_wmb(); /* Ensure memcpy'd data is visible before wptr update. */
- atomic_set(&kfd->interrupt_ring_wptr, wptr);
-
return true;
}
/*
- * This assumes that it can't be called concurrently with itself
- * but only with enqueue_ih_ring_entry.
+ * Assumption: single reader/writer. This function is not re-entrant
*/
static bool dequeue_ih_ring_entry(struct kfd_dev *kfd, void *ih_ring_entry)
{
- /*
- * Assume that wait queues have an implicit barrier, i.e. anything that
- * happened in the ISR before it queued work is visible.
- */
+ int count;
- unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr);
- unsigned int rptr = atomic_read(&kfd->interrupt_ring_rptr);
+ count = kfifo_out(&kfd->ih_fifo, ih_ring_entry,
+ kfd->device_info->ih_ring_entry_size);
- if (rptr == wptr)
- return false;
+ WARN_ON(count && count != kfd->device_info->ih_ring_entry_size);
- memcpy(ih_ring_entry, kfd->interrupt_ring + rptr,
- kfd->device_info->ih_ring_entry_size);
-
- rptr = (rptr + kfd->device_info->ih_ring_entry_size) %
- kfd->interrupt_ring_size;
-
- /*
- * Ensure the rptr write update is not visible until
- * memcpy has finished reading.
- */
- smp_mb();
- atomic_set(&kfd->interrupt_ring_rptr, rptr);
-
- return true;
+ return count == kfd->device_info->ih_ring_entry_size;
}
static void interrupt_wq(struct work_struct *work)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index ed71ad4..8b0c064 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -185,7 +185,7 @@ static void uninitialize(struct kernel_queue *kq)
kq->mqd->destroy_mqd(kq->mqd,
kq->queue->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
- QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
+ KFD_UNMAP_LATENCY_MS,
kq->queue->pipe,
kq->queue->queue);
else if (kq->queue->properties.type == KFD_QUEUE_TYPE_DIQ)
@@ -303,14 +303,20 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
case CHIP_KAVERI:
kernel_queue_init_cik(&kq->ops_asic_specific);
break;
+ default:
+ WARN(1, "Unexpected ASIC family %u",
+ dev->device_info->asic_family);
+ goto out_free;
}
- if (!kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE)) {
- pr_err("Failed to init kernel queue\n");
- kfree(kq);
- return NULL;
- }
- return kq;
+ if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
+ return kq;
+
+ pr_err("Failed to init kernel queue\n");
+
+out_free:
+ kfree(kq);
+ return NULL;
}
void kernel_queue_uninit(struct kernel_queue *kq)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 0d73bea..6c5a9ca 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -103,10 +103,6 @@ static int __init kfd_module_init(void)
return -1;
}
- err = kfd_pasid_init();
- if (err < 0)
- return err;
-
err = kfd_chardev_init();
if (err < 0)
goto err_ioctl;
@@ -126,7 +122,6 @@ static int __init kfd_module_init(void)
err_topology:
kfd_chardev_exit();
err_ioctl:
- kfd_pasid_exit();
return err;
}
@@ -137,7 +132,6 @@ static void __exit kfd_module_exit(void)
kfd_process_destroy_wq();
kfd_topology_shutdown();
kfd_chardev_exit();
- kfd_pasid_exit();
dev_info(kfd_device, "Removed module\n");
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index b1ef136..dfd260e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -31,6 +31,9 @@ struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
return mqd_manager_init_cik(type, dev);
case CHIP_CARRIZO:
return mqd_manager_init_vi(type, dev);
+ default:
+ WARN(1, "Unexpected ASIC family %u",
+ dev->device_info->asic_family);
}
return NULL;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 44ffd23..4859d26 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -189,12 +189,9 @@ static int update_mqd(struct mqd_manager *mm, void *mqd,
if (q->format == KFD_QUEUE_FORMAT_AQL)
m->cp_hqd_pq_control |= NO_UPDATE_RPTR;
- q->is_active = false;
- if (q->queue_size > 0 &&
+ q->is_active = (q->queue_size > 0 &&
q->queue_address != 0 &&
- q->queue_percent > 0) {
- q->is_active = true;
- }
+ q->queue_percent > 0);
return 0;
}
@@ -215,24 +212,17 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);
m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
- m->sdma_rlc_doorbell = q->doorbell_off <<
- SDMA0_RLC0_DOORBELL__OFFSET__SHIFT |
- 1 << SDMA0_RLC0_DOORBELL__ENABLE__SHIFT;
+ m->sdma_rlc_doorbell =
+ q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
m->sdma_rlc_virtual_addr = q->sdma_vm_addr;
m->sdma_engine_id = q->sdma_engine_id;
m->sdma_queue_id = q->sdma_queue_id;
- q->is_active = false;
- if (q->queue_size > 0 &&
+ q->is_active = (q->queue_size > 0 &&
q->queue_address != 0 &&
- q->queue_percent > 0) {
- m->sdma_rlc_rb_cntl |=
- 1 << SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT;
-
- q->is_active = true;
- }
+ q->queue_percent > 0);
return 0;
}
@@ -359,19 +349,13 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
- m->cp_hqd_pq_doorbell_control = DOORBELL_EN |
- DOORBELL_OFFSET(q->doorbell_off);
+ m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);
m->cp_hqd_vmid = q->vmid;
- m->cp_hqd_active = 0;
- q->is_active = false;
- if (q->queue_size > 0 &&
+ q->is_active = (q->queue_size > 0 &&
q->queue_address != 0 &&
- q->queue_percent > 0) {
- m->cp_hqd_active = 1;
- q->is_active = true;
- }
+ q->queue_percent > 0);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index 73cbfe1..4ea854f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -163,12 +163,9 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd,
2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
}
- q->is_active = false;
- if (q->queue_size > 0 &&
+ q->is_active = (q->queue_size > 0 &&
q->queue_address != 0 &&
- q->queue_percent > 0) {
- q->is_active = true;
- }
+ q->queue_percent > 0);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 1d31260..16da8ad 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -140,8 +140,6 @@ static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer,
struct qcm_process_device *qpd)
{
struct pm4_mes_map_process *packet;
- struct queue *cur;
- uint32_t num_queues;
packet = (struct pm4_mes_map_process *)buffer;
@@ -156,10 +154,7 @@ static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer,
packet->bitfields10.gds_size = qpd->gds_size;
packet->bitfields10.num_gws = qpd->num_gws;
packet->bitfields10.num_oac = qpd->num_oac;
- num_queues = 0;
- list_for_each_entry(cur, &qpd->queues_list, list)
- num_queues++;
- packet->bitfields10.num_queues = (qpd->is_debug) ? 0 : num_queues;
+ packet->bitfields10.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
packet->sh_mem_config = qpd->sh_mem_config;
packet->sh_mem_bases = qpd->sh_mem_bases;
@@ -208,7 +203,7 @@ static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer,
queue_type__mes_map_queues__debug_interface_queue_vi;
break;
case KFD_QUEUE_TYPE_SDMA:
- packet->bitfields2.engine_sel =
+ packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
engine_sel__mes_map_queues__sdma0_vi;
use_static = false; /* no static queues under SDMA */
break;
@@ -376,7 +371,7 @@ int pm_send_set_resources(struct packet_manager *pm,
packet->bitfields2.queue_type =
queue_type__mes_set_resources__hsa_interface_queue_hiq;
packet->bitfields2.vmid_mask = res->vmid_mask;
- packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY;
+ packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
packet->bitfields7.oac_mask = res->oac_mask;
packet->bitfields8.gds_heap_base = res->gds_heap_base;
packet->bitfields8.gds_heap_size = res->gds_heap_size;
@@ -476,7 +471,7 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
}
int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
- enum kfd_preempt_type_filter mode,
+ enum kfd_unmap_queues_filter filter,
uint32_t filter_param, bool reset,
unsigned int sdma_engine)
{
@@ -494,8 +489,8 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
packet = (struct pm4_mes_unmap_queues *)buffer;
memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
- pr_debug("static_queue: unmapping queues: mode is %d , reset is %d , type is %d\n",
- mode, reset, type);
+ pr_debug("static_queue: unmapping queues: filter is %d , reset is %d , type is %d\n",
+ filter, reset, type);
packet->header.u32All = build_pm4_header(IT_UNMAP_QUEUES,
sizeof(struct pm4_mes_unmap_queues));
switch (type) {
@@ -521,29 +516,29 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
packet->bitfields2.action =
action__mes_unmap_queues__preempt_queues;
- switch (mode) {
- case KFD_PREEMPT_TYPE_FILTER_SINGLE_QUEUE:
+ switch (filter) {
+ case KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE:
packet->bitfields2.queue_sel =
queue_sel__mes_unmap_queues__perform_request_on_specified_queues;
packet->bitfields2.num_queues = 1;
packet->bitfields3b.doorbell_offset0 = filter_param;
break;
- case KFD_PREEMPT_TYPE_FILTER_BY_PASID:
+ case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
packet->bitfields2.queue_sel =
queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
packet->bitfields3a.pasid = filter_param;
break;
- case KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES:
+ case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
packet->bitfields2.queue_sel =
queue_sel__mes_unmap_queues__unmap_all_queues;
break;
- case KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES:
+ case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
/* in this case, we do not preempt static queues */
packet->bitfields2.queue_sel =
queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
break;
default:
- WARN(1, "filter %d", mode);
+ WARN(1, "filter %d", filter);
retval = -EINVAL;
goto err_invalid;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
index 1e06de0..d6a7961 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
@@ -20,78 +20,64 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <linux/slab.h>
#include <linux/types.h>
#include "kfd_priv.h"
-static unsigned long *pasid_bitmap;
-static unsigned int pasid_limit;
-static DEFINE_MUTEX(pasid_mutex);
-
-int kfd_pasid_init(void)
-{
- pasid_limit = KFD_MAX_NUM_OF_PROCESSES;
-
- pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long),
- GFP_KERNEL);
- if (!pasid_bitmap)
- return -ENOMEM;
-
- set_bit(0, pasid_bitmap); /* PASID 0 is reserved. */
-
- return 0;
-}
-
-void kfd_pasid_exit(void)
-{
- kfree(pasid_bitmap);
-}
+static unsigned int pasid_bits = 16;
+static const struct kfd2kgd_calls *kfd2kgd;
bool kfd_set_pasid_limit(unsigned int new_limit)
{
- if (new_limit < pasid_limit) {
- bool ok;
+ if (new_limit < 2)
+ return false;
- mutex_lock(&pasid_mutex);
+ if (new_limit < (1U << pasid_bits)) {
+ if (kfd2kgd)
+ /* We've already allocated user PASIDs, too late to
+ * change the limit
+ */
+ return false;
- /* ensure that no pasids >= new_limit are in-use */
- ok = (find_next_bit(pasid_bitmap, pasid_limit, new_limit) ==
- pasid_limit);
- if (ok)
- pasid_limit = new_limit;
-
- mutex_unlock(&pasid_mutex);
-
- return ok;
+ while (new_limit < (1U << pasid_bits))
+ pasid_bits--;
}
return true;
}
-inline unsigned int kfd_get_pasid_limit(void)
+unsigned int kfd_get_pasid_limit(void)
{
- return pasid_limit;
+ return 1U << pasid_bits;
}
unsigned int kfd_pasid_alloc(void)
{
- unsigned int found;
+ int r;
- mutex_lock(&pasid_mutex);
+ /* Find the first best KFD device for calling KGD */
+ if (!kfd2kgd) {
+ struct kfd_dev *dev = NULL;
+ unsigned int i = 0;
- found = find_first_zero_bit(pasid_bitmap, pasid_limit);
- if (found == pasid_limit)
- found = 0;
- else
- set_bit(found, pasid_bitmap);
+ while ((dev = kfd_topology_enum_kfd_devices(i)) != NULL) {
+ if (dev && dev->kfd2kgd) {
+ kfd2kgd = dev->kfd2kgd;
+ break;
+ }
+ i++;
+ }
- mutex_unlock(&pasid_mutex);
+ if (!kfd2kgd)
+ return false;
+ }
- return found;
+ r = kfd2kgd->alloc_pasid(pasid_bits);
+
+ return r > 0 ? r : 0;
}
void kfd_pasid_free(unsigned int pasid)
{
- if (!WARN_ON(pasid == 0 || pasid >= pasid_limit))
- clear_bit(pasid, pasid_bitmap);
+ if (kfd2kgd)
+ kfd2kgd->free_pasid(pasid);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index b87e96c..9e4134c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -31,8 +31,12 @@
#include <linux/workqueue.h>
#include <linux/spinlock.h>
#include <linux/kfd_ioctl.h>
+#include <linux/idr.h>
+#include <linux/kfifo.h>
#include <kgd_kfd_interface.h>
+#include "amd_shared.h"
+
#define KFD_SYSFS_FILE_MODE 0444
#define KFD_MMAP_DOORBELL_MASK 0x8000000000000
@@ -112,11 +116,6 @@ enum cache_policy {
cache_policy_noncoherent
};
-enum asic_family_type {
- CHIP_KAVERI = 0,
- CHIP_CARRIZO
-};
-
struct kfd_event_interrupt_class {
bool (*interrupt_isr)(struct kfd_dev *dev,
const uint32_t *ih_ring_entry);
@@ -125,7 +124,7 @@ struct kfd_event_interrupt_class {
};
struct kfd_device_info {
- unsigned int asic_family;
+ enum amd_asic_type asic_family;
const struct kfd_event_interrupt_class *event_interrupt_class;
unsigned int max_pasid_bits;
unsigned int max_no_of_hqd;
@@ -141,6 +140,12 @@ struct kfd_mem_obj {
uint32_t *cpu_ptr;
};
+struct kfd_vmid_info {
+ uint32_t first_vmid_kfd;
+ uint32_t last_vmid_kfd;
+ uint32_t vmid_num_kfd;
+};
+
struct kfd_dev {
struct kgd_dev *kgd;
@@ -157,14 +162,12 @@ struct kfd_dev {
* to HW doorbell, GFX reserved some
* at the start)
*/
- size_t doorbell_process_limit; /* Number of processes we have doorbell
- * space for.
- */
u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
* page used by kernel queue
*/
struct kgd2kfd_shared_resources shared_resources;
+ struct kfd_vmid_info vm_info;
const struct kfd2kgd_calls *kfd2kgd;
struct mutex doorbell_mutex;
@@ -180,10 +183,8 @@ struct kfd_dev {
unsigned int gtt_sa_num_of_chunks;
/* Interrupts */
- void *interrupt_ring;
- size_t interrupt_ring_size;
- atomic_t interrupt_ring_rptr;
- atomic_t interrupt_ring_wptr;
+ struct kfifo ih_fifo;
+ struct workqueue_struct *ih_wq;
struct work_struct interrupt_work;
spinlock_t interrupt_lock;
@@ -221,22 +222,22 @@ void kfd_chardev_exit(void);
struct device *kfd_chardev(void);
/**
- * enum kfd_preempt_type_filter
+ * enum kfd_unmap_queues_filter
*
- * @KFD_PREEMPT_TYPE_FILTER_SINGLE_QUEUE: Preempts single queue.
+ * @KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE: Preempts single queue.
*
- * @KFD_PRERMPT_TYPE_FILTER_ALL_QUEUES: Preempts all queues in the
+ * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the
* running queues list.
*
- * @KFD_PRERMPT_TYPE_FILTER_BY_PASID: Preempts queues that belongs to
+ * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to
* specific process.
*
*/
-enum kfd_preempt_type_filter {
- KFD_PREEMPT_TYPE_FILTER_SINGLE_QUEUE,
- KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES,
- KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES,
- KFD_PREEMPT_TYPE_FILTER_BY_PASID
+enum kfd_unmap_queues_filter {
+ KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE,
+ KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
+ KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
+ KFD_UNMAP_QUEUES_FILTER_BY_PASID
};
/**
@@ -404,7 +405,6 @@ struct scheduling_resources {
struct process_queue_manager {
/* data */
struct kfd_process *process;
- unsigned int num_concurrent_processes;
struct list_head queues;
unsigned long *queue_slot_bitmap;
};
@@ -420,6 +420,12 @@ struct qcm_process_device {
unsigned int queue_count;
unsigned int vmid;
bool is_debug;
+
+ /* This flag tells if we should reset all wavefronts on
+ * process termination
+ */
+ bool reset_wavefronts;
+
/*
* All the memory management data should be here too
*/
@@ -435,6 +441,13 @@ struct qcm_process_device {
uint32_t sh_hidden_private_base;
};
+
+enum kfd_pdd_bound {
+ PDD_UNBOUND = 0,
+ PDD_BOUND,
+ PDD_BOUND_SUSPENDED,
+};
+
/* Data that is per-process-per device. */
struct kfd_process_device {
/*
@@ -446,6 +459,8 @@ struct kfd_process_device {
/* The device that owns this data. */
struct kfd_dev *dev;
+ /* The process that owns this kfd_process_device. */
+ struct kfd_process *process;
/* per-process-per device QCM data structure */
struct qcm_process_device qpd;
@@ -459,12 +474,14 @@ struct kfd_process_device {
uint64_t scratch_limit;
/* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */
- bool bound;
+ enum kfd_pdd_bound bound;
- /* This flag tells if we should reset all
- * wavefronts on process termination
+ /* Flag used to tell the pdd has dequeued from the dqm.
+ * This is used to prevent dev->dqm->ops.process_termination() from
+ * being called twice when it is already called in IOMMU callback
+ * function.
*/
- bool reset_wavefronts;
+ bool already_dequeued;
};
#define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
@@ -477,7 +494,12 @@ struct kfd_process {
*/
struct hlist_node kfd_processes;
- struct mm_struct *mm;
+ /*
+ * Opaque pointer to mm_struct. We don't hold a reference to
+ * it so it should never be dereferenced from here. This is
+ * only used for looking up processes by their mm.
+ */
+ void *mm;
struct mutex mutex;
@@ -485,6 +507,8 @@ struct kfd_process {
* In any process, the thread that started main() is the lead
* thread and outlives the rest.
* It is here because amd_iommu_bind_pasid wants a task_struct.
+ * It can also be used for safely getting a reference to the
+ * mm_struct of the process.
*/
struct task_struct *lead_thread;
@@ -495,6 +519,7 @@ struct kfd_process {
struct rcu_head rcu;
unsigned int pasid;
+ unsigned int doorbell_index;
/*
* List of kfd_process_device structures,
@@ -504,22 +529,16 @@ struct kfd_process {
struct process_queue_manager pqm;
- /* The process's queues. */
- size_t queue_array_size;
-
- /* Size is queue_array_size, up to MAX_PROCESS_QUEUES. */
- struct kfd_queue **queues;
-
/*Is the user space process 32 bit?*/
bool is_32bit_user_mode;
/* Event-related data */
struct mutex event_mutex;
- /* All events in process hashed by ID, linked on kfd_event.events. */
- DECLARE_HASHTABLE(events, 4);
- /* struct slot_page_header.event_pages */
- struct list_head signal_event_pages;
- u32 next_nonsignal_event_id;
+ /* Event ID allocator and lookup */
+ struct idr event_idr;
+ /* Event page */
+ struct kfd_signal_page *signal_page;
+ size_t signal_mapped_size;
size_t signal_event_count;
bool signal_event_limit_reached;
};
@@ -549,8 +568,10 @@ struct kfd_process *kfd_get_process(const struct task_struct *);
struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid);
struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev,
- struct kfd_process *p);
-void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid);
+ struct kfd_process *p);
+int kfd_bind_processes_to_device(struct kfd_dev *dev);
+void kfd_unbind_processes_from_device(struct kfd_dev *dev);
+void kfd_process_iommu_unbind_callback(struct kfd_dev *dev, unsigned int pasid);
struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev,
struct kfd_process *p);
struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev,
@@ -584,6 +605,10 @@ void write_kernel_doorbell(u32 __iomem *db, u32 value);
unsigned int kfd_queue_id_to_doorbell(struct kfd_dev *kfd,
struct kfd_process *process,
unsigned int queue_id);
+phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
+ struct kfd_process *process);
+int kfd_alloc_process_doorbells(struct kfd_process *process);
+void kfd_free_process_doorbells(struct kfd_process *process);
/* GTT Sub-Allocator */
@@ -644,14 +669,14 @@ struct process_queue_node {
struct list_head process_queue_list;
};
+void kfd_process_dequeue_from_device(struct kfd_process_device *pdd);
+void kfd_process_dequeue_from_all_devices(struct kfd_process *p);
int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p);
void pqm_uninit(struct process_queue_manager *pqm);
int pqm_create_queue(struct process_queue_manager *pqm,
struct kfd_dev *dev,
struct file *f,
struct queue_properties *properties,
- unsigned int flags,
- enum kfd_queue_type type,
unsigned int *qid);
int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid,
@@ -661,15 +686,12 @@ struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm,
int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
unsigned int fence_value,
- unsigned long timeout);
+ unsigned int timeout_ms);
/* Packet Manager */
-#define KFD_HIQ_TIMEOUT (500)
-
#define KFD_FENCE_COMPLETED (100)
#define KFD_FENCE_INIT (10)
-#define KFD_UNMAP_LATENCY (150)
struct packet_manager {
struct device_queue_manager *dqm;
@@ -688,33 +710,25 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
uint32_t fence_value);
int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
- enum kfd_preempt_type_filter mode,
+ enum kfd_unmap_queues_filter mode,
uint32_t filter_param, bool reset,
unsigned int sdma_engine);
void pm_release_ib(struct packet_manager *pm);
uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
-phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
- struct kfd_process *process);
/* Events */
extern const struct kfd_event_interrupt_class event_interrupt_class_cik;
extern const struct kfd_device_global_init_class device_global_init_class_cik;
-enum kfd_event_wait_result {
- KFD_WAIT_COMPLETE,
- KFD_WAIT_TIMEOUT,
- KFD_WAIT_ERROR
-};
-
void kfd_event_init_process(struct kfd_process *p);
void kfd_event_free_process(struct kfd_process *p);
int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma);
int kfd_wait_on_events(struct kfd_process *p,
uint32_t num_events, void __user *data,
bool all, uint32_t user_timeout_ms,
- enum kfd_event_wait_result *wait_result);
+ uint32_t *wait_result);
void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
uint32_t valid_id_bits);
void kfd_signal_iommu_event(struct kfd_dev *dev,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index c74cf22..1f5ccd28 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -35,13 +35,6 @@ struct mm_struct;
#include "kfd_dbgmgr.h"
/*
- * Initial size for the array of queues.
- * The allocated size is doubled each time
- * it is exceeded up to MAX_PROCESS_QUEUES.
- */
-#define INITIAL_QUEUE_ARRAY_SIZE 16
-
-/*
* List of struct kfd_process (field kfd_process).
* Unique/indexed by mm_struct*
*/
@@ -171,25 +164,22 @@ static void kfd_process_wq_release(struct work_struct *work)
pr_debug("Releasing pdd (topology id %d) for process (pasid %d) in workqueue\n",
pdd->dev->id, p->pasid);
- if (pdd->reset_wavefronts)
- dbgdev_wave_reset_wavefronts(pdd->dev, p);
+ if (pdd->bound == PDD_BOUND)
+ amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid);
- amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid);
list_del(&pdd->per_device_list);
-
kfree(pdd);
}
kfd_event_free_process(p);
kfd_pasid_free(p->pasid);
+ kfd_free_process_doorbells(p);
mutex_unlock(&p->mutex);
mutex_destroy(&p->mutex);
- kfree(p->queues);
-
kfree(p);
kfree(work);
@@ -201,7 +191,6 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu)
struct kfd_process *p;
p = container_of(rcu, struct kfd_process, rcu);
- WARN_ON(atomic_read(&p->mm->mm_count) <= 0);
mmdrop(p->mm);
@@ -235,24 +224,26 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn,
mutex_lock(&p->mutex);
- /* In case our notifier is called before IOMMU notifier */
- pqm_uninit(&p->pqm);
-
- /* Iterate over all process device data structure and check
- * if we should delete debug managers and reset all wavefronts
+ /* Iterate over all process device data structures and if the
+ * pdd is in debug mode, we should first force unregistration,
+ * then we will be able to destroy the queues
*/
list_for_each_entry(pdd, &p->per_device_data, per_device_list) {
- if ((pdd->dev->dbgmgr) &&
- (pdd->dev->dbgmgr->pasid == p->pasid))
- kfd_dbgmgr_destroy(pdd->dev->dbgmgr);
+ struct kfd_dev *dev = pdd->dev;
- if (pdd->reset_wavefronts) {
- pr_warn("Resetting all wave fronts\n");
- dbgdev_wave_reset_wavefronts(pdd->dev, p);
- pdd->reset_wavefronts = false;
+ mutex_lock(kfd_get_dbgmgr_mutex());
+ if (dev && dev->dbgmgr && dev->dbgmgr->pasid == p->pasid) {
+ if (!kfd_dbgmgr_unregister(dev->dbgmgr, p)) {
+ kfd_dbgmgr_destroy(dev->dbgmgr);
+ dev->dbgmgr = NULL;
+ }
}
+ mutex_unlock(kfd_get_dbgmgr_mutex());
}
+ kfd_process_dequeue_from_all_devices(p);
+ pqm_uninit(&p->pqm);
+
mutex_unlock(&p->mutex);
/*
@@ -279,15 +270,13 @@ static struct kfd_process *create_process(const struct task_struct *thread)
if (!process)
goto err_alloc_process;
- process->queues = kmalloc_array(INITIAL_QUEUE_ARRAY_SIZE,
- sizeof(process->queues[0]), GFP_KERNEL);
- if (!process->queues)
- goto err_alloc_queues;
-
process->pasid = kfd_pasid_alloc();
if (process->pasid == 0)
goto err_alloc_pasid;
+ if (kfd_alloc_process_doorbells(process) < 0)
+ goto err_alloc_doorbells;
+
mutex_init(&process->mutex);
process->mm = thread->mm;
@@ -303,8 +292,6 @@ static struct kfd_process *create_process(const struct task_struct *thread)
process->lead_thread = thread->group_leader;
- process->queue_array_size = INITIAL_QUEUE_ARRAY_SIZE;
-
INIT_LIST_HEAD(&process->per_device_data);
kfd_event_init_process(process);
@@ -329,10 +316,10 @@ static struct kfd_process *create_process(const struct task_struct *thread)
mmu_notifier_unregister_no_release(&process->mmu_notifier, process->mm);
err_mmu_notifier:
mutex_destroy(&process->mutex);
+ kfd_free_process_doorbells(process);
+err_alloc_doorbells:
kfd_pasid_free(process->pasid);
err_alloc_pasid:
- kfree(process->queues);
-err_alloc_queues:
kfree(process);
err_alloc_process:
return ERR_PTR(err);
@@ -345,9 +332,9 @@ struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev,
list_for_each_entry(pdd, &p->per_device_data, per_device_list)
if (pdd->dev == dev)
- break;
+ return pdd;
- return pdd;
+ return NULL;
}
struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev,
@@ -361,7 +348,9 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev,
INIT_LIST_HEAD(&pdd->qpd.queues_list);
INIT_LIST_HEAD(&pdd->qpd.priv_queue_list);
pdd->qpd.dqm = dev->dqm;
- pdd->reset_wavefronts = false;
+ pdd->process = p;
+ pdd->bound = PDD_UNBOUND;
+ pdd->already_dequeued = false;
list_add(&pdd->per_device_list, &p->per_device_data);
}
@@ -387,19 +376,87 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev,
return ERR_PTR(-ENOMEM);
}
- if (pdd->bound)
+ if (pdd->bound == PDD_BOUND) {
return pdd;
+ } else if (unlikely(pdd->bound == PDD_BOUND_SUSPENDED)) {
+ pr_err("Binding PDD_BOUND_SUSPENDED pdd is unexpected!\n");
+ return ERR_PTR(-EINVAL);
+ }
err = amd_iommu_bind_pasid(dev->pdev, p->pasid, p->lead_thread);
if (err < 0)
return ERR_PTR(err);
- pdd->bound = true;
+ pdd->bound = PDD_BOUND;
return pdd;
}
-void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
+/*
+ * Bind processes do the device that have been temporarily unbound
+ * (PDD_BOUND_SUSPENDED) in kfd_unbind_processes_from_device.
+ */
+int kfd_bind_processes_to_device(struct kfd_dev *dev)
+{
+ struct kfd_process_device *pdd;
+ struct kfd_process *p;
+ unsigned int temp;
+ int err = 0;
+
+ int idx = srcu_read_lock(&kfd_processes_srcu);
+
+ hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
+ mutex_lock(&p->mutex);
+ pdd = kfd_get_process_device_data(dev, p);
+ if (pdd->bound != PDD_BOUND_SUSPENDED) {
+ mutex_unlock(&p->mutex);
+ continue;
+ }
+
+ err = amd_iommu_bind_pasid(dev->pdev, p->pasid,
+ p->lead_thread);
+ if (err < 0) {
+ pr_err("Unexpected pasid %d binding failure\n",
+ p->pasid);
+ mutex_unlock(&p->mutex);
+ break;
+ }
+
+ pdd->bound = PDD_BOUND;
+ mutex_unlock(&p->mutex);
+ }
+
+ srcu_read_unlock(&kfd_processes_srcu, idx);
+
+ return err;
+}
+
+/*
+ * Mark currently bound processes as PDD_BOUND_SUSPENDED. These
+ * processes will be restored to PDD_BOUND state in
+ * kfd_bind_processes_to_device.
+ */
+void kfd_unbind_processes_from_device(struct kfd_dev *dev)
+{
+ struct kfd_process_device *pdd;
+ struct kfd_process *p;
+ unsigned int temp;
+
+ int idx = srcu_read_lock(&kfd_processes_srcu);
+
+ hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
+ mutex_lock(&p->mutex);
+ pdd = kfd_get_process_device_data(dev, p);
+
+ if (pdd->bound == PDD_BOUND)
+ pdd->bound = PDD_BOUND_SUSPENDED;
+ mutex_unlock(&p->mutex);
+ }
+
+ srcu_read_unlock(&kfd_processes_srcu, idx);
+}
+
+void kfd_process_iommu_unbind_callback(struct kfd_dev *dev, unsigned int pasid)
{
struct kfd_process *p;
struct kfd_process_device *pdd;
@@ -415,31 +472,23 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
pr_debug("Unbinding process %d from IOMMU\n", pasid);
- if ((dev->dbgmgr) && (dev->dbgmgr->pasid == p->pasid))
- kfd_dbgmgr_destroy(dev->dbgmgr);
+ mutex_lock(kfd_get_dbgmgr_mutex());
- pqm_uninit(&p->pqm);
+ if (dev->dbgmgr && dev->dbgmgr->pasid == p->pasid) {
+ if (!kfd_dbgmgr_unregister(dev->dbgmgr, p)) {
+ kfd_dbgmgr_destroy(dev->dbgmgr);
+ dev->dbgmgr = NULL;
+ }
+ }
+
+ mutex_unlock(kfd_get_dbgmgr_mutex());
pdd = kfd_get_process_device_data(dev, p);
-
- if (!pdd) {
- mutex_unlock(&p->mutex);
- return;
- }
-
- if (pdd->reset_wavefronts) {
- dbgdev_wave_reset_wavefronts(pdd->dev, p);
- pdd->reset_wavefronts = false;
- }
-
- /*
- * Just mark pdd as unbound, because we still need it
- * to call amd_iommu_unbind_pasid() in when the
- * process exits.
- * We don't call amd_iommu_unbind_pasid() here
- * because the IOMMU called us.
- */
- pdd->bound = false;
+ if (pdd)
+ /* For GPU relying on IOMMU, we need to dequeue here
+ * when PASID is still bound.
+ */
+ kfd_process_dequeue_from_device(pdd);
mutex_unlock(&p->mutex);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 03bec76..2bec902 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -63,6 +63,25 @@ static int find_available_queue_slot(struct process_queue_manager *pqm,
return 0;
}
+void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)
+{
+ struct kfd_dev *dev = pdd->dev;
+
+ if (pdd->already_dequeued)
+ return;
+
+ dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd);
+ pdd->already_dequeued = true;
+}
+
+void kfd_process_dequeue_from_all_devices(struct kfd_process *p)
+{
+ struct kfd_process_device *pdd;
+
+ list_for_each_entry(pdd, &p->per_device_data, per_device_list)
+ kfd_process_dequeue_from_device(pdd);
+}
+
int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p)
{
INIT_LIST_HEAD(&pqm->queues);
@@ -78,21 +97,14 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p)
void pqm_uninit(struct process_queue_manager *pqm)
{
- int retval;
struct process_queue_node *pqn, *next;
list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
- retval = pqm_destroy_queue(
- pqm,
- (pqn->q != NULL) ?
- pqn->q->properties.queue_id :
- pqn->kq->queue->properties.queue_id);
-
- if (retval != 0) {
- pr_err("failed to destroy queue\n");
- return;
- }
+ uninit_queue(pqn->q);
+ list_del(&pqn->process_queue_list);
+ kfree(pqn);
}
+
kfree(pqm->queue_slot_bitmap);
pqm->queue_slot_bitmap = NULL;
}
@@ -130,20 +142,16 @@ int pqm_create_queue(struct process_queue_manager *pqm,
struct kfd_dev *dev,
struct file *f,
struct queue_properties *properties,
- unsigned int flags,
- enum kfd_queue_type type,
unsigned int *qid)
{
int retval;
struct kfd_process_device *pdd;
- struct queue_properties q_properties;
struct queue *q;
struct process_queue_node *pqn;
struct kernel_queue *kq;
- int num_queues = 0;
- struct queue *cur;
+ enum kfd_queue_type type = properties->type;
+ unsigned int max_queues = 127; /* HWS limit */
- memcpy(&q_properties, properties, sizeof(struct queue_properties));
q = NULL;
kq = NULL;
@@ -159,19 +167,18 @@ int pqm_create_queue(struct process_queue_manager *pqm,
* If we are just about to create DIQ, the is_debug flag is not set yet
* Hence we also check the type as well
*/
- if ((pdd->qpd.is_debug) ||
- (type == KFD_QUEUE_TYPE_DIQ)) {
- list_for_each_entry(cur, &pdd->qpd.queues_list, list)
- num_queues++;
- if (num_queues >= dev->device_info->max_no_of_hqd/2)
- return -ENOSPC;
- }
+ if ((pdd->qpd.is_debug) || (type == KFD_QUEUE_TYPE_DIQ))
+ max_queues = dev->device_info->max_no_of_hqd/2;
+
+ if (pdd->qpd.queue_count >= max_queues)
+ return -ENOSPC;
retval = find_available_queue_slot(pqm, qid);
if (retval != 0)
return retval;
- if (list_empty(&pqm->queues)) {
+ if (list_empty(&pdd->qpd.queues_list) &&
+ list_empty(&pdd->qpd.priv_queue_list)) {
pdd->qpd.pqm = pqm;
dev->dqm->ops.register_process(dev->dqm, &pdd->qpd);
}
@@ -187,14 +194,14 @@ int pqm_create_queue(struct process_queue_manager *pqm,
case KFD_QUEUE_TYPE_COMPUTE:
/* check if there is over subscription */
if ((sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
- ((dev->dqm->processes_count >= VMID_PER_DEVICE) ||
+ ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||
(dev->dqm->queue_count >= get_queues_num(dev->dqm)))) {
pr_err("Over-subscription is not allowed in radeon_kfd.sched_policy == 1\n");
retval = -EPERM;
goto err_create_queue;
}
- retval = create_cp_queue(pqm, dev, &q, &q_properties, f, *qid);
+ retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
if (retval != 0)
goto err_create_queue;
pqn->q = q;
@@ -231,9 +238,8 @@ int pqm_create_queue(struct process_queue_manager *pqm,
list_add(&pqn->process_queue_list, &pqm->queues);
if (q) {
- *properties = q->properties;
pr_debug("PQM done creating queue\n");
- print_queue_properties(properties);
+ print_queue_properties(&q->properties);
}
return retval;
@@ -243,7 +249,8 @@ int pqm_create_queue(struct process_queue_manager *pqm,
err_allocate_pqn:
/* check if queues list is empty unregister process from device */
clear_bit(*qid, pqm->queue_slot_bitmap);
- if (list_empty(&pqm->queues))
+ if (list_empty(&pdd->qpd.queues_list) &&
+ list_empty(&pdd->qpd.priv_queue_list))
dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd);
return retval;
}
@@ -290,9 +297,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
if (pqn->q) {
dqm = pqn->q->device->dqm;
retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
- if (retval != 0)
- return retval;
-
uninit_queue(pqn->q);
}
@@ -300,7 +304,8 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
kfree(pqn);
clear_bit(qid, pqm->queue_slot_bitmap);
- if (list_empty(&pqm->queues))
+ if (list_empty(&pdd->qpd.queues_list) &&
+ list_empty(&pdd->qpd.priv_queue_list))
dqm->ops.unregister_process(dqm, &pdd->qpd);
return retval;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 3a49fbd..b72f8a4 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -25,6 +25,8 @@
#include <drm/amd_asic_type.h>
+struct seq_file;
+
#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
/*
@@ -119,6 +121,12 @@ enum amd_fan_ctrl_mode {
AMD_FAN_CTRL_AUTO = 2,
};
+enum pp_clock_type {
+ PP_SCLK,
+ PP_MCLK,
+ PP_PCIE,
+};
+
/* CG flags */
#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
@@ -224,4 +232,96 @@ struct amd_ip_funcs {
void (*get_clockgating_state)(void *handle, u32 *flags);
};
+
+enum amd_pp_task;
+enum amd_pp_clock_type;
+struct pp_states_info;
+struct amd_pp_simple_clock_info;
+struct amd_pp_display_configuration;
+struct amd_pp_clock_info;
+struct pp_display_clock_request;
+struct pp_wm_sets_with_clock_ranges_soc15;
+struct pp_clock_levels_with_voltage;
+struct pp_clock_levels_with_latency;
+struct amd_pp_clocks;
+
+struct amd_pm_funcs {
+/* export for dpm on ci and si */
+ int (*pre_set_power_state)(void *handle);
+ int (*set_power_state)(void *handle);
+ void (*post_set_power_state)(void *handle);
+ void (*display_configuration_changed)(void *handle);
+ void (*print_power_state)(void *handle, void *ps);
+ bool (*vblank_too_short)(void *handle);
+ void (*enable_bapm)(void *handle, bool enable);
+ int (*check_state_equal)(void *handle,
+ void *cps,
+ void *rps,
+ bool *equal);
+/* export for sysfs */
+ int (*get_temperature)(void *handle);
+ void (*set_fan_control_mode)(void *handle, u32 mode);
+ u32 (*get_fan_control_mode)(void *handle);
+ int (*set_fan_speed_percent)(void *handle, u32 speed);
+ int (*get_fan_speed_percent)(void *handle, u32 *speed);
+ int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
+ int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
+ int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
+ int (*get_sclk_od)(void *handle);
+ int (*set_sclk_od)(void *handle, uint32_t value);
+ int (*get_mclk_od)(void *handle);
+ int (*set_mclk_od)(void *handle, uint32_t value);
+ int (*read_sensor)(void *handle, int idx, void *value, int *size);
+ enum amd_dpm_forced_level (*get_performance_level)(void *handle);
+ enum amd_pm_state_type (*get_current_power_state)(void *handle);
+ int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
+ int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
+ int (*get_pp_table)(void *handle, char **table);
+ int (*set_pp_table)(void *handle, const char *buf, size_t size);
+ void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
+
+ int (*reset_power_profile_state)(void *handle,
+ struct amd_pp_profile *request);
+ int (*get_power_profile_state)(void *handle,
+ struct amd_pp_profile *query);
+ int (*set_power_profile_state)(void *handle,
+ struct amd_pp_profile *request);
+ int (*switch_power_profile)(void *handle,
+ enum amd_pp_profile_type type);
+/* export to amdgpu */
+ void (*powergate_uvd)(void *handle, bool gate);
+ void (*powergate_vce)(void *handle, bool gate);
+ struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx);
+ int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
+ void *input, void *output);
+ int (*load_firmware)(void *handle);
+ int (*wait_for_fw_loading_complete)(void *handle);
+ int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
+/* export to DC */
+ u32 (*get_sclk)(void *handle, bool low);
+ u32 (*get_mclk)(void *handle, bool low);
+ int (*display_configuration_change)(void *handle,
+ const struct amd_pp_display_configuration *input);
+ int (*get_display_power_level)(void *handle,
+ struct amd_pp_simple_clock_info *output);
+ int (*get_current_clocks)(void *handle,
+ struct amd_pp_clock_info *clocks);
+ int (*get_clock_by_type)(void *handle,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks);
+ int (*get_clock_by_type_with_latency)(void *handle,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_latency *clocks);
+ int (*get_clock_by_type_with_voltage)(void *handle,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks);
+ int (*set_watermarks_for_clocks_ranges)(void *handle,
+ struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
+ int (*display_clock_voltage_request)(void *handle,
+ struct pp_display_clock_request *clock);
+ int (*get_display_mode_validation_clocks)(void *handle,
+ struct amd_pp_simple_clock_info *clocks);
+};
+
+
#endif /* __AMD_SHARED_H__ */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
index 34c6ff5..6af9f02 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
@@ -5454,5 +5454,7 @@
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
+#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en_MASK 0x1
+#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en__SHIFT 0
#endif /* SMU_7_0_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
index 378f4b6..3442372 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
@@ -36,6 +36,16 @@
#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
#define mmUVD_POWER_STATUS_U 0x3bfd
#define mmUVD_NO_OP 0x3bff
+#define mmUVD_RB_BASE_LO2 0x3c21
+#define mmUVD_RB_BASE_HI2 0x3c22
+#define mmUVD_RB_SIZE2 0x3c23
+#define mmUVD_RB_RPTR2 0x3c24
+#define mmUVD_RB_WPTR2 0x3c25
+#define mmUVD_RB_BASE_LO 0x3c26
+#define mmUVD_RB_BASE_HI 0x3c27
+#define mmUVD_RB_SIZE 0x3c28
+#define mmUVD_RB_RPTR 0x3c29
+#define mmUVD_RB_WPTR 0x3c2a
#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69
#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67
@@ -43,6 +53,11 @@
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e
#define mmUVD_SEMA_CNTL 0x3d00
+#define mmUVD_RB_WPTR3 0x3d1c
+#define mmUVD_RB_RPTR3 0x3d1b
+#define mmUVD_RB_BASE_LO3 0x3d1d
+#define mmUVD_RB_BASE_HI3 0x3d1e
+#define mmUVD_RB_SIZE3 0x3d1f
#define mmUVD_LMI_EXT40_ADDR 0x3d26
#define mmUVD_CTX_INDEX 0x3d28
#define mmUVD_CTX_DATA 0x3d29
diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index 181a2c3..f696bbb 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -4292,6 +4292,7 @@ typedef struct _ATOM_DPCD_INFO
#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
+#define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2
/***********************************************************************************/
// Structure used in VRAM_UsageByFirmwareTable
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 837296db..7c92f47 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1017,6 +1017,19 @@ struct atom_14nm_combphy_tmds_vs_set
uint8_t margin_deemph_lane0__deemph_sel_val;
};
+struct atom_i2c_reg_info {
+ uint8_t ucI2cRegIndex;
+ uint8_t ucI2cRegVal;
+};
+
+struct atom_hdmi_retimer_redriver_set {
+ uint8_t HdmiSlvAddr;
+ uint8_t HdmiRegNum;
+ uint8_t Hdmi6GRegNum;
+ struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
+ struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
+};
+
struct atom_integrated_system_info_v1_11
{
struct atom_common_table_header table_header;
@@ -1052,7 +1065,11 @@ struct atom_integrated_system_info_v1_11
struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
struct atom_camera_data camera_info;
- uint32_t reserved[138];
+ struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
+ struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
+ struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
+ struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
+ uint32_t reserved[108];
};
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index 0214f63..675988d 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -100,6 +100,7 @@ enum cgs_system_info_id {
CGS_SYSTEM_INFO_GFX_SE_INFO,
CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
+ CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
CGS_SYSTEM_INFO_ID_MAXIMUM,
};
@@ -193,8 +194,6 @@ struct cgs_acpi_method_info {
* @type: memory type
* @size: size in bytes
* @align: alignment in bytes
- * @min_offset: minimum offset from start of heap
- * @max_offset: maximum offset from start of heap
* @handle: memory handle (output)
*
* The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
@@ -216,7 +215,6 @@ struct cgs_acpi_method_info {
*/
typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
uint64_t size, uint64_t align,
- uint64_t min_offset, uint64_t max_offset,
cgs_handle_t *handle);
/**
@@ -310,6 +308,22 @@ typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum
typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
unsigned index, uint32_t value);
+#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
+#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
+
+#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \
+ (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \
+ (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
+
+#define CGS_REG_GET_FIELD(value, reg, field) \
+ (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
+
+#define CGS_WREG32_FIELD(device, reg, field, val) \
+ cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
+
+#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
+ cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
+
/**
* cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
* @cgs_device: opaque device handle
@@ -409,6 +423,10 @@ typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
+struct amd_pp_init;
+typedef void* (*cgs_register_pp_handle)(struct cgs_device *cgs_device,
+ int (*call_back_func)(struct amd_pp_init *, void **));
+
struct cgs_ops {
/* memory management calls (similar to KFD interface) */
cgs_alloc_gpu_mem_t alloc_gpu_mem;
@@ -445,6 +463,7 @@ struct cgs_ops {
cgs_is_virtualization_enabled_t is_virtualization_enabled;
cgs_enter_safe_mode enter_safe_mode;
cgs_lock_grbm_idx lock_grbm_idx;
+ cgs_register_pp_handle register_pp_handle;
};
struct cgs_os_ops; /* To be define in OS-specific CGS header */
@@ -463,8 +482,8 @@ struct cgs_device
#define CGS_OS_CALL(func,dev,...) \
(((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
-#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
- CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
+#define cgs_alloc_gpu_mem(dev,type,size,align,handle) \
+ CGS_CALL(alloc_gpu_mem,dev,type,size,align,handle)
#define cgs_free_gpu_mem(dev,handle) \
CGS_CALL(free_gpu_mem,dev,handle)
#define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
@@ -523,4 +542,7 @@ struct cgs_device
#define cgs_lock_grbm_idx(cgs_device, lock) \
CGS_CALL(lock_grbm_idx, cgs_device, lock)
+#define cgs_register_pp_handle(cgs_device, call_back_func) \
+ CGS_CALL(register_pp_handle, cgs_device, call_back_func)
+
#endif /* _CGS_COMMON_H */
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 94277cb..f516fd1 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -112,6 +112,9 @@ struct tile_config {
*
* @get_max_engine_clock_in_mhz: Retrieves maximum GPU clock in MHz
*
+ * @alloc_pasid: Allocate a PASID
+ * @free_pasid: Free a PASID
+ *
* @program_sh_mem_settings: A function that should initiate the memory
* properties such as main aperture memory type (cache / non cached) and
* secondary aperture base address, size and memory type.
@@ -160,6 +163,9 @@ struct kfd2kgd_calls {
uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd);
+ int (*alloc_pasid)(unsigned int bits);
+ void (*free_pasid)(unsigned int pasid);
+
/* Register access functions */
void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
diff --git a/drivers/gpu/drm/amd/include/linux/chash.h b/drivers/gpu/drm/amd/include/linux/chash.h
new file mode 100644
index 0000000..6dc1599
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/linux/chash.h
@@ -0,0 +1,366 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _LINUX_CHASH_H
+#define _LINUX_CHASH_H
+
+#include <linux/types.h>
+#include <linux/hash.h>
+#include <linux/bug.h>
+#include <asm/bitsperlong.h>
+
+#if BITS_PER_LONG == 32
+# define _CHASH_LONG_SHIFT 5
+#elif BITS_PER_LONG == 64
+# define _CHASH_LONG_SHIFT 6
+#else
+# error "Unexpected BITS_PER_LONG"
+#endif
+
+struct __chash_table {
+ u8 bits;
+ u8 key_size;
+ unsigned int value_size;
+ u32 size_mask;
+ unsigned long *occup_bitmap, *valid_bitmap;
+ union {
+ u32 *keys32;
+ u64 *keys64;
+ };
+ u8 *values;
+
+#ifdef CONFIG_CHASH_STATS
+ u64 hits, hits_steps, hits_time_ns;
+ u64 miss, miss_steps, miss_time_ns;
+ u64 relocs, reloc_dist;
+#endif
+};
+
+#define __CHASH_BITMAP_SIZE(bits) \
+ (((1 << (bits)) + BITS_PER_LONG - 1) / BITS_PER_LONG)
+#define __CHASH_ARRAY_SIZE(bits, size) \
+ ((((size) << (bits)) + sizeof(long) - 1) / sizeof(long))
+
+#define __CHASH_DATA_SIZE(bits, key_size, value_size) \
+ (__CHASH_BITMAP_SIZE(bits) * 2 + \
+ __CHASH_ARRAY_SIZE(bits, key_size) + \
+ __CHASH_ARRAY_SIZE(bits, value_size))
+
+#define STRUCT_CHASH_TABLE(bits, key_size, value_size) \
+ struct { \
+ struct __chash_table table; \
+ unsigned long data \
+ [__CHASH_DATA_SIZE(bits, key_size, value_size)];\
+ }
+
+/**
+ * struct chash_table - Dynamically allocated closed hash table
+ *
+ * Use this struct for dynamically allocated hash tables (using
+ * chash_table_alloc and chash_table_free), where the size is
+ * determined at runtime.
+ */
+struct chash_table {
+ struct __chash_table table;
+ unsigned long *data;
+};
+
+/**
+ * DECLARE_CHASH_TABLE - macro to declare a closed hash table
+ * @table: name of the declared hash table
+ * @bts: Table size will be 2^bits entries
+ * @key_sz: Size of hash keys in bytes, 4 or 8
+ * @val_sz: Size of data values in bytes, can be 0
+ *
+ * This declares the hash table variable with a static size.
+ *
+ * The closed hash table stores key-value pairs with low memory and
+ * lookup overhead. In operation it performs no dynamic memory
+ * management. The data being stored does not require any
+ * list_heads. The hash table performs best with small @val_sz and as
+ * long as some space (about 50%) is left free in the table. But the
+ * table can still work reasonably efficiently even when filled up to
+ * about 90%. If bigger data items need to be stored and looked up,
+ * store the pointer to it as value in the hash table.
+ *
+ * @val_sz may be 0. This can be useful when all the stored
+ * information is contained in the key itself and the fact that it is
+ * in the hash table (or not).
+ */
+#define DECLARE_CHASH_TABLE(table, bts, key_sz, val_sz) \
+ STRUCT_CHASH_TABLE(bts, key_sz, val_sz) table
+
+#ifdef CONFIG_CHASH_STATS
+#define __CHASH_STATS_INIT(prefix), \
+ prefix.hits = 0, \
+ prefix.hits_steps = 0, \
+ prefix.hits_time_ns = 0, \
+ prefix.miss = 0, \
+ prefix.miss_steps = 0, \
+ prefix.miss_time_ns = 0, \
+ prefix.relocs = 0, \
+ prefix.reloc_dist = 0
+#else
+#define __CHASH_STATS_INIT(prefix)
+#endif
+
+#define __CHASH_TABLE_INIT(prefix, data, bts, key_sz, val_sz) \
+ prefix.bits = (bts), \
+ prefix.key_size = (key_sz), \
+ prefix.value_size = (val_sz), \
+ prefix.size_mask = ((1 << bts) - 1), \
+ prefix.occup_bitmap = &data[0], \
+ prefix.valid_bitmap = &data \
+ [__CHASH_BITMAP_SIZE(bts)], \
+ prefix.keys64 = (u64 *)&data \
+ [__CHASH_BITMAP_SIZE(bts) * 2], \
+ prefix.values = (u8 *)&data \
+ [__CHASH_BITMAP_SIZE(bts) * 2 + \
+ __CHASH_ARRAY_SIZE(bts, key_sz)] \
+ __CHASH_STATS_INIT(prefix)
+
+/**
+ * DEFINE_CHASH_TABLE - macro to define and initialize a closed hash table
+ * @tbl: name of the declared hash table
+ * @bts: Table size will be 2^bits entries
+ * @key_sz: Size of hash keys in bytes, 4 or 8
+ * @val_sz: Size of data values in bytes, can be 0
+ *
+ * Note: the macro can be used for global and local hash table variables.
+ */
+#define DEFINE_CHASH_TABLE(tbl, bts, key_sz, val_sz) \
+ DECLARE_CHASH_TABLE(tbl, bts, key_sz, val_sz) = { \
+ .table = { \
+ __CHASH_TABLE_INIT(, (tbl).data, bts, key_sz, val_sz) \
+ }, \
+ .data = {0} \
+ }
+
+/**
+ * INIT_CHASH_TABLE - Initialize a hash table declared by DECLARE_CHASH_TABLE
+ * @tbl: name of the declared hash table
+ * @bts: Table size will be 2^bits entries
+ * @key_sz: Size of hash keys in bytes, 4 or 8
+ * @val_sz: Size of data values in bytes, can be 0
+ */
+#define INIT_CHASH_TABLE(tbl, bts, key_sz, val_sz) \
+ __CHASH_TABLE_INIT(((tbl).table), (tbl).data, bts, key_sz, val_sz)
+
+int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,
+ unsigned int value_size, gfp_t gfp_mask);
+void chash_table_free(struct chash_table *table);
+
+/**
+ * chash_table_dump_stats - Dump statistics of a closed hash table
+ * @tbl: Pointer to the table structure
+ *
+ * Dumps some performance statistics of the table gathered in operation
+ * in the kernel log using pr_debug. If CONFIG_DYNAMIC_DEBUG is enabled,
+ * user must turn on messages for chash.c (file chash.c +p).
+ */
+#ifdef CONFIG_CHASH_STATS
+#define chash_table_dump_stats(tbl) __chash_table_dump_stats(&(*tbl).table)
+
+void __chash_table_dump_stats(struct __chash_table *table);
+#else
+#define chash_table_dump_stats(tbl)
+#endif
+
+/**
+ * chash_table_reset_stats - Reset statistics of a closed hash table
+ * @tbl: Pointer to the table structure
+ */
+#ifdef CONFIG_CHASH_STATS
+#define chash_table_reset_stats(tbl) __chash_table_reset_stats(&(*tbl).table)
+
+static inline void __chash_table_reset_stats(struct __chash_table *table)
+{
+ (void)table __CHASH_STATS_INIT((*table));
+}
+#else
+#define chash_table_reset_stats(tbl)
+#endif
+
+/**
+ * chash_table_copy_in - Copy a new value into the hash table
+ * @tbl: Pointer to the table structure
+ * @key: Key of the entry to add or update
+ * @value: Pointer to value to copy, may be NULL
+ *
+ * If @key already has an entry, its value is replaced. Otherwise a
+ * new entry is added. If @value is NULL, the value is left unchanged
+ * or uninitialized. Returns 1 if an entry already existed, 0 if a new
+ * entry was added or %-ENOMEM if there was no free space in the
+ * table.
+ */
+#define chash_table_copy_in(tbl, key, value) \
+ __chash_table_copy_in(&(*tbl).table, key, value)
+
+int __chash_table_copy_in(struct __chash_table *table, u64 key,
+ const void *value);
+
+/**
+ * chash_table_copy_out - Copy a value out of the hash table
+ * @tbl: Pointer to the table structure
+ * @key: Key of the entry to find
+ * @value: Pointer to value to copy, may be NULL
+ *
+ * If @value is not NULL and the table has a non-0 value_size, the
+ * value at @key is copied to @value. Returns the slot index of the
+ * entry or %-EINVAL if @key was not found.
+ */
+#define chash_table_copy_out(tbl, key, value) \
+ __chash_table_copy_out(&(*tbl).table, key, value, false)
+
+int __chash_table_copy_out(struct __chash_table *table, u64 key,
+ void *value, bool remove);
+
+/**
+ * chash_table_remove - Remove an entry from the hash table
+ * @tbl: Pointer to the table structure
+ * @key: Key of the entry to find
+ * @value: Pointer to value to copy, may be NULL
+ *
+ * If @value is not NULL and the table has a non-0 value_size, the
+ * value at @key is copied to @value. The entry is removed from the
+ * table. Returns the slot index of the removed entry or %-EINVAL if
+ * @key was not found.
+ */
+#define chash_table_remove(tbl, key, value) \
+ __chash_table_copy_out(&(*tbl).table, key, value, true)
+
+/*
+ * Low level iterator API used internally by the above functions.
+ */
+struct chash_iter {
+ struct __chash_table *table;
+ unsigned long mask;
+ int slot;
+};
+
+/**
+ * CHASH_ITER_INIT - Initialize a hash table iterator
+ * @tbl: Pointer to hash table to iterate over
+ * @s: Initial slot number
+ */
+#define CHASH_ITER_INIT(table, s) { \
+ table, \
+ 1UL << ((s) & (BITS_PER_LONG - 1)), \
+ s \
+ }
+/**
+ * CHASH_ITER_SET - Set hash table iterator to new slot
+ * @iter: Iterator
+ * @s: Slot number
+ */
+#define CHASH_ITER_SET(iter, s) \
+ (iter).mask = 1UL << ((s) & (BITS_PER_LONG - 1)), \
+ (iter).slot = (s)
+/**
+ * CHASH_ITER_INC - Increment hash table iterator
+ * @table: Hash table to iterate over
+ *
+ * Wraps around at the end.
+ */
+#define CHASH_ITER_INC(iter) do { \
+ (iter).mask = (iter).mask << 1 | \
+ (iter).mask >> (BITS_PER_LONG - 1); \
+ (iter).slot = ((iter).slot + 1) & (iter).table->size_mask; \
+ } while (0)
+
+static inline bool chash_iter_is_valid(const struct chash_iter iter)
+{
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ return !!(iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &
+ iter.mask);
+}
+static inline bool chash_iter_is_empty(const struct chash_iter iter)
+{
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ return !(iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &
+ iter.mask);
+}
+
+static inline void chash_iter_set_valid(const struct chash_iter iter)
+{
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask;
+ iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask;
+}
+static inline void chash_iter_set_invalid(const struct chash_iter iter)
+{
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask;
+}
+static inline void chash_iter_set_empty(const struct chash_iter iter)
+{
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask;
+}
+
+static inline u32 chash_iter_key32(const struct chash_iter iter)
+{
+ BUG_ON(iter.table->key_size != 4);
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ return iter.table->keys32[iter.slot];
+}
+static inline u64 chash_iter_key64(const struct chash_iter iter)
+{
+ BUG_ON(iter.table->key_size != 8);
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ return iter.table->keys64[iter.slot];
+}
+static inline u64 chash_iter_key(const struct chash_iter iter)
+{
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ return (iter.table->key_size == 4) ?
+ iter.table->keys32[iter.slot] : iter.table->keys64[iter.slot];
+}
+
+static inline u32 chash_iter_hash32(const struct chash_iter iter)
+{
+ BUG_ON(iter.table->key_size != 4);
+ return hash_32(chash_iter_key32(iter), iter.table->bits);
+}
+
+static inline u32 chash_iter_hash64(const struct chash_iter iter)
+{
+ BUG_ON(iter.table->key_size != 8);
+ return hash_64(chash_iter_key64(iter), iter.table->bits);
+}
+
+static inline u32 chash_iter_hash(const struct chash_iter iter)
+{
+ return (iter.table->key_size == 4) ?
+ hash_32(chash_iter_key32(iter), iter.table->bits) :
+ hash_64(chash_iter_key64(iter), iter.table->bits);
+}
+
+static inline void *chash_iter_value(const struct chash_iter iter)
+{
+ BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
+ return iter.table->values +
+ ((unsigned long)iter.slot * iter.table->value_size);
+}
+
+#endif /* _LINUX_CHASH_H */
diff --git a/drivers/gpu/drm/amd/include/v9_structs.h b/drivers/gpu/drm/amd/include/v9_structs.h
index 9a9e6c7..2fb25ab 100644
--- a/drivers/gpu/drm/amd/include/v9_structs.h
+++ b/drivers/gpu/drm/amd/include/v9_structs.h
@@ -284,8 +284,8 @@ struct v9_mqd {
uint32_t gds_save_mask_hi;
uint32_t ctx_save_base_addr_lo;
uint32_t ctx_save_base_addr_hi;
- uint32_t reserved_126;
- uint32_t reserved_127;
+ uint32_t dynamic_cu_mask_addr_lo;
+ uint32_t dynamic_cu_mask_addr_hi;
uint32_t cp_mqd_base_addr_lo;
uint32_t cp_mqd_base_addr_hi;
uint32_t cp_hqd_active;
@@ -672,6 +672,14 @@ struct v9_mqd {
uint32_t reserved_511;
};
+struct v9_mqd_allocation {
+ struct v9_mqd mqd;
+ uint32_t wptr_poll_mem;
+ uint32_t rptr_report_mem;
+ uint32_t dynamic_cu_mask;
+ uint32_t dynamic_rb_mask;
+};
+
/* from vega10 all CSA format is shifted to chain ib compatible mode */
struct v9_ce_ib_state {
/* section of non chained ib part */
diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h
index 3e606a7..2023482 100644
--- a/drivers/gpu/drm/amd/include/vi_structs.h
+++ b/drivers/gpu/drm/amd/include/vi_structs.h
@@ -423,265 +423,6 @@ struct vi_mqd_allocation {
uint32_t dynamic_rb_mask;
};
-struct cz_mqd {
- uint32_t header;
- uint32_t compute_dispatch_initiator;
- uint32_t compute_dim_x;
- uint32_t compute_dim_y;
- uint32_t compute_dim_z;
- uint32_t compute_start_x;
- uint32_t compute_start_y;
- uint32_t compute_start_z;
- uint32_t compute_num_thread_x;
- uint32_t compute_num_thread_y;
- uint32_t compute_num_thread_z;
- uint32_t compute_pipelinestat_enable;
- uint32_t compute_perfcount_enable;
- uint32_t compute_pgm_lo;
- uint32_t compute_pgm_hi;
- uint32_t compute_tba_lo;
- uint32_t compute_tba_hi;
- uint32_t compute_tma_lo;
- uint32_t compute_tma_hi;
- uint32_t compute_pgm_rsrc1;
- uint32_t compute_pgm_rsrc2;
- uint32_t compute_vmid;
- uint32_t compute_resource_limits;
- uint32_t compute_static_thread_mgmt_se0;
- uint32_t compute_static_thread_mgmt_se1;
- uint32_t compute_tmpring_size;
- uint32_t compute_static_thread_mgmt_se2;
- uint32_t compute_static_thread_mgmt_se3;
- uint32_t compute_restart_x;
- uint32_t compute_restart_y;
- uint32_t compute_restart_z;
- uint32_t compute_thread_trace_enable;
- uint32_t compute_misc_reserved;
- uint32_t compute_dispatch_id;
- uint32_t compute_threadgroup_id;
- uint32_t compute_relaunch;
- uint32_t compute_wave_restore_addr_lo;
- uint32_t compute_wave_restore_addr_hi;
- uint32_t compute_wave_restore_control;
- uint32_t reserved_39;
- uint32_t reserved_40;
- uint32_t reserved_41;
- uint32_t reserved_42;
- uint32_t reserved_43;
- uint32_t reserved_44;
- uint32_t reserved_45;
- uint32_t reserved_46;
- uint32_t reserved_47;
- uint32_t reserved_48;
- uint32_t reserved_49;
- uint32_t reserved_50;
- uint32_t reserved_51;
- uint32_t reserved_52;
- uint32_t reserved_53;
- uint32_t reserved_54;
- uint32_t reserved_55;
- uint32_t reserved_56;
- uint32_t reserved_57;
- uint32_t reserved_58;
- uint32_t reserved_59;
- uint32_t reserved_60;
- uint32_t reserved_61;
- uint32_t reserved_62;
- uint32_t reserved_63;
- uint32_t reserved_64;
- uint32_t compute_user_data_0;
- uint32_t compute_user_data_1;
- uint32_t compute_user_data_2;
- uint32_t compute_user_data_3;
- uint32_t compute_user_data_4;
- uint32_t compute_user_data_5;
- uint32_t compute_user_data_6;
- uint32_t compute_user_data_7;
- uint32_t compute_user_data_8;
- uint32_t compute_user_data_9;
- uint32_t compute_user_data_10;
- uint32_t compute_user_data_11;
- uint32_t compute_user_data_12;
- uint32_t compute_user_data_13;
- uint32_t compute_user_data_14;
- uint32_t compute_user_data_15;
- uint32_t cp_compute_csinvoc_count_lo;
- uint32_t cp_compute_csinvoc_count_hi;
- uint32_t reserved_83;
- uint32_t reserved_84;
- uint32_t reserved_85;
- uint32_t cp_mqd_query_time_lo;
- uint32_t cp_mqd_query_time_hi;
- uint32_t cp_mqd_connect_start_time_lo;
- uint32_t cp_mqd_connect_start_time_hi;
- uint32_t cp_mqd_connect_end_time_lo;
- uint32_t cp_mqd_connect_end_time_hi;
- uint32_t cp_mqd_connect_end_wf_count;
- uint32_t cp_mqd_connect_end_pq_rptr;
- uint32_t cp_mqd_connect_end_pq_wptr;
- uint32_t cp_mqd_connect_end_ib_rptr;
- uint32_t reserved_96;
- uint32_t reserved_97;
- uint32_t cp_mqd_save_start_time_lo;
- uint32_t cp_mqd_save_start_time_hi;
- uint32_t cp_mqd_save_end_time_lo;
- uint32_t cp_mqd_save_end_time_hi;
- uint32_t cp_mqd_restore_start_time_lo;
- uint32_t cp_mqd_restore_start_time_hi;
- uint32_t cp_mqd_restore_end_time_lo;
- uint32_t cp_mqd_restore_end_time_hi;
- uint32_t reserved_106;
- uint32_t reserved_107;
- uint32_t gds_cs_ctxsw_cnt0;
- uint32_t gds_cs_ctxsw_cnt1;
- uint32_t gds_cs_ctxsw_cnt2;
- uint32_t gds_cs_ctxsw_cnt3;
- uint32_t reserved_112;
- uint32_t reserved_113;
- uint32_t cp_pq_exe_status_lo;
- uint32_t cp_pq_exe_status_hi;
- uint32_t cp_packet_id_lo;
- uint32_t cp_packet_id_hi;
- uint32_t cp_packet_exe_status_lo;
- uint32_t cp_packet_exe_status_hi;
- uint32_t gds_save_base_addr_lo;
- uint32_t gds_save_base_addr_hi;
- uint32_t gds_save_mask_lo;
- uint32_t gds_save_mask_hi;
- uint32_t ctx_save_base_addr_lo;
- uint32_t ctx_save_base_addr_hi;
- uint32_t reserved_126;
- uint32_t reserved_127;
- uint32_t cp_mqd_base_addr_lo;
- uint32_t cp_mqd_base_addr_hi;
- uint32_t cp_hqd_active;
- uint32_t cp_hqd_vmid;
- uint32_t cp_hqd_persistent_state;
- uint32_t cp_hqd_pipe_priority;
- uint32_t cp_hqd_queue_priority;
- uint32_t cp_hqd_quantum;
- uint32_t cp_hqd_pq_base_lo;
- uint32_t cp_hqd_pq_base_hi;
- uint32_t cp_hqd_pq_rptr;
- uint32_t cp_hqd_pq_rptr_report_addr_lo;
- uint32_t cp_hqd_pq_rptr_report_addr_hi;
- uint32_t cp_hqd_pq_wptr_poll_addr_lo;
- uint32_t cp_hqd_pq_wptr_poll_addr_hi;
- uint32_t cp_hqd_pq_doorbell_control;
- uint32_t cp_hqd_pq_wptr;
- uint32_t cp_hqd_pq_control;
- uint32_t cp_hqd_ib_base_addr_lo;
- uint32_t cp_hqd_ib_base_addr_hi;
- uint32_t cp_hqd_ib_rptr;
- uint32_t cp_hqd_ib_control;
- uint32_t cp_hqd_iq_timer;
- uint32_t cp_hqd_iq_rptr;
- uint32_t cp_hqd_dequeue_request;
- uint32_t cp_hqd_dma_offload;
- uint32_t cp_hqd_sema_cmd;
- uint32_t cp_hqd_msg_type;
- uint32_t cp_hqd_atomic0_preop_lo;
- uint32_t cp_hqd_atomic0_preop_hi;
- uint32_t cp_hqd_atomic1_preop_lo;
- uint32_t cp_hqd_atomic1_preop_hi;
- uint32_t cp_hqd_hq_status0;
- uint32_t cp_hqd_hq_control0;
- uint32_t cp_mqd_control;
- uint32_t cp_hqd_hq_status1;
- uint32_t cp_hqd_hq_control1;
- uint32_t cp_hqd_eop_base_addr_lo;
- uint32_t cp_hqd_eop_base_addr_hi;
- uint32_t cp_hqd_eop_control;
- uint32_t cp_hqd_eop_rptr;
- uint32_t cp_hqd_eop_wptr;
- uint32_t cp_hqd_eop_done_events;
- uint32_t cp_hqd_ctx_save_base_addr_lo;
- uint32_t cp_hqd_ctx_save_base_addr_hi;
- uint32_t cp_hqd_ctx_save_control;
- uint32_t cp_hqd_cntl_stack_offset;
- uint32_t cp_hqd_cntl_stack_size;
- uint32_t cp_hqd_wg_state_offset;
- uint32_t cp_hqd_ctx_save_size;
- uint32_t cp_hqd_gds_resource_state;
- uint32_t cp_hqd_error;
- uint32_t cp_hqd_eop_wptr_mem;
- uint32_t cp_hqd_eop_dones;
- uint32_t reserved_182;
- uint32_t reserved_183;
- uint32_t reserved_184;
- uint32_t reserved_185;
- uint32_t reserved_186;
- uint32_t reserved_187;
- uint32_t reserved_188;
- uint32_t reserved_189;
- uint32_t reserved_190;
- uint32_t reserved_191;
- uint32_t iqtimer_pkt_header;
- uint32_t iqtimer_pkt_dw0;
- uint32_t iqtimer_pkt_dw1;
- uint32_t iqtimer_pkt_dw2;
- uint32_t iqtimer_pkt_dw3;
- uint32_t iqtimer_pkt_dw4;
- uint32_t iqtimer_pkt_dw5;
- uint32_t iqtimer_pkt_dw6;
- uint32_t iqtimer_pkt_dw7;
- uint32_t iqtimer_pkt_dw8;
- uint32_t iqtimer_pkt_dw9;
- uint32_t iqtimer_pkt_dw10;
- uint32_t iqtimer_pkt_dw11;
- uint32_t iqtimer_pkt_dw12;
- uint32_t iqtimer_pkt_dw13;
- uint32_t iqtimer_pkt_dw14;
- uint32_t iqtimer_pkt_dw15;
- uint32_t iqtimer_pkt_dw16;
- uint32_t iqtimer_pkt_dw17;
- uint32_t iqtimer_pkt_dw18;
- uint32_t iqtimer_pkt_dw19;
- uint32_t iqtimer_pkt_dw20;
- uint32_t iqtimer_pkt_dw21;
- uint32_t iqtimer_pkt_dw22;
- uint32_t iqtimer_pkt_dw23;
- uint32_t iqtimer_pkt_dw24;
- uint32_t iqtimer_pkt_dw25;
- uint32_t iqtimer_pkt_dw26;
- uint32_t iqtimer_pkt_dw27;
- uint32_t iqtimer_pkt_dw28;
- uint32_t iqtimer_pkt_dw29;
- uint32_t iqtimer_pkt_dw30;
- uint32_t iqtimer_pkt_dw31;
- uint32_t reserved_225;
- uint32_t reserved_226;
- uint32_t reserved_227;
- uint32_t set_resources_header;
- uint32_t set_resources_dw1;
- uint32_t set_resources_dw2;
- uint32_t set_resources_dw3;
- uint32_t set_resources_dw4;
- uint32_t set_resources_dw5;
- uint32_t set_resources_dw6;
- uint32_t set_resources_dw7;
- uint32_t reserved_236;
- uint32_t reserved_237;
- uint32_t reserved_238;
- uint32_t reserved_239;
- uint32_t queue_doorbell_id0;
- uint32_t queue_doorbell_id1;
- uint32_t queue_doorbell_id2;
- uint32_t queue_doorbell_id3;
- uint32_t queue_doorbell_id4;
- uint32_t queue_doorbell_id5;
- uint32_t queue_doorbell_id6;
- uint32_t queue_doorbell_id7;
- uint32_t queue_doorbell_id8;
- uint32_t queue_doorbell_id9;
- uint32_t queue_doorbell_id10;
- uint32_t queue_doorbell_id11;
- uint32_t queue_doorbell_id12;
- uint32_t queue_doorbell_id13;
- uint32_t queue_doorbell_id14;
- uint32_t queue_doorbell_id15;
-};
-
struct vi_ce_ib_state {
uint32_t ce_ib_completion_status;
uint32_t ce_constegnine_count;
diff --git a/drivers/gpu/drm/amd/lib/Kconfig b/drivers/gpu/drm/amd/lib/Kconfig
new file mode 100644
index 0000000..776ef34
--- /dev/null
+++ b/drivers/gpu/drm/amd/lib/Kconfig
@@ -0,0 +1,28 @@
+menu "AMD Library routines"
+
+#
+# Closed hash table
+#
+config CHASH
+ tristate
+ default DRM_AMDGPU
+ help
+ Statically sized closed hash table implementation with low
+ memory and CPU overhead.
+
+config CHASH_STATS
+ bool "Closed hash table performance statistics"
+ depends on CHASH
+ default n
+ help
+ Enable collection of performance statistics for closed hash tables.
+
+config CHASH_SELFTEST
+ bool "Closed hash table self test"
+ depends on CHASH
+ default n
+ help
+ Runs a selftest during module load. Several module parameters
+ are available to modify the behaviour of the test.
+
+endmenu
diff --git a/drivers/gpu/drm/amd/lib/Makefile b/drivers/gpu/drm/amd/lib/Makefile
new file mode 100644
index 0000000..87cd700
--- /dev/null
+++ b/drivers/gpu/drm/amd/lib/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile for AMD library routines, which are used by AMD driver
+# components.
+#
+# This is for common library routines that can be shared between AMD
+# driver components or later moved to kernel/lib for sharing with
+# other drivers.
+
+ccflags-y := -I$(src)/../include
+
+obj-$(CONFIG_CHASH) += chash.o
diff --git a/drivers/gpu/drm/amd/lib/chash.c b/drivers/gpu/drm/amd/lib/chash.c
new file mode 100644
index 0000000..b8e45f3
--- /dev/null
+++ b/drivers/gpu/drm/amd/lib/chash.c
@@ -0,0 +1,638 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/hash.h>
+#include <linux/bug.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/sched/clock.h>
+#include <asm/div64.h>
+#include <linux/chash.h>
+
+/**
+ * chash_table_alloc - Allocate closed hash table
+ * @table: Pointer to the table structure
+ * @bits: Table size will be 2^bits entries
+ * @key_size: Size of hash keys in bytes, 4 or 8
+ * @value_size: Size of data values in bytes, can be 0
+ */
+int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,
+ unsigned int value_size, gfp_t gfp_mask)
+{
+ if (bits > 31)
+ return -EINVAL;
+
+ if (key_size != 4 && key_size != 8)
+ return -EINVAL;
+
+ table->data = kcalloc(__CHASH_DATA_SIZE(bits, key_size, value_size),
+ sizeof(long), gfp_mask);
+ if (!table->data)
+ return -ENOMEM;
+
+ __CHASH_TABLE_INIT(table->table, table->data,
+ bits, key_size, value_size);
+
+ return 0;
+}
+EXPORT_SYMBOL(chash_table_alloc);
+
+/**
+ * chash_table_free - Free closed hash table
+ * @table: Pointer to the table structure
+ */
+void chash_table_free(struct chash_table *table)
+{
+ kfree(table->data);
+}
+EXPORT_SYMBOL(chash_table_free);
+
+#ifdef CONFIG_CHASH_STATS
+
+#define DIV_FRAC(nom, denom, quot, frac, frac_digits) do { \
+ u64 __nom = (nom); \
+ u64 __denom = (denom); \
+ u64 __quot, __frac; \
+ u32 __rem; \
+ \
+ while (__denom >> 32) { \
+ __nom >>= 1; \
+ __denom >>= 1; \
+ } \
+ __quot = __nom; \
+ __rem = do_div(__quot, __denom); \
+ __frac = __rem * (frac_digits) + (__denom >> 1); \
+ do_div(__frac, __denom); \
+ (quot) = __quot; \
+ (frac) = __frac; \
+ } while (0)
+
+void __chash_table_dump_stats(struct __chash_table *table)
+{
+ struct chash_iter iter = CHASH_ITER_INIT(table, 0);
+ u32 filled = 0, empty = 0, tombstones = 0;
+ u64 quot1, quot2;
+ u32 frac1, frac2;
+
+ do {
+ if (chash_iter_is_valid(iter))
+ filled++;
+ else if (chash_iter_is_empty(iter))
+ empty++;
+ else
+ tombstones++;
+ CHASH_ITER_INC(iter);
+ } while (iter.slot);
+
+ pr_debug("chash: key size %u, value size %u\n",
+ table->key_size, table->value_size);
+ pr_debug(" Slots total/filled/empty/tombstones: %u / %u / %u / %u\n",
+ 1 << table->bits, filled, empty, tombstones);
+ if (table->hits > 0) {
+ DIV_FRAC(table->hits_steps, table->hits, quot1, frac1, 1000);
+ DIV_FRAC(table->hits * 1000, table->hits_time_ns,
+ quot2, frac2, 1000);
+ } else {
+ quot1 = quot2 = 0;
+ frac1 = frac2 = 0;
+ }
+ pr_debug(" Hits (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n",
+ table->hits, quot1, frac1, quot2, frac2);
+ if (table->miss > 0) {
+ DIV_FRAC(table->miss_steps, table->miss, quot1, frac1, 1000);
+ DIV_FRAC(table->miss * 1000, table->miss_time_ns,
+ quot2, frac2, 1000);
+ } else {
+ quot1 = quot2 = 0;
+ frac1 = frac2 = 0;
+ }
+ pr_debug(" Misses (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n",
+ table->miss, quot1, frac1, quot2, frac2);
+ if (table->hits + table->miss > 0) {
+ DIV_FRAC(table->hits_steps + table->miss_steps,
+ table->hits + table->miss, quot1, frac1, 1000);
+ DIV_FRAC((table->hits + table->miss) * 1000,
+ (table->hits_time_ns + table->miss_time_ns),
+ quot2, frac2, 1000);
+ } else {
+ quot1 = quot2 = 0;
+ frac1 = frac2 = 0;
+ }
+ pr_debug(" Total (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n",
+ table->hits + table->miss, quot1, frac1, quot2, frac2);
+ if (table->relocs > 0) {
+ DIV_FRAC(table->hits + table->miss, table->relocs,
+ quot1, frac1, 1000);
+ DIV_FRAC(table->reloc_dist, table->relocs, quot2, frac2, 1000);
+ pr_debug(" Relocations (freq, avg.dist): %llu (1:%llu.%03u, %llu.%03u)\n",
+ table->relocs, quot1, frac1, quot2, frac2);
+ } else {
+ pr_debug(" No relocations\n");
+ }
+}
+EXPORT_SYMBOL(__chash_table_dump_stats);
+
+#undef DIV_FRAC
+#endif
+
+#define CHASH_INC(table, a) ((a) = ((a) + 1) & (table)->size_mask)
+#define CHASH_ADD(table, a, b) (((a) + (b)) & (table)->size_mask)
+#define CHASH_SUB(table, a, b) (((a) - (b)) & (table)->size_mask)
+#define CHASH_IN_RANGE(table, slot, first, last) \
+ (CHASH_SUB(table, slot, first) <= CHASH_SUB(table, last, first))
+
+/*#define CHASH_DEBUG Uncomment this to enable verbose debug output*/
+#ifdef CHASH_DEBUG
+static void chash_table_dump(struct __chash_table *table)
+{
+ struct chash_iter iter = CHASH_ITER_INIT(table, 0);
+
+ do {
+ if ((iter.slot & 3) == 0)
+ pr_debug("%04x: ", iter.slot);
+
+ if (chash_iter_is_valid(iter))
+ pr_debug("[%016llx] ", chash_iter_key(iter));
+ else if (chash_iter_is_empty(iter))
+ pr_debug("[ <empty> ] ");
+ else
+ pr_debug("[ <tombstone> ] ");
+
+ if ((iter.slot & 3) == 3)
+ pr_debug("\n");
+
+ CHASH_ITER_INC(iter);
+ } while (iter.slot);
+
+ if ((iter.slot & 3) != 0)
+ pr_debug("\n");
+}
+
+static int chash_table_check(struct __chash_table *table)
+{
+ u32 hash;
+ struct chash_iter iter = CHASH_ITER_INIT(table, 0);
+ struct chash_iter cur = CHASH_ITER_INIT(table, 0);
+
+ do {
+ if (!chash_iter_is_valid(iter)) {
+ CHASH_ITER_INC(iter);
+ continue;
+ }
+
+ hash = chash_iter_hash(iter);
+ CHASH_ITER_SET(cur, hash);
+ while (cur.slot != iter.slot) {
+ if (chash_iter_is_empty(cur)) {
+ pr_err("Path to element at %x with hash %x broken at slot %x\n",
+ iter.slot, hash, cur.slot);
+ chash_table_dump(table);
+ return -EINVAL;
+ }
+ CHASH_ITER_INC(cur);
+ }
+
+ CHASH_ITER_INC(iter);
+ } while (iter.slot);
+
+ return 0;
+}
+#endif
+
+static void chash_iter_relocate(struct chash_iter dst, struct chash_iter src)
+{
+ BUG_ON(src.table == dst.table && src.slot == dst.slot);
+ BUG_ON(src.table->key_size != dst.table->key_size);
+ BUG_ON(src.table->value_size != dst.table->value_size);
+
+ if (dst.table->key_size == 4)
+ dst.table->keys32[dst.slot] = src.table->keys32[src.slot];
+ else
+ dst.table->keys64[dst.slot] = src.table->keys64[src.slot];
+
+ if (dst.table->value_size)
+ memcpy(chash_iter_value(dst), chash_iter_value(src),
+ dst.table->value_size);
+
+ chash_iter_set_valid(dst);
+ chash_iter_set_invalid(src);
+
+#ifdef CONFIG_CHASH_STATS
+ if (src.table == dst.table) {
+ dst.table->relocs++;
+ dst.table->reloc_dist +=
+ CHASH_SUB(dst.table, src.slot, dst.slot);
+ }
+#endif
+}
+
+/**
+ * __chash_table_find - Helper for looking up a hash table entry
+ * @iter: Pointer to hash table iterator
+ * @key: Key of the entry to find
+ * @for_removal: set to true if the element will be removed soon
+ *
+ * Searches for an entry in the hash table with a given key. iter must
+ * be initialized by the caller to point to the home position of the
+ * hypothetical entry, i.e. it must be initialized with the hash table
+ * and the key's hash as the initial slot for the search.
+ *
+ * This function also does some local clean-up to speed up future
+ * look-ups by relocating entries to better slots and removing
+ * tombstones that are no longer needed.
+ *
+ * If @for_removal is true, the function avoids relocating the entry
+ * that is being returned.
+ *
+ * Returns 0 if the search is successful. In this case iter is updated
+ * to point to the found entry. Otherwise %-EINVAL is returned and the
+ * iter is updated to point to the first available slot for the given
+ * key. If the table is full, the slot is set to -1.
+ */
+static int chash_table_find(struct chash_iter *iter, u64 key,
+ bool for_removal)
+{
+#ifdef CONFIG_CHASH_STATS
+ u64 ts1 = local_clock();
+#endif
+ u32 hash = iter->slot;
+ struct chash_iter first_redundant = CHASH_ITER_INIT(iter->table, -1);
+ int first_avail = (for_removal ? -2 : -1);
+
+ while (!chash_iter_is_valid(*iter) || chash_iter_key(*iter) != key) {
+ if (chash_iter_is_empty(*iter)) {
+ /* Found an empty slot, which ends the
+ * search. Clean up any preceding tombstones
+ * that are no longer needed because they lead
+ * to no-where
+ */
+ if ((int)first_redundant.slot < 0)
+ goto not_found;
+ while (first_redundant.slot != iter->slot) {
+ if (!chash_iter_is_valid(first_redundant))
+ chash_iter_set_empty(first_redundant);
+ CHASH_ITER_INC(first_redundant);
+ }
+#ifdef CHASH_DEBUG
+ chash_table_check(iter->table);
+#endif
+ goto not_found;
+ } else if (!chash_iter_is_valid(*iter)) {
+ /* Found a tombstone. Remember it as candidate
+ * for relocating the entry we're looking for
+ * or for adding a new entry with the given key
+ */
+ if (first_avail == -1)
+ first_avail = iter->slot;
+ /* Or mark it as the start of a series of
+ * potentially redundant tombstones
+ */
+ else if (first_redundant.slot == -1)
+ CHASH_ITER_SET(first_redundant, iter->slot);
+ } else if (first_redundant.slot >= 0) {
+ /* Found a valid, occupied slot with a
+ * preceding series of tombstones. Relocate it
+ * to a better position that no longer depends
+ * on those tombstones
+ */
+ u32 cur_hash = chash_iter_hash(*iter);
+
+ if (!CHASH_IN_RANGE(iter->table, cur_hash,
+ first_redundant.slot + 1,
+ iter->slot)) {
+ /* This entry has a hash at or before
+ * the first tombstone we found. We
+ * can relocate it to that tombstone
+ * and advance to the next tombstone
+ */
+ chash_iter_relocate(first_redundant, *iter);
+ do {
+ CHASH_ITER_INC(first_redundant);
+ } while (chash_iter_is_valid(first_redundant));
+ } else if (cur_hash != iter->slot) {
+ /* Relocate entry to its home position
+ * or as close as possible so it no
+ * longer depends on any preceding
+ * tombstones
+ */
+ struct chash_iter new_iter =
+ CHASH_ITER_INIT(iter->table, cur_hash);
+
+ while (new_iter.slot != iter->slot &&
+ chash_iter_is_valid(new_iter))
+ CHASH_ITER_INC(new_iter);
+
+ if (new_iter.slot != iter->slot)
+ chash_iter_relocate(new_iter, *iter);
+ }
+ }
+
+ CHASH_ITER_INC(*iter);
+ if (iter->slot == hash) {
+ iter->slot = -1;
+ goto not_found;
+ }
+ }
+
+#ifdef CONFIG_CHASH_STATS
+ iter->table->hits++;
+ iter->table->hits_steps += CHASH_SUB(iter->table, iter->slot, hash) + 1;
+#endif
+
+ if (first_avail >= 0) {
+ CHASH_ITER_SET(first_redundant, first_avail);
+ chash_iter_relocate(first_redundant, *iter);
+ iter->slot = first_redundant.slot;
+ iter->mask = first_redundant.mask;
+ }
+
+#ifdef CONFIG_CHASH_STATS
+ iter->table->hits_time_ns += local_clock() - ts1;
+#endif
+
+ return 0;
+
+not_found:
+#ifdef CONFIG_CHASH_STATS
+ iter->table->miss++;
+ iter->table->miss_steps += (iter->slot < 0) ?
+ (1 << iter->table->bits) :
+ CHASH_SUB(iter->table, iter->slot, hash) + 1;
+#endif
+
+ if (first_avail >= 0)
+ CHASH_ITER_SET(*iter, first_avail);
+
+#ifdef CONFIG_CHASH_STATS
+ iter->table->miss_time_ns += local_clock() - ts1;
+#endif
+
+ return -EINVAL;
+}
+
+int __chash_table_copy_in(struct __chash_table *table, u64 key,
+ const void *value)
+{
+ u32 hash = (table->key_size == 4) ?
+ hash_32(key, table->bits) : hash_64(key, table->bits);
+ struct chash_iter iter = CHASH_ITER_INIT(table, hash);
+ int r = chash_table_find(&iter, key, false);
+
+ /* Found an existing entry */
+ if (!r) {
+ if (value && table->value_size)
+ memcpy(chash_iter_value(iter), value,
+ table->value_size);
+ return 1;
+ }
+
+ /* Is there a place to add a new entry? */
+ if (iter.slot < 0) {
+ pr_err("Hash table overflow\n");
+ return -ENOMEM;
+ }
+
+ chash_iter_set_valid(iter);
+
+ if (table->key_size == 4)
+ table->keys32[iter.slot] = key;
+ else
+ table->keys64[iter.slot] = key;
+ if (value && table->value_size)
+ memcpy(chash_iter_value(iter), value, table->value_size);
+
+ return 0;
+}
+EXPORT_SYMBOL(__chash_table_copy_in);
+
+int __chash_table_copy_out(struct __chash_table *table, u64 key,
+ void *value, bool remove)
+{
+ u32 hash = (table->key_size == 4) ?
+ hash_32(key, table->bits) : hash_64(key, table->bits);
+ struct chash_iter iter = CHASH_ITER_INIT(table, hash);
+ int r = chash_table_find(&iter, key, remove);
+
+ if (r < 0)
+ return r;
+
+ if (value && table->value_size)
+ memcpy(value, chash_iter_value(iter), table->value_size);
+
+ if (remove)
+ chash_iter_set_invalid(iter);
+
+ return iter.slot;
+}
+EXPORT_SYMBOL(__chash_table_copy_out);
+
+#ifdef CONFIG_CHASH_SELFTEST
+/**
+ * chash_self_test - Run a self-test of the hash table implementation
+ * @bits: Table size will be 2^bits entries
+ * @key_size: Size of hash keys in bytes, 4 or 8
+ * @min_fill: Minimum fill level during the test
+ * @max_fill: Maximum fill level during the test
+ * @iterations: Number of test iterations
+ *
+ * The test adds and removes entries from a hash table, cycling the
+ * fill level between min_fill and max_fill entries. Also tests lookup
+ * and value retrieval.
+ */
+static int __init chash_self_test(u8 bits, u8 key_size,
+ int min_fill, int max_fill,
+ u64 iterations)
+{
+ struct chash_table table;
+ int ret;
+ u64 add_count, rmv_count;
+ u64 value;
+
+ if (key_size == 4 && iterations > 0xffffffff)
+ return -EINVAL;
+ if (min_fill >= max_fill)
+ return -EINVAL;
+
+ ret = chash_table_alloc(&table, bits, key_size, sizeof(u64),
+ GFP_KERNEL);
+ if (ret) {
+ pr_err("chash_table_alloc failed: %d\n", ret);
+ return ret;
+ }
+
+ for (add_count = 0, rmv_count = 0; add_count < iterations;
+ add_count++) {
+ /* When we hit the max_fill level, remove entries down
+ * to min_fill
+ */
+ if (add_count - rmv_count == max_fill) {
+ u64 find_count = rmv_count;
+
+ /* First try to find all entries that we're
+ * about to remove, confirm their value, test
+ * writing them back a second time.
+ */
+ for (; add_count - find_count > min_fill;
+ find_count++) {
+ ret = chash_table_copy_out(&table, find_count,
+ &value);
+ if (ret < 0) {
+ pr_err("chash_table_copy_out failed: %d\n",
+ ret);
+ goto out;
+ }
+ if (value != ~find_count) {
+ pr_err("Wrong value retrieved for key 0x%llx, expected 0x%llx got 0x%llx\n",
+ find_count, ~find_count, value);
+#ifdef CHASH_DEBUG
+ chash_table_dump(&table.table);
+#endif
+ ret = -EFAULT;
+ goto out;
+ }
+ ret = chash_table_copy_in(&table, find_count,
+ &value);
+ if (ret != 1) {
+ pr_err("copy_in second time returned %d, expected 1\n",
+ ret);
+ ret = -EFAULT;
+ goto out;
+ }
+ }
+ /* Remove them until we hit min_fill level */
+ for (; add_count - rmv_count > min_fill; rmv_count++) {
+ ret = chash_table_remove(&table, rmv_count,
+ NULL);
+ if (ret < 0) {
+ pr_err("chash_table_remove failed: %d\n",
+ ret);
+ goto out;
+ }
+ }
+ }
+
+ /* Add a new value */
+ value = ~add_count;
+ ret = chash_table_copy_in(&table, add_count, &value);
+ if (ret != 0) {
+ pr_err("copy_in first time returned %d, expected 0\n",
+ ret);
+ ret = -EFAULT;
+ goto out;
+ }
+ }
+
+ chash_table_dump_stats(&table);
+ chash_table_reset_stats(&table);
+
+out:
+ chash_table_free(&table);
+ return ret;
+}
+
+static unsigned int chash_test_bits = 10;
+MODULE_PARM_DESC(test_bits,
+ "Selftest number of hash bits ([4..20], default=10)");
+module_param_named(test_bits, chash_test_bits, uint, 0444);
+
+static unsigned int chash_test_keysize = 8;
+MODULE_PARM_DESC(test_keysize, "Selftest keysize (4 or 8, default=8)");
+module_param_named(test_keysize, chash_test_keysize, uint, 0444);
+
+static unsigned int chash_test_minfill;
+MODULE_PARM_DESC(test_minfill, "Selftest minimum #entries (default=50%)");
+module_param_named(test_minfill, chash_test_minfill, uint, 0444);
+
+static unsigned int chash_test_maxfill;
+MODULE_PARM_DESC(test_maxfill, "Selftest maximum #entries (default=80%)");
+module_param_named(test_maxfill, chash_test_maxfill, uint, 0444);
+
+static unsigned long chash_test_iters;
+MODULE_PARM_DESC(test_iters, "Selftest iterations (default=1000 x #entries)");
+module_param_named(test_iters, chash_test_iters, ulong, 0444);
+
+static int __init chash_init(void)
+{
+ int ret;
+ u64 ts1_ns;
+
+ /* Skip self test on user errors */
+ if (chash_test_bits < 4 || chash_test_bits > 20) {
+ pr_err("chash: test_bits out of range [4..20].\n");
+ return 0;
+ }
+ if (chash_test_keysize != 4 && chash_test_keysize != 8) {
+ pr_err("chash: test_keysize invalid. Must be 4 or 8.\n");
+ return 0;
+ }
+
+ if (!chash_test_minfill)
+ chash_test_minfill = (1 << chash_test_bits) / 2;
+ if (!chash_test_maxfill)
+ chash_test_maxfill = (1 << chash_test_bits) * 4 / 5;
+ if (!chash_test_iters)
+ chash_test_iters = (1 << chash_test_bits) * 1000;
+
+ if (chash_test_minfill >= (1 << chash_test_bits)) {
+ pr_err("chash: test_minfill too big. Must be < table size.\n");
+ return 0;
+ }
+ if (chash_test_maxfill >= (1 << chash_test_bits)) {
+ pr_err("chash: test_maxfill too big. Must be < table size.\n");
+ return 0;
+ }
+ if (chash_test_minfill >= chash_test_maxfill) {
+ pr_err("chash: test_minfill must be < test_maxfill.\n");
+ return 0;
+ }
+ if (chash_test_keysize == 4 && chash_test_iters > 0xffffffff) {
+ pr_err("chash: test_iters must be < 4G for 4 byte keys.\n");
+ return 0;
+ }
+
+ ts1_ns = local_clock();
+ ret = chash_self_test(chash_test_bits, chash_test_keysize,
+ chash_test_minfill, chash_test_maxfill,
+ chash_test_iters);
+ if (!ret) {
+ u64 ts_delta_us = local_clock() - ts1_ns;
+ u64 iters_per_second = (u64)chash_test_iters * 1000000;
+
+ do_div(ts_delta_us, 1000);
+ do_div(iters_per_second, ts_delta_us);
+ pr_info("chash: self test took %llu us, %llu iterations/s\n",
+ ts_delta_us, iters_per_second);
+ } else {
+ pr_err("chash: self test failed: %d\n", ret);
+ }
+
+ return ret;
+}
+
+module_init(chash_init);
+
+#endif /* CONFIG_CHASH_SELFTEST */
+
+MODULE_DESCRIPTION("Closed hash table");
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
index 72d5f50..8c55c6e 100644
--- a/drivers/gpu/drm/amd/powerplay/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/Makefile
@@ -5,12 +5,11 @@
-I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_PATH)/include \
-I$(FULL_AMD_PATH)/powerplay/smumgr\
- -I$(FULL_AMD_PATH)/powerplay/hwmgr \
- -I$(FULL_AMD_PATH)/powerplay/eventmgr
+ -I$(FULL_AMD_PATH)/powerplay/hwmgr
AMD_PP_PATH = ../powerplay
-PP_LIBS = smumgr hwmgr eventmgr
+PP_LIBS = smumgr hwmgr
AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(PP_LIBS)))
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index f73e80c..c7e3412 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -29,72 +29,98 @@
#include "amd_powerplay.h"
#include "pp_instance.h"
#include "power_state.h"
-#include "eventmanager.h"
+#define PP_DPM_DISABLED 0xCCCC
+
+static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
+ void *input, void *output);
static inline int pp_check(struct pp_instance *handle)
{
- if (handle == NULL || handle->pp_valid != PP_VALID)
+ if (handle == NULL)
return -EINVAL;
- if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL)
+ if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
return -EINVAL;
if (handle->pm_en == 0)
return PP_DPM_DISABLED;
- if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL
- || handle->eventmgr == NULL)
+ if (handle->hwmgr->hwmgr_func == NULL)
return PP_DPM_DISABLED;
return 0;
}
+static int amd_powerplay_create(struct amd_pp_init *pp_init,
+ void **handle)
+{
+ struct pp_instance *instance;
+
+ if (pp_init == NULL || handle == NULL)
+ return -EINVAL;
+
+ instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
+ if (instance == NULL)
+ return -ENOMEM;
+
+ instance->chip_family = pp_init->chip_family;
+ instance->chip_id = pp_init->chip_id;
+ instance->pm_en = pp_init->pm_en;
+ instance->feature_mask = pp_init->feature_mask;
+ instance->device = pp_init->device;
+ mutex_init(&instance->pp_lock);
+ *handle = instance;
+ return 0;
+}
+
+static int amd_powerplay_destroy(void *handle)
+{
+ struct pp_instance *instance = (struct pp_instance *)handle;
+
+ kfree(instance->hwmgr->hardcode_pp_table);
+ instance->hwmgr->hardcode_pp_table = NULL;
+
+ kfree(instance->hwmgr);
+ instance->hwmgr = NULL;
+
+ kfree(instance);
+ instance = NULL;
+ return 0;
+}
+
static int pp_early_init(void *handle)
{
int ret;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_instance *pp_handle = NULL;
- ret = smum_early_init(pp_handle);
- if (ret)
- return ret;
+ pp_handle = cgs_register_pp_handle(handle, amd_powerplay_create);
- if ((pp_handle->pm_en == 0)
- || cgs_is_virtualization_enabled(pp_handle->device))
- return PP_DPM_DISABLED;
+ if (!pp_handle)
+ return -EINVAL;
ret = hwmgr_early_init(pp_handle);
- if (ret) {
- pp_handle->pm_en = 0;
- return PP_DPM_DISABLED;
- }
-
- ret = eventmgr_early_init(pp_handle);
- if (ret) {
- kfree(pp_handle->hwmgr);
- pp_handle->hwmgr = NULL;
- pp_handle->pm_en = 0;
- return PP_DPM_DISABLED;
- }
+ if (ret)
+ return -EINVAL;
return 0;
}
static int pp_sw_init(void *handle)
{
- struct pp_smumgr *smumgr;
+ struct pp_hwmgr *hwmgr;
int ret = 0;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
ret = pp_check(pp_handle);
- if (ret == 0 || ret == PP_DPM_DISABLED) {
- smumgr = pp_handle->smu_mgr;
+ if (ret >= 0) {
+ hwmgr = pp_handle->hwmgr;
- if (smumgr->smumgr_funcs->smu_init == NULL)
+ if (hwmgr->smumgr_funcs->smu_init == NULL)
return -EINVAL;
- ret = smumgr->smumgr_funcs->smu_init(smumgr);
+ ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
pr_info("amdgpu: powerplay sw initialized\n");
}
@@ -103,84 +129,86 @@ static int pp_sw_init(void *handle)
static int pp_sw_fini(void *handle)
{
- struct pp_smumgr *smumgr;
+ struct pp_hwmgr *hwmgr;
int ret = 0;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
ret = pp_check(pp_handle);
- if (ret == 0 || ret == PP_DPM_DISABLED) {
- smumgr = pp_handle->smu_mgr;
+ if (ret >= 0) {
+ hwmgr = pp_handle->hwmgr;
- if (smumgr->smumgr_funcs->smu_fini == NULL)
+ if (hwmgr->smumgr_funcs->smu_fini == NULL)
return -EINVAL;
- ret = smumgr->smumgr_funcs->smu_fini(smumgr);
+ ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
}
return ret;
}
static int pp_hw_init(void *handle)
{
- struct pp_smumgr *smumgr;
- struct pp_eventmgr *eventmgr;
int ret = 0;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ struct pp_hwmgr *hwmgr;
ret = pp_check(pp_handle);
- if (ret == 0 || ret == PP_DPM_DISABLED) {
- smumgr = pp_handle->smu_mgr;
+ if (ret >= 0) {
+ hwmgr = pp_handle->hwmgr;
- if (smumgr->smumgr_funcs->start_smu == NULL)
+ if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- if(smumgr->smumgr_funcs->start_smu(smumgr)) {
+ if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
pr_err("smc start failed\n");
- smumgr->smumgr_funcs->smu_fini(smumgr);
+ hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
return -EINVAL;;
}
if (ret == PP_DPM_DISABLED)
- return PP_DPM_DISABLED;
+ goto exit;
+ ret = hwmgr_hw_init(pp_handle);
+ if (ret)
+ goto exit;
}
-
- ret = hwmgr_hw_init(pp_handle);
- if (ret)
- goto err;
-
- eventmgr = pp_handle->eventmgr;
- if (eventmgr->pp_eventmgr_init == NULL ||
- eventmgr->pp_eventmgr_init(eventmgr))
- goto err;
-
- return 0;
-err:
+ return ret;
+exit:
pp_handle->pm_en = 0;
- kfree(pp_handle->eventmgr);
- kfree(pp_handle->hwmgr);
- pp_handle->hwmgr = NULL;
- pp_handle->eventmgr = NULL;
- return PP_DPM_DISABLED;
+ cgs_notify_dpm_enabled(hwmgr->device, false);
+ return 0;
+
}
static int pp_hw_fini(void *handle)
{
- struct pp_eventmgr *eventmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
ret = pp_check(pp_handle);
-
- if (ret == 0) {
- eventmgr = pp_handle->eventmgr;
-
- if (eventmgr->pp_eventmgr_fini != NULL)
- eventmgr->pp_eventmgr_fini(eventmgr);
-
+ if (ret == 0)
hwmgr_hw_fini(pp_handle);
- }
+
return 0;
}
+static int pp_late_init(void *handle)
+{
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ int ret = 0;
+
+ ret = pp_check(pp_handle);
+ if (ret == 0)
+ pp_dpm_dispatch_tasks(pp_handle,
+ AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
+
+ return 0;
+}
+
+static void pp_late_fini(void *handle)
+{
+ amd_powerplay_destroy(handle);
+}
+
+
static bool pp_is_idle(void *handle)
{
return false;
@@ -196,28 +224,6 @@ static int pp_sw_reset(void *handle)
return 0;
}
-
-int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
-{
- struct pp_hwmgr *hwmgr;
- struct pp_instance *pp_handle = (struct pp_instance *)handle;
- int ret = 0;
-
- ret = pp_check(pp_handle);
-
- if (ret != 0)
- return ret;
-
- hwmgr = pp_handle->hwmgr;
-
- if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
- pr_info("%s was not implemented.\n", __func__);
- return 0;
- }
-
- return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-}
-
static int pp_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
@@ -227,7 +233,7 @@ static int pp_set_powergating_state(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -244,67 +250,52 @@ static int pp_set_powergating_state(void *handle,
static int pp_suspend(void *handle)
{
- struct pp_eventmgr *eventmgr;
- struct pem_event_data event_data = { {0} };
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
ret = pp_check(pp_handle);
-
- if (ret == PP_DPM_DISABLED)
- return 0;
- else if (ret != 0)
- return ret;
-
- eventmgr = pp_handle->eventmgr;
- pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
-
+ if (ret == 0)
+ hwmgr_hw_suspend(pp_handle);
return 0;
}
static int pp_resume(void *handle)
{
- struct pp_eventmgr *eventmgr;
- struct pem_event_data event_data = { {0} };
- struct pp_smumgr *smumgr;
- int ret, ret1;
+ struct pp_hwmgr *hwmgr;
+ int ret;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
- ret1 = pp_check(pp_handle);
+ ret = pp_check(pp_handle);
- if (ret1 != 0 && ret1 != PP_DPM_DISABLED)
- return ret1;
+ if (ret < 0)
+ return ret;
- smumgr = pp_handle->smu_mgr;
+ hwmgr = pp_handle->hwmgr;
- if (smumgr->smumgr_funcs->start_smu == NULL)
+ if (hwmgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
- ret = smumgr->smumgr_funcs->start_smu(smumgr);
- if (ret) {
+ if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
pr_err("smc start failed\n");
- smumgr->smumgr_funcs->smu_fini(smumgr);
- return ret;
+ hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
+ return -EINVAL;
}
- if (ret1 == PP_DPM_DISABLED)
+ if (ret == PP_DPM_DISABLED)
return 0;
- eventmgr = pp_handle->eventmgr;
-
- pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
-
- return 0;
+ return hwmgr_hw_resume(pp_handle);
}
const struct amd_ip_funcs pp_ip_funcs = {
.name = "powerplay",
.early_init = pp_early_init,
- .late_init = NULL,
+ .late_init = pp_late_init,
.sw_init = pp_sw_init,
.sw_fini = pp_sw_fini,
.hw_init = pp_hw_init,
.hw_fini = pp_hw_fini,
+ .late_fini = pp_late_fini,
.suspend = pp_suspend,
.resume = pp_resume,
.is_idle = pp_is_idle,
@@ -324,6 +315,63 @@ static int pp_dpm_fw_loading_complete(void *handle)
return 0;
}
+static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
+{
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+ int ret = 0;
+
+ ret = pp_check(pp_handle);
+
+ if (ret)
+ return ret;
+
+ hwmgr = pp_handle->hwmgr;
+
+ if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return 0;
+ }
+
+ return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
+}
+
+static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
+ enum amd_dpm_forced_level *level)
+{
+ uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
+ AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
+
+ if (!(hwmgr->dpm_level & profile_mode_mask)) {
+ /* enter umd pstate, save current level, disable gfx cg*/
+ if (*level & profile_mode_mask) {
+ hwmgr->saved_dpm_level = hwmgr->dpm_level;
+ hwmgr->en_umd_pstate = true;
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_CG_STATE_UNGATE);
+ cgs_set_powergating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_PG_STATE_UNGATE);
+ }
+ } else {
+ /* exit umd pstate, restore level, enable gfx cg*/
+ if (!(*level & profile_mode_mask)) {
+ if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
+ *level = hwmgr->saved_dpm_level;
+ hwmgr->en_umd_pstate = false;
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_CG_STATE_GATE);
+ cgs_set_powergating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_PG_STATE_GATE);
+ }
+ }
+}
+
static int pp_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
@@ -333,18 +381,27 @@ static int pp_dpm_force_performance_level(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
+ if (level == hwmgr->dpm_level)
+ return 0;
+
if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
mutex_lock(&pp_handle->pp_lock);
- hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
+ pp_dpm_en_umd_pstate(hwmgr, &level);
+ hwmgr->request_dpm_level = level;
+ hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
+ ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
+ if (!ret)
+ hwmgr->dpm_level = hwmgr->request_dpm_level;
+
mutex_unlock(&pp_handle->pp_lock);
return 0;
}
@@ -359,7 +416,7 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -369,15 +426,16 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
return level;
}
-static int pp_dpm_get_sclk(void *handle, bool low)
+static uint32_t pp_dpm_get_sclk(void *handle, bool low)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
+ uint32_t clk = 0;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -387,20 +445,21 @@ static int pp_dpm_get_sclk(void *handle, bool low)
return 0;
}
mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
+ clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
mutex_unlock(&pp_handle->pp_lock);
- return ret;
+ return clk;
}
-static int pp_dpm_get_mclk(void *handle, bool low)
+static uint32_t pp_dpm_get_mclk(void *handle, bool low)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
+ uint32_t clk = 0;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -410,12 +469,12 @@ static int pp_dpm_get_mclk(void *handle, bool low)
return 0;
}
mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
+ clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
mutex_unlock(&pp_handle->pp_lock);
- return ret;
+ return clk;
}
-static int pp_dpm_powergate_vce(void *handle, bool gate)
+static void pp_dpm_powergate_vce(void *handle, bool gate)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
@@ -423,22 +482,21 @@ static int pp_dpm_powergate_vce(void *handle, bool gate)
ret = pp_check(pp_handle);
- if (ret != 0)
- return ret;
+ if (ret)
+ return;
hwmgr = pp_handle->hwmgr;
if (hwmgr->hwmgr_func->powergate_vce == NULL) {
pr_info("%s was not implemented.\n", __func__);
- return 0;
+ return;
}
mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
+ hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
mutex_unlock(&pp_handle->pp_lock);
- return ret;
}
-static int pp_dpm_powergate_uvd(void *handle, bool gate)
+static void pp_dpm_powergate_uvd(void *handle, bool gate)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
@@ -446,75 +504,35 @@ static int pp_dpm_powergate_uvd(void *handle, bool gate)
ret = pp_check(pp_handle);
- if (ret != 0)
- return ret;
+ if (ret)
+ return;
hwmgr = pp_handle->hwmgr;
if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
pr_info("%s was not implemented.\n", __func__);
- return 0;
+ return;
}
mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
+ hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
mutex_unlock(&pp_handle->pp_lock);
- return ret;
}
-static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
-{
- switch (state) {
- case POWER_STATE_TYPE_BATTERY:
- return PP_StateUILabel_Battery;
- case POWER_STATE_TYPE_BALANCED:
- return PP_StateUILabel_Balanced;
- case POWER_STATE_TYPE_PERFORMANCE:
- return PP_StateUILabel_Performance;
- default:
- return PP_StateUILabel_None;
- }
-}
-
-static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
+static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
void *input, void *output)
{
int ret = 0;
- struct pem_event_data data = { {0} };
struct pp_instance *pp_handle = (struct pp_instance *)handle;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
+
mutex_lock(&pp_handle->pp_lock);
- switch (event_id) {
- case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
- ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
- break;
- case AMD_PP_EVENT_ENABLE_USER_STATE:
- {
- enum amd_pm_state_type ps;
-
- if (input == NULL) {
- ret = -EINVAL;
- break;
- }
- ps = *(unsigned long *)input;
-
- data.requested_ui_label = power_state_convert(ps);
- ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
- break;
- }
- case AMD_PP_EVENT_COMPLETE_INIT:
- ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
- break;
- case AMD_PP_EVENT_READJUST_POWER_STATE:
- ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
- break;
- default:
- break;
- }
+ ret = hwmgr_handle_task(pp_handle, task_id, input, output);
mutex_unlock(&pp_handle->pp_lock);
+
return ret;
}
@@ -528,7 +546,7 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -562,7 +580,7 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
return pm_type;
}
-static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
+static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
@@ -570,30 +588,30 @@ static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
ret = pp_check(pp_handle);
- if (ret != 0)
- return ret;
+ if (ret)
+ return;
hwmgr = pp_handle->hwmgr;
if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
- return 0;
+ return;
}
mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
+ hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
mutex_unlock(&pp_handle->pp_lock);
- return ret;
}
-static int pp_dpm_get_fan_control_mode(void *handle)
+static uint32_t pp_dpm_get_fan_control_mode(void *handle)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
+ uint32_t mode = 0;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -603,9 +621,9 @@ static int pp_dpm_get_fan_control_mode(void *handle)
return 0;
}
mutex_lock(&pp_handle->pp_lock);
- ret = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
+ mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
mutex_unlock(&pp_handle->pp_lock);
- return ret;
+ return mode;
}
static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
@@ -616,7 +634,7 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -639,7 +657,7 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -663,7 +681,7 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -685,7 +703,7 @@ static int pp_dpm_get_temperature(void *handle)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -710,7 +728,7 @@ static int pp_dpm_get_pp_num_states(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -755,7 +773,7 @@ static int pp_dpm_get_pp_table(void *handle, char **table)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -778,7 +796,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -820,7 +838,7 @@ static int pp_dpm_force_clock_level(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -844,7 +862,7 @@ static int pp_dpm_print_clock_levels(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -867,7 +885,7 @@ static int pp_dpm_get_sclk_od(void *handle)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -890,7 +908,7 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -914,7 +932,7 @@ static int pp_dpm_get_mclk_od(void *handle)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -937,7 +955,7 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -961,7 +979,7 @@ static int pp_dpm_read_sensor(void *handle, int idx,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -987,7 +1005,7 @@ pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return NULL;
hwmgr = pp_handle->hwmgr;
@@ -1128,7 +1146,7 @@ static int pp_dpm_switch_power_profile(void *handle,
return 0;
}
-const struct amd_powerplay_funcs pp_dpm_funcs = {
+const struct amd_pm_funcs pp_dpm_funcs = {
.get_temperature = pp_dpm_get_temperature,
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1160,81 +1178,27 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
.get_power_profile_state = pp_dpm_get_power_profile_state,
.set_power_profile_state = pp_dpm_set_power_profile_state,
.switch_power_profile = pp_dpm_switch_power_profile,
+ .set_clockgating_by_smu = pp_set_clockgating_by_smu,
};
-int amd_powerplay_create(struct amd_pp_init *pp_init,
- void **handle)
-{
- struct pp_instance *instance;
-
- if (pp_init == NULL || handle == NULL)
- return -EINVAL;
-
- instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
- if (instance == NULL)
- return -ENOMEM;
-
- instance->pp_valid = PP_VALID;
- instance->chip_family = pp_init->chip_family;
- instance->chip_id = pp_init->chip_id;
- instance->pm_en = pp_init->pm_en;
- instance->feature_mask = pp_init->feature_mask;
- instance->device = pp_init->device;
- mutex_init(&instance->pp_lock);
- *handle = instance;
- return 0;
-}
-
-int amd_powerplay_destroy(void *handle)
-{
- struct pp_instance *instance = (struct pp_instance *)handle;
-
- if (instance->pm_en) {
- kfree(instance->eventmgr);
- kfree(instance->hwmgr);
- instance->hwmgr = NULL;
- instance->eventmgr = NULL;
- }
-
- kfree(instance->smu_mgr);
- instance->smu_mgr = NULL;
- kfree(instance);
- instance = NULL;
- return 0;
-}
-
int amd_powerplay_reset(void *handle)
{
struct pp_instance *instance = (struct pp_instance *)handle;
- struct pp_eventmgr *eventmgr;
- struct pem_event_data event_data = { {0} };
int ret;
- if (cgs_is_virtualization_enabled(instance->smu_mgr->device))
- return PP_DPM_DISABLED;
-
ret = pp_check(instance);
- if (ret != 0)
+ if (ret)
return ret;
- ret = pp_hw_fini(handle);
+ ret = pp_hw_fini(instance);
if (ret)
return ret;
ret = hwmgr_hw_init(instance);
if (ret)
- return PP_DPM_DISABLED;
-
- eventmgr = instance->eventmgr;
-
- if (eventmgr->pp_eventmgr_init == NULL)
- return PP_DPM_DISABLED;
-
- ret = eventmgr->pp_eventmgr_init(eventmgr);
- if (ret)
return ret;
- return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
+ return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
}
/* export this function to DAL */
@@ -1248,7 +1212,7 @@ int amd_powerplay_display_configuration_change(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -1267,7 +1231,7 @@ int amd_powerplay_get_display_power_level(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -1292,7 +1256,7 @@ int amd_powerplay_get_current_clocks(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -1309,7 +1273,7 @@ int amd_powerplay_get_current_clocks(void *handle,
ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
&hw_clocks, PHM_PerformanceLevelDesignation_Activity);
- if (ret != 0) {
+ if (ret) {
pr_info("Error in phm_get_clock_info \n");
mutex_unlock(&pp_handle->pp_lock);
return -EINVAL;
@@ -1343,7 +1307,7 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
@@ -1366,7 +1330,7 @@ int amd_powerplay_get_clock_by_type_with_latency(void *handle,
int ret = 0;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
if (!clocks)
@@ -1388,7 +1352,7 @@ int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
int ret = 0;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
if (!clocks)
@@ -1412,7 +1376,7 @@ int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
int ret = 0;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
if (!wm_with_clock_ranges)
@@ -1436,7 +1400,7 @@ int amd_powerplay_display_clock_voltage_request(void *handle,
int ret = 0;
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
if (!clock)
@@ -1460,7 +1424,7 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle,
ret = pp_check(pp_handle);
- if (ret != 0)
+ if (ret)
return ret;
hwmgr = pp_handle->hwmgr;
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile b/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile
deleted file mode 100644
index 7509e38..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the 'event manager' sub-component of powerplay.
-# It provides the event management services for the driver.
-
-EVENT_MGR = eventmgr.o eventinit.o eventmanagement.o \
- eventactionchains.o eventsubchains.o eventtasks.o psm.o
-
-AMD_PP_EVENT = $(addprefix $(AMD_PP_PATH)/eventmgr/,$(EVENT_MGR))
-
-AMD_POWERPLAY_FILES += $(AMD_PP_EVENT)
-
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
deleted file mode 100644
index 8cee4e0..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "eventmgr.h"
-#include "eventactionchains.h"
-#include "eventsubchains.h"
-
-static const pem_event_action * const initialize_event[] = {
- block_adjust_power_state_tasks,
- power_budget_tasks,
- system_config_tasks,
- setup_asic_tasks,
- enable_dynamic_state_management_tasks,
- get_2d_performance_state_tasks,
- set_performance_state_tasks,
- initialize_thermal_controller_tasks,
- conditionally_force_3d_performance_state_tasks,
- process_vbios_eventinfo_tasks,
- broadcast_power_policy_tasks,
- NULL
-};
-
-const struct action_chain initialize_action_chain = {
- "Initialize",
- initialize_event
-};
-
-static const pem_event_action * const uninitialize_event[] = {
- ungate_all_display_phys_tasks,
- uninitialize_display_phy_access_tasks,
- disable_gfx_voltage_island_power_gating_tasks,
- disable_gfx_clock_gating_tasks,
- uninitialize_thermal_controller_tasks,
- set_boot_state_tasks,
- adjust_power_state_tasks,
- disable_dynamic_state_management_tasks,
- disable_clock_power_gatings_tasks,
- cleanup_asic_tasks,
- prepare_for_pnp_stop_tasks,
- NULL
-};
-
-const struct action_chain uninitialize_action_chain = {
- "Uninitialize",
- uninitialize_event
-};
-
-static const pem_event_action * const power_source_change_event_pp_enabled[] = {
- set_power_source_tasks,
- set_power_saving_state_tasks,
- adjust_power_state_tasks,
- enable_disable_fps_tasks,
- set_nbmcu_state_tasks,
- broadcast_power_policy_tasks,
- NULL
-};
-
-const struct action_chain power_source_change_action_chain_pp_enabled = {
- "Power source change - PowerPlay enabled",
- power_source_change_event_pp_enabled
-};
-
-static const pem_event_action * const power_source_change_event_pp_disabled[] = {
- set_power_source_tasks,
- set_nbmcu_state_tasks,
- NULL
-};
-
-const struct action_chain power_source_changes_action_chain_pp_disabled = {
- "Power source change - PowerPlay disabled",
- power_source_change_event_pp_disabled
-};
-
-static const pem_event_action * const power_source_change_event_hardware_dc[] = {
- set_power_source_tasks,
- set_power_saving_state_tasks,
- adjust_power_state_tasks,
- enable_disable_fps_tasks,
- reset_hardware_dc_notification_tasks,
- set_nbmcu_state_tasks,
- broadcast_power_policy_tasks,
- NULL
-};
-
-const struct action_chain power_source_change_action_chain_hardware_dc = {
- "Power source change - with Hardware DC switching",
- power_source_change_event_hardware_dc
-};
-
-static const pem_event_action * const suspend_event[] = {
- reset_display_phy_access_tasks,
- unregister_interrupt_tasks,
- disable_gfx_voltage_island_power_gating_tasks,
- disable_gfx_clock_gating_tasks,
- notify_smu_suspend_tasks,
- disable_smc_firmware_ctf_tasks,
- set_boot_state_tasks,
- adjust_power_state_tasks,
- disable_fps_tasks,
- vari_bright_suspend_tasks,
- reset_fan_speed_to_default_tasks,
- power_down_asic_tasks,
- disable_stutter_mode_tasks,
- set_connected_standby_tasks,
- block_hw_access_tasks,
- NULL
-};
-
-const struct action_chain suspend_action_chain = {
- "Suspend",
- suspend_event
-};
-
-static const pem_event_action * const resume_event[] = {
- unblock_hw_access_tasks,
- resume_connected_standby_tasks,
- notify_smu_resume_tasks,
- reset_display_configCounter_tasks,
- update_dal_configuration_tasks,
- vari_bright_resume_tasks,
- setup_asic_tasks,
- enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
- enable_dynamic_state_management_tasks,
- enable_disable_bapm_tasks,
- initialize_thermal_controller_tasks,
- get_2d_performance_state_tasks,
- set_performance_state_tasks,
- adjust_power_state_tasks,
- enable_disable_fps_tasks,
- notify_hw_power_source_tasks,
- process_vbios_event_info_tasks,
- enable_gfx_clock_gating_tasks,
- enable_gfx_voltage_island_power_gating_tasks,
- reset_clock_gating_tasks,
- notify_smu_vpu_recovery_end_tasks,
- disable_vpu_cap_tasks,
- execute_escape_sequence_tasks,
- NULL
-};
-
-
-const struct action_chain resume_action_chain = {
- "resume",
- resume_event
-};
-
-static const pem_event_action * const complete_init_event[] = {
- unblock_adjust_power_state_tasks,
- adjust_power_state_tasks,
- enable_gfx_clock_gating_tasks,
- enable_gfx_voltage_island_power_gating_tasks,
- notify_power_state_change_tasks,
- NULL
-};
-
-const struct action_chain complete_init_action_chain = {
- "complete init",
- complete_init_event
-};
-
-static const pem_event_action * const enable_gfx_clock_gating_event[] = {
- enable_gfx_clock_gating_tasks,
- NULL
-};
-
-const struct action_chain enable_gfx_clock_gating_action_chain = {
- "enable gfx clock gate",
- enable_gfx_clock_gating_event
-};
-
-static const pem_event_action * const disable_gfx_clock_gating_event[] = {
- disable_gfx_clock_gating_tasks,
- NULL
-};
-
-const struct action_chain disable_gfx_clock_gating_action_chain = {
- "disable gfx clock gate",
- disable_gfx_clock_gating_event
-};
-
-static const pem_event_action * const enable_cgpg_event[] = {
- enable_cgpg_tasks,
- NULL
-};
-
-const struct action_chain enable_cgpg_action_chain = {
- "eable cg pg",
- enable_cgpg_event
-};
-
-static const pem_event_action * const disable_cgpg_event[] = {
- disable_cgpg_tasks,
- NULL
-};
-
-const struct action_chain disable_cgpg_action_chain = {
- "disable cg pg",
- disable_cgpg_event
-};
-
-
-/* Enable user _2d performance and activate */
-
-static const pem_event_action * const enable_user_state_event[] = {
- create_new_user_performance_state_tasks,
- adjust_power_state_tasks,
- NULL
-};
-
-const struct action_chain enable_user_state_action_chain = {
- "Enable user state",
- enable_user_state_event
-};
-
-static const pem_event_action * const enable_user_2d_performance_event[] = {
- enable_user_2d_performance_tasks,
- add_user_2d_performance_state_tasks,
- set_performance_state_tasks,
- adjust_power_state_tasks,
- delete_user_2d_performance_state_tasks,
- NULL
-};
-
-const struct action_chain enable_user_2d_performance_action_chain = {
- "enable_user_2d_performance_event_activate",
- enable_user_2d_performance_event
-};
-
-
-static const pem_event_action * const disable_user_2d_performance_event[] = {
- disable_user_2d_performance_tasks,
- delete_user_2d_performance_state_tasks,
- NULL
-};
-
-const struct action_chain disable_user_2d_performance_action_chain = {
- "disable_user_2d_performance_event",
- disable_user_2d_performance_event
-};
-
-
-static const pem_event_action * const display_config_change_event[] = {
- /* countDisplayConfigurationChangeEventTasks, */
- unblock_adjust_power_state_tasks,
- set_cpu_power_state,
- notify_hw_power_source_tasks,
- get_2d_performance_state_tasks,
- set_performance_state_tasks,
- /* updateDALConfigurationTasks,
- variBrightDisplayConfigurationChangeTasks, */
- adjust_power_state_tasks,
- /*enableDisableFPSTasks,
- setNBMCUStateTasks,
- notifyPCIEDeviceReadyTasks,*/
- NULL
-};
-
-const struct action_chain display_config_change_action_chain = {
- "Display configuration change",
- display_config_change_event
-};
-
-static const pem_event_action * const readjust_power_state_event[] = {
- adjust_power_state_tasks,
- NULL
-};
-
-const struct action_chain readjust_power_state_action_chain = {
- "re-adjust power state",
- readjust_power_state_event
-};
-
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h
deleted file mode 100644
index f181e53..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _EVENT_ACTION_CHAINS_H_
-#define _EVENT_ACTION_CHAINS_H_
-#include "eventmgr.h"
-
-extern const struct action_chain initialize_action_chain;
-
-extern const struct action_chain uninitialize_action_chain;
-
-extern const struct action_chain power_source_change_action_chain_pp_enabled;
-
-extern const struct action_chain power_source_changes_action_chain_pp_disabled;
-
-extern const struct action_chain power_source_change_action_chain_hardware_dc;
-
-extern const struct action_chain suspend_action_chain;
-
-extern const struct action_chain resume_action_chain;
-
-extern const struct action_chain complete_init_action_chain;
-
-extern const struct action_chain enable_gfx_clock_gating_action_chain;
-
-extern const struct action_chain disable_gfx_clock_gating_action_chain;
-
-extern const struct action_chain enable_cgpg_action_chain;
-
-extern const struct action_chain disable_cgpg_action_chain;
-
-extern const struct action_chain enable_user_2d_performance_action_chain;
-
-extern const struct action_chain disable_user_2d_performance_action_chain;
-
-extern const struct action_chain enable_user_state_action_chain;
-
-extern const struct action_chain readjust_power_state_action_chain;
-
-extern const struct action_chain display_config_change_action_chain;
-
-#endif /*_EVENT_ACTION_CHAINS_H_*/
-
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
deleted file mode 100644
index a3cd230..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "eventmgr.h"
-#include "eventinit.h"
-#include "ppinterrupt.h"
-#include "hardwaremanager.h"
-
-void pem_init_feature_info(struct pp_eventmgr *eventmgr)
-{
-
- /* PowerPlay info */
- eventmgr->ui_state_info[PP_PowerSource_AC].default_ui_lable =
- PP_StateUILabel_Performance;
-
- eventmgr->ui_state_info[PP_PowerSource_AC].current_ui_label =
- PP_StateUILabel_Performance;
-
- eventmgr->ui_state_info[PP_PowerSource_DC].default_ui_lable =
- PP_StateUILabel_Battery;
-
- eventmgr->ui_state_info[PP_PowerSource_DC].current_ui_label =
- PP_StateUILabel_Battery;
-
- if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_PowerPlaySupport)) {
- eventmgr->features[PP_Feature_PowerPlay].supported = true;
- eventmgr->features[PP_Feature_PowerPlay].version = PEM_CURRENT_POWERPLAY_FEATURE_VERSION;
- eventmgr->features[PP_Feature_PowerPlay].enabled_default = true;
- eventmgr->features[PP_Feature_PowerPlay].enabled = true;
- } else {
- eventmgr->features[PP_Feature_PowerPlay].supported = false;
- eventmgr->features[PP_Feature_PowerPlay].enabled = false;
- eventmgr->features[PP_Feature_PowerPlay].enabled_default = false;
- }
-
- eventmgr->features[PP_Feature_Force3DClock].supported = true;
- eventmgr->features[PP_Feature_Force3DClock].enabled = false;
- eventmgr->features[PP_Feature_Force3DClock].enabled_default = false;
- eventmgr->features[PP_Feature_Force3DClock].version = 1;
-
- /* over drive*/
- eventmgr->features[PP_Feature_User2DPerformance].version = 4;
- eventmgr->features[PP_Feature_User3DPerformance].version = 4;
- eventmgr->features[PP_Feature_OverdriveTest].version = 4;
-
- eventmgr->features[PP_Feature_OverDrive].version = 4;
- eventmgr->features[PP_Feature_OverDrive].enabled = false;
- eventmgr->features[PP_Feature_OverDrive].enabled_default = false;
-
- eventmgr->features[PP_Feature_User2DPerformance].supported = false;
- eventmgr->features[PP_Feature_User2DPerformance].enabled = false;
- eventmgr->features[PP_Feature_User2DPerformance].enabled_default = false;
-
- eventmgr->features[PP_Feature_User3DPerformance].supported = false;
- eventmgr->features[PP_Feature_User3DPerformance].enabled = false;
- eventmgr->features[PP_Feature_User3DPerformance].enabled_default = false;
-
- eventmgr->features[PP_Feature_OverdriveTest].supported = false;
- eventmgr->features[PP_Feature_OverdriveTest].enabled = false;
- eventmgr->features[PP_Feature_OverdriveTest].enabled_default = false;
-
- eventmgr->features[PP_Feature_OverDrive].supported = false;
-
- eventmgr->features[PP_Feature_PowerBudgetWaiver].enabled_default = false;
- eventmgr->features[PP_Feature_PowerBudgetWaiver].version = 1;
- eventmgr->features[PP_Feature_PowerBudgetWaiver].supported = false;
- eventmgr->features[PP_Feature_PowerBudgetWaiver].enabled = false;
-
- /* Multi UVD States support */
- eventmgr->features[PP_Feature_MultiUVDState].supported = false;
- eventmgr->features[PP_Feature_MultiUVDState].enabled = false;
- eventmgr->features[PP_Feature_MultiUVDState].enabled_default = false;
-
- /* Dynamic UVD States support */
- eventmgr->features[PP_Feature_DynamicUVDState].supported = false;
- eventmgr->features[PP_Feature_DynamicUVDState].enabled = false;
- eventmgr->features[PP_Feature_DynamicUVDState].enabled_default = false;
-
- /* VCE DPM support */
- eventmgr->features[PP_Feature_VCEDPM].supported = false;
- eventmgr->features[PP_Feature_VCEDPM].enabled = false;
- eventmgr->features[PP_Feature_VCEDPM].enabled_default = false;
-
- /* ACP PowerGating support */
- eventmgr->features[PP_Feature_ACP_POWERGATING].supported = false;
- eventmgr->features[PP_Feature_ACP_POWERGATING].enabled = false;
- eventmgr->features[PP_Feature_ACP_POWERGATING].enabled_default = false;
-
- /* PPM support */
- eventmgr->features[PP_Feature_PPM].version = 1;
- eventmgr->features[PP_Feature_PPM].supported = false;
- eventmgr->features[PP_Feature_PPM].enabled = false;
-
- /* FFC support (enables fan and temp settings, Gemini needs temp settings) */
- if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_ODFuzzyFanControlSupport) ||
- phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_GeminiRegulatorFanControlSupport)) {
- eventmgr->features[PP_Feature_FFC].version = 1;
- eventmgr->features[PP_Feature_FFC].supported = true;
- eventmgr->features[PP_Feature_FFC].enabled = true;
- eventmgr->features[PP_Feature_FFC].enabled_default = true;
- } else {
- eventmgr->features[PP_Feature_FFC].supported = false;
- eventmgr->features[PP_Feature_FFC].enabled = false;
- eventmgr->features[PP_Feature_FFC].enabled_default = false;
- }
-
- eventmgr->features[PP_Feature_VariBright].supported = false;
- eventmgr->features[PP_Feature_VariBright].enabled = false;
- eventmgr->features[PP_Feature_VariBright].enabled_default = false;
-
- eventmgr->features[PP_Feature_BACO].supported = false;
- eventmgr->features[PP_Feature_BACO].supported = false;
- eventmgr->features[PP_Feature_BACO].enabled_default = false;
-
- /* PowerDown feature support */
- eventmgr->features[PP_Feature_PowerDown].supported = false;
- eventmgr->features[PP_Feature_PowerDown].enabled = false;
- eventmgr->features[PP_Feature_PowerDown].enabled_default = false;
-
- eventmgr->features[PP_Feature_FPS].version = 1;
- eventmgr->features[PP_Feature_FPS].supported = false;
- eventmgr->features[PP_Feature_FPS].enabled_default = false;
- eventmgr->features[PP_Feature_FPS].enabled = false;
-
- eventmgr->features[PP_Feature_ViPG].version = 1;
- eventmgr->features[PP_Feature_ViPG].supported = false;
- eventmgr->features[PP_Feature_ViPG].enabled_default = false;
- eventmgr->features[PP_Feature_ViPG].enabled = false;
-}
-
-static int thermal_interrupt_callback(void *private_data,
- unsigned src_id, const uint32_t *iv_entry)
-{
- /* TO DO hanle PEM_Event_ThermalNotification (struct pp_eventmgr *)private_data*/
- pr_info("current thermal is out of range \n");
- return 0;
-}
-
-int pem_register_interrupts(struct pp_eventmgr *eventmgr)
-{
- int result = 0;
- struct pp_interrupt_registration_info info;
-
- info.call_back = thermal_interrupt_callback;
- info.context = eventmgr;
-
- result = phm_register_thermal_interrupt(eventmgr->hwmgr, &info);
-
- /* TODO:
- * 2. Register CTF event interrupt
- * 3. Register for vbios events interrupt
- * 4. Register External Throttle Interrupt
- * 5. Register Smc To Host Interrupt
- * */
- return result;
-}
-
-
-int pem_unregister_interrupts(struct pp_eventmgr *eventmgr)
-{
- return 0;
-}
-
-
-void pem_uninit_featureInfo(struct pp_eventmgr *eventmgr)
-{
- eventmgr->features[PP_Feature_MultiUVDState].supported = false;
- eventmgr->features[PP_Feature_VariBright].supported = false;
- eventmgr->features[PP_Feature_PowerBudgetWaiver].supported = false;
- eventmgr->features[PP_Feature_OverDrive].supported = false;
- eventmgr->features[PP_Feature_OverdriveTest].supported = false;
- eventmgr->features[PP_Feature_User3DPerformance].supported = false;
- eventmgr->features[PP_Feature_User2DPerformance].supported = false;
- eventmgr->features[PP_Feature_PowerPlay].supported = false;
- eventmgr->features[PP_Feature_Force3DClock].supported = false;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
deleted file mode 100644
index cd1ca07..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "eventmanagement.h"
-#include "eventmgr.h"
-#include "eventactionchains.h"
-
-int pem_init_event_action_chains(struct pp_eventmgr *eventmgr)
-{
- int i;
-
- for (i = 0; i < AMD_PP_EVENT_MAX; i++)
- eventmgr->event_chain[i] = NULL;
-
- eventmgr->event_chain[AMD_PP_EVENT_SUSPEND] = pem_get_suspend_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_INITIALIZE] = pem_get_initialize_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_UNINITIALIZE] = pem_get_uninitialize_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_POWER_SOURCE_CHANGE] = pem_get_power_source_change_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_HIBERNATE] = pem_get_hibernate_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_RESUME] = pem_get_resume_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_THERMAL_NOTIFICATION] = pem_get_thermal_notification_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_VBIOS_NOTIFICATION] = pem_get_vbios_notification_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_ENTER_THERMAL_STATE] = pem_get_enter_thermal_state_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_EXIT_THERMAL_STATE] = pem_get_exit_thermal_state_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_ENABLE_POWER_PLAY] = pem_get_enable_powerplay_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_DISABLE_POWER_PLAY] = pem_get_disable_powerplay_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST] = pem_get_enable_overdrive_test_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST] = pem_get_disable_overdrive_test_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING] = pem_get_enable_gfx_clock_gating_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING] = pem_get_disable_gfx_clock_gating_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_ENABLE_CGPG] = pem_get_enable_cgpg_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_DISABLE_CGPG] = pem_get_disable_cgpg_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_COMPLETE_INIT] = pem_get_complete_init_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_SCREEN_ON] = pem_get_screen_on_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_SCREEN_OFF] = pem_get_screen_off_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_PRE_SUSPEND] = pem_get_pre_suspend_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_PRE_RESUME] = pem_get_pre_resume_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_ENABLE_USER_STATE] = pem_enable_user_state_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_READJUST_POWER_STATE] = pem_readjust_power_state_action_chain(eventmgr);
- eventmgr->event_chain[AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE] = pem_display_config_change_action_chain(eventmgr);
- return 0;
-}
-
-int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data)
-{
- const pem_event_action * const *paction_chain;
- const pem_event_action *psub_chain;
- int tmp_result = 0;
- int result = 0;
-
- if (eventmgr == NULL || event_chain == NULL || event_data == NULL)
- return -EINVAL;
-
- for (paction_chain = event_chain->action_chain; NULL != *paction_chain; paction_chain++) {
- if (0 != result)
- return result;
-
- for (psub_chain = *paction_chain; NULL != *psub_chain; psub_chain++) {
- tmp_result = (*psub_chain)(eventmgr, event_data);
- if (0 == result)
- result = tmp_result;
- }
- }
-
- return result;
-}
-
-const struct action_chain *pem_get_suspend_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &suspend_action_chain;
-}
-
-const struct action_chain *pem_get_initialize_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &initialize_action_chain;
-}
-
-const struct action_chain *pem_get_uninitialize_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &uninitialize_action_chain;
-}
-
-const struct action_chain *pem_get_power_source_change_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &power_source_change_action_chain_pp_enabled; /* other case base on feature info*/
-}
-
-const struct action_chain *pem_get_resume_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &resume_action_chain;
-}
-
-const struct action_chain *pem_get_hibernate_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_thermal_notification_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_vbios_notification_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_enter_thermal_state_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_exit_thermal_state_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_enable_powerplay_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_disable_powerplay_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_enable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_disable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_enable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &enable_gfx_clock_gating_action_chain;
-}
-
-const struct action_chain *pem_get_disable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &disable_gfx_clock_gating_action_chain;
-}
-
-const struct action_chain *pem_get_enable_cgpg_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &enable_cgpg_action_chain;
-}
-
-const struct action_chain *pem_get_disable_cgpg_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &disable_cgpg_action_chain;
-}
-
-const struct action_chain *pem_get_complete_init_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &complete_init_action_chain;
-}
-
-const struct action_chain *pem_get_screen_on_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_screen_off_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_pre_suspend_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_get_pre_resume_action_chain(struct pp_eventmgr *eventmgr)
-{
- return NULL;
-}
-
-const struct action_chain *pem_enable_user_state_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &enable_user_state_action_chain;
-}
-
-const struct action_chain *pem_readjust_power_state_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &readjust_power_state_action_chain;
-}
-
-const struct action_chain *pem_display_config_change_action_chain(struct pp_eventmgr *eventmgr)
-{
- return &display_config_change_action_chain;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h
deleted file mode 100644
index 383d4b2..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _EVENT_MANAGEMENT_H_
-#define _EVENT_MANAGEMENT_H_
-
-#include "eventmgr.h"
-
-int pem_init_event_action_chains(struct pp_eventmgr *eventmgr);
-int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data);
-const struct action_chain *pem_get_suspend_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_initialize_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_uninitialize_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_power_source_change_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_resume_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_hibernate_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_thermal_notification_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_vbios_notification_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_enter_thermal_state_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_exit_thermal_state_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_enable_powerplay_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_disable_powerplay_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_enable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_disable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_enable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_disable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_enable_cgpg_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_disable_cgpg_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_complete_init_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_screen_on_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_screen_off_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_pre_suspend_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_get_pre_resume_action_chain(struct pp_eventmgr *eventmgr);
-
-extern const struct action_chain *pem_enable_user_state_action_chain(struct pp_eventmgr *eventmgr);
-extern const struct action_chain *pem_readjust_power_state_action_chain(struct pp_eventmgr *eventmgr);
-const struct action_chain *pem_display_config_change_action_chain(struct pp_eventmgr *eventmgr);
-
-
-#endif /* _EVENT_MANAGEMENT_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
deleted file mode 100644
index 3e3ca03..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include "eventmgr.h"
-#include "hwmgr.h"
-#include "eventinit.h"
-#include "eventmanagement.h"
-
-static int pem_init(struct pp_eventmgr *eventmgr)
-{
- int result = 0;
- struct pem_event_data event_data = { {0} };
-
- /* Initialize PowerPlay feature info */
- pem_init_feature_info(eventmgr);
-
- /* Initialize event action chains */
- pem_init_event_action_chains(eventmgr);
-
- /* Call initialization event */
- result = pem_handle_event(eventmgr, AMD_PP_EVENT_INITIALIZE, &event_data);
-
- /* if (0 != result)
- return result; */
-
- /* Register interrupt callback functions */
- result = pem_register_interrupts(eventmgr);
- return 0;
-}
-
-static void pem_fini(struct pp_eventmgr *eventmgr)
-{
- struct pem_event_data event_data = { {0} };
-
- pem_uninit_featureInfo(eventmgr);
- pem_unregister_interrupts(eventmgr);
-
- pem_handle_event(eventmgr, AMD_PP_EVENT_UNINITIALIZE, &event_data);
-}
-
-int eventmgr_early_init(struct pp_instance *handle)
-{
- struct pp_eventmgr *eventmgr;
-
- if (handle == NULL)
- return -EINVAL;
-
- eventmgr = kzalloc(sizeof(struct pp_eventmgr), GFP_KERNEL);
- if (eventmgr == NULL)
- return -ENOMEM;
-
- eventmgr->hwmgr = handle->hwmgr;
- handle->eventmgr = eventmgr;
-
- eventmgr->platform_descriptor = &(eventmgr->hwmgr->platform_descriptor);
- eventmgr->pp_eventmgr_init = pem_init;
- eventmgr->pp_eventmgr_fini = pem_fini;
-
- return 0;
-}
-
-static int pem_handle_event_unlocked(struct pp_eventmgr *eventmgr, enum amd_pp_event event, struct pem_event_data *data)
-{
- if (eventmgr == NULL || event >= AMD_PP_EVENT_MAX || data == NULL)
- return -EINVAL;
-
- return pem_excute_event_chain(eventmgr, eventmgr->event_chain[event], data);
-}
-
-int pem_handle_event(struct pp_eventmgr *eventmgr, enum amd_pp_event event, struct pem_event_data *event_data)
-{
- int r = 0;
-
- r = pem_handle_event_unlocked(eventmgr, event, event_data);
-
- return r;
-}
-
-bool pem_is_hw_access_blocked(struct pp_eventmgr *eventmgr)
-{
- return (eventmgr->block_adjust_power_state || phm_is_hw_access_blocked(eventmgr->hwmgr));
-}
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
deleted file mode 100644
index b82c43a..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "eventmgr.h"
-#include "eventsubchains.h"
-#include "eventtasks.h"
-#include "hardwaremanager.h"
-
-const pem_event_action reset_display_phy_access_tasks[] = {
- pem_task_reset_display_phys_access,
- NULL
-};
-
-const pem_event_action broadcast_power_policy_tasks[] = {
- /* PEM_Task_BroadcastPowerPolicyChange, */
- NULL
-};
-
-const pem_event_action unregister_interrupt_tasks[] = {
- pem_task_unregister_interrupts,
- NULL
-};
-
-/* Disable GFX Voltage Islands Power Gating */
-const pem_event_action disable_gfx_voltage_island_powergating_tasks[] = {
- pem_task_disable_voltage_island_power_gating,
- NULL
-};
-
-const pem_event_action disable_gfx_clockgating_tasks[] = {
- pem_task_disable_gfx_clock_gating,
- NULL
-};
-
-const pem_event_action block_adjust_power_state_tasks[] = {
- pem_task_block_adjust_power_state,
- NULL
-};
-
-
-const pem_event_action unblock_adjust_power_state_tasks[] = {
- pem_task_unblock_adjust_power_state,
- NULL
-};
-
-const pem_event_action set_performance_state_tasks[] = {
- pem_task_set_performance_state,
- NULL
-};
-
-const pem_event_action get_2d_performance_state_tasks[] = {
- pem_task_get_2D_performance_state_id,
- NULL
-};
-
-const pem_event_action conditionally_force3D_performance_state_tasks[] = {
- pem_task_conditionally_force_3d_performance_state,
- NULL
-};
-
-const pem_event_action process_vbios_eventinfo_tasks[] = {
- /* PEM_Task_ProcessVbiosEventInfo,*/
- NULL
-};
-
-const pem_event_action enable_dynamic_state_management_tasks[] = {
- /* PEM_Task_ResetBAPMPolicyChangedFlag,*/
- pem_task_get_boot_state_id,
- pem_task_enable_dynamic_state_management,
- pem_task_register_interrupts,
- NULL
-};
-
-const pem_event_action enable_clock_power_gatings_tasks[] = {
- pem_task_enable_clock_power_gatings_tasks,
- pem_task_powerdown_uvd_tasks,
- pem_task_powerdown_vce_tasks,
- NULL
-};
-
-const pem_event_action setup_asic_tasks[] = {
- pem_task_setup_asic,
- NULL
-};
-
-const pem_event_action power_budget_tasks[] = {
- /* TODO
- * PEM_Task_PowerBudgetWaiverAvailable,
- * PEM_Task_PowerBudgetWarningMessage,
- * PEM_Task_PruneStatesBasedOnPowerBudget,
- */
- NULL
-};
-
-const pem_event_action system_config_tasks[] = {
- /* PEM_Task_PruneStatesBasedOnSystemConfig,*/
- NULL
-};
-
-
-const pem_event_action conditionally_force_3d_performance_state_tasks[] = {
- pem_task_conditionally_force_3d_performance_state,
- NULL
-};
-
-const pem_event_action ungate_all_display_phys_tasks[] = {
- /* PEM_Task_GetDisplayPhyAccessInfo */
- NULL
-};
-
-const pem_event_action uninitialize_display_phy_access_tasks[] = {
- /* PEM_Task_UninitializeDisplayPhysAccess, */
- NULL
-};
-
-const pem_event_action disable_gfx_voltage_island_power_gating_tasks[] = {
- /* PEM_Task_DisableVoltageIslandPowerGating, */
- NULL
-};
-
-const pem_event_action disable_gfx_clock_gating_tasks[] = {
- pem_task_disable_gfx_clock_gating,
- NULL
-};
-
-const pem_event_action set_boot_state_tasks[] = {
- pem_task_get_boot_state_id,
- pem_task_set_boot_state,
- NULL
-};
-
-const pem_event_action adjust_power_state_tasks[] = {
- pem_task_notify_hw_mgr_display_configuration_change,
- pem_task_adjust_power_state,
- pem_task_notify_smc_display_config_after_power_state_adjustment,
- pem_task_update_allowed_performance_levels,
- /* to do pem_task_Enable_disable_bapm, */
- NULL
-};
-
-const pem_event_action disable_dynamic_state_management_tasks[] = {
- pem_task_unregister_interrupts,
- pem_task_get_boot_state_id,
- pem_task_disable_dynamic_state_management,
- NULL
-};
-
-const pem_event_action disable_clock_power_gatings_tasks[] = {
- pem_task_disable_clock_power_gatings_tasks,
- NULL
-};
-
-const pem_event_action cleanup_asic_tasks[] = {
- /* PEM_Task_DisableFPS,*/
- pem_task_cleanup_asic,
- NULL
-};
-
-const pem_event_action prepare_for_pnp_stop_tasks[] = {
- /* PEM_Task_PrepareForPnpStop,*/
- NULL
-};
-
-const pem_event_action set_power_source_tasks[] = {
- pem_task_set_power_source,
- pem_task_notify_hw_of_power_source,
- NULL
-};
-
-const pem_event_action set_power_saving_state_tasks[] = {
- pem_task_reset_power_saving_state,
- pem_task_get_power_saving_state,
- pem_task_set_power_saving_state,
- /* PEM_Task_ResetODDCState,
- * PEM_Task_GetODDCState,
- * PEM_Task_SetODDCState,*/
- NULL
-};
-
-const pem_event_action enable_disable_fps_tasks[] = {
- /* PEM_Task_EnableDisableFPS,*/
- NULL
-};
-
-const pem_event_action set_nbmcu_state_tasks[] = {
- /* PEM_Task_NBMCUStateChange,*/
- NULL
-};
-
-const pem_event_action reset_hardware_dc_notification_tasks[] = {
- /* PEM_Task_ResetHardwareDCNotification,*/
- NULL
-};
-
-
-const pem_event_action notify_smu_suspend_tasks[] = {
- /* PEM_Task_NotifySMUSuspend,*/
- NULL
-};
-
-const pem_event_action disable_smc_firmware_ctf_tasks[] = {
- pem_task_disable_smc_firmware_ctf,
- NULL
-};
-
-const pem_event_action disable_fps_tasks[] = {
- /* PEM_Task_DisableFPS,*/
- NULL
-};
-
-const pem_event_action vari_bright_suspend_tasks[] = {
- /* PEM_Task_VariBright_Suspend,*/
- NULL
-};
-
-const pem_event_action reset_fan_speed_to_default_tasks[] = {
- /* PEM_Task_ResetFanSpeedToDefault,*/
- NULL
-};
-
-const pem_event_action power_down_asic_tasks[] = {
- /* PEM_Task_DisableFPS,*/
- pem_task_power_down_asic,
- NULL
-};
-
-const pem_event_action disable_stutter_mode_tasks[] = {
- /* PEM_Task_DisableStutterMode,*/
- NULL
-};
-
-const pem_event_action set_connected_standby_tasks[] = {
- /* PEM_Task_SetConnectedStandby,*/
- NULL
-};
-
-const pem_event_action block_hw_access_tasks[] = {
- pem_task_block_hw_access,
- NULL
-};
-
-const pem_event_action unblock_hw_access_tasks[] = {
- pem_task_un_block_hw_access,
- NULL
-};
-
-const pem_event_action resume_connected_standby_tasks[] = {
- /* PEM_Task_ResumeConnectedStandby,*/
- NULL
-};
-
-const pem_event_action notify_smu_resume_tasks[] = {
- /* PEM_Task_NotifySMUResume,*/
- NULL
-};
-
-const pem_event_action reset_display_configCounter_tasks[] = {
- pem_task_reset_display_phys_access,
- NULL
-};
-
-const pem_event_action update_dal_configuration_tasks[] = {
- /* PEM_Task_CheckVBlankTime,*/
- NULL
-};
-
-const pem_event_action vari_bright_resume_tasks[] = {
- /* PEM_Task_VariBright_Resume,*/
- NULL
-};
-
-const pem_event_action notify_hw_power_source_tasks[] = {
- pem_task_notify_hw_of_power_source,
- NULL
-};
-
-const pem_event_action process_vbios_event_info_tasks[] = {
- /* PEM_Task_ProcessVbiosEventInfo,*/
- NULL
-};
-
-const pem_event_action enable_gfx_clock_gating_tasks[] = {
- pem_task_enable_gfx_clock_gating,
- NULL
-};
-
-const pem_event_action enable_gfx_voltage_island_power_gating_tasks[] = {
- pem_task_enable_voltage_island_power_gating,
- NULL
-};
-
-const pem_event_action reset_clock_gating_tasks[] = {
- /* PEM_Task_ResetClockGating*/
- NULL
-};
-
-const pem_event_action notify_smu_vpu_recovery_end_tasks[] = {
- /* PEM_Task_NotifySmuVPURecoveryEnd,*/
- NULL
-};
-
-const pem_event_action disable_vpu_cap_tasks[] = {
- /* PEM_Task_DisableVPUCap,*/
- NULL
-};
-
-const pem_event_action execute_escape_sequence_tasks[] = {
- /* PEM_Task_ExecuteEscapesequence,*/
- NULL
-};
-
-const pem_event_action notify_power_state_change_tasks[] = {
- pem_task_notify_power_state_change,
- NULL
-};
-
-const pem_event_action enable_cgpg_tasks[] = {
- pem_task_enable_cgpg,
- NULL
-};
-
-const pem_event_action disable_cgpg_tasks[] = {
- pem_task_disable_cgpg,
- NULL
-};
-
-const pem_event_action enable_user_2d_performance_tasks[] = {
- /* PEM_Task_SetUser2DPerformanceFlag,*/
- /* PEM_Task_UpdateUser2DPerformanceEnableEvents,*/
- NULL
-};
-
-const pem_event_action add_user_2d_performance_state_tasks[] = {
- /* PEM_Task_Get2DPerformanceTemplate,*/
- /* PEM_Task_AllocateNewPowerStateMemory,*/
- /* PEM_Task_CopyNewPowerStateInfo,*/
- /* PEM_Task_UpdateNewPowerStateClocks,*/
- /* PEM_Task_UpdateNewPowerStateUser2DPerformanceFlag,*/
- /* PEM_Task_AddPowerState,*/
- /* PEM_Task_ReleaseNewPowerStateMemory,*/
- NULL
-};
-
-const pem_event_action delete_user_2d_performance_state_tasks[] = {
- /* PEM_Task_GetCurrentUser2DPerformanceStateID,*/
- /* PEM_Task_DeletePowerState,*/
- /* PEM_Task_SetCurrentUser2DPerformanceStateID,*/
- NULL
-};
-
-const pem_event_action disable_user_2d_performance_tasks[] = {
- /* PEM_Task_ResetUser2DPerformanceFlag,*/
- /* PEM_Task_UpdateUser2DPerformanceDisableEvents,*/
- NULL
-};
-
-const pem_event_action enable_stutter_mode_tasks[] = {
- pem_task_enable_stutter_mode,
- NULL
-};
-
-const pem_event_action enable_disable_bapm_tasks[] = {
- /*PEM_Task_EnableDisableBAPM,*/
- NULL
-};
-
-const pem_event_action reset_boot_state_tasks[] = {
- pem_task_reset_boot_state,
- NULL
-};
-
-const pem_event_action create_new_user_performance_state_tasks[] = {
- pem_task_create_user_performance_state,
- NULL
-};
-
-const pem_event_action initialize_thermal_controller_tasks[] = {
- pem_task_initialize_thermal_controller,
- NULL
-};
-
-const pem_event_action uninitialize_thermal_controller_tasks[] = {
- pem_task_uninitialize_thermal_controller,
- NULL
-};
-
-const pem_event_action set_cpu_power_state[] = {
- pem_task_set_cpu_power_state,
- NULL
-};
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
deleted file mode 100644
index 7714cb92..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _EVENT_SUB_CHAINS_H_
-#define _EVENT_SUB_CHAINS_H_
-
-#include "eventmgr.h"
-
-extern const pem_event_action reset_display_phy_access_tasks[];
-extern const pem_event_action broadcast_power_policy_tasks[];
-extern const pem_event_action unregister_interrupt_tasks[];
-extern const pem_event_action disable_GFX_voltage_island_powergating_tasks[];
-extern const pem_event_action disable_GFX_clockgating_tasks[];
-extern const pem_event_action block_adjust_power_state_tasks[];
-extern const pem_event_action unblock_adjust_power_state_tasks[];
-extern const pem_event_action set_performance_state_tasks[];
-extern const pem_event_action get_2D_performance_state_tasks[];
-extern const pem_event_action conditionally_force3D_performance_state_tasks[];
-extern const pem_event_action process_vbios_eventinfo_tasks[];
-extern const pem_event_action enable_dynamic_state_management_tasks[];
-extern const pem_event_action enable_clock_power_gatings_tasks[];
-extern const pem_event_action conditionally_force3D_performance_state_tasks[];
-extern const pem_event_action setup_asic_tasks[];
-extern const pem_event_action power_budget_tasks[];
-extern const pem_event_action system_config_tasks[];
-extern const pem_event_action get_2d_performance_state_tasks[];
-extern const pem_event_action conditionally_force_3d_performance_state_tasks[];
-extern const pem_event_action ungate_all_display_phys_tasks[];
-extern const pem_event_action uninitialize_display_phy_access_tasks[];
-extern const pem_event_action disable_gfx_voltage_island_power_gating_tasks[];
-extern const pem_event_action disable_gfx_clock_gating_tasks[];
-extern const pem_event_action set_boot_state_tasks[];
-extern const pem_event_action adjust_power_state_tasks[];
-extern const pem_event_action disable_dynamic_state_management_tasks[];
-extern const pem_event_action disable_clock_power_gatings_tasks[];
-extern const pem_event_action cleanup_asic_tasks[];
-extern const pem_event_action prepare_for_pnp_stop_tasks[];
-extern const pem_event_action set_power_source_tasks[];
-extern const pem_event_action set_power_saving_state_tasks[];
-extern const pem_event_action enable_disable_fps_tasks[];
-extern const pem_event_action set_nbmcu_state_tasks[];
-extern const pem_event_action reset_hardware_dc_notification_tasks[];
-extern const pem_event_action notify_smu_suspend_tasks[];
-extern const pem_event_action disable_smc_firmware_ctf_tasks[];
-extern const pem_event_action disable_fps_tasks[];
-extern const pem_event_action vari_bright_suspend_tasks[];
-extern const pem_event_action reset_fan_speed_to_default_tasks[];
-extern const pem_event_action power_down_asic_tasks[];
-extern const pem_event_action disable_stutter_mode_tasks[];
-extern const pem_event_action set_connected_standby_tasks[];
-extern const pem_event_action block_hw_access_tasks[];
-extern const pem_event_action unblock_hw_access_tasks[];
-extern const pem_event_action resume_connected_standby_tasks[];
-extern const pem_event_action notify_smu_resume_tasks[];
-extern const pem_event_action reset_display_configCounter_tasks[];
-extern const pem_event_action update_dal_configuration_tasks[];
-extern const pem_event_action vari_bright_resume_tasks[];
-extern const pem_event_action notify_hw_power_source_tasks[];
-extern const pem_event_action process_vbios_event_info_tasks[];
-extern const pem_event_action enable_gfx_clock_gating_tasks[];
-extern const pem_event_action enable_gfx_voltage_island_power_gating_tasks[];
-extern const pem_event_action reset_clock_gating_tasks[];
-extern const pem_event_action notify_smu_vpu_recovery_end_tasks[];
-extern const pem_event_action disable_vpu_cap_tasks[];
-extern const pem_event_action execute_escape_sequence_tasks[];
-extern const pem_event_action notify_power_state_change_tasks[];
-extern const pem_event_action enable_cgpg_tasks[];
-extern const pem_event_action disable_cgpg_tasks[];
-extern const pem_event_action enable_user_2d_performance_tasks[];
-extern const pem_event_action add_user_2d_performance_state_tasks[];
-extern const pem_event_action delete_user_2d_performance_state_tasks[];
-extern const pem_event_action disable_user_2d_performance_tasks[];
-extern const pem_event_action enable_stutter_mode_tasks[];
-extern const pem_event_action enable_disable_bapm_tasks[];
-extern const pem_event_action reset_boot_state_tasks[];
-extern const pem_event_action create_new_user_performance_state_tasks[];
-extern const pem_event_action initialize_thermal_controller_tasks[];
-extern const pem_event_action uninitialize_thermal_controller_tasks[];
-extern const pem_event_action set_cpu_power_state[];
-#endif /* _EVENT_SUB_CHAINS_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
deleted file mode 100644
index 8c4ebaa..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "eventmgr.h"
-#include "eventinit.h"
-#include "eventmanagement.h"
-#include "eventmanager.h"
-#include "hardwaremanager.h"
-#include "eventtasks.h"
-#include "power_state.h"
-#include "hwmgr.h"
-#include "amd_powerplay.h"
-#include "psm.h"
-
-#define TEMP_RANGE_MIN (90 * 1000)
-#define TEMP_RANGE_MAX (120 * 1000)
-
-int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
-
- if (eventmgr == NULL || eventmgr->hwmgr == NULL)
- return -EINVAL;
-
- if (pem_is_hw_access_blocked(eventmgr))
- return 0;
-
- phm_force_dpm_levels(eventmgr->hwmgr, eventmgr->hwmgr->dpm_level);
-
- return 0;
-}
-
-/* eventtasks_generic.c */
-int pem_task_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- struct pp_hwmgr *hwmgr;
-
- if (pem_is_hw_access_blocked(eventmgr))
- return 0;
-
- hwmgr = eventmgr->hwmgr;
- if (event_data->pnew_power_state != NULL)
- hwmgr->request_ps = event_data->pnew_power_state;
-
- if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
- psm_adjust_power_state_dynamic(eventmgr, event_data->skip_state_adjust_rules);
- else
- psm_adjust_power_state_static(eventmgr, event_data->skip_state_adjust_rules);
-
- return 0;
-}
-
-int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_power_down_asic(eventmgr->hwmgr);
-}
-
-int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- if (pem_is_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID))
- return psm_set_states(eventmgr, &(event_data->requested_state_id));
-
- return 0;
-}
-
-int pem_task_reset_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_update_new_power_state_clocks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_system_shutdown(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_register_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_unregister_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return pem_unregister_interrupts(eventmgr);
-}
-
-int pem_task_get_boot_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- int result;
-
- result = psm_get_state_by_classification(eventmgr,
- PP_StateClassificationFlag_Boot,
- &(event_data->requested_state_id)
- );
-
- if (0 == result)
- pem_set_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
- else
- pem_unset_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
-
- return result;
-}
-
-int pem_task_enable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_enable_dynamic_state_management(eventmgr->hwmgr);
-}
-
-int pem_task_disable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_disable_dynamic_state_management(eventmgr->hwmgr);
-}
-
-int pem_task_enable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_enable_clock_power_gatings(eventmgr->hwmgr);
-}
-
-int pem_task_powerdown_uvd_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_powerdown_uvd(eventmgr->hwmgr);
-}
-
-int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- phm_powergate_uvd(eventmgr->hwmgr, true);
- phm_powergate_vce(eventmgr->hwmgr, true);
- return 0;
-}
-
-int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- phm_disable_clock_power_gatings(eventmgr->hwmgr);
- return 0;
-}
-
-int pem_task_start_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_stop_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_disable_smc_firmware_ctf(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_disable_smc_firmware_ctf(eventmgr->hwmgr);
-}
-
-int pem_task_setup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_setup_asic(eventmgr->hwmgr);
-}
-
-int pem_task_cleanup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_store_dal_configuration(struct pp_eventmgr *eventmgr, const struct amd_display_configuration *display_config)
-{
- /* TODO */
- return 0;
- /*phm_store_dal_configuration_data(eventmgr->hwmgr, display_config) */
-}
-
-int pem_task_notify_hw_mgr_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- if (pem_is_hw_access_blocked(eventmgr))
- return 0;
-
- return phm_display_configuration_changed(eventmgr->hwmgr);
-}
-
-int pem_task_notify_hw_mgr_pre_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return 0;
-}
-
-int pem_task_notify_smc_display_config_after_power_state_adjustment(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- if (pem_is_hw_access_blocked(eventmgr))
- return 0;
-
- return phm_notify_smc_display_config_after_ps_adjustment(eventmgr->hwmgr);
-}
-
-int pem_task_block_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- eventmgr->block_adjust_power_state = true;
- /* to do PHM_ResetIPSCounter(pEventMgr->pHwMgr);*/
- return 0;
-}
-
-int pem_task_unblock_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- eventmgr->block_adjust_power_state = false;
- return 0;
-}
-
-int pem_task_notify_power_state_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_un_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_set_cpu_power_state(eventmgr->hwmgr);
-}
-
-/*powersaving*/
-
-int pem_task_set_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_notify_hw_of_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_get_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_reset_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_set_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_set_screen_state_on(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_set_screen_state_off(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_enable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_disable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_enable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_enable_clock_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-
-int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_disable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-
-/* performance */
-int pem_task_set_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- if (pem_is_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID))
- return psm_set_states(eventmgr, &(event_data->requested_state_id));
-
- return 0;
-}
-
-int pem_task_conditionally_force_3d_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_enable_stutter_mode(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- /* TODO */
- return 0;
-}
-
-int pem_task_get_2D_performance_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- int result;
-
- if (eventmgr->features[PP_Feature_PowerPlay].supported &&
- !(eventmgr->features[PP_Feature_PowerPlay].enabled))
- result = psm_get_state_by_classification(eventmgr,
- PP_StateClassificationFlag_Boot,
- &(event_data->requested_state_id));
- else if (eventmgr->features[PP_Feature_User2DPerformance].enabled)
- result = psm_get_state_by_classification(eventmgr,
- PP_StateClassificationFlag_User2DPerformance,
- &(event_data->requested_state_id));
- else
- result = psm_get_ui_state(eventmgr, PP_StateUILabel_Performance,
- &(event_data->requested_state_id));
-
- if (0 == result)
- pem_set_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
- else
- pem_unset_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
-
- return result;
-}
-
-int pem_task_create_user_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- struct pp_power_state *state;
- int table_entries;
- struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
- int i;
-
- table_entries = hwmgr->num_ps;
- state = hwmgr->ps;
-
-restart_search:
- for (i = 0; i < table_entries; i++) {
- if (state->classification.ui_label & event_data->requested_ui_label) {
- event_data->pnew_power_state = state;
- return 0;
- }
- state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- }
-
- switch (event_data->requested_ui_label) {
- case PP_StateUILabel_Battery:
- case PP_StateUILabel_Balanced:
- event_data->requested_ui_label = PP_StateUILabel_Performance;
- goto restart_search;
- default:
- break;
- }
- return -1;
-}
-
-int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- struct PP_TemperatureRange range;
-
- range.max = TEMP_RANGE_MAX;
- range.min = TEMP_RANGE_MIN;
-
- if (eventmgr == NULL || eventmgr->platform_descriptor == NULL)
- return -EINVAL;
-
- if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_ThermalController))
- return phm_start_thermal_controller(eventmgr->hwmgr, &range);
-
- return 0;
-}
-
-int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-{
- return phm_stop_thermal_controller(eventmgr->hwmgr);
-}
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
deleted file mode 100644
index 37e7ca5..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _EVENT_TASKS_H_
-#define _EVENT_TASKS_H_
-#include "eventmgr.h"
-
-struct amd_display_configuration;
-
-/* eventtasks_generic.c */
-int pem_task_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_get_boot_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_reset_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_update_new_power_state_clocks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_system_shutdown(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_register_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_unregister_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_enable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_disable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_enable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_powerdown_uvd_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_start_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_stop_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_setup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_cleanup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_store_dal_configuration (struct pp_eventmgr *eventmgr, const struct amd_display_configuration *display_config);
-int pem_task_notify_hw_mgr_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_notify_hw_mgr_pre_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_block_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_unblock_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_notify_power_state_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_un_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_notify_smc_display_config_after_power_state_adjustment(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-/*powersaving*/
-
-int pem_task_set_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_notify_hw_of_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_get_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_reset_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_set_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_set_screen_state_on(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_set_screen_state_off(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_enable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_disable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_enable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_disable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_enable_stutter_mode(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-
-/* performance */
-int pem_task_set_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_conditionally_force_3d_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_get_2D_performance_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_create_user_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-/*thermal */
-int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-int pem_task_disable_smc_firmware_ctf(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-
-#endif /* _EVENT_TASKS_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
deleted file mode 100644
index 4899088..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "psm.h"
-
-int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label, unsigned long *state_id)
-{
- struct pp_power_state *state;
- int table_entries;
- struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
- int i;
-
- table_entries = hwmgr->num_ps;
- state = hwmgr->ps;
-
- for (i = 0; i < table_entries; i++) {
- if (state->classification.ui_label & ui_label) {
- *state_id = state->id;
- return 0;
- }
- state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- }
- return -1;
-}
-
-int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateClassificationFlag flag, unsigned long *state_id)
-{
- struct pp_power_state *state;
- int table_entries;
- struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
- int i;
-
- table_entries = hwmgr->num_ps;
- state = hwmgr->ps;
-
- for (i = 0; i < table_entries; i++) {
- if (state->classification.flags & flag) {
- *state_id = state->id;
- return 0;
- }
- state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- }
- return -1;
-}
-
-int psm_set_states(struct pp_eventmgr *eventmgr, unsigned long *state_id)
-{
- struct pp_power_state *state;
- int table_entries;
- struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
- int i;
-
- table_entries = hwmgr->num_ps;
-
- state = hwmgr->ps;
-
- for (i = 0; i < table_entries; i++) {
- if (state->id == *state_id) {
- memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
- return 0;
- }
- state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- }
- return -1;
-}
-
-int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip)
-{
-
- struct pp_power_state *pcurrent;
- struct pp_power_state *requested;
- struct pp_hwmgr *hwmgr;
- bool equal;
-
- if (skip)
- return 0;
-
- hwmgr = eventmgr->hwmgr;
- pcurrent = hwmgr->current_ps;
- requested = hwmgr->request_ps;
-
- if (requested == NULL)
- return 0;
-
- phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
-
- if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr, &pcurrent->hardware, &requested->hardware, &equal)))
- equal = false;
-
- if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
- phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
- memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
- }
- return 0;
-}
-
-int psm_adjust_power_state_static(struct pp_eventmgr *eventmgr, bool skip)
-{
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
deleted file mode 100644
index fbdff3e..0000000
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "eventmgr.h"
-#include "eventinit.h"
-#include "eventmanagement.h"
-#include "eventmanager.h"
-#include "power_state.h"
-#include "hardwaremanager.h"
-
-int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label, unsigned long *state_id);
-
-int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateClassificationFlag flag, unsigned long *state_id);
-
-int psm_set_states(struct pp_eventmgr *eventmgr, unsigned long *state_id);
-
-int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip);
-
-int psm_adjust_power_state_static(struct pp_eventmgr *eventmgr, bool skip);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index d13fdad..824fb6f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -3,14 +3,15 @@
# Makefile for the 'hw manager' sub-component of powerplay.
# It provides the hardware management services for the driver.
-HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
+HARDWARE_MGR = hwmgr.o processpptables.o \
hardwaremanager.o pp_acpi.o cz_hwmgr.o \
cz_clockpowergating.o pppcielanes.o\
process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
smu7_clockpowergating.o \
vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
- vega10_thermal.o pp_overdriver.o rv_hwmgr.o
+ vega10_thermal.o rv_hwmgr.o pp_psm.o\
+ pp_overdriver.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index b33935f..44de087 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -103,16 +103,6 @@ int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
return 0;
}
-static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
-{
- return 0;
-}
-
-static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
-{
- return 0;
-}
-
int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
@@ -123,12 +113,12 @@ int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
PHM_PlatformCaps_UVDDPM)) {
cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
dpm_features |= UVD_DPM_MASK;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
} else {
dpm_features |= UVD_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
}
return 0;
@@ -144,12 +134,12 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
PHM_PlatformCaps_VCEDPM)) {
cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
dpm_features |= VCE_DPM_MASK;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
} else {
dpm_features |= VCE_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
}
@@ -157,7 +147,7 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
}
-int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
+void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
@@ -183,10 +173,9 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
cz_dpm_update_uvd_dpm(hwmgr, false);
}
- return 0;
}
-int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
+void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
@@ -215,29 +204,6 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
AMD_CG_STATE_UNGATE);
cz_dpm_update_vce_dpm(hwmgr);
cz_enable_disable_vce_dpm(hwmgr, true);
- return 0;
}
-
- return 0;
}
-
-static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
- /*we don't need an exit table here, because there is only D3 cold on Kv*/
- {
- .isFunctionNeededInRuntimeTable = phm_cf_want_uvd_power_gating,
- .tableFunction = cz_tf_uvd_power_gating_initialize
- },
- {
- .isFunctionNeededInRuntimeTable = phm_cf_want_vce_power_gating,
- .tableFunction = cz_tf_vce_power_gating_initialize
- },
- /* to do { NULL, cz_tf_xdma_power_gating_enable }, */
- { }
-};
-
-const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
- 0,
- PHM_MasterTableFlag_None,
- cz_enable_clock_power_gatings_list
-};
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
index 1954cea..92f707b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
@@ -29,8 +29,8 @@
extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
-extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
+extern void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
+extern void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
extern int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
#endif /* _CZ_CLOCK_POWER_GATING_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index bc839ff..ad1f6b5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -162,8 +162,8 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
if (cz_hwmgr->max_sclk_level == 0) {
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
- cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
+ cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1;
}
return cz_hwmgr->max_sclk_level;
@@ -440,14 +440,7 @@ static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
return 0;
}
-static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
-{
- return 0;
-}
-
-static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
{
struct SMU8_Fusion_ClkTable *clock_table;
int ret;
@@ -469,7 +462,7 @@ static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
if (!hwmgr->need_pp_table_upload)
return 0;
- ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
+ ret = smum_download_powerplay_table(hwmgr, &table);
PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
"Fail to get clock table from SMU!", return -EINVAL;);
@@ -561,13 +554,12 @@ static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
(uint8_t)dividers.pll_post_divider;
}
- ret = smum_upload_powerplay_table(hwmgr->smumgr);
+ ret = smum_upload_powerplay_table(hwmgr);
return ret;
}
-static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_clock_voltage_dependency_table *table =
@@ -593,8 +585,7 @@ static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
return 0;
}
-static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_uvd_clock_voltage_dependency_table *table =
@@ -607,8 +598,8 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
cz_hwmgr->uvd_dpm.soft_min_clk = 0;
cz_hwmgr->uvd_dpm.hard_min_clk = 0;
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
- level = smum_get_argument(hwmgr->smumgr);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
+ level = smum_get_argument(hwmgr);
if (level < table->count)
clock = table->entries[level].vclk;
@@ -621,8 +612,7 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
return 0;
}
-static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_vce_clock_voltage_dependency_table *table =
@@ -635,8 +625,8 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
cz_hwmgr->vce_dpm.soft_min_clk = 0;
cz_hwmgr->vce_dpm.hard_min_clk = 0;
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
- level = smum_get_argument(hwmgr->smumgr);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
+ level = smum_get_argument(hwmgr);
if (level < table->count)
clock = table->entries[level].ecclk;
@@ -649,8 +639,7 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
return 0;
}
-static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_acp_clock_voltage_dependency_table *table =
@@ -663,8 +652,8 @@ static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
cz_hwmgr->acp_dpm.soft_min_clk = 0;
cz_hwmgr->acp_dpm.hard_min_clk = 0;
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
- level = smum_get_argument(hwmgr->smumgr);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
+ level = smum_get_argument(hwmgr);
if (level < table->count)
clock = table->entries[level].acpclk;
@@ -676,8 +665,7 @@ static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
return 0;
}
-static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
@@ -686,22 +674,16 @@ static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
cz_hwmgr->samu_power_gated = false;
cz_hwmgr->acp_power_gated = false;
cz_hwmgr->pgacpinit = true;
-
- return 0;
}
-static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
cz_hwmgr->low_sclk_interrupt_threshold = 0;
-
- return 0;
}
-static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+
+static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_clock_voltage_dependency_table *table =
@@ -722,12 +704,12 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
clock = hwmgr->display_config.min_core_set_clock;
if (clock == 0)
- pr_info("min_core_set_clock not set\n");
+ pr_debug("min_core_set_clock not set\n");
if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
cz_hwmgr->sclk_dpm.hard_min_clk = clock;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkHardMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.hard_min_clk,
@@ -753,7 +735,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
cz_hwmgr->sclk_dpm.soft_min_clk = clock;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
@@ -764,7 +746,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
PHM_PlatformCaps_StablePState) &&
cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
cz_hwmgr->sclk_dpm.soft_max_clk = clock;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -774,9 +756,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
return 0;
}
-static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) {
@@ -786,7 +766,7 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepSclk,
clks);
}
@@ -794,51 +774,18 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
return 0;
}
-static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr =
(struct cz_hwmgr *)(hwmgr->backend);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetWatermarkFrequency,
cz_hwmgr->sclk_dpm.soft_max_clk);
return 0;
}
-static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
-{
- return 0;
-}
-
-
-static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
-{
- int ret = 0;
-
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- unsigned long dpm_features = 0;
-
- if (!cz_hwmgr->is_nb_dpm_enabled) {
- PP_DBG_LOG("enabling ALL SMU features.\n");
- dpm_features |= NB_DPM_MASK;
- ret = smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
- PPSMC_MSG_EnableAllSmuFeatures,
- dpm_features);
- if (ret == 0)
- cz_hwmgr->is_nb_dpm_enabled = true;
- }
-
- return ret;
-}
-
static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
{
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
@@ -847,13 +794,13 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b
if (enable) {
PP_DBG_LOG("enable Low Memory PState.\n");
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableLowMemoryPstate,
(lock ? 1 : 0));
} else {
PP_DBG_LOG("disable Low Memory PState.\n");
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableLowMemoryPstate,
(lock ? 1 : 0));
}
@@ -862,9 +809,49 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b
return 0;
}
-static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
+{
+ int ret = 0;
+
+ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ unsigned long dpm_features = 0;
+
+ if (cz_hwmgr->is_nb_dpm_enabled) {
+ cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
+ dpm_features |= NB_DPM_MASK;
+ ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr,
+ PPSMC_MSG_DisableAllSmuFeatures,
+ dpm_features);
+ if (ret == 0)
+ cz_hwmgr->is_nb_dpm_enabled = false;
+ }
+
+ return ret;
+}
+
+static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
+{
+ int ret = 0;
+
+ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ unsigned long dpm_features = 0;
+
+ if (!cz_hwmgr->is_nb_dpm_enabled) {
+ PP_DBG_LOG("enabling ALL SMU features.\n");
+ dpm_features |= NB_DPM_MASK;
+ ret = smum_send_msg_to_smc_with_parameter(
+ hwmgr,
+ PPSMC_MSG_EnableAllSmuFeatures,
+ dpm_features);
+ if (ret == 0)
+ cz_hwmgr->is_nb_dpm_enabled = true;
+ }
+
+ return ret;
+}
+
+static int cz_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
{
bool disable_switch;
bool enable_low_mem_state;
@@ -886,64 +873,64 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
return 0;
}
-static const struct phm_master_table_item cz_set_power_state_list[] = {
- { .tableFunction = cz_tf_update_sclk_limit },
- { .tableFunction = cz_tf_set_deep_sleep_sclk_threshold },
- { .tableFunction = cz_tf_set_watermark_threshold },
- { .tableFunction = cz_tf_set_enabled_levels },
- { .tableFunction = cz_tf_enable_nb_dpm },
- { .tableFunction = cz_tf_update_low_mem_pstate },
- { }
+static int cz_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+{
+ int ret = 0;
+
+ cz_update_sclk_limit(hwmgr);
+ cz_set_deep_sleep_sclk_threshold(hwmgr);
+ cz_set_watermark_threshold(hwmgr);
+ ret = cz_enable_nb_dpm(hwmgr);
+ if (ret)
+ return ret;
+ cz_update_low_mem_pstate(hwmgr, input);
+
+ return 0;
};
-static const struct phm_master_table_header cz_set_power_state_master = {
- 0,
- PHM_MasterTableFlag_None,
- cz_set_power_state_list
-};
-static const struct phm_master_table_item cz_setup_asic_list[] = {
- { .tableFunction = cz_tf_reset_active_process_mask },
- { .tableFunction = cz_tf_upload_pptable_to_smu },
- { .tableFunction = cz_tf_init_sclk_limit },
- { .tableFunction = cz_tf_init_uvd_limit },
- { .tableFunction = cz_tf_init_vce_limit },
- { .tableFunction = cz_tf_init_acp_limit },
- { .tableFunction = cz_tf_init_power_gate_state },
- { .tableFunction = cz_tf_init_sclk_threshold },
- { }
-};
+static int cz_setup_asic_task(struct pp_hwmgr *hwmgr)
+{
+ int ret;
-static const struct phm_master_table_header cz_setup_asic_master = {
- 0,
- PHM_MasterTableFlag_None,
- cz_setup_asic_list
-};
+ ret = cz_upload_pptable_to_smu(hwmgr);
+ if (ret)
+ return ret;
+ ret = cz_init_sclk_limit(hwmgr);
+ if (ret)
+ return ret;
+ ret = cz_init_uvd_limit(hwmgr);
+ if (ret)
+ return ret;
+ ret = cz_init_vce_limit(hwmgr);
+ if (ret)
+ return ret;
+ ret = cz_init_acp_limit(hwmgr);
+ if (ret)
+ return ret;
-static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+ cz_init_power_gate_state(hwmgr);
+ cz_init_sclk_threshold(hwmgr);
+
+ return 0;
+}
+
+static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+
hw_data->disp_clk_bypass_pending = false;
hw_data->disp_clk_bypass = false;
-
- return 0;
}
-static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- hw_data->is_nb_dpm_enabled = false;
- return 0;
+ hw_data->is_nb_dpm_enabled = false;
}
-static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
@@ -951,63 +938,68 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
hw_data->cc6_settings.cpu_pstate_separation_time = 0;
hw_data->cc6_settings.cpu_cc6_disable = false;
hw_data->cc6_settings.cpu_pstate_disable = false;
-
- return 0;
}
-static const struct phm_master_table_item cz_power_down_asic_list[] = {
- { .tableFunction = cz_tf_power_up_display_clock_sys_pll },
- { .tableFunction = cz_tf_clear_nb_dpm_flag },
- { .tableFunction = cz_tf_reset_cc6_data },
- { }
+static int cz_power_off_asic(struct pp_hwmgr *hwmgr)
+{
+ cz_power_up_display_clock_sys_pll(hwmgr);
+ cz_clear_nb_dpm_flag(hwmgr);
+ cz_reset_cc6_data(hwmgr);
+ return 0;
};
-static const struct phm_master_table_header cz_power_down_asic_master = {
- 0,
- PHM_MasterTableFlag_None,
- cz_power_down_asic_list
-};
-
-static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static void cz_program_voting_clients(struct pp_hwmgr *hwmgr)
{
PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
- return 0;
}
-static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
- void *storage, int result)
+static void cz_clear_voting_clients(struct pp_hwmgr *hwmgr)
{
- int res = 0xff;
+ PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, 0);
+}
+
+static int cz_start_dpm(struct pp_hwmgr *hwmgr)
+{
+ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+
+ cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
+
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_EnableAllSmuFeatures,
+ SCLK_DPM_MASK);
+}
+
+static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
+{
+ int ret = 0;
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
unsigned long dpm_features = 0;
- cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
- dpm_features |= SCLK_DPM_MASK;
-
- res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_EnableAllSmuFeatures,
- dpm_features);
-
- return res;
+ if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
+ dpm_features |= SCLK_DPM_MASK;
+ cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
+ ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DisableAllSmuFeatures,
+ dpm_features);
+ }
+ return ret;
}
-static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -1016,13 +1008,11 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
return 0;
}
-static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
cz_hwmgr->acp_boot_level = 0xff;
- return 0;
}
static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
@@ -1031,67 +1021,52 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
int result;
unsigned long features;
- result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
+ result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
if (result == 0) {
- features = smum_get_argument(hwmgr->smumgr);
+ features = smum_get_argument(hwmgr);
if (features & check_feature)
return true;
}
- return result;
+ return false;
}
-static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static bool cz_check_for_dpm_enabled(struct pp_hwmgr *hwmgr)
{
if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
- return PP_Result_TableImmediateExit;
- return 0;
+ return true;
+ return false;
}
-static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int cz_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
- /* TO DO */
- return 0;
-}
+ if (!cz_check_for_dpm_enabled(hwmgr)) {
+ pr_info("dpm has been disabled\n");
+ return 0;
+ }
+ cz_disable_nb_dpm(hwmgr);
-static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+ cz_clear_voting_clients(hwmgr);
+ if (cz_stop_dpm(hwmgr))
+ return -EINVAL;
+
+ return 0;
+};
+
+static int cz_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
- if (!cz_dpm_check_smu_features(hwmgr,
- SMU_EnabledFeatureScoreboard_SclkDpmOn))
- return PP_Result_TableImmediateExit;
+ if (cz_check_for_dpm_enabled(hwmgr)) {
+ pr_info("dpm has been enabled\n");
+ return 0;
+ }
+
+ cz_program_voting_clients(hwmgr);
+ if (cz_start_dpm(hwmgr))
+ return -EINVAL;
+ cz_program_bootup_state(hwmgr);
+ cz_reset_acp_boot_level(hwmgr);
+
return 0;
-}
-
-static const struct phm_master_table_item cz_disable_dpm_list[] = {
- { .tableFunction = cz_tf_check_for_dpm_enabled },
- { },
-};
-
-
-static const struct phm_master_table_header cz_disable_dpm_master = {
- 0,
- PHM_MasterTableFlag_None,
- cz_disable_dpm_list
-};
-
-static const struct phm_master_table_item cz_enable_dpm_list[] = {
- { .tableFunction = cz_tf_check_for_dpm_disabled },
- { .tableFunction = cz_tf_program_voting_clients },
- { .tableFunction = cz_tf_start_dpm },
- { .tableFunction = cz_tf_program_bootup_state },
- { .tableFunction = cz_tf_enable_didt },
- { .tableFunction = cz_tf_reset_acp_boot_level },
- { },
-};
-
-static const struct phm_master_table_header cz_enable_dpm_master = {
- 0,
- PHM_MasterTableFlag_None,
- cz_enable_dpm_list
};
static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
@@ -1138,7 +1113,11 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
cz_ps->action = cz_current_ps->action;
- if (!force_high && (cz_ps->action == FORCE_HIGH))
+ if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
+ else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
+ cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
+ else if (!force_high && (cz_ps->action == FORCE_HIGH))
cz_ps->action = CANCEL_FORCE_HIGH;
else if (force_high && (cz_ps->action != FORCE_HIGH))
cz_ps->action = FORCE_HIGH;
@@ -1173,62 +1152,16 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
cz_construct_boot_state(hwmgr);
- result = phm_construct_table(hwmgr, &cz_setup_asic_master,
- &(hwmgr->setup_asic));
- if (result != 0) {
- pr_err("Fail to construct setup ASIC\n");
- return result;
- }
-
- result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
- &(hwmgr->power_down_asic));
- if (result != 0) {
- pr_err("Fail to construct power down ASIC\n");
- return result;
- }
-
- result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
- &(hwmgr->disable_dynamic_state_management));
- if (result != 0) {
- pr_err("Fail to disable_dynamic_state\n");
- return result;
- }
- result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
- &(hwmgr->enable_dynamic_state_management));
- if (result != 0) {
- pr_err("Fail to enable_dynamic_state\n");
- return result;
- }
- result = phm_construct_table(hwmgr, &cz_set_power_state_master,
- &(hwmgr->set_power_state));
- if (result != 0) {
- pr_err("Fail to construct set_power_state\n");
- return result;
- }
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = CZ_MAX_HARDWARE_POWERLEVELS;
- result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
- if (result != 0) {
- pr_err("Fail to construct enable_clock_power_gatings\n");
- return result;
- }
return result;
}
static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
if (hwmgr != NULL) {
- phm_destroy_table(hwmgr, &(hwmgr->enable_clock_power_gatings));
- phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
- phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
- phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
- phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
- phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
-
- if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
- kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
- hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
- }
+ kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
+ hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
kfree(hwmgr->backend);
hwmgr->backend = NULL;
@@ -1240,13 +1173,13 @@ static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMin));
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -1278,13 +1211,13 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
cz_hwmgr->sclk_dpm.soft_max_clk = clock;
cz_hwmgr->sclk_dpm.hard_max_clk = clock;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
@@ -1297,13 +1230,13 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMax));
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
@@ -1312,106 +1245,25 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
return 0;
}
-static int cz_phm_force_dpm_sclk(struct pp_hwmgr *hwmgr, uint32_t sclk)
-{
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetSclkSoftMin,
- cz_get_sclk_level(hwmgr,
- sclk,
- PPSMC_MSG_SetSclkSoftMin));
-
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetSclkSoftMax,
- cz_get_sclk_level(hwmgr,
- sclk,
- PPSMC_MSG_SetSclkSoftMax));
- return 0;
-}
-
-static int cz_get_profiling_clk(struct pp_hwmgr *hwmgr, uint32_t *sclk)
-{
- struct phm_clock_voltage_dependency_table *table =
- hwmgr->dyn_state.vddc_dependency_on_sclk;
- int32_t tmp_sclk;
- int32_t count;
-
- tmp_sclk = table->entries[table->count-1].clk * 70 / 100;
-
- for (count = table->count-1; count >= 0; count--) {
- if (tmp_sclk >= table->entries[count].clk) {
- tmp_sclk = table->entries[count].clk;
- *sclk = tmp_sclk;
- break;
- }
- }
- if (count < 0)
- *sclk = table->entries[0].clk;
-
- return 0;
-}
-
static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
- uint32_t sclk = 0;
int ret = 0;
- uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
- AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
-
- if (level == hwmgr->dpm_level)
- return ret;
-
- if (!(hwmgr->dpm_level & profile_mode_mask)) {
- /* enter profile mode, save current level, disable gfx cg*/
- if (level & profile_mode_mask) {
- hwmgr->saved_dpm_level = hwmgr->dpm_level;
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_UNGATE);
- }
- } else {
- /* exit profile mode, restore level, enable gfx cg*/
- if (!(level & profile_mode_mask)) {
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
- level = hwmgr->saved_dpm_level;
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_GATE);
- }
- }
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
ret = cz_phm_force_dpm_highest(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
ret = cz_phm_force_dpm_lowest(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
ret = cz_phm_unforce_dpm_levels(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
- break;
- case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = cz_get_profiling_clk(hwmgr, &sclk);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
- cz_phm_force_dpm_sclk(hwmgr, sclk);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
- hwmgr->dpm_level = level;
- break;
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
default:
break;
@@ -1422,27 +1274,18 @@ static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDPowerGating))
- return smum_send_msg_to_smc(hwmgr->smumgr,
- PPSMC_MSG_UVDPowerOFF);
+ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
return 0;
}
int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
{
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDPowerGating)) {
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDDynamicPowerGating)) {
- return smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
- PPSMC_MSG_UVDPowerON, 1);
- } else {
- return smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
- PPSMC_MSG_UVDPowerON, 0);
- }
+ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
+ return smum_send_msg_to_smc_with_parameter(
+ hwmgr,
+ PPSMC_MSG_UVDPowerON,
+ PP_CAP(PHM_PlatformCaps_UVDDynamicPowerGating) ? 1 : 0);
}
return 0;
@@ -1456,16 +1299,16 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
if (!bgate) {
/* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState)) {
+ if (PP_CAP(PHM_PlatformCaps_StablePState) ||
+ hwmgr->en_umd_pstate) {
cz_hwmgr->uvd_dpm.hard_min_clk =
ptable->entries[ptable->count - 1].vclk;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetUvdHardMin,
- cz_get_uvd_level(hwmgr,
- cz_hwmgr->uvd_dpm.hard_min_clk,
- PPSMC_MSG_SetUvdHardMin));
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetUvdHardMin,
+ cz_get_uvd_level(hwmgr,
+ cz_hwmgr->uvd_dpm.hard_min_clk,
+ PPSMC_MSG_SetUvdHardMin));
cz_enable_disable_uvd_dpm(hwmgr, true);
} else {
@@ -1485,32 +1328,32 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState)) {
+ if (PP_CAP(PHM_PlatformCaps_StablePState) ||
+ hwmgr->en_umd_pstate) {
cz_hwmgr->vce_dpm.hard_min_clk =
ptable->entries[ptable->count - 1].ecclk;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetEclkHardMin,
- cz_get_eclk_level(hwmgr,
- cz_hwmgr->vce_dpm.hard_min_clk,
- PPSMC_MSG_SetEclkHardMin));
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetEclkHardMin,
+ cz_get_eclk_level(hwmgr,
+ cz_hwmgr->vce_dpm.hard_min_clk,
+ PPSMC_MSG_SetEclkHardMin));
} else {
/*Program HardMin based on the vce_arbiter.ecclk */
if (hwmgr->vce_arbiter.ecclk == 0) {
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin, 0);
/* disable ECLK DPM 0. Otherwise VCE could hang if
* switching SCLK from DPM 0 to 6/7 */
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkSoftMin, 1);
} else {
cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetEclkHardMin,
- cz_get_eclk_level(hwmgr,
- cz_hwmgr->vce_dpm.hard_min_clk,
- PPSMC_MSG_SetEclkHardMin));
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetEclkHardMin,
+ cz_get_eclk_level(hwmgr,
+ cz_hwmgr->vce_dpm.hard_min_clk,
+ PPSMC_MSG_SetEclkHardMin));
}
}
return 0;
@@ -1518,30 +1361,28 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
{
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_VCEPowerGating))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerOFF);
return 0;
}
int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
{
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_VCEPowerGating))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerON);
return 0;
}
-static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
return cz_hwmgr->sys_info.bootup_uma_clock;
}
-static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
struct cz_power_state *cz_ps;
@@ -1679,7 +1520,7 @@ static void cz_hw_print_display_cfg(
PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
data);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDisplaySizePowerParams,
data);
}
@@ -1744,10 +1585,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
switch (type) {
case PP_SCLK:
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
mask);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
mask);
break;
@@ -1989,7 +1830,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
*((uint32_t *)value) = 0;
return 0;
case AMDGPU_PP_SENSOR_GPU_LOAD:
- result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
+ result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
if (0 == result) {
activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
activity_percent = activity_percent > 100 ? 100 : activity_percent;
@@ -2012,10 +1853,36 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
}
}
+static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+ uint32_t virtual_addr_low,
+ uint32_t virtual_addr_hi,
+ uint32_t mc_addr_low,
+ uint32_t mc_addr_hi,
+ uint32_t size)
+{
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramAddrHiVirtual,
+ mc_addr_hi);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramAddrLoVirtual,
+ mc_addr_low);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramAddrHiPhysical,
+ virtual_addr_hi);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramAddrLoPhysical,
+ virtual_addr_low);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramBufferSize,
+ size);
+ return 0;
+}
+
+
static const struct pp_hwmgr_func cz_hwmgr_funcs = {
.backend_init = cz_hwmgr_backend_init,
.backend_fini = cz_hwmgr_backend_fini,
- .asic_setup = NULL,
.apply_state_adjust_rules = cz_apply_state_adjust_rules,
.force_dpm_level = cz_dpm_force_dpm_level,
.get_power_state_size = cz_get_power_state_size,
@@ -2036,7 +1903,14 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
.get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
.get_clock_by_type = cz_get_clock_by_type,
.get_max_high_clocks = cz_get_max_high_clocks,
+ .get_temperature = cz_thermal_get_temperature,
.read_sensor = cz_read_sensor,
+ .power_off_asic = cz_power_off_asic,
+ .asic_setup = cz_setup_asic_task,
+ .dynamic_state_management_enable = cz_enable_dpm_tasks,
+ .power_state_set = cz_set_power_state_tasks,
+ .dynamic_state_management_disable = cz_disable_dpm_tasks,
+ .notify_cac_buffer_info = cz_notify_cac_buffer_info,
};
int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
deleted file mode 100644
index bc7d8bd..0000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include "hwmgr.h"
-
-static int phm_run_table(struct pp_hwmgr *hwmgr,
- struct phm_runtime_table_header *rt_table,
- void *input,
- void *output,
- void *temp_storage)
-{
- int result = 0;
- phm_table_function *function;
-
- if (rt_table->function_list == NULL) {
- pr_debug("this function not implement!\n");
- return 0;
- }
-
- for (function = rt_table->function_list; NULL != *function; function++) {
- int tmp = (*function)(hwmgr, input, output, temp_storage, result);
-
- if (tmp == PP_Result_TableImmediateExit)
- break;
- if (tmp) {
- if (0 == result)
- result = tmp;
- if (rt_table->exit_error)
- break;
- }
- }
-
- return result;
-}
-
-int phm_dispatch_table(struct pp_hwmgr *hwmgr,
- struct phm_runtime_table_header *rt_table,
- void *input, void *output)
-{
- int result;
- void *temp_storage;
-
- if (hwmgr == NULL || rt_table == NULL) {
- pr_err("Invalid Parameter!\n");
- return -EINVAL;
- }
-
- if (0 != rt_table->storage_size) {
- temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL);
- if (temp_storage == NULL) {
- pr_err("Could not allocate table temporary storage\n");
- return -ENOMEM;
- }
- } else {
- temp_storage = NULL;
- }
-
- result = phm_run_table(hwmgr, rt_table, input, output, temp_storage);
-
- kfree(temp_storage);
-
- return result;
-}
-
-int phm_construct_table(struct pp_hwmgr *hwmgr,
- const struct phm_master_table_header *master_table,
- struct phm_runtime_table_header *rt_table)
-{
- uint32_t function_count = 0;
- const struct phm_master_table_item *table_item;
- uint32_t size;
- phm_table_function *run_time_list;
- phm_table_function *rtf;
-
- if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
- pr_err("Invalid Parameter!\n");
- return -EINVAL;
- }
-
- for (table_item = master_table->master_list;
- NULL != table_item->tableFunction; table_item++) {
- if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
- (table_item->isFunctionNeededInRuntimeTable(hwmgr)))
- function_count++;
- }
-
- size = (function_count + 1) * sizeof(phm_table_function);
- run_time_list = kzalloc(size, GFP_KERNEL);
-
- if (NULL == run_time_list)
- return -ENOMEM;
-
- rtf = run_time_list;
- for (table_item = master_table->master_list;
- NULL != table_item->tableFunction; table_item++) {
- if ((rtf - run_time_list) > function_count) {
- pr_err("Check function results have changed\n");
- kfree(run_time_list);
- return -EINVAL;
- }
-
- if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
- (table_item->isFunctionNeededInRuntimeTable(hwmgr))) {
- *(rtf++) = table_item->tableFunction;
- }
- }
-
- if ((rtf - run_time_list) > function_count) {
- pr_err("Check function results have changed\n");
- kfree(run_time_list);
- return -EINVAL;
- }
-
- *rtf = NULL;
- rt_table->function_list = run_time_list;
- rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError));
- rt_table->storage_size = master_table->storage_size;
- return 0;
-}
-
-int phm_destroy_table(struct pp_hwmgr *hwmgr,
- struct phm_runtime_table_header *rt_table)
-{
- if (hwmgr == NULL || rt_table == NULL) {
- pr_err("Invalid Parameter\n");
- return -EINVAL;
- }
-
- if (NULL == rt_table->function_list)
- return 0;
-
- kfree(rt_table->function_list);
-
- rt_table->function_list = NULL;
- rt_table->storage_size = 0;
- rt_table->exit_error = false;
-
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index fcc722e..623cff9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -26,35 +26,22 @@
#include "hardwaremanager.h"
#include "power_state.h"
+
+#define TEMP_RANGE_MIN (0)
+#define TEMP_RANGE_MAX (80 * 1000)
+
#define PHM_FUNC_CHECK(hw) \
do { \
if ((hw) == NULL || (hw)->hwmgr_func == NULL) \
return -EINVAL; \
} while (0)
-bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
-{
- return hwmgr->block_hw_access;
-}
-
-int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
-{
- hwmgr->block_hw_access = block;
- return 0;
-}
-
int phm_setup_asic(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (NULL != hwmgr->hwmgr_func->asic_setup)
- return hwmgr->hwmgr_func->asic_setup(hwmgr);
- } else {
- return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
- NULL, NULL);
- }
+ if (NULL != hwmgr->hwmgr_func->asic_setup)
+ return hwmgr->hwmgr_func->asic_setup(hwmgr);
return 0;
}
@@ -63,14 +50,8 @@ int phm_power_down_asic(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (NULL != hwmgr->hwmgr_func->power_off_asic)
- return hwmgr->hwmgr_func->power_off_asic(hwmgr);
- } else {
- return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
- NULL, NULL);
- }
+ if (NULL != hwmgr->hwmgr_func->power_off_asic)
+ return hwmgr->hwmgr_func->power_off_asic(hwmgr);
return 0;
}
@@ -86,13 +67,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
states.pcurrent_state = pcurrent_state;
states.pnew_state = pnew_power_state;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (NULL != hwmgr->hwmgr_func->power_state_set)
- return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
- } else {
- return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
- }
+ if (NULL != hwmgr->hwmgr_func->power_state_set)
+ return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
return 0;
}
@@ -103,15 +79,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
bool enabled;
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
- ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
- } else {
- ret = phm_dispatch_table(hwmgr,
- &(hwmgr->enable_dynamic_state_management),
- NULL, NULL);
- }
+ if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
+ ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
enabled = ret == 0;
@@ -127,15 +96,8 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (hwmgr->hwmgr_func->dynamic_state_management_disable)
- ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
- } else {
- ret = phm_dispatch_table(hwmgr,
- &(hwmgr->disable_dynamic_state_management),
- NULL, NULL);
- }
+ if (hwmgr->hwmgr_func->dynamic_state_management_disable)
+ ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
enabled = ret == 0 ? false : true;
@@ -193,35 +155,13 @@ int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
return 0;
}
-int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
-{
- PHM_FUNC_CHECK(hwmgr);
-
- if (hwmgr->hwmgr_func->powergate_uvd != NULL)
- return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
- return 0;
-}
-
-int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
-{
- PHM_FUNC_CHECK(hwmgr);
-
- if (hwmgr->hwmgr_func->powergate_vce != NULL)
- return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- return 0;
-}
-
int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
- return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
- } else {
- return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
- }
+ if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
+ return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
+
return 0;
}
@@ -229,11 +169,9 @@ int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
- return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
- }
+ if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
+ return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
+
return 0;
}
@@ -242,12 +180,9 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface)) {
- if (NULL != hwmgr->hwmgr_func->display_config_changed)
- hwmgr->hwmgr_func->display_config_changed(hwmgr);
- } else
- return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
+ if (NULL != hwmgr->hwmgr_func->display_config_changed)
+ hwmgr->hwmgr_func->display_config_changed(hwmgr);
+
return 0;
}
@@ -255,9 +190,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface))
- if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
+ if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
return 0;
@@ -277,10 +210,10 @@ int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
{
PHM_FUNC_CHECK(hwmgr);
- if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
- return -EINVAL;
+ if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL)
+ return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
- return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
+ return 0;
}
/**
@@ -292,7 +225,21 @@ int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
*/
int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
{
- return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
+ struct PP_TemperatureRange range;
+
+ if (temperature_range == NULL) {
+ range.max = TEMP_RANGE_MAX;
+ range.min = TEMP_RANGE_MIN;
+ } else {
+ range.max = temperature_range->max;
+ range.min = temperature_range->min;
+ }
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ThermalController)
+ && hwmgr->hwmgr_func->start_thermal_controller != NULL)
+ return hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
+
+ return 0;
}
@@ -323,6 +270,9 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
const struct amd_pp_display_configuration *display_config)
{
+ int index = 0;
+ int number_of_active_display = 0;
+
PHM_FUNC_CHECK(hwmgr);
if (display_config == NULL)
@@ -330,6 +280,17 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
hwmgr->display_config = *display_config;
+ if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
+ hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk);
+
+ for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) {
+ if (hwmgr->display_config.displays[index].controller_id != 0)
+ number_of_active_display++;
+ }
+
+ if (NULL != hwmgr->hwmgr_func->set_active_display_count)
+ hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
+
if (hwmgr->hwmgr_func->store_cc6_data == NULL)
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 9547f26..ce59e0e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -26,8 +26,8 @@
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/types.h>
+#include <linux/pci.h>
#include <drm/amdgpu_drm.h>
-#include "cgs_common.h"
#include "power_state.h"
#include "hwmgr.h"
#include "pppcielanes.h"
@@ -35,21 +35,100 @@
#include "ppsmc.h"
#include "pp_acpi.h"
#include "amd_acpi.h"
+#include "pp_psm.h"
+
+extern const struct pp_smumgr_func ci_smu_funcs;
+extern const struct pp_smumgr_func cz_smu_funcs;
+extern const struct pp_smumgr_func iceland_smu_funcs;
+extern const struct pp_smumgr_func tonga_smu_funcs;
+extern const struct pp_smumgr_func fiji_smu_funcs;
+extern const struct pp_smumgr_func polaris10_smu_funcs;
+extern const struct pp_smumgr_func vega10_smu_funcs;
+extern const struct pp_smumgr_func rv_smu_funcs;
extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
-
static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
+static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
uint8_t convert_to_vid(uint16_t vddc)
{
return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
}
+static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr,
+ struct cgs_system_info *sys_info)
+{
+ sys_info->size = sizeof(struct cgs_system_info);
+ sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN;
+
+ return cgs_query_system_info(hwmgr->device, sys_info);
+}
+
+static int phm_thermal_l2h_irq(void *private_data,
+ unsigned src_id, const uint32_t *iv_entry)
+{
+ struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
+ struct cgs_system_info sys_info = {0};
+ int result;
+
+ result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
+ if (result)
+ return -EINVAL;
+
+ pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n",
+ PCI_BUS_NUM(sys_info.value),
+ PCI_SLOT(sys_info.value),
+ PCI_FUNC(sys_info.value));
+ return 0;
+}
+
+static int phm_thermal_h2l_irq(void *private_data,
+ unsigned src_id, const uint32_t *iv_entry)
+{
+ struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
+ struct cgs_system_info sys_info = {0};
+ int result;
+
+ result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
+ if (result)
+ return -EINVAL;
+
+ pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n",
+ PCI_BUS_NUM(sys_info.value),
+ PCI_SLOT(sys_info.value),
+ PCI_FUNC(sys_info.value));
+ return 0;
+}
+
+static int phm_ctf_irq(void *private_data,
+ unsigned src_id, const uint32_t *iv_entry)
+{
+ struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
+ struct cgs_system_info sys_info = {0};
+ int result;
+
+ result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
+ if (result)
+ return -EINVAL;
+
+ pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n",
+ PCI_BUS_NUM(sys_info.value),
+ PCI_SLOT(sys_info.value),
+ PCI_FUNC(sys_info.value));
+ return 0;
+}
+
+static const struct cgs_irq_src_funcs thermal_irq_src[3] = {
+ { .handler = phm_thermal_l2h_irq },
+ { .handler = phm_thermal_h2l_irq },
+ { .handler = phm_ctf_irq }
+};
+
int hwmgr_early_init(struct pp_instance *handle)
{
struct pp_hwmgr *hwmgr;
@@ -62,7 +141,6 @@ int hwmgr_early_init(struct pp_instance *handle)
return -ENOMEM;
handle->hwmgr = hwmgr;
- hwmgr->smumgr = handle->smu_mgr;
hwmgr->device = handle->device;
hwmgr->chip_family = handle->chip_family;
hwmgr->chip_id = handle->chip_id;
@@ -73,24 +151,38 @@ int hwmgr_early_init(struct pp_instance *handle)
hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
hwmgr_init_default_caps(hwmgr);
hwmgr_set_user_specify_caps(hwmgr);
+ hwmgr->fan_ctrl_is_in_default_mode = true;
+ hwmgr->reload_fw = 1;
switch (hwmgr->chip_family) {
+ case AMDGPU_FAMILY_CI:
+ hwmgr->smumgr_funcs = &ci_smu_funcs;
+ ci_set_asic_special_caps(hwmgr);
+ hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
+ PP_ENABLE_GFX_CG_THRU_SMU);
+ hwmgr->pp_table_version = PP_TABLE_V0;
+ smu7_init_function_pointers(hwmgr);
+ break;
case AMDGPU_FAMILY_CZ:
+ hwmgr->smumgr_funcs = &cz_smu_funcs;
cz_init_function_pointers(hwmgr);
break;
case AMDGPU_FAMILY_VI:
switch (hwmgr->chip_id) {
case CHIP_TOPAZ:
+ hwmgr->smumgr_funcs = &iceland_smu_funcs;
topaz_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
PP_ENABLE_GFX_CG_THRU_SMU);
hwmgr->pp_table_version = PP_TABLE_V0;
break;
case CHIP_TONGA:
+ hwmgr->smumgr_funcs = &tonga_smu_funcs;
tonga_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
break;
case CHIP_FIJI:
+ hwmgr->smumgr_funcs = &fiji_smu_funcs;
fiji_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
PP_ENABLE_GFX_CG_THRU_SMU);
@@ -98,6 +190,7 @@ int hwmgr_early_init(struct pp_instance *handle)
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
+ hwmgr->smumgr_funcs = &polaris10_smu_funcs;
polaris_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
break;
@@ -109,6 +202,7 @@ int hwmgr_early_init(struct pp_instance *handle)
case AMDGPU_FAMILY_AI:
switch (hwmgr->chip_id) {
case CHIP_VEGA10:
+ hwmgr->smumgr_funcs = &vega10_smu_funcs;
vega10_hwmgr_init(hwmgr);
break;
default:
@@ -118,6 +212,7 @@ int hwmgr_early_init(struct pp_instance *handle)
case AMDGPU_FAMILY_RV:
switch (hwmgr->chip_id) {
case CHIP_RAVEN:
+ hwmgr->smumgr_funcs = &rv_smu_funcs;
rv_init_function_pointers(hwmgr);
break;
default:
@@ -131,80 +226,6 @@ int hwmgr_early_init(struct pp_instance *handle)
return 0;
}
-static int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- unsigned int i;
- unsigned int table_entries;
- struct pp_power_state *state;
- int size;
-
- if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
- return -EINVAL;
-
- if (hwmgr->hwmgr_func->get_power_state_size == NULL)
- return -EINVAL;
-
- hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
-
- hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
- sizeof(struct pp_power_state);
-
- hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
- if (hwmgr->ps == NULL)
- return -ENOMEM;
-
- hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
- if (hwmgr->request_ps == NULL) {
- kfree(hwmgr->ps);
- hwmgr->ps = NULL;
- return -ENOMEM;
- }
-
- hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
- if (hwmgr->current_ps == NULL) {
- kfree(hwmgr->request_ps);
- kfree(hwmgr->ps);
- hwmgr->request_ps = NULL;
- hwmgr->ps = NULL;
- return -ENOMEM;
- }
-
- state = hwmgr->ps;
-
- for (i = 0; i < table_entries; i++) {
- result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
-
- if (state->classification.flags & PP_StateClassificationFlag_Boot) {
- hwmgr->boot_ps = state;
- memcpy(hwmgr->current_ps, state, size);
- memcpy(hwmgr->request_ps, state, size);
- }
-
- state->id = i + 1; /* assigned unique num for every power state id */
-
- if (state->classification.flags & PP_StateClassificationFlag_Uvd)
- hwmgr->uvd_ps = state;
- state = (struct pp_power_state *)((unsigned long)state + size);
- }
-
- return 0;
-}
-
-static int hw_fini_power_state_table(struct pp_hwmgr *hwmgr)
-{
- if (hwmgr == NULL)
- return -EINVAL;
-
- kfree(hwmgr->current_ps);
- kfree(hwmgr->request_ps);
- kfree(hwmgr->ps);
- hwmgr->request_ps = NULL;
- hwmgr->ps = NULL;
- hwmgr->current_ps = NULL;
- return 0;
-}
-
int hwmgr_hw_init(struct pp_instance *handle)
{
struct pp_hwmgr *hwmgr;
@@ -228,9 +249,26 @@ int hwmgr_hw_init(struct pp_instance *handle)
if (ret)
goto err1;
- ret = hw_init_power_state_table(hwmgr);
+ ret = psm_init_power_state_table(hwmgr);
if (ret)
goto err2;
+
+ ret = phm_setup_asic(hwmgr);
+ if (ret)
+ goto err2;
+
+ ret = phm_enable_dynamic_state_management(hwmgr);
+ if (ret)
+ goto err2;
+ ret = phm_start_thermal_controller(hwmgr, NULL);
+ ret |= psm_set_performance_states(hwmgr);
+ if (ret)
+ goto err2;
+
+ ret = phm_register_thermal_interrupt(hwmgr, &thermal_irq_src);
+ if (ret)
+ goto err2;
+
return 0;
err2:
if (hwmgr->hwmgr_func->backend_fini)
@@ -247,19 +285,137 @@ int hwmgr_hw_fini(struct pp_instance *handle)
{
struct pp_hwmgr *hwmgr;
- if (handle == NULL)
+ if (handle == NULL || handle->hwmgr == NULL)
return -EINVAL;
hwmgr = handle->hwmgr;
+ phm_stop_thermal_controller(hwmgr);
+ psm_set_boot_states(hwmgr);
+ psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+ phm_disable_dynamic_state_management(hwmgr);
+ phm_disable_clock_power_gatings(hwmgr);
+
if (hwmgr->hwmgr_func->backend_fini)
hwmgr->hwmgr_func->backend_fini(hwmgr);
if (hwmgr->pptable_func->pptable_fini)
hwmgr->pptable_func->pptable_fini(hwmgr);
- return hw_fini_power_state_table(hwmgr);
+ return psm_fini_power_state_table(hwmgr);
}
+int hwmgr_hw_suspend(struct pp_instance *handle)
+{
+ struct pp_hwmgr *hwmgr;
+ int ret = 0;
+ if (handle == NULL || handle->hwmgr == NULL)
+ return -EINVAL;
+
+ hwmgr = handle->hwmgr;
+ phm_disable_smc_firmware_ctf(hwmgr);
+ ret = psm_set_boot_states(hwmgr);
+ if (ret)
+ return ret;
+ ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+ if (ret)
+ return ret;
+ ret = phm_power_down_asic(hwmgr);
+
+ return ret;
+}
+
+int hwmgr_hw_resume(struct pp_instance *handle)
+{
+ struct pp_hwmgr *hwmgr;
+ int ret = 0;
+
+ if (handle == NULL || handle->hwmgr == NULL)
+ return -EINVAL;
+
+ hwmgr = handle->hwmgr;
+ ret = phm_setup_asic(hwmgr);
+ if (ret)
+ return ret;
+
+ ret = phm_enable_dynamic_state_management(hwmgr);
+ if (ret)
+ return ret;
+ ret = phm_start_thermal_controller(hwmgr, NULL);
+ if (ret)
+ return ret;
+
+ ret |= psm_set_performance_states(hwmgr);
+ if (ret)
+ return ret;
+
+ ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+
+ return ret;
+}
+
+static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
+{
+ switch (state) {
+ case POWER_STATE_TYPE_BATTERY:
+ return PP_StateUILabel_Battery;
+ case POWER_STATE_TYPE_BALANCED:
+ return PP_StateUILabel_Balanced;
+ case POWER_STATE_TYPE_PERFORMANCE:
+ return PP_StateUILabel_Performance;
+ default:
+ return PP_StateUILabel_None;
+ }
+}
+
+int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
+ void *input, void *output)
+{
+ int ret = 0;
+ struct pp_hwmgr *hwmgr;
+
+ if (handle == NULL || handle->hwmgr == NULL)
+ return -EINVAL;
+
+ hwmgr = handle->hwmgr;
+
+ switch (task_id) {
+ case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
+ ret = phm_set_cpu_power_state(hwmgr);
+ if (ret)
+ return ret;
+ ret = psm_set_performance_states(hwmgr);
+ if (ret)
+ return ret;
+ ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+ break;
+ case AMD_PP_TASK_ENABLE_USER_STATE:
+ {
+ enum amd_pm_state_type ps;
+ enum PP_StateUILabel requested_ui_label;
+ struct pp_power_state *requested_ps = NULL;
+
+ if (input == NULL) {
+ ret = -EINVAL;
+ break;
+ }
+ ps = *(unsigned long *)input;
+
+ requested_ui_label = power_state_convert(ps);
+ ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
+ if (ret)
+ return ret;
+ ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
+ break;
+ }
+ case AMD_PP_TASK_COMPLETE_INIT:
+ case AMD_PP_TASK_READJUST_POWER_STATE:
+ ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
/**
* Returns once the part of the register indicated by the mask has
* reached the given value.
@@ -294,7 +450,7 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
* reached the given value.The indirect space is described by giving
* the memory-mapped index of the indirect index register.
*/
-void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
@@ -302,14 +458,50 @@ void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
{
if (hwmgr == NULL || hwmgr->device == NULL) {
pr_err("Invalid Hardware Manager!");
- return;
+ return -EINVAL;
}
cgs_write_register(hwmgr->device, indirect_port, index);
- phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
+ return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
}
+int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t index,
+ uint32_t value, uint32_t mask)
+{
+ uint32_t i;
+ uint32_t cur_value;
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ for (i = 0; i < hwmgr->usec_timeout; i++) {
+ cur_value = cgs_read_register(hwmgr->device,
+ index);
+ if ((cur_value & mask) != (value & mask))
+ break;
+ udelay(1);
+ }
+
+ /* timeout means wrong logic */
+ if (i == hwmgr->usec_timeout)
+ return -ETIME;
+ return 0;
+}
+
+int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port,
+ uint32_t index,
+ uint32_t value,
+ uint32_t mask)
+{
+ if (hwmgr == NULL || hwmgr->device == NULL)
+ return -EINVAL;
+
+ cgs_write_register(hwmgr->device, indirect_port, index);
+ return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
+ value, mask);
+}
bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
{
@@ -678,7 +870,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
for (i = 0; i < vddc_table->count; i++) {
if (req_vddc <= vddc_table->entries[i].vddc) {
req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VddC_Request, req_volt);
return;
}
@@ -689,28 +881,8 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
{
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
- phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
-
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
-
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
@@ -735,7 +907,6 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_FanSpeedInTableIsRPM);
-
return;
}
@@ -784,7 +955,8 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
-
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EVV);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
@@ -793,10 +965,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition);
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface);
-
-
if (hwmgr->chip_id != CHIP_POLARIS10)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SPLLShutdownSupport);
@@ -814,6 +982,8 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EVV);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
@@ -822,15 +992,13 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_TDRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
-
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface);
-
return 0;
}
int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EVV);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
@@ -844,15 +1012,26 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDPowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating);
-
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface);
-
return 0;
}
int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EVV);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SQRamping);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DBRamping);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_TDRamping);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_TCPRamping);
+ return 0;
+}
+
+int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
+{
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
@@ -862,8 +1041,8 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface);
+ PHM_PlatformCaps_MemorySpreadSpectrumSupport);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_EVV);
+ PHM_PlatformCaps_EngineSpreadSpectrumSupport);
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
index e0766c5..67fae83 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
@@ -2,1263 +2,1252 @@
#include "pp_overdriver.h"
#include <linux/errno.h>
-struct phm_fuses_default vega10_fuses_default[] = {
- {"0000001000010011111010101001010011011110000011100100100101100100",0x00003C96,0xFFFFE226,0x00000656,0x00002203,0xFFFFF201,0x000003FF,0x00002203,0xFFFFF201,0x000003FF},
- {"0000001000010011111010101001010011011110000010100001100010000100",0x00003CC5,0xFFFFE23A,0x0000064E,0x00002258,0xFFFFF1F7,0x000003FC,0x00002258,0xFFFFF1F7,0x000003FC},
- {"0000001000010011111010101001010011011110000011100011000110100100",0x00003CAF,0xFFFFE36E,0x00000602,0x00001E98,0xFFFFF569,0x00000357,0x00001E98,0xFFFFF569,0x00000357},
- {"0000001000010011111010101001010011011110001011000001000101000100",0x0000391A,0xFFFFE548,0x000005C9,0x00001B98,0xFFFFF707,0x00000324,0x00001B98,0xFFFFF707,0x00000324},
- {"0000001000010011111010101001010011011110001011000001100011000100",0x00003821,0xFFFFE674,0x00000597,0x00002196,0xFFFFF361,0x000003C0,0x00002196,0xFFFFF361,0x000003C0},
- {"0000001000010011111010101001010011011110001001100011100010000100",0x000044A2,0xFFFFDCB7,0x00000738,0x0000325C,0xFFFFE6A7,0x000005E6,0x0000325C,0xFFFFE6A7,0x000005E6},
- {"0000001000010011111010101001010011011110000010000010100100100100",0x00004057,0xFFFFE1CF,0x0000063C,0x00002E2E,0xFFFFEB62,0x000004FD,0x00002E2E,0xFFFFEB62,0x000004FD},
- {"0000001000010011111010101001010011011110001010000100100100100100",0x00003FD0,0xFFFFDF0F,0x000006E5,0x0000267C,0xFFFFEE2D,0x000004AB,0x0000267C,0xFFFFEE2D,0x000004AB},
- {"0000001000010011111010101001010011011110001010000000100100000100",0x00003F13,0xFFFFE010,0x000006AD,0x000020E7,0xFFFFF266,0x000003EC,0x000020E7,0xFFFFF266,0x000003EC},
- {"0000001000010011111010101001010011011110000010000010000001000100",0x00004088,0xFFFFDFAB,0x000006B6,0x0000252B,0xFFFFEFDB,0x00000458,0x0000252B,0xFFFFEFDB,0x00000458},
- {"0000001000010011111010101001010011011110001010000011100010000100",0x00003EF6,0xFFFFE017,0x000006AA,0x00001F67,0xFFFFF369,0x000003BE,0x00001F67,0xFFFFF369,0x000003BE},
- {"0000001000010011111010101001010011011110001011000010000110000100",0x00003CDD,0xFFFFE2A7,0x0000063C,0x000026C6,0xFFFFEF38,0x00000478,0x000026C6,0xFFFFEF38,0x00000478},
- {"0000001000010011111010101001010011011110000100000101000100100100",0x00003FA8,0xFFFFDF02,0x000006F0,0x000027FE,0xFFFFECF6,0x000004EA,0x000027FE,0xFFFFECF6,0x000004EA},
- {"0000001000010011111010101001010011011110001001100011100011000100",0x00004670,0xFFFFDC40,0x00000742,0x00003A7A,0xFFFFE1A7,0x000006B6,0x00003A7A,0xFFFFE1A7,0x000006B6},
- {"0000001000010011111010101001010011011110001011000011000000100100",0x00003CDC,0xFFFFE18C,0x00000683,0x00002A69,0xFFFFEBE7,0x00000515,0x00002A69,0xFFFFEBE7,0x00000515},
- {"0000001000010011111010101001010011011110000011100011100011000100",0x00003CEC,0xFFFFE38E,0x00000601,0x00002752,0xFFFFEFA7,0x00000453,0x00002752,0xFFFFEFA7,0x00000453},
- {"0000001000010011111010101001010011011110001011000001000100100100",0x000037D0,0xFFFFE634,0x000005A7,0x00001CD2,0xFFFFF644,0x00000348,0x00001CD2,0xFFFFF644,0x00000348},
- {"0000001000010011111010101001010011011110001010000011100101100100",0x00003DF5,0xFFFFE0A5,0x00000698,0x00001FD5,0xFFFFF30E,0x000003D1,0x00001FD5,0xFFFFF30E,0x000003D1},
- {"0000001000010011111010101001010011011110000010000010100011000100",0x00004201,0xFFFFE03E,0x00000688,0x00003206,0xFFFFE852,0x0000058A,0x00003206,0xFFFFE852,0x0000058A},
- {"0000001000010011111010101001010011011110001011000001100001100100",0x00003BED,0xFFFFE2F5,0x00000638,0x0000270D,0xFFFFEED0,0x0000048E,0x0000270D,0xFFFFEED0,0x0000048E},
- {"0000001000010011111010101001010011011110000010100001100100000100",0x00003E82,0xFFFFE1BE,0x00000654,0x000025FB,0xFFFFEFFA,0x00000448,0x000025FB,0xFFFFEFFA,0x00000448},
- {"0000001000010011111010101001010011011110001011000100000011000100",0x00003962,0xFFFFE4B9,0x000005EF,0x00002385,0xFFFFF156,0x00000423,0x00002385,0xFFFFF156,0x00000423},
- {"0000001000010011111010101001010011011110001011000000100101000100",0x00003D88,0xFFFFE21A,0x00000655,0x0000295A,0xFFFFED68,0x000004C4,0x0000295A,0xFFFFED68,0x000004C4},
- {"0000001000010011111010101001010011011110001011000001000100000100",0x00003AA4,0xFFFFE4A3,0x000005E0,0x000022EF,0xFFFFF250,0x000003EB,0x000022EF,0xFFFFF250,0x000003EB},
- {"0000001000010011111010101001010011011110000011100010100110100100",0x00003D97,0xFFFFE30D,0x0000060D,0x0000205D,0xFFFFF45D,0x00000380,0x0000205D,0xFFFFF45D,0x00000380},
- {"0000001000010011111010101001010011011110001011000100000010100100",0x000039B6,0xFFFFE446,0x00000605,0x00002325,0xFFFFF16C,0x0000041F,0x00002325,0xFFFFF16C,0x0000041F},
- {"0000001000010011111010101001010011011110001001100011100100000100",0x0000457E,0xFFFFDCF6,0x00000722,0x00003972,0xFFFFE27B,0x0000068E,0x00003972,0xFFFFE27B,0x0000068E},
- {"0000001000010011111010101001010011011110000010100001100100100100",0x00003FB8,0xFFFFE101,0x00000670,0x00002787,0xFFFFEEF5,0x00000471,0x00002787,0xFFFFEEF5,0x00000471},
- {"0000001000010011111010101001010011011110000011100011100010100100",0x00003BB2,0xFFFFE430,0x000005EA,0x000024A5,0xFFFFF162,0x00000409,0x000024A5,0xFFFFF162,0x00000409},
- {"0000001000010011111010101001010011011110000010000010000101000100",0x00003EC5,0xFFFFE1BD,0x0000064F,0x000022F0,0xFFFFF227,0x000003E8,0x000022F0,0xFFFFF227,0x000003E8},
- {"0000001000010011111010101001010011011110001011000011000101100100",0x000038A7,0xFFFFE59F,0x000005C1,0x000021CC,0xFFFFF2DF,0x000003D9,0x000021CC,0xFFFFF2DF,0x000003D9},
- {"0000001000010011111010101001010011011110001100100100000110000100",0x00002995,0xFFFFEF7A,0x0000044C,0x00001552,0xFFFFFB5D,0x00000292,0x00001552,0xFFFFFB5D,0x00000292},
- {"0000001000010011111010101001010011011110001011000100000001100100",0x00003B26,0xFFFFE2D3,0x00000649,0x000023B4,0xFFFFF09B,0x00000449,0x000023B4,0xFFFFF09B,0x00000449},
- {"0000001000010011111010101001010011011110000010000001000100100100",0x000040D2,0xFFFFE00A,0x00000696,0x000022DA,0xFFFFF1E9,0x000003F2,0x000022DA,0xFFFFF1E9,0x000003F2},
- {"0000001000010011111010101001010011011110001011000011100100100100",0x00003C98,0xFFFFE365,0x00000618,0x00002D5D,0xFFFFEB3A,0x0000051D,0x00002D5D,0xFFFFEB3A,0x0000051D},
- {"0000001000010011111010101001010011011110001011000001000010100100",0x00003BBD,0xFFFFE37E,0x00000617,0x0000252E,0xFFFFF06E,0x00000441,0x0000252E,0xFFFFF06E,0x00000441},
- {"0000001000010011111010101001010011011110001001100010100100100100",0x00004363,0xFFFFDF7A,0x000006A0,0x000031F5,0xFFFFE880,0x0000057B,0x000031F5,0xFFFFE880,0x0000057B},
- {"0000001000010011111010101001010011011110000011100011100001000100",0x00003CFC,0xFFFFE2AF,0x0000062E,0x0000212A,0xFFFFF335,0x000003BF,0x0000212A,0xFFFFF335,0x000003BF},
- {"0000001000010011111010101001010011011110000111000100100100100100",0x0000252D,0xFFFFF31B,0x000003C3,0x00001A1A,0xFFFFF882,0x00000325,0x00001A1A,0xFFFFF882,0x00000325},
- {"0000001000010011111010101001010011011110000010100010100110100100",0x00003FE2,0xFFFFDFEF,0x000006AC,0x000025A2,0xFFFFEF84,0x00000462,0x000025A2,0xFFFFEF84,0x00000462},
- {"0000001000010011111010101001010011011110000010000010000011100100",0x000040A5,0xFFFFE13B,0x0000065B,0x00002C13,0xFFFFEC75,0x000004D7,0x00002C13,0xFFFFEC75,0x000004D7},
- {"0000001000010011111010101001010011011110000011100100100010100100",0x00003E42,0xFFFFE1B3,0x00000657,0x0000221D,0xFFFFF273,0x000003DE,0x0000221D,0xFFFFF273,0x000003DE},
- {"0000001000010011111010101001010011011110000010100010000011100100",0x00003E7F,0xFFFFE255,0x00000638,0x00002D30,0xFFFFEB8A,0x00000503,0x00002D30,0xFFFFEB8A,0x00000503},
- {"0000001000010011111010101001010011011110001011000010100111000100",0x00003E56,0xFFFFE16D,0x00000670,0x000028DC,0xFFFFEDA0,0x000004BA,0x000028DC,0xFFFFEDA0,0x000004BA},
- {"0000001000010011111010101001010011011110001001100011000010100100",0x000044AD,0xFFFFDE24,0x000006DD,0x000031AD,0xFFFFE850,0x00000585,0x000031AD,0xFFFFE850,0x00000585},
- {"0000001000010011111010101001010011011110001011000010000011100100",0x00003AF3,0xFFFFE5B0,0x000005A6,0x00002CF6,0xFFFFEC75,0x000004DD,0x00002CF6,0xFFFFEC75,0x000004DD},
- {"0000001000010011111010101001010011011110000010100010000010000100",0x00003E66,0xFFFFE19E,0x0000065B,0x00002332,0xFFFFF1B9,0x000003FD,0x00002332,0xFFFFF1B9,0x000003FD},
- {"0000001000010011111010101001010011011110000010000010100010000100",0x00003FB4,0xFFFFE0A5,0x00000686,0x0000253E,0xFFFFF02E,0x00000444,0x0000253E,0xFFFFF02E,0x00000444},
- {"0000001000010011111010101001010011011110001010000001100010100100",0x00003E28,0xFFFFE14D,0x0000066E,0x00001FE2,0xFFFFF39A,0x000003B1,0x00001FE2,0xFFFFF39A,0x000003B1},
- {"0000001000010011111010101001010011011110001011000000100100000100",0x000039E6,0xFFFFE44B,0x000005FE,0x0000210C,0xFFFFF2F4,0x000003DA,0x0000210C,0xFFFFF2F4,0x000003DA},
- {"0000001000010011111010101001010011011110001011000101000100000100",0x00003A4D,0xFFFFE252,0x0000067A,0x000027E2,0xFFFFECED,0x000004FA,0x000027E2,0xFFFFECED,0x000004FA},
- {"0000001000010011111010101001010011011110000010100010100101100100",0x00004065,0xFFFFE02F,0x0000069B,0x0000299D,0xFFFFED38,0x000004C2,0x0000299D,0xFFFFED38,0x000004C2},
- {"0000001000010011111010101001010011011110000011100010000010100100",0x000039EE,0xFFFFE603,0x00000594,0x0000214F,0xFFFFF429,0x0000038E,0x0000214F,0xFFFFF429,0x0000038E},
- {"0000001000010011111010101001010011011110000011100100100011100100",0x00003BD2,0xFFFFE351,0x00000618,0x000020B8,0xFFFFF377,0x000003B4,0x000020B8,0xFFFFF377,0x000003B4},
- {"0000001000010011111010101001010011011110000010100011000100100100",0x00003FAA,0xFFFFE183,0x0000065E,0x000032AE,0xFFFFE7C2,0x000005A6,0x000032AE,0xFFFFE7C2,0x000005A6},
- {"0000001000010011111010101001010011011110001011000010100110000100",0x00003AFB,0xFFFFE3E4,0x00000608,0x00002293,0xFFFFF21F,0x000003FA,0x00002293,0xFFFFF21F,0x000003FA},
- {"0000001000010011111010101001010011011110001001100010000001100100",0x0000448B,0xFFFFDD5D,0x0000070D,0x00002E4E,0xFFFFE9DF,0x00000551,0x00002E4E,0xFFFFE9DF,0x00000551},
- {"0000001000010011111010101001010011011110000011100010000110000100",0x00003D46,0xFFFFE39B,0x000005F3,0x0000218E,0xFFFFF3CD,0x00000398,0x0000218E,0xFFFFF3CD,0x00000398},
- {"0000001000010011111010101001010011011110000010000100100011100100",0x00003F01,0xFFFFDFD9,0x000006BF,0x000023AF,0xFFFFF04E,0x0000044C,0x000023AF,0xFFFFF04E,0x0000044C},
- {"0000001000010011111010101001010011011110000100000010100110100100",0x0000403D,0xFFFFDF6B,0x000006C9,0x0000270D,0xFFFFEE4B,0x0000049E,0x0000270D,0xFFFFEE4B,0x0000049E},
- {"0000001000010011111010101001010011011110000011100011100101100100",0x00003C11,0xFFFFE35C,0x00000613,0x000020F9,0xFFFFF365,0x000003B9,0x000020F9,0xFFFFF365,0x000003B9},
- {"0000001000010011111010101001010011011110001011000011100010000100",0x00003B58,0xFFFFE37D,0x0000061F,0x00002698,0xFFFFEF46,0x00000478,0x00002698,0xFFFFEF46,0x00000478},
- {"0000001000010011111010101001010011011110001010000100000110100100",0x00003EBC,0xFFFFDF7A,0x000006D6,0x0000212B,0xFFFFF195,0x0000041B,0x0000212B,0xFFFFF195,0x0000041B},
- {"0000001000010011111010101001010011011110000010000100100011000100",0x00004050,0xFFFFDEB3,0x000006FE,0x00002D6C,0xFFFFE961,0x00000582,0x00002D6C,0xFFFFE961,0x00000582},
- {"0000001000010011111010101001010011011110001001100010000001000100",0x000043F0,0xFFFFDD9C,0x00000702,0x00002B31,0xFFFFEBEA,0x000004F7,0x00002B31,0xFFFFEBEA,0x000004F7},
- {"0000001000010011111010101001010011011110000100000000100100100100",0x00003EFA,0xFFFFE093,0x00000696,0x000026DB,0xFFFFEEB3,0x00000489,0x000026DB,0xFFFFEEB3,0x00000489},
- {"0000001000010011111010101001010011011110000010000010000001100100",0x0000425D,0xFFFFDE8D,0x000006E6,0x00002CA4,0xFFFFEAD2,0x00000531,0x00002CA4,0xFFFFEAD2,0x00000531},
- {"0000001000010011111010101001010011011110001001100011100110100100",0x000043B0,0xFFFFDD03,0x00000728,0x00002946,0xFFFFECA6,0x000004DE,0x00002946,0xFFFFECA6,0x000004DE},
- {"0000001000010011111010101001010011011110001010000010100001100100",0x00003F6A,0xFFFFE03A,0x0000069D,0x00002208,0xFFFFF1F8,0x000003F6,0x00002208,0xFFFFF1F8,0x000003F6},
- {"0000001000010011111010101001010011011110001011000010100101100100",0x00003A94,0xFFFFE4A7,0x000005E2,0x000024D0,0xFFFFF100,0x00000426,0x000024D0,0xFFFFF100,0x00000426},
- {"0000001000010011111010101001010011011110001010000001000011000100",0x00003F2F,0xFFFFE0A3,0x00000688,0x00002198,0xFFFFF271,0x000003E2,0x00002198,0xFFFFF271,0x000003E2},
- {"0000001000010011111010101001010011011110000100000100100011100100",0x00003EA5,0xFFFFE032,0x000006AE,0x0000227C,0xFFFFF130,0x00000426,0x0000227C,0xFFFFF130,0x00000426},
- {"0000001000010011111010101001010011011110001001100100000101000100",0x0000442F,0xFFFFDBC4,0x0000078B,0x00003CD6,0xFFFFDE6C,0x0000076C,0x00003CD6,0xFFFFDE6C,0x0000076C},
- {"0000001000010011111010101001010011011110001010000010100010000100",0x00003DDE,0xFFFFE174,0x00000668,0x00001FF4,0xFFFFF38F,0x000003B1,0x00001FF4,0xFFFFF38F,0x000003B1},
- {"0000001000010011111010101001010011011110000010100011000101000100",0x000040B0,0xFFFFE016,0x000006A0,0x00002DBB,0xFFFFEA7F,0x00000537,0x00002DBB,0xFFFFEA7F,0x00000537},
- {"0000001000010011111010101001010011011110001011000011000100000100",0x00003429,0xFFFFEA97,0x000004DD,0x000024D5,0xFFFFF26F,0x000003DF,0x000024D5,0xFFFFF26F,0x000003DF},
- {"0000001000010011111010101001010011011110000011100001100100000100",0x00003AEB,0xFFFFE590,0x000005A3,0x000022CB,0xFFFFF347,0x000003B2,0x000022CB,0xFFFFF347,0x000003B2},
- {"0000001000010011111010101001010011011110001010000011100100000100",0x00003B8E,0xFFFFE2EF,0x00000636,0x00002351,0xFFFFF143,0x0000041C,0x00002351,0xFFFFF143,0x0000041C},
- {"0000001000010011111010101001010011011110001100100100000011000100",0x00002926,0xFFFFF0B0,0x00000410,0x0000194E,0xFFFFF94E,0x000002E9,0x0000194E,0xFFFFF94E,0x000002E9},
- {"0000001000010011111010101001010011011110001010000011000110000100",0x0000402B,0xFFFFDF78,0x000006C2,0x00002273,0xFFFFF16C,0x00000414,0x00002273,0xFFFFF16C,0x00000414},
- {"0000001000010011111010101001010011011110000010100001000010100100",0x00003D6A,0xFFFFE1D3,0x00000659,0x00002006,0xFFFFF394,0x000003B1,0x00002006,0xFFFFF394,0x000003B1},
- {"0000001000010011111010101001010011011110001010000100000001100100",0x00004042,0xFFFFDFD8,0x000006A8,0x00002135,0xFFFFF29F,0x000003D9,0x00002135,0xFFFFF29F,0x000003D9},
- {"0000001000010011111010101001010011011110000010000010000010100100",0x0000405B,0xFFFFE093,0x00000682,0x0000288F,0xFFFFEE3A,0x00000491,0x0000288F,0xFFFFEE3A,0x00000491},
- {"0000001000010011111010101001010011011110001011000100100010100100",0x00003A49,0xFFFFE30C,0x00000648,0x000023F9,0xFFFFF02D,0x00000460,0x000023F9,0xFFFFF02D,0x00000460},
- {"0000001000010011111010101001010011011110001010000010100101100100",0x00003D59,0xFFFFE1CC,0x0000065B,0x00002013,0xFFFFF37D,0x000003B6,0x00002013,0xFFFFF37D,0x000003B6},
- {"0000001000010011111010101001010011011110001011000011100110000100",0x000040C1,0xFFFFDF8C,0x000006CA,0x00003271,0xFFFFE6CA,0x000005EA,0x00003271,0xFFFFE6CA,0x000005EA},
- {"0000001000010011111010101001010011011110001001100010000011100100",0x000042E9,0xFFFFDFDC,0x0000068C,0x00002ED9,0xFFFFEAAF,0x0000051B,0x00002ED9,0xFFFFEAAF,0x0000051B},
- {"0000001000010011111010101001010011011110000010000011000010000100",0x000042ED,0xFFFFDE50,0x000006F0,0x00002FCF,0xFFFFE8BB,0x0000058C,0x00002FCF,0xFFFFE8BB,0x0000058C},
- {"0000001000010011111010101001010011011110000010100100000100000100",0x00003EBD,0xFFFFE099,0x00000698,0x00002709,0xFFFFEE7B,0x00000495,0x00002709,0xFFFFEE7B,0x00000495},
- {"0000001000010011111010101001010011011110001010000100100100000100",0x00003F71,0xFFFFDF82,0x000006C9,0x0000219B,0xFFFFF1AD,0x0000040F,0x0000219B,0xFFFFF1AD,0x0000040F},
- {"0000001000010011111010101001010011011110001010000000100011100100",0x00003E73,0xFFFFE080,0x0000069B,0x000020E7,0xFFFFF273,0x000003E9,0x000020E7,0xFFFFF273,0x000003E9},
- {"0000001000010011111010101001010011011110000011100011000110000100",0x00003E14,0xFFFFE278,0x0000062C,0x00002275,0xFFFFF2B3,0x000003CE,0x00002275,0xFFFFF2B3,0x000003CE},
- {"0000001000010011111010101001010011011110001011000010000110100100",0x00003ABB,0xFFFFE3B9,0x00000615,0x00002192,0xFFFFF28F,0x000003EB,0x00002192,0xFFFFF28F,0x000003EB},
- {"0000001000010011111010101001010011011110001010000011000100100100",0x00003D53,0xFFFFE255,0x00000643,0x0000275B,0xFFFFEEED,0x00000479,0x0000275B,0xFFFFEEED,0x00000479},
- {"0000001000010011111010101001010011011110001001100010100001100100",0x000043E3,0xFFFFDDC3,0x000006FB,0x00002B6B,0xFFFFEBD6,0x000004FA,0x00002B6B,0xFFFFEBD6,0x000004FA},
- {"0000001000010011111010101001010011011110000011100010000101000100",0x00003BDE,0xFFFFE507,0x000005B4,0x000022CE,0xFFFFF358,0x000003AB,0x000022CE,0xFFFFF358,0x000003AB},
- {"0000001000010011111010101001010011011110001100100011000101100100",0x00002460,0xFFFFF3B5,0x000003A2,0x000014E7,0xFFFFFC32,0x0000027C,0x000014E7,0xFFFFFC32,0x0000027C},
- {"0000001000010011111010101001010011011110001010000010000011000100",0x00003D20,0xFFFFE298,0x0000062F,0x00002080,0xFFFFF3AF,0x000003A8,0x00002080,0xFFFFF3AF,0x000003A8},
- {"0000001000010011111010101001010011011110000010000001100100000100",0x00003E14,0xFFFFE221,0x00000641,0x000021BB,0xFFFFF2EA,0x000003CA,0x000021BB,0xFFFFF2EA,0x000003CA},
- {"0000001000010011111010101001010011011110000010100100000011000100",0x00003DE1,0xFFFFE14E,0x00000677,0x00002468,0xFFFFF068,0x00000440,0x00002468,0xFFFFF068,0x00000440},
- {"0000001000010011111010101001010011011110001001100001000010000100",0x00004372,0xFFFFDDF8,0x000006F5,0x00002B3F,0xFFFFEBE8,0x000004F8,0x00002B3F,0xFFFFEBE8,0x000004F8},
- {"0000001000010011111010101001010011011110000010100010100011000100",0x00003E4F,0xFFFFE2A3,0x0000062B,0x00002F5A,0xFFFFEA37,0x0000053B,0x00002F5A,0xFFFFEA37,0x0000053B},
- {"0000001000010011111010101001010011011110001010000101000011100100",0x00003E07,0xFFFFE02F,0x000006B6,0x0000216B,0xFFFFF1A3,0x00000416,0x0000216B,0xFFFFF1A3,0x00000416},
- {"0000001000010011111010101001010011011110001010000011100010100100",0x00003DAB,0xFFFFE128,0x0000067F,0x0000216F,0xFFFFF236,0x000003F3,0x0000216F,0xFFFFF236,0x000003F3},
- {"0000001000010011111010101001010011011110001011000010100100100100",0x0000364B,0xFFFFE8CB,0x0000052A,0x00002568,0xFFFFF1B2,0x00000400,0x00002568,0xFFFFF1B2,0x00000400},
- {"0000001000010011111010101001010011011110001001100001000001100100",0x00004219,0xFFFFDE87,0x000006E8,0x00002C59,0xFFFFEAEE,0x00000529,0x00002C59,0xFFFFEAEE,0x00000529},
- {"0000001000010011111010101001010011011110000011100001100101000100",0x000039A8,0xFFFFE602,0x00000594,0x00001D06,0xFFFFF6F0,0x00000316,0x00001D06,0xFFFFF6F0,0x00000316},
- {"0000001000010011111010101001010011011110001001100001000011100100",0x00004052,0xFFFFE01C,0x00000698,0x00002310,0xFFFFF1A1,0x000003FE,0x00002310,0xFFFFF1A1,0x000003FE},
- {"0000001000010011111010101001010011011110000011100010100000100100",0x00003C1C,0xFFFFE3EB,0x000005F1,0x00002289,0xFFFFF2CF,0x000003C9,0x00002289,0xFFFFF2CF,0x000003C9},
- {"0000001000010011111010101001010011011110000011100101000100100100",0x00003F19,0xFFFFE085,0x0000069E,0x00002B94,0xFFFFEB72,0x0000051D,0x00002B94,0xFFFFEB72,0x0000051D},
- {"0000001000010011111010101001010011011110000011100100000110100100",0x00003C51,0xFFFFE2AD,0x00000638,0x0000206B,0xFFFFF361,0x000003BE,0x0000206B,0xFFFFF361,0x000003BE},
- {"0000001000010011111010101001010011011110001001100001000011000100",0x000040B9,0xFFFFDFBB,0x000006AB,0x0000241F,0xFFFFF0CC,0x00000425,0x0000241F,0xFFFFF0CC,0x00000425},
- {"0000001000010011111010101001010011011110000010100010000001100100",0x00003E62,0xFFFFE12C,0x00000678,0x00002445,0xFFFFF09E,0x00000435,0x00002445,0xFFFFF09E,0x00000435},
- {"0000001000010011111010101001010011011110000011100001100110000100",0x00003C97,0xFFFFE399,0x000005FB,0x0000209D,0xFFFFF41D,0x0000038F,0x0000209D,0xFFFFF41D,0x0000038F},
- {"0000001000010011111010101001010011011110000011100011000101000100",0x00003FF9,0xFFFFE1E9,0x0000063E,0x00002E96,0xFFFFEAF5,0x00000516,0x00002E96,0xFFFFEAF5,0x00000516},
- {"0000001000010011111010101001010011011110000010100011000010000100",0x00003F04,0xFFFFE109,0x0000067A,0x000026E1,0xFFFFEF0B,0x00000476,0x000026E1,0xFFFFEF0B,0x00000476},
- {"0000001000010011111010101001010011011110000100000001000100100100",0x00003E3E,0xFFFFE187,0x00000660,0x00002049,0xFFFFF38D,0x000003B0,0x00002049,0xFFFFF38D,0x000003B0},
- {"0000001000010011111010101001010011011110001010000010100101000100",0x00003D58,0xFFFFE253,0x0000063D,0x00002158,0xFFFFF308,0x000003C3,0x00002158,0xFFFFF308,0x000003C3},
- {"0000001000010011111010101001010011011110000010000100000011000100",0x00004074,0xFFFFDF8D,0x000006C0,0x00002799,0xFFFFEE19,0x000004A5,0x00002799,0xFFFFEE19,0x000004A5},
- {"0000001000010011111010101001010011011110001010000001100100100100",0x00003DAF,0xFFFFE1C9,0x00000659,0x000020E5,0xFFFFF313,0x000003C6,0x000020E5,0xFFFFF313,0x000003C6},
- {"0000001000010011111010101001010011011110000010100011100101100100",0x000041DD,0xFFFFDDFA,0x0000071B,0x0000348D,0xFFFFE4B4,0x0000064C,0x0000348D,0xFFFFE4B4,0x0000064C},
- {"0000001000010011111010101001010011011110001011000010100010000100",0x00003947,0xFFFFE5AE,0x000005B8,0x000024A6,0xFFFFF140,0x0000041D,0x000024A6,0xFFFFF140,0x0000041D},
- {"0000001000010011111010101001010011011110000100000001100001000100",0x00003D35,0xFFFFE197,0x0000066E,0x00002248,0xFFFFF1BC,0x00000408,0x00002248,0xFFFFF1BC,0x00000408},
- {"0000001000010011111010101001010011011110000010100001100011100100",0x00003F4F,0xFFFFE13E,0x0000066D,0x00002AF0,0xFFFFEC99,0x000004DB,0x00002AF0,0xFFFFEC99,0x000004DB},
- {"0000001000010011111010101001010011011110001001100011100101000100",0x0000430F,0xFFFFDDFB,0x000006FC,0x00002D4D,0xFFFFEA55,0x00000540,0x00002D4D,0xFFFFEA55,0x00000540},
- {"0000001000010011111010101001010011011110000011100010100101000100",0x00003B22,0xFFFFE543,0x000005B1,0x000022E1,0xFFFFF31B,0x000003B9,0x000022E1,0xFFFFF31B,0x000003B9},
- {"0000001000010011111010101001010011011110000011100010000010000100",0x00003978,0xFFFFE611,0x00000592,0x00001C36,0xFFFFF771,0x00000302,0x00001C36,0xFFFFF771,0x00000302},
- {"0000001000010011111010101001010011011110001001100010000101100100",0x000044DF,0xFFFFDDAB,0x000006F2,0x00002CEA,0xFFFFEB47,0x00000507,0x00002CEA,0xFFFFEB47,0x00000507},
- {"0000001000010011111010101001010011011110000010100011100011000100",0x00003E9B,0xFFFFE12C,0x0000067C,0x00002B79,0xFFFFEBD9,0x00000503,0x00002B79,0xFFFFEBD9,0x00000503},
- {"0000001000010011111010101001010011011110001001100011000001000100",0x00004464,0xFFFFDCD3,0x00000731,0x00002D14,0xFFFFEA2D,0x0000054E,0x00002D14,0xFFFFEA2D,0x0000054E},
- {"0000001000010011111010101001010011011110001010000001000100100100",0x00003FB3,0xFFFFE052,0x00000693,0x000020AC,0xFFFFF311,0x000003C6,0x000020AC,0xFFFFF311,0x000003C6},
- {"0000001000010011111010101001010011011110001011000001000010000100",0x00003BDA,0xFFFFE2FB,0x00000636,0x0000261E,0xFFFFEF72,0x00000471,0x0000261E,0xFFFFEF72,0x00000471},
- {"0000001000010011111010101001010011011110001011000001100101100100",0x00003D72,0xFFFFE28A,0x0000063E,0x000029D8,0xFFFFED54,0x000004C7,0x000029D8,0xFFFFED54,0x000004C7},
- {"0000001000010011111010101001010011011110001011000010100000100100",0x00003E26,0xFFFFE102,0x00000694,0x00002DD1,0xFFFFE9CA,0x0000056D,0x00002DD1,0xFFFFE9CA,0x0000056D},
- {"0000001000010011111010101001010011011110000100000100000100100100",0x000041CD,0xFFFFDE97,0x000006ED,0x00002DE5,0xFFFFE9B9,0x00000565,0x00002DE5,0xFFFFE9B9,0x00000565},
- {"0000001000010011111010101001010011011110000010100010100110000100",0x00003F30,0xFFFFE06E,0x00000698,0x000024FF,0xFFFFEFFC,0x0000044F,0x000024FF,0xFFFFEFFC,0x0000044F},
- {"0000001000010011111010101001010011011110001011000011100011000100",0x0000378B,0xFFFFE6B4,0x00000594,0x000023A7,0xFFFFF1DC,0x00000407,0x000023A7,0xFFFFF1DC,0x00000407},
- {"0000001000010011111010101001010011011110000011100100000101100100",0x00003CD7,0xFFFFE28D,0x00000636,0x00002036,0xFFFFF3B5,0x000003AA,0x00002036,0xFFFFF3B5,0x000003AA},
- {"0000001000010011111010101001010011011110000010100011100010000100",0x00003EF9,0xFFFFE0AA,0x0000068D,0x000024D3,0xFFFFF02F,0x00000445,0x000024D3,0xFFFFF02F,0x00000445},
- {"0000001000010011111010101001010011011110001010000011100101000100",0x00003D08,0xFFFFE1BB,0x00000665,0x00002159,0xFFFFF26F,0x000003E6,0x00002159,0xFFFFF26F,0x000003E6},
- {"0000001000010011111010101001010011011110001011000010000011000100",0x000038A9,0xFFFFE6CA,0x00000580,0x000025D3,0xFFFFF101,0x00000421,0x000025D3,0xFFFFF101,0x00000421},
- {"0000001000010011111010101001010011011110000010100010000010100100",0x00003E45,0xFFFFE1F8,0x0000064D,0x000027E3,0xFFFFEEBB,0x0000047F,0x000027E3,0xFFFFEEBB,0x0000047F},
- {"0000001000010011111010101001010011011110000011100011100001100100",0x00003F76,0xFFFFE128,0x0000066E,0x0000286B,0xFFFFEE4C,0x00000493,0x0000286B,0xFFFFEE4C,0x00000493},
- {"0000001000010011111010101001010011011110001001100100000100000100",0x0000440D,0xFFFFDCA2,0x0000074F,0x00003817,0xFFFFE256,0x000006AF,0x00003817,0xFFFFE256,0x000006AF},
- {"0000001000010011111010101001010011011110000100000101000100000100",0x00003EE1,0xFFFFDFA7,0x000006D4,0x000027EA,0xFFFFED2B,0x000004DE,0x000027EA,0xFFFFED2B,0x000004DE},
- {"0000001000010011111010101001010011011110001011000011100001100100",0x00003C62,0xFFFFE285,0x0000064A,0x00002520,0xFFFFF001,0x0000045C,0x00002520,0xFFFFF001,0x0000045C},
- {"0000001000010011111010101001010011011110001100100011100101100100",0x0000272E,0xFFFFF17A,0x000003FA,0x0000150B,0xFFFFFBD5,0x00000284,0x0000150B,0xFFFFFBD5,0x00000284},
- {"0000001000010011111010101001010011011110001001100001100100100100",0x00004275,0xFFFFDF69,0x000006A5,0x000025AA,0xFFFFF05C,0x0000042B,0x000025AA,0xFFFFF05C,0x0000042B},
- {"0000001000010011111010101001010011011110000011100100000011100100",0x00003CAA,0xFFFFE392,0x000005FF,0x000023A8,0xFFFFF20E,0x000003E9,0x000023A8,0xFFFFF20E,0x000003E9},
- {"0000001000010011111010101001010011011110001011000101000011000100",0x00003CF8,0xFFFFE0FB,0x000006A6,0x00002CA7,0xFFFFE9FF,0x0000056E,0x00002CA7,0xFFFFE9FF,0x0000056E},
- {"0000001000010011111010101001010011011110001010000010000100100100",0x00003D00,0xFFFFE296,0x00000633,0x000021C1,0xFFFFF2C8,0x000003CF,0x000021C1,0xFFFFF2C8,0x000003CF},
- {"0000001000010011111010101001010011011110001010000011100011100100",0x00003B46,0xFFFFE301,0x00000632,0x0000204C,0xFFFFF33B,0x000003C8,0x0000204C,0xFFFFF33B,0x000003C8},
- {"0000001000010011111010101001010011011110001000000100000101100100",0x00002026,0xFFFFF5CE,0x00000368,0x00001598,0xFFFFFB29,0x000002C3,0x00001598,0xFFFFFB29,0x000002C3},
- {"0000001000010011111010101001010011011110001010000011000101100100",0x00003DCA,0xFFFFE178,0x00000668,0x00001FDB,0xFFFFF39D,0x000003AF,0x00001FDB,0xFFFFF39D,0x000003AF},
- {"0000001000010011111010101001010011011110001011000100100011000100",0x00003A59,0xFFFFE327,0x00000642,0x000024B9,0xFFFFEFC4,0x00000471,0x000024B9,0xFFFFEFC4,0x00000471},
- {"0000001000010011111010101001010011011110001011000010100101000100",0x00003C26,0xFFFFE440,0x000005EB,0x00002C0F,0xFFFFEC88,0x000004E0,0x00002C0F,0xFFFFEC88,0x000004E0},
- {"0000001000010011111010101001010011011110000010000011100010000100",0x00004149,0xFFFFDEB8,0x000006E7,0x0000280A,0xFFFFED89,0x000004C2,0x0000280A,0xFFFFED89,0x000004C2},
- {"0000001000010011111010101001010011011110000011100100000100100100",0x00003EB4,0xFFFFE1E5,0x0000064D,0x0000299F,0xFFFFEDB3,0x000004A9,0x0000299F,0xFFFFEDB3,0x000004A9},
- {"0000001000010011111010101001010011011110001011000011100110100100",0x00003BBF,0xFFFFE268,0x0000065A,0x00002504,0xFFFFEFB0,0x00000470,0x00002504,0xFFFFEFB0,0x00000470},
- {"0000001000010011111010101001010011011110000010000100100100000100",0x00004203,0xFFFFDDC6,0x00000720,0x0000303B,0xFFFFE78F,0x000005D0,0x0000303B,0xFFFFE78F,0x000005D0},
- {"0000001000010011111010101001010011011110000011100011100110000100",0x00003DA3,0xFFFFE244,0x0000063E,0x000021B4,0xFFFFF2DA,0x000003CD,0x000021B4,0xFFFFF2DA,0x000003CD},
- {"0000001000010011111010101001010011011110000010100011100011100100",0x00004035,0xFFFFE065,0x0000069B,0x00003323,0xFFFFE6D6,0x000005D8,0x00003323,0xFFFFE6D6,0x000005D8},
- {"0000001000010011111010101001010011011110001011000001000101100100",0x00003944,0xFFFFE4E5,0x000005E2,0x00001F3C,0xFFFFF456,0x0000039D,0x00001F3C,0xFFFFF456,0x0000039D},
- {"0000001000010011111010101001010011011110000001100001100100000100",0x000032D8,0xFFFFEAE8,0x000004E6,0x00001812,0xFFFFFA1C,0x000002BC,0x00001812,0xFFFFFA1C,0x000002BC},
- {"0000001000010011111100001111110101000010110100100010100101000100",0x000041F6,0xFFFFE025,0x0000069A,0x0000241E,0xFFFFF1B4,0x00000402,0x0000241E,0xFFFFF1B4,0x00000402},
- {"0000001000010011111100001111111010011001000011000011000010100100",0x00003300,0xFFFFEB60,0x000004C1,0x00001E15,0xFFFFF6A6,0x0000033B,0x00001E15,0xFFFFF6A6,0x0000033B},
- {"0000001000010011111010101001010011011110000001000000100010100100",0x000037F0,0xFFFFE68F,0x0000059B,0x00001F8A,0xFFFFF467,0x000003A3,0x00001F8A,0xFFFFF467,0x000003A3},
- {"0000001000010011111100001111111010011001000110000010100110000100",0x000025D8,0xFFFFF2AA,0x000003C3,0x000018A8,0xFFFFF9BE,0x000002D2,0x000018A8,0xFFFFF9BE,0x000002D2},
- {"0000001000010011111100001111111010011001000001100010000011000100",0x0000364F,0xFFFFE988,0x000004FC,0x00001E51,0xFFFFF633,0x0000034F,0x00001E51,0xFFFFF633,0x0000034F},
- {"0000001000010011111010101001010011011110000001100001000101000100",0x00002288,0xFFFFF483,0x0000036C,0x0000280F,0xFFFFEF39,0x0000047B,0x0000280F,0xFFFFEF39,0x0000047B},
- {"0000001000010011111100001111111010011001000010000010000010000100",0x00003322,0xFFFFEA7E,0x000004ED,0x00001DAD,0xFFFFF62B,0x00000355,0x00001DAD,0xFFFFF62B,0x00000355},
- {"0000001000010011111010101001010011011110000000100101000011100100",0x00002B7B,0xFFFFEE4F,0x0000045B,0x00001AA2,0xFFFFF710,0x0000033E,0x00001AA2,0xFFFFF710,0x0000033E},
- {"0000001000010011111100001111111010011001000001000010000011000100",0x000034CC,0xFFFFEA79,0x000004E4,0x00001B05,0xFFFFF8B3,0x000002EC,0x00001B05,0xFFFFF8B3,0x000002EC},
- {"0000001000010011111100001111110101000010110111000010100001100100",0x00003837,0xFFFFE5ED,0x000005C3,0x00001ACB,0xFFFFF7B2,0x00000314,0x00001ACB,0xFFFFF7B2,0x00000314},
- {"0000001000010011111100001111111010011001000001000100000101100100",0x0000352D,0xFFFFE88F,0x00000548,0x000021E6,0xFFFFF3B5,0x000003AA,0x000021E6,0xFFFFF3B5,0x000003AA},
- {"0000001000010011111100001111111010011001000010100100100010000100",0x00003300,0xFFFFE835,0x0000057B,0x00001A85,0xFFFFF715,0x00000336,0x00001A85,0xFFFFF715,0x00000336},
- {"0000001000010011111010101001010011011110000001000100100010100100",0x000033FA,0xFFFFE851,0x00000565,0x00001A8E,0xFFFFF727,0x0000033B,0x00001A8E,0xFFFFF727,0x0000033B},
- {"0000001000010011111100001111110101000010110110100011100100100100",0x000039D3,0xFFFFE5D3,0x000005B0,0x00001888,0xFFFFF978,0x000002C8,0x00001888,0xFFFFF978,0x000002C8},
- {"0000001000010011111100001111111010011001000011100100100001100100",0x00002F6B,0xFFFFEC53,0x000004B9,0x00001C15,0xFFFFF71B,0x00000337,0x00001C15,0xFFFFF71B,0x00000337},
- {"0000001000010011111100001111111010011001000001100100000101000100",0x0000384D,0xFFFFE737,0x00000569,0x00001D2D,0xFFFFF673,0x00000343,0x00001D2D,0xFFFFF673,0x00000343},
- {"0000001000010011111100001111111010011001000001100010000010100100",0x00003A49,0xFFFFE70B,0x0000055F,0x00001A63,0xFFFFF8CD,0x000002E2,0x00001A63,0xFFFFF8CD,0x000002E2},
- {"0000001000010011111100001111111010011001000001000010100110000100",0x0000311E,0xFFFFEB97,0x000004C6,0x00001EAE,0xFFFFF5A9,0x00000367,0x00001EAE,0xFFFFF5A9,0x00000367},
- {"0000001000010011111100001111111010011001000011100001000100100100",0x000027D3,0xFFFFF075,0x00000417,0x00002001,0xFFFFF44A,0x000003A2,0x00002001,0xFFFFF44A,0x000003A2},
- {"0000001000010011111100001111111010011001000001100100100100000100",0x00003B72,0xFFFFE4BD,0x000005DC,0x00001D76,0xFFFFF606,0x0000035A,0x00001D76,0xFFFFF606,0x0000035A},
- {"0000001000010011111100001111111010011001000100000001000100100100",0x00002E0F,0xFFFFECA7,0x000004AE,0x00001DC6,0xFFFFF5BF,0x0000036A,0x00001DC6,0xFFFFF5BF,0x0000036A},
- {"0000001000010011111100001111111010011001000000100011100010100100",0x000032C7,0xFFFFEA7A,0x000004F0,0x00001A7B,0xFFFFF827,0x00000301,0x00001A7B,0xFFFFF827,0x00000301},
- {"0000001000010011111010101001010011011110000001000100100010000100",0x0000312D,0xFFFFEA39,0x00000515,0x00001948,0xFFFFF800,0x00000318,0x00001948,0xFFFFF800,0x00000318},
- {"0000001000010011111010101001010011011110000001100010000010000100",0x00003611,0xFFFFE8D7,0x00000533,0x00001929,0xFFFFF965,0x000002D2,0x00001929,0xFFFFF965,0x000002D2},
- {"0000001000010011111100001111111010011001001011000011000011100100",0x00002FE2,0xFFFFED89,0x00000470,0x00001A3C,0xFFFFF955,0x000002D5,0x00001A3C,0xFFFFF955,0x000002D5},
- {"0000001000010011111010101001010011011110000000100000100010100100",0x000035FF,0xFFFFE884,0x00000548,0x0000182A,0xFFFFF9AB,0x000002CF,0x0000182A,0xFFFFF9AB,0x000002CF},
- {"0000001000010011111100001111111010011001000000100010000011100100",0x00003597,0xFFFFE904,0x00000528,0x00001A94,0xFFFFF840,0x00000300,0x00001A94,0xFFFFF840,0x00000300},
- {"0000001000010011111100001111111010011001000110000001100101000100",0x000026CB,0xFFFFF1FB,0x000003E4,0x000017CC,0xFFFFFA25,0x000002C8,0x000017CC,0xFFFFFA25,0x000002C8},
- {"0000001000010011111010101001010011011110000001100000100011000100",0x00003274,0xFFFFEA39,0x0000050C,0x00001B20,0xFFFFF7C1,0x00000314,0x00001B20,0xFFFFF7C1,0x00000314},
- {"0000001000010011111100001111110101000010110110000010100100100100",0x0000280B,0xFFFFF283,0x000003B5,0x000018D0,0xFFFFF992,0x000002EC,0x000018D0,0xFFFFF992,0x000002EC},
- {"0000001000010011111100001111111010011001000001100010000100000100",0x000033AB,0xFFFFEB1B,0x000004C4,0x00001FEE,0xFFFFF53A,0x00000378,0x00001FEE,0xFFFFF53A,0x00000378},
- {"0000001000010011111100001111111010011001000010100011100101100100",0x00002F79,0xFFFFEB0C,0x000004FA,0x00001E57,0xFFFFF4BF,0x0000039B,0x00001E57,0xFFFFF4BF,0x0000039B},
- {"0000001000010011111100001111111010011001000001000100100011100100",0x00003487,0xFFFFE8F2,0x00000539,0x0000185B,0xFFFFF9AE,0x000002BA,0x0000185B,0xFFFFF9AE,0x000002BA},
- {"0000001000010011111100001111111010011001000010100001100010100100",0x00003500,0xFFFFE793,0x0000058A,0x00001AA2,0xFFFFF792,0x0000031D,0x00001AA2,0xFFFFF792,0x0000031D},
- {"0000001000010011111100001111111010011001000010000001000101100100",0x00003943,0xFFFFE54D,0x000005D9,0x00001BC8,0xFFFFF6E0,0x00000339,0x00001BC8,0xFFFFF6E0,0x00000339},
- {"0000001000010011111010101001010011011110000001000011000010100100",0x0000306D,0xFFFFEC5E,0x000004A5,0x00001A3A,0xFFFFF85F,0x00000304,0x00001A3A,0xFFFFF85F,0x00000304},
- {"0000001000010011111100001111110101000010110110000011000010000100",0x00002BA4,0xFFFFEE8D,0x0000046A,0x0000198C,0xFFFFF88E,0x00000307,0x0000198C,0xFFFFF88E,0x00000307},
- {"0000001000010011111100001111110101000010110100100001100011100100",0x00003D30,0xFFFFE2F6,0x0000062A,0x000025DC,0xFFFFF074,0x00000435,0x000025DC,0xFFFFF074,0x00000435},
- {"0000001000010011111100001111110101000010110110000011100101100100",0x00002CD6,0xFFFFED79,0x0000049B,0x000016D0,0xFFFFFA53,0x000002BB,0x000016D0,0xFFFFFA53,0x000002BB},
- {"0000001000010011111100001111111010011001000101100011000101100100",0x00002484,0xFFFFF3BD,0x000003A0,0x000015B8,0xFFFFFB6B,0x000002A4,0x000015B8,0xFFFFFB6B,0x000002A4},
- {"0000001000010011111100001111111010011001000011100011100101000100",0x000038AE,0xFFFFE6D1,0x00000587,0x00001A2A,0xFFFFF8F1,0x000002D4,0x00001A2A,0xFFFFF8F1,0x000002D4},
- {"0000001000010011111100001111111010011001000001000100100101000100",0x000036FD,0xFFFFE76C,0x00000576,0x00001EE4,0xFFFFF58D,0x00000361,0x00001EE4,0xFFFFF58D,0x00000361},
- {"0000001000010011111100001111110101000010110110000011000010100100",0x00002BCF,0xFFFFEF28,0x00000448,0x00001B93,0xFFFFF7BA,0x00000327,0x00001B93,0xFFFFF7BA,0x00000327},
- {"0000001000010011111100001111111010011001000001100010100010000100",0x00003834,0xFFFFE818,0x0000053B,0x00001AFE,0xFFFFF85C,0x000002F3,0x00001AFE,0xFFFFF85C,0x000002F3},
- {"0000001000010011111100001111111010011001001100100011000110100100",0x00002EF7,0xFFFFEBFC,0x000004CE,0x00001897,0xFFFFF8EF,0x000002EC,0x00001897,0xFFFFF8EF,0x000002EC},
- {"0000001000010011111100001111111010011001001011000001100011000100",0x000035BD,0xFFFFE8BB,0x0000053B,0x00001F22,0xFFFFF561,0x00000373,0x00001F22,0xFFFFF561,0x00000373},
- {"0000001000010011111100001111111010011001000110000011100110000100",0x00002D42,0xFFFFEE1D,0x00000478,0x000016F0,0xFFFFFAAE,0x000002B3,0x000016F0,0xFFFFFAAE,0x000002B3},
- {"0000001000010011111010101001010011011110000001000101000100100100",0x00002F98,0xFFFFEB3C,0x000004F0,0x00001903,0xFFFFF818,0x00000319,0x00001903,0xFFFFF818,0x00000319},
- {"0000001000010011111100001111110101000010110101000010000101000100",0x00004081,0xFFFFDF13,0x000006F3,0x00002A6D,0xFFFFEC1B,0x00000509,0x00002A6D,0xFFFFEC1B,0x00000509},
- {"0000001000010011111010101001010011011110000001000000100100000100",0x00002D68,0xFFFFED21,0x00000498,0x00001FF6,0xFFFFF427,0x000003B0,0x00001FF6,0xFFFFF427,0x000003B0},
- {"0000001000010011111100001111111010011001000000100011100010000100",0x00003243,0xFFFFEA5C,0x000004FD,0x000020FB,0xFFFFF39E,0x000003C0,0x000020FB,0xFFFFF39E,0x000003C0},
- {"0000001000010011111100001111110101000010110110000100100010100100",0x00002F20,0xFFFFEC19,0x000004C6,0x00001748,0xFFFFF99F,0x000002DA,0x00001748,0xFFFFF99F,0x000002DA},
- {"0000001000010011111100001111111010011001000100000011100110000100",0x00002D68,0xFFFFED21,0x00000498,0x00001A43,0xFFFFF843,0x000002F9,0x00001A43,0xFFFFF843,0x000002F9},
- {"0000001000010011111100001111111010011001000000100010000010100100",0x0000396E,0xFFFFE616,0x000005A9,0x00001A51,0xFFFFF850,0x000002FA,0x00001A51,0xFFFFF850,0x000002FA},
- {"0000001000010011111100001111111010011001000001000011000101000100",0x0000305C,0xFFFFED4B,0x0000046C,0x00001CF9,0xFFFFF7BA,0x00000304,0x00001CF9,0xFFFFF7BA,0x00000304},
- {"0000001000010011111100001111110101000010110110100100000101100100",0x0000343C,0xFFFFE869,0x00000559,0x00001CE2,0xFFFFF614,0x00000359,0x00001CE2,0xFFFFF614,0x00000359},
- {"0000001000010011111100001111111010011001000110000011100101100100",0x00002782,0xFFFFF1FE,0x000003D9,0x000015DC,0xFFFFFB8B,0x00000290,0x000015DC,0xFFFFFB8B,0x00000290},
- {"0000001000010011111100001111111010011001000110000001100011000100",0x00002B9C,0xFFFFEF63,0x00000443,0x00001369,0xFFFFFD51,0x00000244,0x00001369,0xFFFFFD51,0x00000244},
- {"0000001000010011111100001111111010011001000010100010000010000100",0x000035F8,0xFFFFE743,0x00000592,0x000018D8,0xFFFFF8EE,0x000002E4,0x000018D8,0xFFFFF8EE,0x000002E4},
- {"0000001000010011111010101001010011011110000001100010100001000100",0x00002B72,0xFFFFEF1E,0x0000043C,0x00002647,0xFFFFF092,0x0000043E,0x00002647,0xFFFFF092,0x0000043E},
- {"0000001000010011111100001111111010011001000100000010000110000100",0x00002EC9,0xFFFFEC5F,0x000004B8,0x000018B6,0xFFFFF936,0x000002D8,0x000018B6,0xFFFFF936,0x000002D8},
- {"0000001000010011111100001111111010011001000001100100000010000100",0x000038A7,0xFFFFE6AC,0x00000589,0x00001C42,0xFFFFF70B,0x00000329,0x00001C42,0xFFFFF70B,0x00000329},
- {"0000001000010011111100001111111010011001001100000000100010100100",0x00002F6B,0xFFFFEBF6,0x000004CF,0x000018AE,0xFFFFF928,0x000002E3,0x000018AE,0xFFFFF928,0x000002E3},
- {"0000001000010011111100001111110101000010110110100101000100000100",0x000029CD,0xFFFFEEE1,0x00000459,0x00001AB5,0xFFFFF76F,0x00000324,0x00001AB5,0xFFFFF76F,0x00000324},
- {"0000001000010011111010101001010011011110000001100011100011000100",0x00003921,0xFFFFE71D,0x00000577,0x00001646,0xFFFFFB24,0x00000293,0x00001646,0xFFFFFB24,0x00000293},
- {"0000001000010011111010101001010011011110000001000100000101100100",0x00003940,0xFFFFE521,0x000005E8,0x00001947,0xFFFFF839,0x0000030D,0x00001947,0xFFFFF839,0x0000030D},
- {"0000001000010011111100001111110101000010110100100100000101100100",0x00003DCA,0xFFFFE211,0x00000659,0x0000250E,0xFFFFF072,0x00000443,0x0000250E,0xFFFFF072,0x00000443},
- {"0000001000010011111100001111111010011001000011000000100100000100",0x00002E95,0xFFFFEC20,0x000004C9,0x000015B4,0xFFFFFAD3,0x0000029D,0x000015B4,0xFFFFFAD3,0x0000029D},
- {"0000001000010011111100001111111010011001000001000001000010000100",0x00002C11,0xFFFFEE6E,0x00000468,0x00001901,0xFFFFF924,0x000002E7,0x00001901,0xFFFFF924,0x000002E7},
- {"0000001000010011111010101001010011011110000001100010000100000100",0x0000293F,0xFFFFF158,0x000003E6,0x0000183F,0xFFFFF9F6,0x000002D2,0x0000183F,0xFFFFF9F6,0x000002D2},
- {"0000001000010011111100001111111010011001000011100001000100000100",0x00002A67,0xFFFFEF34,0x0000043E,0x00001C6F,0xFFFFF6F1,0x0000032B,0x00001C6F,0xFFFFF6F1,0x0000032B},
- {"0000001000010011111010101001010011011110000001100101000100100100",0x00002F8D,0xFFFFEB77,0x000004DA,0x00001C0D,0xFFFFF627,0x00000365,0x00001C0D,0xFFFFF627,0x00000365},
- {"0000001000010011111100001111111010011001000011000011100011000100",0x00003476,0xFFFFEA5B,0x000004E7,0x00001DBF,0xFFFFF6C7,0x00000333,0x00001DBF,0xFFFFF6C7,0x00000333},
- {"0000001000010011111100001111111010011001000011100000100101000100",0x00003336,0xFFFFE92F,0x00000546,0x00001614,0xFFFFFAE0,0x00000296,0x00001614,0xFFFFFAE0,0x00000296},
- {"0000001000010011111100001111111010011001000101100010000101100100",0x00002513,0xFFFFF323,0x000003BC,0x000016DB,0xFFFFFA79,0x000002CD,0x000016DB,0xFFFFFA79,0x000002CD},
- {"0000001000010011111100001111111010011001000010100010100101000100",0x000035A7,0xFFFFE78E,0x00000584,0x00001B0D,0xFFFFF77D,0x0000031F,0x00001B0D,0xFFFFF77D,0x0000031F},
- {"0000001000010011111100001111111010011001001100100011100011100100",0x00003171,0xFFFFEB98,0x000004C6,0x00001C76,0xFFFFF71F,0x0000032F,0x00001C76,0xFFFFF71F,0x0000032F},
- {"0000001000010011111100001111110101000010110110100001000010000100",0x00002C52,0xFFFFED2E,0x000004A7,0x00002182,0xFFFFF2F4,0x000003E4,0x00002182,0xFFFFF2F4,0x000003E4},
- {"0000001000010011111100001111111010011001000100000010100100100100",0x000032E1,0xFFFFEB39,0x000004D0,0x00001B55,0xFFFFF859,0x000002FA,0x00001B55,0xFFFFF859,0x000002FA},
- {"0000001000010011111100001111111010011001000110000100100010100100",0x000029B6,0xFFFFEFF7,0x00000430,0x0000151B,0xFFFFFBC6,0x0000027F,0x0000151B,0xFFFFFBC6,0x0000027F},
- {"0000001000010011111100001111110101000010110110100001100101100100",0x00002FF7,0xFFFFEB67,0x000004DA,0x000020E9,0xFFFFF363,0x000003CE,0x000020E9,0xFFFFF363,0x000003CE},
- {"0000001000010011111100001111110101000010110110100101000100100100",0x00003CDD,0xFFFFE2B2,0x00000649,0x00001B18,0xFFFFF739,0x00000329,0x00001B18,0xFFFFF739,0x00000329},
- {"0000001000010011111100001111111010011001000001100010100010100100",0x00003C82,0xFFFFE5C6,0x0000058E,0x00001F3F,0xFFFFF5AD,0x00000361,0x00001F3F,0xFFFFF5AD,0x00000361},
- {"0000001000010011111100001111110101000010110111000100000010000100",0x0000319B,0xFFFFEA15,0x0000051B,0x00001CC9,0xFFFFF62E,0x00000358,0x00001CC9,0xFFFFF62E,0x00000358},
- {"0000001000010011111010101001010011011110000001100011100011100100",0x000032B6,0xFFFFEB2B,0x000004D6,0x000018E0,0xFFFFF966,0x000002DE,0x000018E0,0xFFFFF966,0x000002DE},
- {"0000001000010011111010101001010011011110000000100011100110000100",0x0000300A,0xFFFFEBA6,0x000004D1,0x00001CFD,0xFFFFF5F6,0x0000036D,0x00001CFD,0xFFFFF5F6,0x0000036D},
- {"0000001000010011111100001111110101000010110110000010100110000100",0x000026A9,0xFFFFF15D,0x00000400,0x00001561,0xFFFFFB1F,0x000002A0,0x00001561,0xFFFFFB1F,0x000002A0},
- {"0000001000010011111100001111111010011001000011100101000100100100",0x00003123,0xFFFFEAD2,0x000004FA,0x000018CB,0xFFFFF8F5,0x000002EC,0x000018CB,0xFFFFF8F5,0x000002EC},
- {"0000001000010011111100001111111010011001000110000100000011000100",0x00003577,0xFFFFE935,0x00000533,0x000016CD,0xFFFFFB44,0x00000289,0x000016CD,0xFFFFFB44,0x00000289},
- {"0000001000010011111100001111111010011001001010000010000110000100",0x00002875,0xFFFFF170,0x000003F3,0x00001567,0xFFFFFBD5,0x00000289,0x00001567,0xFFFFFBD5,0x00000289},
- {"0000001000010011111100001111111010011001000010000100000010000100",0x00003AE2,0xFFFFE538,0x000005C1,0x00001CB4,0xFFFFF6A3,0x0000033C,0x00001CB4,0xFFFFF6A3,0x0000033C},
- {"0000001000010011111100001111111010011001000011000011100011100100",0x000031DF,0xFFFFEC2A,0x000004A3,0x00001EF0,0xFFFFF626,0x00000352,0x00001EF0,0xFFFFF626,0x00000352},
- {"0000001000010011111100001111110101000010110100100101000101000100",0x00004A6A,0xFFFFDB15,0x00000758,0x000027F3,0xFFFFEEEE,0x00000479,0x000027F3,0xFFFFEEEE,0x00000479},
- {"0000001000010011111010101001010011011110000001100011100100000100",0x00002BB9,0xFFFFEF5D,0x00000433,0x00001589,0xFFFFFB57,0x00000295,0x00001589,0xFFFFFB57,0x00000295},
- {"0000001000010011111100001111111010011001000001000010000101100100",0x000033A0,0xFFFFE98F,0x00000528,0x00001CB4,0xFFFFF706,0x0000032D,0x00001CB4,0xFFFFF706,0x0000032D},
- {"0000001000010011111100001111111010011001000101100011000001100100",0x0000248E,0xFFFFF380,0x000003AC,0x000016EA,0xFFFFFA6C,0x000002CE,0x000016EA,0xFFFFFA6C,0x000002CE},
- {"0000001000010011111100001111111010011001000000100010000110100100",0x00002FE2,0xFFFFEB2F,0x000004E9,0x00001D4E,0xFFFFF56B,0x00000380,0x00001D4E,0xFFFFF56B,0x00000380},
- {"0000001000010011111100001111111010011001000010100010100010000100",0x00003283,0xFFFFE9E7,0x0000051D,0x00000694,0xFFFFFD32,0x000003C3,0x00000694,0xFFFFFD32,0x000003C3},
- {"0000001000010011111100001111110101000010110110000101000011000100",0x00002EE4,0xFFFFEBFD,0x000004D3,0x0000151A,0xFFFFFAF6,0x000002A4,0x0000151A,0xFFFFFAF6,0x000002A4},
- {"0000001000010011111100001111110101000010110111000001100011100100",0x0000302D,0xFFFFEB7F,0x000004DA,0x00001E6D,0xFFFFF54B,0x00000380,0x00001E6D,0xFFFFF54B,0x00000380},
- {"0000001000010011111100001111110101000010110110100101000011000100",0x000033DA,0xFFFFE7FB,0x0000057F,0x00001DED,0xFFFFF50E,0x0000038D,0x00001DED,0xFFFFF50E,0x0000038D},
- {"0000001000010011111100001111111010011001001011000100000010000100",0x000030B5,0xFFFFEBB8,0x000004C4,0x00001C3F,0xFFFFF726,0x0000032A,0x00001C3F,0xFFFFF726,0x0000032A},
- {"0000001000010011111100001111111010011001000010000011000111000100",0x00003BBD,0xFFFFE55C,0x000005B8,0x000019DB,0xFFFFF8BB,0x000002EF,0x000019DB,0xFFFFF8BB,0x000002EF},
- {"0000001000010011111100001111111010011001000011100011100010000100",0x00002964,0xFFFFF051,0x0000040E,0x000025CD,0xFFFFF11B,0x0000041F,0x000025CD,0xFFFFF11B,0x0000041F},
- {"0000001000010011111100001111110101000010110111000100100010000100",0x000033F5,0xFFFFE863,0x00000560,0x00001BCE,0xFFFFF689,0x0000034B,0x00001BCE,0xFFFFF689,0x0000034B},
- {"0000001000010011111100001111111010011001000010100010100001100100",0x00003294,0xFFFFE924,0x00000548,0x00001D41,0xFFFFF580,0x0000037D,0x00001D41,0xFFFFF580,0x0000037D},
- {"0000001000010011111100001111110101000010110111000011100110100100",0x000034FB,0xFFFFE7FE,0x0000056D,0x00001CB1,0xFFFFF635,0x00000357,0x00001CB1,0xFFFFF635,0x00000357},
- {"0000001000010011111100001111111010011001000010100001000010100100",0x00002E28,0xFFFFEBB9,0x000004E0,0x00001B20,0xFFFFF6E3,0x0000033C,0x00001B20,0xFFFFF6E3,0x0000033C},
- {"0000001000010011111100001111110101000010110110100001100100000100",0x00002799,0xFFFFF0F4,0x000003FC,0x00001C9D,0xFFFFF6A1,0x00000345,0x00001C9D,0xFFFFF6A1,0x00000345},
- {"0000001000010011111100001111111010011001000001100100000100000100",0x00003AEA,0xFFFFE5DB,0x0000059D,0x00001B61,0xFFFFF7F0,0x00000301,0x00001B61,0xFFFFF7F0,0x00000301},
- {"0000001000010011111010101001010011011110000001000001100110000100",0x000031F6,0xFFFFEAB8,0x000004F3,0x00001D90,0xFFFFF622,0x00000359,0x00001D90,0xFFFFF622,0x00000359},
- {"0000001000010011111100001111111010011001000011000100000001100100",0x000031B8,0xFFFFEA61,0x0000050F,0x0000199D,0xFFFFF87C,0x000002FD,0x0000199D,0xFFFFF87C,0x000002FD},
- {"0000001000010011111100001111110101000010110100100011000101000100",0x00004514,0xFFFFDDFF,0x000006F6,0x000022CD,0xFFFFF29F,0x000003D9,0x000022CD,0xFFFFF29F,0x000003D9},
- {"0000001000010011111010101001010011011110000001000011000101100100",0x00002F30,0xFFFFECB8,0x000004A0,0x00001B07,0xFFFFF7E2,0x00000313,0x00001B07,0xFFFFF7E2,0x00000313},
- {"0000001000010011111100001111110101000010110111000011000010100100",0x0000383B,0xFFFFE702,0x00000581,0x00001A08,0xFFFFF8CA,0x000002E2,0x00001A08,0xFFFFF8CA,0x000002E2},
- {"0000001000010011111100001111111010011001000000100010000101100100",0x00002CC5,0xFFFFEDF8,0x00000465,0x00001F47,0xFFFFF4B2,0x00000393,0x00001F47,0xFFFFF4B2,0x00000393},
- {"0000001000010011111100001111111010011001000101100010000111000100",0x00002304,0xFFFFF453,0x00000384,0x0000170A,0xFFFFFA3F,0x000002CE,0x0000170A,0xFFFFFA3F,0x000002CE},
- {"0000001000010011111100001111111010011001000010100101000100100100",0x0000337E,0xFFFFE850,0x0000056E,0x00001BDD,0xFFFFF668,0x00000353,0x00001BDD,0xFFFFF668,0x00000353},
- {"0000001000010011111100001111111010011001000011100100100100100100",0x00002E2F,0xFFFFEC9B,0x000004AE,0x00001C4D,0xFFFFF6D3,0x00000338,0x00001C4D,0xFFFFF6D3,0x00000338},
- {"0000001000010011111010101001010011011110000001100001000100100100",0x00002DDD,0xFFFFEDA4,0x00000477,0x00002010,0xFFFFF4BB,0x00000390,0x00002010,0xFFFFF4BB,0x00000390},
- {"0000001000010011111100001111110101000010110110100100100011100100",0x0000290C,0xFFFFEF61,0x00000445,0x00002133,0xFFFFF324,0x000003D8,0x00002133,0xFFFFF324,0x000003D8},
- {"0000001000010011111100001111111010011001000001100010100100100100",0x0000371E,0xFFFFE8D5,0x00000524,0x00001C3A,0xFFFFF7AE,0x00000314,0x00001C3A,0xFFFFF7AE,0x00000314},
- {"0000001000010011111100001111110101000010110110000011100011100100",0x00002A58,0xFFFFF007,0x00000429,0x000018A6,0xFFFFF98F,0x000002E1,0x000018A6,0xFFFFF98F,0x000002E1},
- {"0000001000010011111100001111111010011001000000100011000010000100",0x00002FED,0xFFFFEC48,0x000004AA,0x00001E9D,0xFFFFF584,0x00000370,0x00001E9D,0xFFFFF584,0x00000370},
- {"0000001000010011111100001111111010011001000110000001100010000100",0x00002829,0xFFFFF15F,0x000003F7,0x0000157E,0xFFFFFBD4,0x00000282,0x0000157E,0xFFFFFBD4,0x00000282},
- {"0000001000010011111100001111111010011001000100000001100100100100",0x000030CF,0xFFFFEB8D,0x000004CE,0x00001A4C,0xFFFFF868,0x000002F7,0x00001A4C,0xFFFFF868,0x000002F7},
- {"0000001000010011111100001111110101000010110110100010000010000100",0x00002C8F,0xFFFFEDD2,0x0000047D,0x00001CCE,0xFFFFF6A1,0x00000343,0x00001CCE,0xFFFFF6A1,0x00000343},
- {"0000001000010011111100001111111010011001000110000010000101100100",0x00002A84,0xFFFFEFBA,0x0000043E,0x000015EF,0xFFFFFB4B,0x0000029E,0x000015EF,0xFFFFFB4B,0x0000029E},
- {"0000001000010011111100001111111010011001000011000010100010100100",0x000034CA,0xFFFFEA08,0x000004FF,0x00001C19,0xFFFFF7ED,0x00000309,0x00001C19,0xFFFFF7ED,0x00000309},
- {"0000001000010011111100001111111010011001000101100011100110100100",0x00002187,0xFFFFF4B0,0x0000037E,0x0000154A,0xFFFFFB0C,0x000002AE,0x0000154A,0xFFFFFB0C,0x000002AE},
- {"0000001000010011111100001111110101000010110110100011100001000100",0x00002F4F,0xFFFFEB3C,0x000004F8,0x0000181F,0xFFFFF92D,0x000002DF,0x0000181F,0xFFFFF92D,0x000002DF},
- {"0000001000010011111100001111111010011001000001000001000011100100",0x0000290C,0xFFFFF0B1,0x000003FC,0x00001DB0,0xFFFFF636,0x00000355,0x00001DB0,0xFFFFF636,0x00000355},
- {"0000001000010011111100001111111010011001000010100001000001100100",0x000034C1,0xFFFFE888,0x0000055A,0x000019BF,0xFFFFF881,0x000002FB,0x000019BF,0xFFFFF881,0x000002FB},
- {"0000001000010011111100001111110101000010110111000001100011000100",0x00003139,0xFFFFEA98,0x00000504,0x000019F2,0xFFFFF820,0x0000030B,0x000019F2,0xFFFFF820,0x0000030B},
- {"0000001000010011111100001111110101000010110110000011000101000100",0x00002CAC,0xFFFFEEB2,0x00000458,0x0000152C,0xFFFFFBEF,0x0000027B,0x0000152C,0xFFFFFBEF,0x0000027B},
- {"0000001000010011111100001111111010011001001011000011100011100100",0x00003577,0xFFFFE99C,0x0000050D,0x00001E64,0xFFFFF679,0x0000033F,0x00001E64,0xFFFFF679,0x0000033F},
- {"0000001000010011111100001111110101000010110110100100000100000100",0x0000263A,0xFFFFF1E4,0x000003D4,0x00001F68,0xFFFFF4ED,0x00000386,0x00001F68,0xFFFFF4ED,0x00000386},
- {"0000001000010011111100001111110101000010110110000001100110000100",0x00002CE9,0xFFFFED63,0x00000497,0x00001810,0xFFFFF94D,0x000002E3,0x00001810,0xFFFFF94D,0x000002E3},
- {"0000001000010011111010101001010011011110000001000100000100000100",0x0000318A,0xFFFFEAC8,0x000004F5,0x0000195C,0xFFFFF896,0x000002FB,0x0000195C,0xFFFFF896,0x000002FB},
- {"0000001000010011111100001111110101000010110110000011100100000100",0x00002C41,0xFFFFEEC6,0x0000045D,0x000017DD,0xFFFFFA16,0x000002CB,0x000017DD,0xFFFFFA16,0x000002CB},
- {"0000001000010011111100001111111010011001000000100011000110100100",0x00002DD4,0xFFFFEC98,0x000004AD,0x00001BD7,0xFFFFF69F,0x00000347,0x00001BD7,0xFFFFF69F,0x00000347},
- {"0000001000010011111100001111110101000010110110100011100101000100",0x00003351,0xFFFFE9B2,0x0000051A,0x00001CA1,0xFFFFF6A4,0x00000341,0x00001CA1,0xFFFFF6A4,0x00000341},
- {"0000001000010011111100001111111010011001000000100001000100000100",0x0000322D,0xFFFFE9BE,0x00000527,0x00001CF9,0xFFFFF5EB,0x00000366,0x00001CF9,0xFFFFF5EB,0x00000366},
- {"0000001000010011111100001111111010011001000011000010100011000100",0x00003678,0xFFFFE9A8,0x00000503,0x00001AD4,0xFFFFF8F6,0x000002E3,0x00001AD4,0xFFFFF8F6,0x000002E3},
- {"0000001000010011111100001111111010011001000101100001100100100100",0x0000260E,0xFFFFF2C1,0x000003CA,0x00001139,0xFFFFFE48,0x00000236,0x00001139,0xFFFFFE48,0x00000236},
- {"0000001000010011111100001111111010011001000010100010000101100100",0x000033D3,0xFFFFE872,0x00000565,0x00001B72,0xFFFFF713,0x00000332,0x00001B72,0xFFFFF713,0x00000332},
- {"0000001000010011111100001111111010011001001100100011100001000100",0x0000309B,0xFFFFEB42,0x000004E4,0x00001918,0xFFFFF8C8,0x000002F2,0x00001918,0xFFFFF8C8,0x000002F2},
- {"0000001000010011111100001111111010011001000110000010100001100100",0x000028B8,0xFFFFF105,0x00000402,0x000018BB,0xFFFFF9BC,0x000002D3,0x000018BB,0xFFFFF9BC,0x000002D3},
- {"0000001000010011111100001111111010011001000010100001100010000100",0x00003123,0xFFFFE9D1,0x00000534,0x00001B19,0xFFFFF6FE,0x0000033C,0x00001B19,0xFFFFF6FE,0x0000033C},
- {"0000001000010011111100001111111010011001000000100010000101000100",0x00003216,0xFFFFEA8E,0x000004F6,0x00001F72,0xFFFFF4CE,0x0000038B,0x00001F72,0xFFFFF4CE,0x0000038B},
- {"0000001000010011111100001111111010011001000101100010100101100100",0x00002564,0xFFFFF32D,0x000003B6,0x00001685,0xFFFFFADB,0x000002BB,0x00001685,0xFFFFFADB,0x000002BB},
- {"0000001000010011111100001111110101000010110110100010100100100100",0x00002E60,0xFFFFED13,0x00000497,0x00001CA5,0xFFFFF6B9,0x00000346,0x00001CA5,0xFFFFF6B9,0x00000346},
- {"0000001000010011111100001111111010011001000011100011100110100100",0x0000336D,0xFFFFE934,0x0000053B,0x00001B3E,0xFFFFF763,0x00000327,0x00001B3E,0xFFFFF763,0x00000327},
- {"0000001000010011111100001111111010011001000100000001000010000100",0x0000274A,0xFFFFF119,0x000003FA,0x00001D75,0xFFFFF5CD,0x0000036F,0x00001D75,0xFFFFF5CD,0x0000036F},
- {"0000001000010011111100001111110101000010110110100010000101100100",0x0000366B,0xFFFFE70A,0x0000059A,0x00001ED8,0xFFFFF501,0x00000389,0x00001ED8,0xFFFFF501,0x00000389},
- {"0000001000010011111100001111111010011001001000100011100101100100",0x00003164,0xFFFFEAB4,0x000004FA,0x00001C52,0xFFFFF6E0,0x00000336,0x00001C52,0xFFFFF6E0,0x00000336},
- {"0000001000010011111100001111110101000010110100100011000001100100",0x00004224,0xFFFFDF7F,0x000006C1,0x00002A52,0xFFFFED5E,0x000004BB,0x00002A52,0xFFFFED5E,0x000004BB},
- {"0000001000010011111100001111111010011001000100000010100001100100",0x000030E3,0xFFFFEB07,0x000004ED,0x00001FD3,0xFFFFF46D,0x000003A1,0x00001FD3,0xFFFFF46D,0x000003A1},
- {"0000001000010011111100001111110101000010110110000010100010000100",0x00002AEB,0xFFFFEF1B,0x00000454,0x00001829,0xFFFFF995,0x000002DD,0x00001829,0xFFFFF995,0x000002DD},
- {"0000001000010011111100001111110101000010110111000101000011100100",0x0000346B,0xFFFFE7A2,0x0000058B,0x000020C5,0xFFFFF2E8,0x000003EC,0x000020C5,0xFFFFF2E8,0x000003EC},
- {"0000001000010011111100001111110101000010110111000100000101100100",0x000039CF,0xFFFFE5D7,0x000005A9,0x00001D66,0xFFFFF5D6,0x00000366,0x00001D66,0xFFFFF5D6,0x00000366},
- {"0000001000010011111100001111111010011001000001000001100011100100",0x000034AC,0xFFFFE9AE,0x00000515,0x00001A28,0xFFFFF904,0x000002DC,0x00001A28,0xFFFFF904,0x000002DC},
- {"0000001000010011111100001111110101000010110111000010000010000100",0x00002D68,0xFFFFED21,0x00000498,0x00001C6F,0xFFFFF686,0x0000034C,0x00001C6F,0xFFFFF686,0x0000034C},
- {"0000001000010011111100001111111010011001000010000010000011000100",0x0000328B,0xFFFFEBA1,0x000004B4,0x00001DA3,0xFFFFF683,0x00000349,0x00001DA3,0xFFFFF683,0x00000349},
- {"0000001000010011111100001111111010011001000110000010100011000100",0x000027DC,0xFFFFF295,0x000003BF,0x000019C1,0xFFFFF98E,0x000002E8,0x000019C1,0xFFFFF98E,0x000002E8},
- {"0000001000010011111100001111111010011001000110000100000010000100",0x00002756,0xFFFFF1D7,0x000003DF,0x000015D9,0xFFFFFB51,0x00000298,0x000015D9,0xFFFFFB51,0x00000298},
- {"0000001000010011111100001111111010011001000010000011100010000100",0x00003526,0xFFFFE907,0x00000526,0x000017AB,0xFFFFFA12,0x000002AB,0x000017AB,0xFFFFFA12,0x000002AB},
- {"0000001000010011111100001111110101000010110110100001100011100100",0x0000351B,0xFFFFE8B7,0x00000540,0x00001A86,0xFFFFF821,0x00000303,0x00001A86,0xFFFFF821,0x00000303},
- {"0000001000010011111100001111111010011001000101100100000101000100",0x000024B2,0xFFFFF34E,0x000003B1,0x000018E2,0xFFFFF926,0x000002FC,0x000018E2,0xFFFFF926,0x000002FC},
- {"0000001000010011111100001111110101000010110110000010100010100100",0x00002F36,0xFFFFED5D,0x00000486,0x0000157A,0xFFFFFB85,0x00000293,0x0000157A,0xFFFFFB85,0x00000293},
- {"0000001000010011111100001111110101000010110111000101000011000100",0x00003A6E,0xFFFFE456,0x000005FD,0x00001F68,0xFFFFF3D1,0x000003C3,0x00001F68,0xFFFFF3D1,0x000003C3},
- {"0000001000010011111100001111111010011001000010100011000110100100",0x00002BC3,0xFFFFED2D,0x000004A7,0x00001C3F,0xFFFFF609,0x00000364,0x00001C3F,0xFFFFF609,0x00000364},
- {"0000001000010011111100001111111010011001000011100010000010000100",0x000032E1,0xFFFFEA83,0x000004F6,0x00001B37,0xFFFFF842,0x000002F5,0x00001B37,0xFFFFF842,0x000002F5},
- {"0000001000010011111100001111110101000010110110000011000110000100",0x000028E3,0xFFFFF07F,0x00000412,0x00001676,0xFFFFFA68,0x000002BE,0x00001676,0xFFFFFA68,0x000002BE},
- {"0000001000010011111100001111110101000010110100100001000100000100",0x0000444C,0xFFFFDDAD,0x00000712,0x00002634,0xFFFFEF89,0x0000046C,0x00002634,0xFFFFEF89,0x0000046C},
- {"0000001000010011111100001111111010011001000001000001100011000100",0x00003121,0xFFFFEBBB,0x000004C6,0x00001C98,0xFFFFF72B,0x0000032D,0x00001C98,0xFFFFF72B,0x0000032D},
- {"0000001000010011111100001111110101000010110110000100000010100100",0x00002C31,0xFFFFEDC4,0x00000490,0x0000162D,0xFFFFFA8E,0x000002B4,0x0000162D,0xFFFFFA8E,0x000002B4},
- {"0000001000010011111100001111110101000010110110100001100011000100",0x00002749,0xFFFFF112,0x000003FC,0x00001C85,0xFFFFF6B8,0x00000342,0x00001C85,0xFFFFF6B8,0x00000342},
- {"0000001000010011111100001111111010011001000001000100000100000100",0x00003159,0xFFFFEB99,0x000004C2,0x00001BD0,0xFFFFF7CA,0x00000307,0x00001BD0,0xFFFFF7CA,0x00000307},
- {"0000001000010011111100001111111010011001000101100100000101100100",0x00002610,0xFFFFF1FD,0x000003EC,0x000016BE,0xFFFFFA53,0x000002CB,0x000016BE,0xFFFFFA53,0x000002CB},
- {"0000001000010011111100001111111010011001000000100011000110000100",0x000037B5,0xFFFFE63D,0x000005B5,0x00002285,0xFFFFF25D,0x000003F7,0x00002285,0xFFFFF25D,0x000003F7},
- {"0000001000010011111100001111111010011001000010100010100010100100",0x00002FEE,0xFFFFEB47,0x000004EF,0x00001CBE,0xFFFFF64E,0x00000358,0x00001CBE,0xFFFFF64E,0x00000358},
- {"0000001000010011111100001111111010011001000100000101000100000100",0x00002E90,0xFFFFEC48,0x000004C0,0x00001A47,0xFFFFF7D1,0x0000031A,0x00001A47,0xFFFFF7D1,0x0000031A},
- {"0000001000010011111100001111110101000010110110100100000010000100",0x000034AB,0xFFFFE84A,0x00000559,0x00001A72,0xFFFFF79A,0x0000031C,0x00001A72,0xFFFFF79A,0x0000031C},
- {"0000001000010011111100001111111010011001000110000011100010000100",0x00002F7B,0xFFFFECFC,0x0000049C,0x00001814,0xFFFFFA22,0x000002C2,0x00001814,0xFFFFFA22,0x000002C2},
- {"0000001000010011111100001111111010011001000000100001100101100100",0x00003618,0xFFFFE709,0x00000596,0x00001EBF,0xFFFFF482,0x000003A5,0x00001EBF,0xFFFFF482,0x000003A5},
- {"0000001000010011111010101001010011011110000000100100100100000100",0x0000341B,0xFFFFE8B2,0x0000054F,0x00001D26,0xFFFFF578,0x00000388,0x00001D26,0xFFFFF578,0x00000388},
- {"0000001000010011111100001111111010011001000100000010000101000100",0x000030F6,0xFFFFEB89,0x000004CD,0x000019C0,0xFFFFF8CC,0x000002E6,0x000019C0,0xFFFFF8CC,0x000002E6},
- {"0000001000010011111100001111111010011001001010000100000110100100",0x00002B76,0xFFFFEF6C,0x00000444,0x00001563,0xFFFFFBBE,0x0000028D,0x00001563,0xFFFFFBBE,0x0000028D},
- {"0000001000010011111100001111110101000010110110000001100001100100",0x00002BA2,0xFFFFEE31,0x0000047F,0x00001A3D,0xFFFFF7F3,0x00000320,0x00001A3D,0xFFFFF7F3,0x00000320},
- {"0000001000010011111100001111111010011001001011000100100011100100",0x00003545,0xFFFFE87A,0x0000054A,0x00001B5A,0xFFFFF7B0,0x0000030C,0x00001B5A,0xFFFFF7B0,0x0000030C},
- {"0000001000010011111010101001010011011110000001000010100101000100",0x00003879,0xFFFFE73F,0x00000578,0x00001649,0xFFFFFB57,0x00000283,0x00001649,0xFFFFFB57,0x00000283},
- {"0000001000010011111100001111110101000010110110000100000011000100",0x00002772,0xFFFFF0F1,0x00000410,0x0000142F,0xFFFFFBCF,0x00000287,0x0000142F,0xFFFFFBCF,0x00000287},
- {"0000001000010011111100001111110101000010110110100011000110000100",0x00003228,0xFFFFE98E,0x00000535,0x00001F48,0xFFFFF495,0x00000399,0x00001F48,0xFFFFF495,0x00000399},
- {"0000001000010011111100001111111010011001000011100100000011100100",0x00002887,0xFFFFF119,0x000003E8,0x000021AA,0xFFFFF3F5,0x000003A5,0x000021AA,0xFFFFF3F5,0x000003A5},
- {"0000001000010011111100001111110101000010110110100010100010100100",0x0000301F,0xFFFFEBB2,0x000004D2,0x00001C02,0xFFFFF736,0x0000032B,0x00001C02,0xFFFFF736,0x0000032B},
- {"0000001000010011111100001111111010011001000110000010000010100100",0x00002E13,0xFFFFEE3F,0x00000468,0x000016AC,0xFFFFFB32,0x0000029E,0x000016AC,0xFFFFFB32,0x0000029E},
- {"0000001000010011111100001111111010011001000001000100100100100100",0x00003478,0xFFFFE8F9,0x00000538,0x00001DAB,0xFFFFF645,0x00000345,0x00001DAB,0xFFFFF645,0x00000345},
- {"0000001000010011111100001111111010011001000001100000100011000100",0x000030C6,0xFFFFEB6C,0x000004D4,0x0000184A,0xFFFFF934,0x000002E1,0x0000184A,0xFFFFF934,0x000002E1},
- {"0000001000010011111100001111111010011001000010100010000001000100",0x00002F1B,0xFFFFEBD3,0x000004D3,0x000019E7,0xFFFFF813,0x0000030D,0x000019E7,0xFFFFF813,0x0000030D},
- {"0000001000010011111100001111111010011001000000100011100100000100",0x00003214,0xFFFFEAE9,0x000004E0,0x0000178F,0xFFFFFA1C,0x000002B1,0x0000178F,0xFFFFFA1C,0x000002B1},
- {"0000001000010011111100001111110101000010110111000011000101000100",0x0000399C,0xFFFFE738,0x0000055E,0x00001EA1,0xFFFFF5E7,0x0000035A,0x00001EA1,0xFFFFF5E7,0x0000035A},
- {"0000001000010011111100001111111010011001000001100101000011000100",0x00003A01,0xFFFFE5B2,0x000005B6,0x00001D95,0xFFFFF5D2,0x0000036A,0x00001D95,0xFFFFF5D2,0x0000036A},
- {"0000001000010011111100001111111010011001000001000011100010000100",0x0000310D,0xFFFFEB78,0x000004D0,0x00001C06,0xFFFFF76E,0x0000031A,0x00001C06,0xFFFFF76E,0x0000031A},
- {"0000001000010011111100001111111010011001000001100011100001100100",0x00003CD1,0xFFFFE42F,0x000005EB,0x00001933,0xFFFFF91F,0x000002D4,0x00001933,0xFFFFF91F,0x000002D4},
- {"0000001000010011111100001111110101000010110110100011000101100100",0x00003119,0xFFFFEB1B,0x000004E1,0x00001FC7,0xFFFFF46A,0x000003A2,0x00001FC7,0xFFFFF46A,0x000003A2},
- {"0000001000010011111010101001010011011110000001100100100010100100",0x0000390D,0xFFFFE566,0x000005D8,0x00001EC6,0xFFFFF4DC,0x00000391,0x00001EC6,0xFFFFF4DC,0x00000391},
- {"0000001000010011111100001111110101000010110110100001000011000100",0x00003446,0xFFFFE858,0x00000561,0x00001FDB,0xFFFFF3FF,0x000003B9,0x00001FDB,0xFFFFF3FF,0x000003B9},
- {"0000001000010011111100001111111010011001000001000100100100000100",0x000032BA,0xFFFFEA07,0x00000511,0x00001B25,0xFFFFF7C9,0x0000030D,0x00001B25,0xFFFFF7C9,0x0000030D},
- {"0000001000010011111100001111111010011001000011100001100001100100",0x00002CCF,0xFFFFEDE5,0x00000478,0x00001BC8,0xFFFFF761,0x00000326,0x00001BC8,0xFFFFF761,0x00000326},
- {"0000001000010011111100001111111010011001000001100010100110000100",0x0000400E,0xFFFFE1CB,0x00000652,0x00001AF8,0xFFFFF7B9,0x00000312,0x00001AF8,0xFFFFF7B9,0x00000312},
- {"0000001000010011111100001111111010011001000001000000100011100100",0x00002F24,0xFFFFEC2A,0x000004C7,0x00001B94,0xFFFFF748,0x00000333,0x00001B94,0xFFFFF748,0x00000333},
- {"0000001000010011111100001111110101000010110100100001100100100100",0x00003FDA,0xFFFFE1C1,0x0000064B,0x00002427,0xFFFFF180,0x0000040C,0x00002427,0xFFFFF180,0x0000040C},
- {"0000001000010011111100001111111010011001000010100001100011000100",0x00002F6B,0xFFFFEBA7,0x000004DD,0x00001C25,0xFFFFF6C1,0x00000344,0x00001C25,0xFFFFF6C1,0x00000344},
- {"0000001000010011111100001111111010011001000110000010000100000100",0x00002A53,0xFFFFF0EE,0x00000402,0x000017C6,0xFFFFFAA0,0x000002BF,0x000017C6,0xFFFFFAA0,0x000002BF},
- {"0000001000010011111100001111111010011001000100000101000101000100",0x000031F4,0xFFFFEA34,0x00000517,0x000016FF,0xFFFFFA4E,0x000002AC,0x000016FF,0xFFFFFA4E,0x000002AC},
- {"0000001000010011111100001111111010011001001100100010000101000100",0x00002E24,0xFFFFED46,0x00000489,0x00001712,0xFFFFFA5D,0x000002AC,0x00001712,0xFFFFFA5D,0x000002AC},
- {"0000001000010011111100001111111010011001000110000010100000100100",0x000028CD,0xFFFFF0E3,0x0000040E,0x00001606,0xFFFFFB37,0x000002A4,0x00001606,0xFFFFFB37,0x000002A4},
- {"0000001000010011111100001111111010011001000000100010000011000100",0x00003184,0xFFFFEB88,0x000004C3,0x000018DA,0xFFFFF939,0x000002DB,0x000018DA,0xFFFFF939,0x000002DB},
- {"0000001000010011111100001111111010011001000101100010000100100100",0x0000239B,0xFFFFF470,0x00000386,0x00001714,0xFFFFFA9F,0x000002C8,0x00001714,0xFFFFFA9F,0x000002C8},
- {"0000001000010011111100001111110101000010110111000011100011100100",0x00003641,0xFFFFE92B,0x00000515,0x00001BE2,0xFFFFF795,0x0000031B,0x00001BE2,0xFFFFF795,0x0000031B},
- {"0000001000010011111100001111111010011001001011000001000101000100",0x00003278,0xFFFFEA17,0x00000510,0x00001B71,0xFFFFF778,0x0000031D,0x00001B71,0xFFFFF778,0x0000031D},
- {"0000001000010011111100001111111010011001000001100010100001000100",0x000035B9,0xFFFFE8DA,0x0000052D,0x00001A6A,0xFFFFF83B,0x000002FF,0x00001A6A,0xFFFFF83B,0x000002FF},
- {"0000001000010011111100001111111010011001000011100001100011000100",0x00002E5E,0xFFFFED32,0x0000048B,0x00001E7D,0xFFFFF60E,0x0000034E,0x00001E7D,0xFFFFF60E,0x0000034E},
- {"0000001000010011111100001111111010011001000100000001100110100100",0x00003178,0xFFFFEA52,0x00000513,0x00001AD0,0xFFFFF793,0x0000031F,0x00001AD0,0xFFFFF793,0x0000031F},
- {"0000001000010011111100001111110101000010110101000100000100000100",0x00003A2C,0xFFFFE346,0x00000641,0x000023D0,0xFFFFF0CE,0x00000433,0x000023D0,0xFFFFF0CE,0x00000433},
- {"0000001000010011111100001111110101000010110110000001100011000100",0x000028FD,0xFFFFF02A,0x0000042B,0x0000152B,0xFFFFFB90,0x00000289,0x0000152B,0xFFFFFB90,0x00000289},
- {"0000001000010011111100001111111010011001000011100011000010000100",0x000030DE,0xFFFFEBDF,0x000004BE,0x00001CDC,0xFFFFF747,0x0000031C,0x00001CDC,0xFFFFF747,0x0000031C},
- {"0000001000010011111100001111111010011001000000100001100101000100",0x000036CB,0xFFFFE6EE,0x00000596,0x00002096,0xFFFFF3C2,0x000003BB,0x00002096,0xFFFFF3C2,0x000003BB},
- {"0000001000010011111100001111111010011001000011000100100011000100",0x00003172,0xFFFFEAC1,0x000004F4,0x00001C87,0xFFFFF6CD,0x00000337,0x00001C87,0xFFFFF6CD,0x00000337},
- {"0000001000010011111100001111110101000010110100100100100001100100",0x00004A18,0xFFFFDB34,0x00000758,0x0000213C,0xFFFFF3A2,0x000003AC,0x0000213C,0xFFFFF3A2,0x000003AC},
- {"0000001000010011111100001111111010011001000000100010000100000100",0x000031F3,0xFFFFEB73,0x000004C6,0x00001B23,0xFFFFF7CB,0x0000031A,0x00001B23,0xFFFFF7CB,0x0000031A},
- {"0000001000010011111100001111111010011001000010100010100100100100",0x000031C0,0xFFFFEABA,0x000004F7,0x00001A5A,0xFFFFF845,0x000002FF,0x00001A5A,0xFFFFF845,0x000002FF},
- {"0000001000010011111100001111111010011001000100000100100101000100",0x00003B77,0xFFFFE3B3,0x00000623,0x00001BCA,0xFFFFF6F8,0x00000333,0x00001BCA,0xFFFFF6F8,0x00000333},
- {"0000001000010011111100001111111010011001000010100011100101000100",0x000035AF,0xFFFFE76D,0x00000588,0x00001C16,0xFFFFF6AB,0x00000341,0x00001C16,0xFFFFF6AB,0x00000341},
- {"0000001000010011111010101001010011011110000001000011100011000100",0x000032AD,0xFFFFEA8E,0x000004F8,0x00001A3A,0xFFFFF832,0x0000030E,0x00001A3A,0xFFFFF832,0x0000030E},
- {"0000001000010011111100001111111010011001000100000100100010000100",0x00002E92,0xFFFFEBD2,0x000004DA,0x00001E04,0xFFFFF51E,0x0000038A,0x00001E04,0xFFFFF51E,0x0000038A},
- {"0000001000010011111100001111110101000010110101000100000010100100",0x00003E57,0xFFFFE0F7,0x0000068F,0x000021F1,0xFFFFF1C6,0x00000411,0x000021F1,0xFFFFF1C6,0x00000411},
- {"0000001000010011111100001111111010011001000010000010000110100100",0x00003598,0xFFFFE8BB,0x00000535,0x00001B62,0xFFFFF764,0x00000326,0x00001B62,0xFFFFF764,0x00000326},
- {"0000001000010011111100001111111010011001000010100011100010000100",0x00002B15,0xFFFFEDEC,0x00000487,0x00001E8B,0xFFFFF4AB,0x0000039F,0x00001E8B,0xFFFFF4AB,0x0000039F},
- {"0000001000010011111010101001010011011110000001100000100100000100",0x0000267E,0xFFFFF1A7,0x000003E1,0x000021C1,0xFFFFF2E9,0x000003EA,0x000021C1,0xFFFFF2E9,0x000003EA},
- {"0000001000010011111010101001010011011110000000100011100110100100",0x00002ED7,0xFFFFEC88,0x000004A6,0x00001DEC,0xFFFFF57C,0x00000378,0x00001DEC,0xFFFFF57C,0x00000378},
- {"0000001000010011111010101001010011011110000001000100000110100100",0x00003365,0xFFFFE946,0x00000536,0x000019E9,0xFFFFF7E0,0x0000031D,0x000019E9,0xFFFFF7E0,0x0000031D},
- {"0000001000010011111100001111111010011001000110000001100011100100",0x000029A4,0xFFFFF0FD,0x000003FE,0x0000163F,0xFFFFFB68,0x00000299,0x0000163F,0xFFFFFB68,0x00000299},
- {"0000001000010011111010101001010011011110000000100001100100000100",0x0000348D,0xFFFFE9F7,0x00000509,0x000017A0,0xFFFFFA59,0x000002B6,0x000017A0,0xFFFFFA59,0x000002B6},
- {"0000001000010011111100001111111010011001000001100001000011000100",0x00003144,0xFFFFEB23,0x000004D9,0x00001C9B,0xFFFFF664,0x00000351,0x00001C9B,0xFFFFF664,0x00000351},
- {"0000001000010011111010101001010011011110000001100010000011100100",0x00002E95,0xFFFFEE1A,0x00000463,0x00001707,0xFFFFFAB7,0x000002B3,0x00001707,0xFFFFFAB7,0x000002B3},
- {"0000001000010011111100001111110101000010110101000001100001100100",0x0000489C,0xFFFFDA43,0x000007AC,0x00002866,0xFFFFED6B,0x000004D0,0x00002866,0xFFFFED6B,0x000004D0},
- {"0000001000010011111100001111111010011001000101100001100001000100",0x00002895,0xFFFFF10A,0x0000040A,0x000013E9,0xFFFFFC9F,0x0000026E,0x000013E9,0xFFFFFC9F,0x0000026E},
- {"0000001000010011111100001111111010011001000001100001100101100100",0x000033A0,0xFFFFE9B1,0x00000510,0x00001D96,0xFFFFF5AE,0x0000036F,0x00001D96,0xFFFFF5AE,0x0000036F},
- {"0000001000010011111100001111111010011001000010000011100110000100",0x0000327C,0xFFFFEAEA,0x000004DD,0x00001D45,0xFFFFF649,0x00000356,0x00001D45,0xFFFFF649,0x00000356},
- {"0000001000010011111010101001010011011110000000100100100010100100",0x000031DF,0xFFFFE9AB,0x0000052F,0x000019C8,0xFFFFF7B7,0x00000321,0x000019C8,0xFFFFF7B7,0x00000321},
- {"0000001000010011111100001111111010011001000101100100000010100100",0x00002BCC,0xFFFFEEF4,0x0000045C,0x000015CD,0xFFFFFB58,0x0000029E,0x000015CD,0xFFFFFB58,0x0000029E},
- {"0000001000010011111100001111111010011001000001100011100011100100",0x00003534,0xFFFFEA10,0x000004EB,0x00001BB6,0xFFFFF7B9,0x00000314,0x00001BB6,0xFFFFF7B9,0x00000314},
- {"0000001000010011111100001111111010011001000001000001100110000100",0x00002F4F,0xFFFFEC35,0x000004B9,0x0000205D,0xFFFFF47F,0x00000392,0x0000205D,0xFFFFF47F,0x00000392},
- {"0000001000010011111100001111111010011001000011000010000010100100",0x00003295,0xFFFFEB1C,0x000004D6,0x000019C1,0xFFFFF931,0x000002D5,0x000019C1,0xFFFFF931,0x000002D5},
- {"0000001000010011111100001111111010011001000000100100000101000100",0x00003557,0xFFFFE7F7,0x00000568,0x00002342,0xFFFFF1F9,0x00000405,0x00002342,0xFFFFF1F9,0x00000405},
- {"0000001000010011111100001111111010011001000001000101000011000100",0x00003487,0xFFFFE872,0x0000055D,0x000019D7,0xFFFFF823,0x0000030C,0x000019D7,0xFFFFF823,0x0000030C},
- {"0000001000010011111100001111111010011001001011000011100101000100",0x0000378F,0xFFFFE7A6,0x00000566,0x00001875,0xFFFFFA04,0x000002AF,0x00001875,0xFFFFFA04,0x000002AF},
- {"0000001000010011111010101001010011011110000000100011000011100100",0x00002A67,0xFFFFF157,0x000003DD,0x000017BD,0xFFFFFA53,0x000002D1,0x000017BD,0xFFFFFA53,0x000002D1},
- {"0000001000010011111100001111110101000010110100100010000011100100",0x000030B5,0xFFFFEB32,0x000004D9,0x00002129,0xFFFFF38A,0x000003BB,0x00002129,0xFFFFF38A,0x000003BB},
- {"0000001000010011111100001111111010011001000001100001000010100100",0x00003786,0xFFFFE703,0x00000584,0x00001D63,0xFFFFF5DC,0x00000367,0x00001D63,0xFFFFF5DC,0x00000367},
- {"0000001000010011111100001111110101000010110110100010000011000100",0x0000346A,0xFFFFE93E,0x0000052C,0x00001B27,0xFFFFF79D,0x0000031F,0x00001B27,0xFFFFF79D,0x0000031F},
- {"0000001000010011111100001111111010011001000011100011000000100100",0x0000294E,0xFFFFF0A5,0x00000409,0x00001928,0xFFFFF93B,0x000002E6,0x00001928,0xFFFFF93B,0x000002E6},
- {"0000001000010011111100001111110101000010110101000001000011000100",0x00003E09,0xFFFFE0FF,0x00000694,0x000025A0,0xFFFFEF0F,0x0000048F,0x000025A0,0xFFFFEF0F,0x0000048F},
- {"0000001000010011111100001111111010011001000010100010100101100100",0x00003197,0xFFFFEA06,0x00000520,0x00001B42,0xFFFFF73B,0x0000032A,0x00001B42,0xFFFFF73B,0x0000032A},
- {"0000001000010011111100001111111010011001000101100001100001100100",0x000022CB,0xFFFFF3FC,0x000003A3,0x00001449,0xFFFFFBD0,0x00000297,0x00001449,0xFFFFFBD0,0x00000297},
- {"0000001000010011111100001111110101000010110110000010100101000100",0x00002A79,0xFFFFEFD2,0x00000433,0x00001585,0xFFFFFB92,0x0000028E,0x00001585,0xFFFFFB92,0x0000028E},
- {"0000001000010011111100001111111010011001000011000100000110000100",0x00003249,0xFFFFEA92,0x000004F4,0x000019CB,0xFFFFF8CF,0x000002E1,0x000019CB,0xFFFFF8CF,0x000002E1},
- {"0000001000010011111010101001010011011110000000100001100010100100",0x00002CEA,0xFFFFEE46,0x00000463,0x00001A5E,0xFFFFF83C,0x0000030D,0x00001A5E,0xFFFFF83C,0x0000030D},
- {"0000001000010011111100001111110101000010110111000101000101000100",0x00003AE2,0xFFFFE422,0x00000600,0x00001C65,0xFFFFF62F,0x0000034B,0x00001C65,0xFFFFF62F,0x0000034B},
- {"0000001000010011111100001111111010011001000110000001000110000100",0x000026A0,0xFFFFF1C2,0x000003F8,0x000010E5,0xFFFFFE56,0x0000022A,0x000010E5,0xFFFFFE56,0x0000022A},
- {"0000001000010011111100001111111010011001001010000010100110100100",0x00002A7B,0xFFFFF063,0x00000417,0x000016FC,0xFFFFFAD7,0x000002B1,0x000016FC,0xFFFFFAD7,0x000002B1},
- {"0000001000010011111100001111111010011001001100100001000011000100",0x00003092,0xFFFFEAB9,0x00000507,0x00001AE3,0xFFFFF783,0x00000323,0x00001AE3,0xFFFFF783,0x00000323},
- {"0000001000010011111100001111111010011001000001000011100011100100",0x00003265,0xFFFFEBE8,0x000004AA,0x00001D65,0xFFFFF73F,0x00000321,0x00001D65,0xFFFFF73F,0x00000321},
- {"0000001000010011111010101001010011011110000000100011000010000100",0x00002F14,0xFFFFECC2,0x000004A4,0x00001A8D,0xFFFFF7F3,0x0000031D,0x00001A8D,0xFFFFF7F3,0x0000031D},
- {"0000001000010011111100001111110101000010110111000001000011100100",0x000035FB,0xFFFFE6D3,0x000005AC,0x00001B19,0xFFFFF712,0x00000338,0x00001B19,0xFFFFF712,0x00000338},
- {"0000001000010011111100001111110101000010110110100010000100100100",0x00003519,0xFFFFE8CC,0x0000053A,0x00001A0F,0xFFFFF86E,0x000002F5,0x00001A0F,0xFFFFF86E,0x000002F5},
- {"0000001000010011111100001111111010011001001011000010000101000100",0x0000364C,0xFFFFE879,0x00000541,0x00001A42,0xFFFFF8BA,0x000002E2,0x00001A42,0xFFFFF8BA,0x000002E2},
- {"0000001000010011111010101001010011011110000000100001100011000100",0x000029BA,0xFFFFF09A,0x00000408,0x00001986,0xFFFFF8D9,0x000002FE,0x00001986,0xFFFFF8D9,0x000002FE},
- {"0000001000010011111100001111110101000010110110100011100011100100",0x00003507,0xFFFFE961,0x00000518,0x00001B79,0xFFFFF775,0x00000325,0x00001B79,0xFFFFF775,0x00000325},
- {"0000001000010011111100001111110101000010110111000011000110000100",0x00003AD5,0xFFFFE415,0x00000613,0x00001CB4,0xFFFFF66D,0x00000348,0x00001CB4,0xFFFFF66D,0x00000348},
- {"0000001000010011111100001111111010011001000101100100000011100100",0x000023D1,0xFFFFF42B,0x0000038F,0x00001546,0xFFFFFBA0,0x0000029F,0x00001546,0xFFFFFBA0,0x0000029F},
- {"0000001000010011111100001111111010011001000010100001100100100100",0x0000399E,0xFFFFE518,0x000005E7,0x00001990,0xFFFFF871,0x000002FB,0x00001990,0xFFFFF871,0x000002FB},
- {"0000001000010011111100001111110101000010110110000010100101100100",0x00002EDE,0xFFFFEC93,0x000004B8,0x0000152C,0xFFFFFBB3,0x0000027E,0x0000152C,0xFFFFFBB3,0x0000027E},
- {"0000001000010011111010101001010011011110000001000010100101100100",0x00003140,0xFFFFEBC9,0x000004BB,0x000016BE,0xFFFFFB0A,0x00000288,0x000016BE,0xFFFFFB0A,0x00000288},
- {"0000001000010011111100001111111010011001000001100100000001100100",0x000030F6,0xFFFFEB89,0x000004CD,0x0000185D,0xFFFFF95A,0x000002D9,0x0000185D,0xFFFFF95A,0x000002D9},
- {"0000001000010011111100001111111010011001000000100011100001000100",0x0000389C,0xFFFFE65A,0x000005A2,0x0000195D,0xFFFFF8C8,0x000002E8,0x0000195D,0xFFFFF8C8,0x000002E8},
- {"0000001000010011111100001111111010011001000001000010000100000100",0x0000362B,0xFFFFE9EC,0x000004F6,0x00001605,0xFFFFFC1C,0x00000263,0x00001605,0xFFFFFC1C,0x00000263},
- {"0000001000010011111100001111111010011001001010100001100101100100",0x00002946,0xFFFFF04F,0x00000426,0x000015BA,0xFFFFFB2F,0x000002A3,0x000015BA,0xFFFFFB2F,0x000002A3},
- {"0000001000010011111100001111111010011001000010000010000110000100",0x0000368E,0xFFFFE837,0x0000054A,0x000017D7,0xFFFFF9EB,0x000002BA,0x000017D7,0xFFFFF9EB,0x000002BA},
- {"0000001000010011111100001111110101000010110110100010100001000100",0x00002E74,0xFFFFEBE8,0x000004DA,0x00001DD6,0xFFFFF57E,0x00000379,0x00001DD6,0xFFFFF57E,0x00000379},
- {"0000001000010011111100001111111010011001000001000001100101000100",0x0000322D,0xFFFFEAA8,0x000004F5,0x00001B55,0xFFFFF7DD,0x0000030B,0x00001B55,0xFFFFF7DD,0x0000030B},
- {"0000001000010011111100001111111010011001000110000001100100000100",0x00002A29,0xFFFFF07B,0x00000416,0x00001671,0xFFFFFB3E,0x0000029F,0x00001671,0xFFFFFB3E,0x0000029F},
- {"0000001000010011111100001111110101000010110110100010000100000100",0x000030F6,0xFFFFEB89,0x000004CD,0x00001815,0xFFFFF9AE,0x000002C9,0x00001815,0xFFFFF9AE,0x000002C9},
- {"0000001000010011111100001111111010011001000011100001000011100100",0x0000265F,0xFFFFF1CB,0x000003D5,0x00001ED2,0xFFFFF539,0x0000037A,0x00001ED2,0xFFFFF539,0x0000037A},
- {"0000001000010011111100001111111010011001000101100010000110000100",0x000027A8,0xFFFFF10D,0x00000413,0x000014B5,0xFFFFFBA1,0x00000299,0x000014B5,0xFFFFFBA1,0x00000299},
- {"0000001000010011111100001111111010011001000001000011000001100100",0x00002CEE,0xFFFFEDF6,0x00000476,0x00001A99,0xFFFFF83E,0x00000305,0x00001A99,0xFFFFF83E,0x00000305},
- {"0000001000010011111100001111111010011001000001100100000011000100",0x0000346C,0xFFFFEA17,0x000004EF,0x00001D38,0xFFFFF69F,0x0000033D,0x00001D38,0xFFFFF69F,0x0000033D},
- {"0000001000010011111100001111110101000010110110100010100101000100",0x00002DBB,0xFFFFED35,0x00000490,0x000018C1,0xFFFFF930,0x000002DA,0x000018C1,0xFFFFF930,0x000002DA},
- {"0000001000010011111100001111111010011001000001000010100100100100",0x000038DF,0xFFFFE8A7,0x0000051E,0x00001B59,0xFFFFF915,0x000002D3,0x00001B59,0xFFFFF915,0x000002D3},
- {"0000001000010011111100001111111010011001000010000000100101000100",0x00003384,0xFFFFE979,0x00000524,0x00001AF3,0xFFFFF74C,0x0000032F,0x00001AF3,0xFFFFF74C,0x0000032F},
- {"0000001000010011111100001111111010011001000110000001100001100100",0x0000258B,0xFFFFF2AE,0x000003CB,0x0000190C,0xFFFFF93E,0x000002EF,0x0000190C,0xFFFFF93E,0x000002EF},
- {"0000001000010011111100001111111010011001000100000011100010000100",0x000034F1,0xFFFFE84B,0x0000055E,0x00001CB8,0xFFFFF670,0x0000034A,0x00001CB8,0xFFFFF670,0x0000034A},
- {"0000001000010011111100001111111010011001000011000010000100000100",0x000030FB,0xFFFFECD2,0x00000488,0x00001BF4,0xFFFFF821,0x00000302,0x00001BF4,0xFFFFF821,0x00000302},
- {"0000001000010011111100001111111010011001000001100011000001000100",0x000036A6,0xFFFFE815,0x00000556,0x000018FD,0xFFFFF925,0x000002DF,0x000018FD,0xFFFFF925,0x000002DF},
- {"0000001000010011111010101001010011011110000000100011000001000100",0x0000302A,0xFFFFEB79,0x000004E0,0x00001C11,0xFFFFF694,0x00000358,0x00001C11,0xFFFFF694,0x00000358},
- {"0000001000010011111100001111111010011001000110000001000100100100",0x00002555,0xFFFFF2C4,0x000003CB,0x000017E3,0xFFFFFA1F,0x000002CB,0x000017E3,0xFFFFFA1F,0x000002CB},
- {"0000001000010011111100001111111010011001000010100011000101100100",0x000032A3,0xFFFFE933,0x00000544,0x000019D3,0xFFFFF81A,0x00000306,0x000019D3,0xFFFFF81A,0x00000306},
- {"0000001000010011111100001111110101000010110110000101000100000100",0x00002B91,0xFFFFED81,0x000004A9,0x0000158B,0xFFFFFAB9,0x000002AC,0x0000158B,0xFFFFFAB9,0x000002AC},
- {"0000001000010011111100001111111010011001000011100010000011000100",0x00003537,0xFFFFE912,0x0000052C,0x00001C8A,0xFFFFF754,0x0000031B,0x00001C8A,0xFFFFF754,0x0000031B},
- {"0000001000010011111010101001010011011110000001100011000110000100",0x000032E1,0xFFFFEA5A,0x000004F9,0x000017B4,0xFFFFF9D9,0x000002C2,0x000017B4,0xFFFFF9D9,0x000002C2},
- {"0000001000010011111100001111110101000010110100100001000011000100",0x00003B76,0xFFFFE330,0x00000636,0x000026FB,0xFFFFEF06,0x00000481,0x000026FB,0xFFFFEF06,0x00000481},
- {"0000001000010011111100001111111010011001000001000010000101000100",0x0000320C,0xFFFFEB84,0x000004C3,0x00001A3A,0xFFFFF8E9,0x000002DF,0x00001A3A,0xFFFFF8E9,0x000002DF},
- {"0000001000010011111100001111111010011001000000100011100110000100",0x0000317D,0xFFFFEA1F,0x00000515,0x00002100,0xFFFFF31B,0x000003DD,0x00002100,0xFFFFF31B,0x000003DD},
- {"0000001000010011111100001111110101000010110101000011000101100100",0x00003DCB,0xFFFFE0B4,0x000006B4,0x00002160,0xFFFFF269,0x000003F0,0x00002160,0xFFFFF269,0x000003F0},
- {"0000001000010011111100001111111010011001000101100001100011000100",0x00002737,0xFFFFF218,0x000003E1,0x000015B5,0xFFFFFB8F,0x0000029C,0x000015B5,0xFFFFFB8F,0x0000029C},
- {"0000001000010011111010101001010011011110000000100011000110000100",0x0000318F,0xFFFFEB3F,0x000004D8,0x00001938,0xFFFFF8E9,0x000002EB,0x00001938,0xFFFFF8E9,0x000002EB},
- {"0000001000010011111100001111111010011001000100000100100011000100",0x000031BD,0xFFFFE9DE,0x00000527,0x000018A7,0xFFFFF8CA,0x000002ED,0x000018A7,0xFFFFF8CA,0x000002ED},
- {"0000001000010011111100001111110101000010110110100011100010000100",0x00002F77,0xFFFFEC2F,0x000004B4,0x00001D25,0xFFFFF61B,0x0000035D,0x00001D25,0xFFFFF61B,0x0000035D},
- {"0000001000010011111100001111111010011001000011100100100100000100",0x00002CCA,0xFFFFEDB3,0x0000047C,0x00001FBD,0xFFFFF4A7,0x00000391,0x00001FBD,0xFFFFF4A7,0x00000391},
- {"0000001000010011111100001111110101000010110101000011100010100100",0x00003FF6,0xFFFFE058,0x000006A2,0x000024CD,0xFFFFF026,0x00000452,0x000024CD,0xFFFFF026,0x00000452},
- {"0000001000010011111100001111111010011001000010100011100011100100",0x00003161,0xFFFFEAC8,0x000004F3,0x00001BB6,0xFFFFF72A,0x0000032B,0x00001BB6,0xFFFFF72A,0x0000032B},
- {"0000001000010011111100001111110101000010110110000011100010100100",0x00002EA0,0xFFFFECA6,0x000004B7,0x000018C2,0xFFFFF94E,0x000002E1,0x000018C2,0xFFFFF94E,0x000002E1},
- {"0000001000010011111100001111111010011001000110000010000110000100",0x00002F62,0xFFFFEC9E,0x000004B8,0x00001531,0xFFFFFBCD,0x00000285,0x00001531,0xFFFFFBCD,0x00000285},
- {"0000001000010011111100001111111010011001000001000100000010100100",0x00003013,0xFFFFEBD6,0x000004C2,0x00001B01,0xFFFFF802,0x000002FF,0x00001B01,0xFFFFF802,0x000002FF},
- {"0000001000010011111100001111111010011001000110000011000001100100",0x00002972,0xFFFFF08D,0x00000417,0x00001A32,0xFFFFF8A4,0x00000305,0x00001A32,0xFFFFF8A4,0x00000305},
- {"0000001000010011111100001111110101000010110110000010000011100100",0x00002E95,0xFFFFED94,0x00000487,0x00001529,0xFFFFFC26,0x00000271,0x00001529,0xFFFFFC26,0x00000271},
- {"0000001000010011111100001111111010011001000010100001000010000100",0x00002D6A,0xFFFFEC79,0x000004C1,0x00001AE2,0xFFFFF725,0x00000337,0x00001AE2,0xFFFFF725,0x00000337},
- {"0000001000010011111100001111111010011001000000100001100010000100",0x000036B4,0xFFFFE704,0x00000591,0x00001E7E,0xFFFFF51C,0x00000383,0x00001E7E,0xFFFFF51C,0x00000383},
- {"0000001000010011111100001111111010011001000001000001100001000100",0x00002A6F,0xFFFFEF70,0x00000443,0x00001BAA,0xFFFFF752,0x00000336,0x00001BAA,0xFFFFF752,0x00000336},
- {"0000001000010011111100001111111010011001000110000011100101000100",0x00002C66,0xFFFFEF5F,0x0000043A,0x000019F7,0xFFFFF931,0x000002EC,0x000019F7,0xFFFFF931,0x000002EC},
- {"0000001000010011111010101001010011011110000001100011000111000100",0x00003852,0xFFFFE6AB,0x00000590,0x000019C1,0xFFFFF8B1,0x000002E5,0x000019C1,0xFFFFF8B1,0x000002E5},
- {"0000001000010011111100001111110101000010110110100011000100100100",0x00003521,0xFFFFE932,0x00000523,0x000018A9,0xFFFFF96B,0x000002D0,0x000018A9,0xFFFFF96B,0x000002D0},
- {"0000001000010011111100001111111010011001000001100010000101100100",0x000031B9,0xFFFFEB36,0x000004D0,0x00001D65,0xFFFFF612,0x0000035D,0x00001D65,0xFFFFF612,0x0000035D},
- {"0000001000010011111100001111110101000010110101000001000001100100",0x00003ED0,0xFFFFE135,0x00000679,0x00002351,0xFFFFF0FE,0x00000433,0x00002351,0xFFFFF0FE,0x00000433},
- {"0000001000010011111100001111111010011001000010100010000011100100",0x000033ED,0xFFFFE91A,0x00000541,0x00001C93,0xFFFFF6A0,0x0000034A,0x00001C93,0xFFFFF6A0,0x0000034A},
- {"0000001000010011111010101001010011011110000000100001100001000100",0x0000356F,0xFFFFE8F7,0x00000530,0x000016BF,0xFFFFFA85,0x000002AB,0x000016BF,0xFFFFFA85,0x000002AB},
- {"0000001000010011111100001111111010011001000110000100000011100100",0x00002304,0xFFFFF4F3,0x00000364,0x000017CC,0xFFFFFA41,0x000002CA,0x000017CC,0xFFFFFA41,0x000002CA},
- {"0000001000010011111100001111111010011001000101100001000101100100",0x00002887,0xFFFFEFD7,0x00000450,0x00001474,0xFFFFFB94,0x00000299,0x00001474,0xFFFFFB94,0x00000299},
- {"0000001000010011111100001111111010011001000001100011000001100100",0x00003D0B,0xFFFFE416,0x000005EF,0x00001C7E,0xFFFFF71D,0x00000325,0x00001C7E,0xFFFFF71D,0x00000325},
- {"0000001000010011111100001111111010011001000010000001000011100100",0x00003185,0xFFFFEAFA,0x000004E4,0x00001A12,0xFFFFF83C,0x00000303,0x00001A12,0xFFFFF83C,0x00000303},
- {"0000001000010011111100001111111010011001000010100001100101000100",0x00003032,0xFFFFEAE6,0x000004FC,0x00001B2A,0xFFFFF73F,0x0000032B,0x00001B2A,0xFFFFF73F,0x0000032B},
- {"0000001000010011111100001111110101000010110110000011100011000100",0x00002691,0xFFFFF22D,0x000003D6,0x00001700,0xFFFFFA6E,0x000002C0,0x00001700,0xFFFFFA6E,0x000002C0},
- {"0000001000010011111100001111111010011001000000100001100010100100",0x00002B2F,0xFFFFEEC4,0x0000044B,0x0000215F,0xFFFFF33F,0x000003D2,0x0000215F,0xFFFFF33F,0x000003D2},
- {"0000001000010011111100001111111010011001000010100100000110000100",0x000034AA,0xFFFFE706,0x000005B1,0x00001B28,0xFFFFF6B5,0x00000349,0x00001B28,0xFFFFF6B5,0x00000349},
- {"0000001000010011111100001111110101000010110110100010100101100100",0x0000307E,0xFFFFEB38,0x000004E6,0x00001A22,0xFFFFF83F,0x00000300,0x00001A22,0xFFFFF83F,0x00000300},
- {"0000001000010011111100001111111010011001000001100001100010100100",0x000038D6,0xFFFFE6D8,0x0000057C,0x00001B24,0xFFFFF7E4,0x00000307,0x00001B24,0xFFFFF7E4,0x00000307},
- {"0000001000010011111100001111111010011001000110000011000001000100",0x00002757,0xFFFFF1E8,0x000003DD,0x000017F5,0xFFFFFA15,0x000002C8,0x000017F5,0xFFFFFA15,0x000002C8},
- {"0000001000010011111100001111111010011001000010000011000110000100",0x000031FC,0xFFFFEB3E,0x000004CE,0x00001B4C,0xFFFFF7AD,0x00000319,0x00001B4C,0xFFFFF7AD,0x00000319},
- {"0000001000010011111100001111111010011001001100000001100001100100",0x00002933,0xFFFFF073,0x0000040E,0x00001C3C,0xFFFFF701,0x0000033C,0x00001C3C,0xFFFFF701,0x0000033C},
- {"0000001000010011111100001111110101000010110100100001100010100100",0x000040BB,0xFFFFE066,0x0000069A,0x0000257F,0xFFFFF08A,0x00000435,0x0000257F,0xFFFFF08A,0x00000435},
- {"0000001000010011111100001111111010011001000100000001000010100100",0x0000305B,0xFFFFEB9B,0x000004CB,0x00001996,0xFFFFF846,0x00000308,0x00001996,0xFFFFF846,0x00000308},
- {"0000001000010011111100001111111010011001000001100100100010000100",0x000039C0,0xFFFFE5D3,0x000005B0,0x00001A8D,0xFFFFF7DA,0x00000313,0x00001A8D,0xFFFFF7DA,0x00000313},
- {"0000001000010011111010101001010011011110000000100001000010100100",0x00002E23,0xFFFFED3F,0x0000048F,0x0000189D,0xFFFFF94C,0x000002DE,0x0000189D,0xFFFFF94C,0x000002DE},
- {"0000001000010011111010101001010011011110000000100001100110000100",0x0000332B,0xFFFFE9F1,0x00000516,0x000018E6,0xFFFFF8FE,0x000002EC,0x000018E6,0xFFFFF8FE,0x000002EC},
- {"0000001000010011111100001111111010011001000010000011100011000100",0x000034A0,0xFFFFEA44,0x000004E4,0x00001ECD,0xFFFFF5B4,0x00000364,0x00001ECD,0xFFFFF5B4,0x00000364},
- {"0000001000010011111100001111110101000010110100100100000100000100",0x0000448C,0xFFFFDF34,0x000006A8,0x0000231C,0xFFFFF286,0x000003D9,0x0000231C,0xFFFFF286,0x000003D9},
- {"0000001000010011111010101001010011011110000001100010000101000100",0x00002D8C,0xFFFFEE65,0x00000456,0x000018B1,0xFFFFF9C8,0x000002C8,0x000018B1,0xFFFFF9C8,0x000002C8},
- {"0000001000010011111100001111111010011001000001100001100100000100",0x00003527,0xFFFFE9BF,0x000004FD,0x00001D23,0xFFFFF69F,0x00000342,0x00001D23,0xFFFFF69F,0x00000342},
- {"0000001000010011111100001111110101000010110111000011100010100100",0x00002C51,0xFFFFEDC3,0x00000483,0x00001BE0,0xFFFFF720,0x0000032D,0x00001BE0,0xFFFFF720,0x0000032D},
- {"0000001000010011111100001111111010011001000010100011000001000100",0x00002C6C,0xFFFFECEB,0x000004B7,0x00001C86,0xFFFFF5E7,0x00000371,0x00001C86,0xFFFFF5E7,0x00000371},
- {"0000001000010011111100001111111010011001000001000101000101000100",0x000037CF,0xFFFFE6BE,0x00000599,0x000018CD,0xFFFFF967,0x000002C7,0x000018CD,0xFFFFF967,0x000002C7},
- {"0000001000010011111100001111111010011001000100000011000101100100",0x00002E6F,0xFFFFED1D,0x0000048E,0x00001ADC,0xFFFFF7F4,0x0000030E,0x00001ADC,0xFFFFF7F4,0x0000030E},
- {"0000001000010011111100001111110101000010110101000010100110000100",0x00003FF3,0xFFFFDF13,0x000006F9,0x000025BF,0xFFFFEEEE,0x00000497,0x000025BF,0xFFFFEEEE,0x00000497},
- {"0000001000010011111100001111110101000010110111000101000100000100",0x00004135,0xFFFFDF97,0x000006CC,0x00001D52,0xFFFFF541,0x00000383,0x00001D52,0xFFFFF541,0x00000383},
- {"0000001000010011111100001111110101000010110111000010000011100100",0x00002EA9,0xFFFFEDDB,0x0000045F,0x0000197C,0xFFFFF8E1,0x000002F0,0x0000197C,0xFFFFF8E1,0x000002F0},
- {"0000001000010011111010101001010011011110000001000011000010000100",0x0000345C,0xFFFFE922,0x00000532,0x00001922,0xFFFFF8C7,0x000002F1,0x00001922,0xFFFFF8C7,0x000002F1},
- {"0000001000010011111100001111111010011001000001100100000100100100",0x000035C4,0xFFFFE8FE,0x00000521,0x00001C87,0xFFFFF6F3,0x00000330,0x00001C87,0xFFFFF6F3,0x00000330},
- {"0000001000010011111100001111110101000010110110000011000101100100",0x00002888,0xFFFFF08A,0x0000041E,0x0000150F,0xFFFFFB87,0x00000291,0x0000150F,0xFFFFFB87,0x00000291},
- {"0000001000010011111100001111111010011001000010100001000100100100",0x000035E9,0xFFFFE657,0x000005CC,0x00001BD6,0xFFFFF664,0x00000355,0x00001BD6,0xFFFFF664,0x00000355},
- {"0000001000010011111100001111111010011001000101100100100011100100",0x00002F94,0xFFFFEBD0,0x000004E5,0x00001333,0xFFFFFCA7,0x00000266,0x00001333,0xFFFFFCA7,0x00000266},
- {"0000001000010011111100001111111010011001000110000001100101100100",0x000029E7,0xFFFFF009,0x00000433,0x0000144A,0xFFFFFC37,0x0000027D,0x0000144A,0xFFFFFC37,0x0000027D},
- {"0000001000010011111100001111111010011001001011000001100101000100",0x00003418,0xFFFFE979,0x00000521,0x00001D33,0xFFFFF66B,0x0000034A,0x00001D33,0xFFFFF66B,0x0000034A},
- {"0000001000010011111010101001010011011110000001000100000011100100",0x00003656,0xFFFFE79D,0x0000057A,0x000017C2,0xFFFFF992,0x000002D4,0x000017C2,0xFFFFF992,0x000002D4},
- {"0000001000010011111100001111111010011001000011000100000011000100",0x00002EB2,0xFFFFECFE,0x00000493,0x00001F2A,0xFFFFF543,0x0000037B,0x00001F2A,0xFFFFF543,0x0000037B},
- {"0000001000010011111100001111111010011001000000100001000100100100",0x00002FC1,0xFFFFEB3F,0x000004E8,0x00001CD0,0xFFFFF5F7,0x00000364,0x00001CD0,0xFFFFF5F7,0x00000364},
- {"0000001000010011111100001111111010011001000011000001000100100100",0x0000307B,0xFFFFEB66,0x000004DE,0x00001953,0xFFFFF8ED,0x000002E4,0x00001953,0xFFFFF8ED,0x000002E4},
- {"0000001000010011111100001111110101000010110110100001100010000100",0x00002CAA,0xFFFFED07,0x000004AC,0x0000251C,0xFFFFF086,0x0000044D,0x0000251C,0xFFFFF086,0x0000044D},
- {"0000001000010011111010101001010011011110000001000011100101000100",0x00002C94,0xFFFFEE5F,0x0000045B,0x000018D7,0xFFFFF900,0x000002EB,0x000018D7,0xFFFFF900,0x000002EB},
- {"0000001000010011111100001111111010011001000000100001100001100100",0x000031F1,0xFFFFE9BE,0x0000052E,0x00001DDF,0xFFFFF558,0x00000380,0x00001DDF,0xFFFFF558,0x00000380},
- {"0000001000010011111100001111111010011001000011100101000011000100",0x00002603,0xFFFFF1E9,0x000003DA,0x00001B37,0xFFFFF75A,0x0000032F,0x00001B37,0xFFFFF75A,0x0000032F},
- {"0000001000010011111100001111110101000010110110100011000001000100",0x00003992,0xFFFFE4F9,0x000005EB,0x00001775,0xFFFFF9B8,0x000002C2,0x00001775,0xFFFFF9B8,0x000002C2},
- {"0000001000010011111100001111111010011001000110000100100101100100",0x000029DA,0xFFFFF052,0x0000041F,0x000016E2,0xFFFFFA99,0x000002BB,0x000016E2,0xFFFFFA99,0x000002BB},
- {"0000001000010011111100001111111010011001000100000001000001100100",0x00002FF2,0xFFFFEB8F,0x000004DF,0x00001AF6,0xFFFFF7A1,0x00000321,0x00001AF6,0xFFFFF7A1,0x00000321},
- {"0000001000010011111100001111111010011001000101100000100011100100",0x00002590,0xFFFFF222,0x000003EE,0x0000130B,0xFFFFFCC9,0x00000268,0x0000130B,0xFFFFFCC9,0x00000268},
- {"0000001000010011111100001111111010011001000000100100000001100100",0x000038A2,0xFFFFE65F,0x000005A2,0x000018B1,0xFFFFF917,0x000002E1,0x000018B1,0xFFFFF917,0x000002E1},
- {"0000001000010011111100001111110101000010110111000100100011100100",0x000035FD,0xFFFFE73C,0x0000058D,0x00001BB3,0xFFFFF6E1,0x00000337,0x00001BB3,0xFFFFF6E1,0x00000337},
- {"0000001000010011111100001111111010011001000100000011100011000100",0x00002AB7,0xFFFFEF98,0x00000429,0x00001F35,0xFFFFF539,0x0000037C,0x00001F35,0xFFFFF539,0x0000037C},
- {"0000001000010011111100001111111010011001000010100000100101000100",0x000034BA,0xFFFFE73D,0x000005A6,0x000018A6,0xFFFFF888,0x000002FB,0x000018A6,0xFFFFF888,0x000002FB},
- {"0000001000010011111100001111111010011001000001100011100001000100",0x000032EA,0xFFFFEA78,0x000004F4,0x00001AB6,0xFFFFF812,0x00000308,0x00001AB6,0xFFFFF812,0x00000308},
- {"0000001000010011111100001111111010011001000011000011000001000100",0x00002BE9,0xFFFFEE9A,0x00000457,0x00001942,0xFFFFF8D2,0x000002F2,0x00001942,0xFFFFF8D2,0x000002F2},
- {"0000001000010011111100001111111010011001000100000101000100100100",0x00002FAB,0xFFFFEB76,0x000004E1,0x00001DCA,0xFFFFF57D,0x00000378,0x00001DCA,0xFFFFF57D,0x00000378},
- {"0000001000010011111100001111111010011001001011100010100001000100",0x0000330A,0xFFFFE9E1,0x0000051B,0x00001CC4,0xFFFFF6DF,0x00000335,0x00001CC4,0xFFFFF6DF,0x00000335},
- {"0000001000010011111100001111111010011001000110000010100010100100",0x000027D8,0xFFFFF276,0x000003BF,0x0000178A,0xFFFFFABF,0x000002B5,0x0000178A,0xFFFFFABF,0x000002B5},
- {"0000001000010011111100001111110101000010110111000011100001100100",0x0000340A,0xFFFFE86D,0x00000562,0x00001B85,0xFFFFF719,0x0000032F,0x00001B85,0xFFFFF719,0x0000032F},
- {"0000001000010011111010101001010011011110000001100011000010000100",0x00003879,0xFFFFE73F,0x00000578,0x0000161C,0xFFFFFB6B,0x00000281,0x0000161C,0xFFFFFB6B,0x00000281},
- {"0000001000010011111100001111111010011001000110000100000001100100",0x00002879,0xFFFFF0F8,0x0000040A,0x00001749,0xFFFFFA37,0x000002CC,0x00001749,0xFFFFFA37,0x000002CC},
- {"0000001000010011111100001111111010011001000001000011100101100100",0x00002C3A,0xFFFFEEA0,0x0000044F,0x00001D57,0xFFFFF6C2,0x00000332,0x00001D57,0xFFFFF6C2,0x00000332},
- {"0000001000010011111010101001010011011110000000100001100101100100",0x000035BB,0xFFFFE90D,0x0000052A,0x000017D9,0xFFFFF9F5,0x000002C3,0x000017D9,0xFFFFF9F5,0x000002C3},
- {"0000001000010011111010101001010011011110000001000001000100100100",0x000031F1,0xFFFFEAD4,0x000004ED,0x00001F10,0xFFFFF539,0x0000037D,0x00001F10,0xFFFFF539,0x0000037D},
- {"0000001000010011111100001111111010011001000100000010100000100100",0x00002A1A,0xFFFFEFAD,0x00000430,0x00001D47,0xFFFFF62F,0x0000035E,0x00001D47,0xFFFFF62F,0x0000035E},
- {"0000001000010011111100001111111010011001000101100100100100100100",0x00002AF0,0xFFFFEEDC,0x00000465,0x0000145F,0xFFFFFBEB,0x00000281,0x0000145F,0xFFFFFBEB,0x00000281},
- {"0000001000010011111100001111111010011001000110000011000101100100",0x00002657,0xFFFFF2E0,0x000003B6,0x00001664,0xFFFFFB37,0x000002A2,0x00001664,0xFFFFFB37,0x000002A2},
- {"0000001000010011111100001111110101000010110100000011100001100100",0x00003183,0xFFFFE9F1,0x0000052B,0x00002020,0xFFFFF3CE,0x000003C1,0x00002020,0xFFFFF3CE,0x000003C1},
- {"0000001000010011111100001111110101000010110001100010100011100100",0x00003240,0xFFFFEB65,0x000004C7,0x00002425,0xFFFFF245,0x000003F3,0x00002425,0xFFFFF245,0x000003F3},
- {"0000001000010011111010101001010011011110001100100001000100000100",0x000023D0,0xFFFFF400,0x00000397,0x00001345,0xFFFFFD6B,0x00000241,0x00001345,0xFFFFFD6B,0x00000241},
- {"0000001000010011111100001111110101000010110011100011100010100100",0x00003440,0xFFFFE872,0x0000055B,0x00002247,0xFFFFF296,0x000003E8,0x00002247,0xFFFFF296,0x000003E8},
- {"0000001000010011111100001111110101000010110100000100100100000100",0x00003275,0xFFFFE970,0x00000538,0x00001F94,0xFFFFF429,0x000003AD,0x00001F94,0xFFFFF429,0x000003AD},
- {"0000001000010011111100001111110101000010110001100100000010100100",0x00003918,0xFFFFE5DA,0x000005B6,0x000024FC,0xFFFFF106,0x00000426,0x000024FC,0xFFFFF106,0x00000426},
- {"0000001000010011111010101001010011011110000001100010000001000100",0x0000334B,0xFFFFEA39,0x000004FD,0x00001983,0xFFFFF8F6,0x000002E2,0x00001983,0xFFFFF8F6,0x000002E2},
- {"0000001000010011111100001111110101000010110001100100100110000100",0x00003B59,0xFFFFE4D0,0x000005DA,0x00002605,0xFFFFF090,0x00000439,0x00002605,0xFFFFF090,0x00000439},
- {"0000001000010011111100001111110101000010110100000011000100100100",0x00003251,0xFFFFEA46,0x00000511,0x00002781,0xFFFFEF84,0x00000470,0x00002781,0xFFFFEF84,0x00000470},
- {"0000001000010011111100001111110101000010110010100011000101100100",0x00003304,0xFFFFE926,0x00000542,0x00001EE9,0xFFFFF4E4,0x0000038B,0x00001EE9,0xFFFFF4E4,0x0000038B},
- {"0000001000010011111100001111110101000010110011000011100011000100",0x00002F4C,0xFFFFEC0C,0x000004C4,0x00001E49,0xFFFFF578,0x00000374,0x00001E49,0xFFFFF578,0x00000374},
- {"0000001000010011111010101001010011011110000111000010000101100100",0x00002034,0xFFFFF692,0x0000034C,0x000014B8,0xFFFFFC5B,0x00000294,0x000014B8,0xFFFFFC5B,0x00000294},
- {"0000001000010011111100001111110101000010110011100100100100100100",0x0000385F,0xFFFFE513,0x000005F3,0x000024E7,0xFFFFF053,0x00000450,0x000024E7,0xFFFFF053,0x00000450},
- {"0000001000010011111010101001010011011110000111000100000011100100",0x00001D70,0xFFFFF821,0x0000030F,0x00001541,0xFFFFFBB4,0x000002B0,0x00001541,0xFFFFFBB4,0x000002B0},
- {"0000001000010011111100001111110101000010110100000010000010000100",0x000034EB,0xFFFFE7FF,0x00000575,0x000019B4,0xFFFFF836,0x00000308,0x000019B4,0xFFFFF836,0x00000308},
- {"0000001000010011111100001111110101000010110100000101000011100100",0x000037C9,0xFFFFE5D4,0x000005CD,0x000026A1,0xFFFFEF0C,0x00000491,0x000026A1,0xFFFFEF0C,0x00000491},
- {"0000001000010011111010101001010011011110000100100001100101000100",0x00002918,0xFFFFF148,0x000003E9,0x00001A49,0xFFFFF94C,0x000002CF,0x00001A49,0xFFFFF94C,0x000002CF},
- {"0000001000010011111100001111110101000010110010100100000001100100",0x00002F90,0xFFFFEAB5,0x00000514,0x00001707,0xFFFFF9C7,0x000002C4,0x00001707,0xFFFFF9C7,0x000002C4},
- {"0000001000010011111010101001010011011110000001100010000001100100",0x0000327E,0xFFFFEA99,0x000004F4,0x0000194F,0xFFFFF929,0x000002DC,0x0000194F,0xFFFFF929,0x000002DC},
- {"0000001000010011111100001111110101000010110001100100000010000100",0x0000326F,0xFFFFE9CF,0x00000519,0x00002240,0xFFFFF299,0x000003E7,0x00002240,0xFFFFF299,0x000003E7},
- {"0000001000010011111010101001010011011110001100100001000100100100",0x000022FB,0xFFFFF4C6,0x00000371,0x00001506,0xFFFFFC73,0x00000265,0x00001506,0xFFFFFC73,0x00000265},
- {"0000001000010011111100001111110101000010110010100011100100100100",0x00003AD6,0xFFFFE470,0x000005FE,0x00001F03,0xFFFFF4F3,0x00000387,0x00001F03,0xFFFFF4F3,0x00000387},
- {"0000001000010011111010101001010011011110001000000001000100100100",0x00001F11,0xFFFFF756,0x00000332,0x00001666,0xFFFFFB8A,0x000002B2,0x00001666,0xFFFFFB8A,0x000002B2},
- {"0000001000010011111010101001010011011110000000100011100010100100",0x00002A5F,0xFFFFEFA7,0x00000430,0x00001943,0xFFFFF8C6,0x000002F7,0x00001943,0xFFFFF8C6,0x000002F7},
- {"0000001000010011111010101001010011011110000101100101000011100100",0x0000235E,0xFFFFF3B4,0x000003B3,0x00001489,0xFFFFFBCF,0x0000029B,0x00001489,0xFFFFFBCF,0x0000029B},
- {"0000001000010011111100001111110101000010110011000011100010100100",0x00003570,0xFFFFE780,0x0000058D,0x00001B1D,0xFFFFF767,0x00000325,0x00001B1D,0xFFFFF767,0x00000325},
- {"0000001000010011111010101001010011011110000001000010000001100100",0x00003678,0xFFFFE7C3,0x00000569,0x00001831,0xFFFFF98E,0x000002C8,0x00001831,0xFFFFF98E,0x000002C8},
- {"0000001000010011111010101001010011011110001000000001100001100100",0x000020B9,0xFFFFF625,0x0000035A,0x000015C5,0xFFFFFB8A,0x000002B5,0x000015C5,0xFFFFFB8A,0x000002B5},
- {"0000001000010011111100001111110101000010110001100011000110000100",0x00003985,0xFFFFE529,0x000005DD,0x00002165,0xFFFFF351,0x000003C5,0x00002165,0xFFFFF351,0x000003C5},
- {"0000001000010011111100001111110101000010110100000010000001100100",0x0000322A,0xFFFFE99D,0x00000535,0x000019A1,0xFFFFF844,0x00000305,0x000019A1,0xFFFFF844,0x00000305},
- {"0000001000010011111100001111110101000010110100000101000100000100",0x000033ED,0xFFFFE834,0x00000571,0x00002094,0xFFFFF33A,0x000003DB,0x00002094,0xFFFFF33A,0x000003DB},
- {"0000001000010011111010101001010011011110001000000100000011000100",0x00001D10,0xFFFFF84D,0x0000030B,0x00001659,0xFFFFFB0A,0x000002CB,0x00001659,0xFFFFFB0A,0x000002CB},
- {"0000001000010011111010101001010011011110000111000001000100100100",0x0000210F,0xFFFFF644,0x00000355,0x00001A4A,0xFFFFF90F,0x00000310,0x00001A4A,0xFFFFF90F,0x00000310},
- {"0000001000010011111010101001010011011110000101100100000101100100",0x00001CA8,0xFFFFF813,0x00000316,0x00001440,0xFFFFFC1C,0x0000029D,0x00001440,0xFFFFFC1C,0x0000029D},
- {"0000001000010011111010101001010011011110001100100001000011000100",0x00002864,0xFFFFF15A,0x000003FA,0x0000137F,0xFFFFFD43,0x00000248,0x0000137F,0xFFFFFD43,0x00000248},
- {"0000001000010011111100001111110101000010110100000100000110000100",0x00002CDB,0xFFFFECFD,0x000004A7,0x00002472,0xFFFFF0E1,0x00000437,0x00002472,0xFFFFF0E1,0x00000437},
- {"0000001000010011111100001111110101000010110011000101000100000100",0x00003348,0xFFFFE8CA,0x00000554,0x00001E91,0xFFFFF4D4,0x00000392,0x00001E91,0xFFFFF4D4,0x00000392},
- {"0000001000010011111100001111110101000010110001100100100101000100",0x00003989,0xFFFFE4BB,0x000005F8,0x00001ACB,0xFFFFF780,0x00000319,0x00001ACB,0xFFFFF780,0x00000319},
- {"0000001000010011111100001111110101000010110010100010000100000100",0x00003238,0xFFFFEA09,0x0000051E,0x00001F08,0xFFFFF4F4,0x0000038C,0x00001F08,0xFFFFF4F4,0x0000038C},
- {"0000001000010011111010101001010011011110000100100000100100000100",0x00002453,0xFFFFF3B0,0x0000038D,0x00001AED,0xFFFFF8A2,0x000002EA,0x00001AED,0xFFFFF8A2,0x000002EA},
- {"0000001000010011111010101001010011011110000111000011000000100100",0x00002459,0xFFFFF409,0x000003A8,0x000017B5,0xFFFFFA53,0x000002E1,0x000017B5,0xFFFFFA53,0x000002E1},
- {"0000001000010011111010101001010011011110000000100001000110000100",0x0000310D,0xFFFFEB78,0x000004D0,0x00001DC9,0xFFFFF5D5,0x00000368,0x00001DC9,0xFFFFF5D5,0x00000368},
- {"0000001000010011111010101001010011011110000000100011000100000100",0x000031BF,0xFFFFECA3,0x00000498,0x00001DC9,0xFFFFF717,0x00000336,0x00001DC9,0xFFFFF717,0x00000336},
- {"0000001000010011111100001111110101000010110011100010000100000100",0x00003896,0xFFFFE5DD,0x000005C5,0x000023E2,0xFFFFF1A1,0x00000416,0x000023E2,0xFFFFF1A1,0x00000416},
- {"0000001000010011111010101001010011011110001100100011100100000100",0x000023CB,0xFFFFF4C8,0x00000372,0x00001C33,0xFFFFF7D5,0x0000032A,0x00001C33,0xFFFFF7D5,0x0000032A},
- {"0000001000010011111100001111110101000010110100000010000011000100",0x00002F6B,0xFFFFEBF0,0x000004CE,0x00001C89,0xFFFFF689,0x0000034D,0x00001C89,0xFFFFF689,0x0000034D},
- {"0000001000010011111100001111110101000010110011100011100100000100",0x00003E72,0xFFFFE211,0x0000065D,0x0000218D,0xFFFFF309,0x000003DC,0x0000218D,0xFFFFF309,0x000003DC},
- {"0000001000010011111010101001010011011110000000100010000010000100",0x00002612,0xFFFFF2C3,0x000003AD,0x000019F7,0xFFFFF891,0x000002FE,0x000019F7,0xFFFFF891,0x000002FE},
- {"0000001000010011111010101001010011011110000101100100000110000100",0x0000205D,0xFFFFF59F,0x00000372,0x000012E6,0xFFFFFD0A,0x00000270,0x000012E6,0xFFFFFD0A,0x00000270},
- {"0000001000010011111100001111110101000010110010100010000100100100",0x00002ECB,0xFFFFEC47,0x000004BD,0x00001936,0xFFFFF8D9,0x000002E4,0x00001936,0xFFFFF8D9,0x000002E4},
- {"0000001000010011111010101001010011011110000001100100100100000100",0x00002BDB,0xFFFFEE6D,0x00000458,0x00001852,0xFFFFF943,0x000002D9,0x00001852,0xFFFFF943,0x000002D9},
- {"0000001000010011111010101001010011011110000100100100100100000100",0x00003387,0xFFFFE958,0x00000534,0x00001932,0xFFFFF8FA,0x000002E4,0x00001932,0xFFFFF8FA,0x000002E4},
- {"0000001000010011111010101001010011011110000000100000100011000100",0x00002E3C,0xFFFFED26,0x00000495,0x00001858,0xFFFFF990,0x000002D1,0x00001858,0xFFFFF990,0x000002D1},
- {"0000001000010011111010101001010011011110000000100010100101100100",0x000033B8,0xFFFFEA5C,0x000004F9,0x00001BD1,0xFFFFF76A,0x0000032E,0x00001BD1,0xFFFFF76A,0x0000032E},
- {"0000001000010011111010101001010011011110000001100010100110000100",0x00002BCE,0xFFFFEEE9,0x00000443,0x00001982,0xFFFFF90D,0x000002DF,0x00001982,0xFFFFF90D,0x000002DF},
- {"0000001000010011111100001111110101000010110100000100100011100100",0x00003495,0xFFFFE7D9,0x0000057B,0x00001D2A,0xFFFFF5A5,0x00000372,0x00001D2A,0xFFFFF5A5,0x00000372},
- {"0000001000010011111100001111110101000010110010100011100011100100",0x000034B1,0xFFFFE88D,0x00000556,0x00002014,0xFFFFF43A,0x000003AA,0x00002014,0xFFFFF43A,0x000003AA},
- {"0000001000010011111100001111110101000010110011000011000100100100",0x00002F96,0xFFFFEC84,0x000004AD,0x000024A2,0xFFFFF1CE,0x0000040A,0x000024A2,0xFFFFF1CE,0x0000040A},
- {"0000001000010011111010101001010011011110000101100001000001100100",0x0000203B,0xFFFFF640,0x00000359,0x000014EC,0xFFFFFC14,0x0000029C,0x000014EC,0xFFFFFC14,0x0000029C},
- {"0000001000010011111100001111110101000010110100000010100110000100",0x000034E2,0xFFFFE7B8,0x00000582,0x00001938,0xFFFFF872,0x000002FA,0x00001938,0xFFFFF872,0x000002FA},
- {"0000001000010011111010101001010011011110000001100011000100100100",0x00002AC7,0xFFFFF0C1,0x000003F5,0x00002268,0xFFFFF39C,0x000003C9,0x00002268,0xFFFFF39C,0x000003C9},
- {"0000001000010011111100001111110101000010110001100011000101000100",0x000036F6,0xFFFFE77F,0x00000571,0x000027D9,0xFFFFEF6F,0x00000461,0x000027D9,0xFFFFEF6F,0x00000461},
- {"0000001000010011111010101001010011011110000100100011000100100100",0x00002BAB,0xFFFFF018,0x00000419,0x00002126,0xFFFFF4E2,0x0000038F,0x00002126,0xFFFFF4E2,0x0000038F},
- {"0000001000010011111010101001010011011110001100100011100100100100",0x000028C4,0xFFFFF161,0x000003F8,0x0000180C,0xFFFFFA4B,0x000002C8,0x0000180C,0xFFFFFA4B,0x000002C8},
- {"0000001000010011111100001111110101000010110010100010100001100100",0x00002F48,0xFFFFEB62,0x000004EE,0x00001912,0xFFFFF8C8,0x000002EA,0x00001912,0xFFFFF8C8,0x000002EA},
- {"0000001000010011111100001111110101000010110011100010100001100100",0x000032DF,0xFFFFE911,0x00000545,0x00001F06,0xFFFFF485,0x0000039C,0x00001F06,0xFFFFF485,0x0000039C},
- {"0000001000010011111100001111110101000010110100000100000101000100",0x000035B8,0xFFFFE74F,0x00000590,0x00001FD7,0xFFFFF410,0x000003AF,0x00001FD7,0xFFFFF410,0x000003AF},
- {"0000001000010011111100001111110101000010110100000101000011000100",0x00003608,0xFFFFE6D7,0x000005A9,0x000024A6,0xFFFFF075,0x00000450,0x000024A6,0xFFFFF075,0x00000450},
- {"0000001000010011111100001111110101000010110010100011100010000100",0x000030AB,0xFFFFEAED,0x000004F5,0x000019EE,0xFFFFF84E,0x000002FC,0x000019EE,0xFFFFF84E,0x000002FC},
- {"0000001000010011111010101001010011011110000001100010000011000100",0x000030C6,0xFFFFEC92,0x0000049E,0x000019BB,0xFFFFF8F1,0x000002F3,0x000019BB,0xFFFFF8F1,0x000002F3},
- {"0000001000010011111100001111110101000010110001100011000010100100",0x00003B27,0xFFFFE544,0x000005C1,0x00002697,0xFFFFF072,0x00000438,0x00002697,0xFFFFF072,0x00000438},
- {"0000001000010011111010101001010011011110000100100100100011100100",0x00002F23,0xFFFFEC48,0x000004B9,0x0000199A,0xFFFFF8CF,0x000002E9,0x0000199A,0xFFFFF8CF,0x000002E9},
- {"0000001000010011111010101001010011011110000001100010100110100100",0x00002BD7,0xFFFFEEAC,0x00000450,0x00001991,0xFFFFF8F4,0x000002E2,0x00001991,0xFFFFF8F4,0x000002E2},
- {"0000001000010011111010101001010011011110000000100010000000100100",0x00003210,0xFFFFEB24,0x000004DE,0x00001BDF,0xFFFFF744,0x00000333,0x00001BDF,0xFFFFF744,0x00000333},
- {"0000001000010011111010101001010011011110001001000100000101000100",0x00002DDC,0xFFFFED0D,0x000004AC,0x000019D0,0xFFFFF869,0x0000030F,0x000019D0,0xFFFFF869,0x0000030F},
- {"0000001000010011111010101001010011011110001000000011100101100100",0x000023E6,0xFFFFF40C,0x000003A9,0x000014EB,0xFFFFFBC4,0x000002AF,0x000014EB,0xFFFFFBC4,0x000002AF},
- {"0000001000010011111100001111110101000010110010100010100110100100",0x000030CE,0xFFFFE9A5,0x0000053C,0x00001C45,0xFFFFF60E,0x0000035D,0x00001C45,0xFFFFF60E,0x0000035D},
- {"0000001000010011111010101001010011011110000101100001000010000100",0x00001E89,0xFFFFF73A,0x00000337,0x0000157C,0xFFFFFBC0,0x000002AA,0x0000157C,0xFFFFFBC0,0x000002AA},
- {"0000001000010011111100001111110101000010110100000100000100100100",0x000036C6,0xFFFFE6CF,0x000005A1,0x00002457,0xFFFFF11D,0x0000042D,0x00002457,0xFFFFF11D,0x0000042D},
- {"0000001000010011111010101001010011011110001100100001100101000100",0x00002815,0xFFFFF19A,0x000003F2,0x000016D2,0xFFFFFB40,0x00000299,0x000016D2,0xFFFFFB40,0x00000299},
- {"0000001000010011111010101001010011011110000111000001100110100100",0x00001FE2,0xFFFFF660,0x00000354,0x000015A7,0xFFFFFB47,0x000002C1,0x000015A7,0xFFFFFB47,0x000002C1},
- {"0000001000010011111010101001010011011110000101100001100101100100",0x00002114,0xFFFFF634,0x00000356,0x000016C1,0xFFFFFB43,0x000002B8,0x000016C1,0xFFFFFB43,0x000002B8},
- {"0000001000010011111100001111110101000010110011000010100011000100",0x000028E3,0xFFFFF075,0x00000414,0x0000203C,0xFFFFF438,0x000003B3,0x0000203C,0xFFFFF438,0x000003B3},
- {"0000001000010011111010101001010011011110000111000011100100100100",0x00001EEB,0xFFFFF7BB,0x0000031A,0x00001580,0xFFFFFBD7,0x000002AD,0x00001580,0xFFFFFBD7,0x000002AD},
- {"0000001000010011111010101001010011011110001001000000100011000100",0x00002BB2,0xFFFFEE72,0x00000470,0x0000192C,0xFFFFF91E,0x000002E7,0x0000192C,0xFFFFF91E,0x000002E7},
- {"0000001000010011111010101001010011011110000001100101000011100100",0x00003A3D,0xFFFFE49D,0x000005F5,0x00001A3B,0xFFFFF7B1,0x00000320,0x00001A3B,0xFFFFF7B1,0x00000320},
- {"0000001000010011111100001111110101000010110011100011000101100100",0x00002E93,0xFFFFEC5A,0x000004B4,0x000025EB,0xFFFFF03C,0x0000044A,0x000025EB,0xFFFFF03C,0x0000044A},
- {"0000001000010011111100001111110101000010110010100010000011000100",0x0000331F,0xFFFFE97A,0x00000531,0x00001A06,0xFFFFF850,0x000002FD,0x00001A06,0xFFFFF850,0x000002FD},
- {"0000001000010011111100001111110101000010110001100011100101100100",0x00003937,0xFFFFE5A0,0x000005C7,0x0000235E,0xFFFFF234,0x000003F2,0x0000235E,0xFFFFF234,0x000003F2},
- {"0000001000010011111010101001010011011110000111100011100100100100",0x00001DD0,0xFFFFF80E,0x00000319,0x000015C7,0xFFFFFB91,0x000002BC,0x000015C7,0xFFFFFB91,0x000002BC},
- {"0000001000010011111100001111110101000010110100000011100101100100",0x00003328,0xFFFFE905,0x0000054A,0x00002054,0xFFFFF3BF,0x000003C0,0x00002054,0xFFFFF3BF,0x000003C0},
- {"0000001000010011111100001111110101000010110011000001000100000100",0x00002FE5,0xFFFFEA65,0x00000520,0x0000188B,0xFFFFF8A7,0x000002F5,0x0000188B,0xFFFFF8A7,0x000002F5},
- {"0000001000010011111100001111110101000010110010100011100010100100",0x00002ED3,0xFFFFEC51,0x000004B9,0x00001888,0xFFFFF96A,0x000002CA,0x00001888,0xFFFFF96A,0x000002CA},
- {"0000001000010011111100001111110101000010110100000011000010000100",0x00002FCC,0xFFFFEB60,0x000004EA,0x00001F8D,0xFFFFF436,0x000003B4,0x00001F8D,0xFFFFF436,0x000003B4},
- {"0000001000010011111100001111110101000010110011100100000010000100",0x0000329F,0xFFFFE8F7,0x0000054F,0x000023DB,0xFFFFF0EE,0x0000043A,0x000023DB,0xFFFFF0EE,0x0000043A},
- {"0000001000010011111010101001010011011110000001000011100010100100",0x000030B5,0xFFFFEBB8,0x000004C4,0x00001AFD,0xFFFFF781,0x00000329,0x00001AFD,0xFFFFF781,0x00000329},
- {"0000001000010011111010101001010011011110000111100001100110100100",0x00001BBF,0xFFFFF8E2,0x000002F7,0x00001722,0xFFFFFA85,0x000002DB,0x00001722,0xFFFFFA85,0x000002DB},
- {"0000001000010011111010101001010011011110000000100010000001000100",0x000030E4,0xFFFFEBE6,0x000004BB,0x00001C80,0xFFFFF6E1,0x0000033E,0x00001C80,0xFFFFF6E1,0x0000033E},
- {"0000001000010011111010101001010011011110000100100010100101000100",0x000030E2,0xFFFFECD0,0x00000492,0x00001CE0,0xFFFFF753,0x0000032F,0x00001CE0,0xFFFFF753,0x0000032F},
- {"0000001000010011111010101001010011011110001100100010100001100100",0x00002513,0xFFFFF323,0x000003BC,0x00001965,0xFFFFF93C,0x000002F0,0x00001965,0xFFFFF93C,0x000002F0},
- {"0000001000010011111010101001010011011110000101100001000010100100",0x00002147,0xFFFFF585,0x0000037A,0x000014CC,0xFFFFFC3B,0x00000296,0x000014CC,0xFFFFFC3B,0x00000296},
- {"0000001000010011111010101001010011011110001100100010000100100100",0x00002507,0xFFFFF432,0x0000038A,0x00001890,0xFFFFFA61,0x000002C6,0x00001890,0xFFFFFA61,0x000002C6},
- {"0000001000010011111010101001010011011110000001100011100010100100",0x0000339B,0xFFFFEA7D,0x000004F0,0x0000191E,0xFFFFF944,0x000002DF,0x0000191E,0xFFFFF944,0x000002DF},
- {"0000001000010011111100001111110101000010110011000010100010100100",0x00002842,0xFFFFF043,0x00000427,0x00001988,0xFFFFF892,0x000002F7,0x00001988,0xFFFFF892,0x000002F7},
- {"0000001000010011111100001111110101000010110001100001100010100100",0x0000389D,0xFFFFE5D8,0x000005BF,0x00001EE1,0xFFFFF4EF,0x00000387,0x00001EE1,0xFFFFF4EF,0x00000387},
- {"0000001000010011111100001111110101000010110011100011000110000100",0x0000396D,0xFFFFE4D7,0x000005F2,0x000020DA,0xFFFFF34E,0x000003CD,0x000020DA,0xFFFFF34E,0x000003CD},
- {"0000001000010011111100001111110101000010110010100011000100000100",0x0000355F,0xFFFFE85A,0x0000055F,0x0000281F,0xFFFFEF28,0x0000047D,0x0000281F,0xFFFFEF28,0x0000047D},
- {"0000001000010011111010101001010011011110000111000101000011100100",0x00002284,0xFFFFF46E,0x00000399,0x00001498,0xFFFFFBE3,0x0000029C,0x00001498,0xFFFFFBE3,0x0000029C},
- {"0000001000010011111010101001010011011110000000100011100101000100",0x000031B6,0xFFFFEB42,0x000004D9,0x00001F54,0xFFFFF4D2,0x00000399,0x00001F54,0xFFFFF4D2,0x00000399},
- {"0000001000010011111100001111110101000010110001100011000001100100",0x000035CE,0xFFFFE79D,0x00000578,0x00001C78,0xFFFFF68C,0x00000344,0x00001C78,0xFFFFF68C,0x00000344},
- {"0000001000010011111010101001010011011110000111100100100101100100",0x00001C0A,0xFFFFF81B,0x00000318,0x00001492,0xFFFFFBCC,0x000002A5,0x00001492,0xFFFFFBCC,0x000002A5},
- {"0000001000010011111010101001010011011110000000100010000110000100",0x00003492,0xFFFFE95C,0x00000526,0x00001A97,0xFFFFF81B,0x0000030B,0x00001A97,0xFFFFF81B,0x0000030B},
- {"0000001000010011111010101001010011011110000101100011000101100100",0x00001E89,0xFFFFF7D0,0x0000031A,0x000017A5,0xFFFFFA99,0x000002D9,0x000017A5,0xFFFFFA99,0x000002D9},
- {"0000001000010011111100001111110101000010110010100100100011000100",0x00002DCC,0xFFFFEBE0,0x000004DE,0x000019BA,0xFFFFF7F5,0x0000030D,0x000019BA,0xFFFFF7F5,0x0000030D},
- {"0000001000010011111010101001010011011110000001000010100110000100",0x000030EF,0xFFFFEBC1,0x000004C0,0x00001AA9,0xFFFFF814,0x0000030A,0x00001AA9,0xFFFFF814,0x0000030A},
- {"0000001000010011111010101001010011011110001001000101000100100100",0x00002EA3,0xFFFFEBF6,0x000004D8,0x00001DCF,0xFFFFF521,0x00000399,0x00001DCF,0xFFFFF521,0x00000399},
- {"0000001000010011111010101001010011011110001100100100000101100100",0x00002B5F,0xFFFFEEA1,0x0000046C,0x000017EB,0xFFFFF9C9,0x000002D4,0x000017EB,0xFFFFF9C9,0x000002D4},
- {"0000001000010011111010101001010011011110000000100100000100000100",0x00002C63,0xFFFFEE82,0x00000455,0x00002268,0xFFFFF29D,0x000003F6,0x00002268,0xFFFFF29D,0x000003F6},
- {"0000001000010011111010101001010011011110000100100001100100000100",0x00002B1A,0xFFFFF016,0x0000041C,0x000019AA,0xFFFFF988,0x000002D2,0x000019AA,0xFFFFF988,0x000002D2},
- {"0000001000010011111100001111110101000010110010100010100101100100",0x0000332F,0xFFFFE934,0x0000053B,0x00001E47,0xFFFFF566,0x00000374,0x00001E47,0xFFFFF566,0x00000374},
- {"0000001000010011111100001111110101000010110010100100100011100100",0x00002995,0xFFFFEEC1,0x00000465,0x0000178F,0xFFFFF995,0x000002C5,0x0000178F,0xFFFFF995,0x000002C5},
- {"0000001000010011111010101001010011011110001000000001100010000100",0x00001C2E,0xFFFFF932,0x000002E9,0x000015C2,0xFFFFFBC5,0x000002AD,0x000015C2,0xFFFFFBC5,0x000002AD},
- {"0000001000010011111100001111110101000010110001100100000011100100",0x00003B08,0xFFFFE4E8,0x000005D8,0x0000209D,0xFFFFF444,0x00000398,0x0000209D,0xFFFFF444,0x00000398},
- {"0000001000010011111010101001010011011110000001000101000011100100",0x00002F1F,0xFFFFEB74,0x000004EB,0x00001F4C,0xFFFFF3D4,0x000003CE,0x00001F4C,0xFFFFF3D4,0x000003CE},
- {"0000001000010011111010101001010011011110000001000011100010000100",0x00003415,0xFFFFE89F,0x00000553,0x0000186B,0xFFFFF8E1,0x000002EF,0x0000186B,0xFFFFF8E1,0x000002EF},
- {"0000001000010011111100001111110101000010110011000001000011000100",0x00003441,0xFFFFE779,0x0000059D,0x000019EA,0xFFFFF7B2,0x0000031F,0x000019EA,0xFFFFF7B2,0x0000031F},
- {"0000001000010011111010101001010011011110000101100100000001100100",0x00002174,0xFFFFF546,0x00000378,0x00001456,0xFFFFFC5F,0x00000284,0x00001456,0xFFFFFC5F,0x00000284},
- {"0000001000010011111100001111110101000010110011100100000011000100",0x00003788,0xFFFFE61E,0x000005BF,0x00001DF4,0xFFFFF562,0x00000374,0x00001DF4,0xFFFFF562,0x00000374},
- {"0000001000010011111010101001010011011110000111100001100001000100",0x00001C41,0xFFFFF8C1,0x000002FC,0x0000171E,0xFFFFFA93,0x000002DE,0x0000171E,0xFFFFFA93,0x000002DE},
- {"0000001000010011111100001111110101000010110010100011100001100100",0x00002B15,0xFFFFEDEC,0x00000487,0x000017E4,0xFFFFF934,0x000002DF,0x000017E4,0xFFFFF934,0x000002DF},
- {"0000001000010011111100001111110101000010110011000011000101000100",0x0000327A,0xFFFFEA71,0x000004FF,0x00001D96,0xFFFFF63B,0x00000351,0x00001D96,0xFFFFF63B,0x00000351},
- {"0000001000010011111010101001010011011110000111100100000001100100",0x000023C6,0xFFFFF3E5,0x000003B6,0x000014DE,0xFFFFFC29,0x00000294,0x000014DE,0xFFFFFC29,0x00000294},
- {"0000001000010011111010101001010011011110000101100100100101000100",0x00001F96,0xFFFFF5FA,0x00000364,0x00001397,0xFFFFFC9D,0x0000027D,0x00001397,0xFFFFFC9D,0x0000027D},
- {"0000001000010011111010101001010011011110000001100011000101000100",0x00002B51,0xFFFFEFB5,0x00000420,0x00001ACA,0xFFFFF824,0x0000030D,0x00001ACA,0xFFFFF824,0x0000030D},
- {"0000001000010011111010101001010011011110000111100100100101000100",0x000020DB,0xFFFFF55B,0x0000037C,0x0000153D,0xFFFFFB5F,0x000002BA,0x0000153D,0xFFFFFB5F,0x000002BA},
- {"0000001000010011111010101001010011011110000000100010000110100100",0x000030BB,0xFFFFEBDA,0x000004BC,0x00001B0E,0xFFFFF7A8,0x0000031E,0x00001B0E,0xFFFFF7A8,0x0000031E},
- {"0000001000010011111100001111110101000010110001100010100100000100",0x000033C4,0xFFFFEA41,0x000004FA,0x000022C6,0xFFFFF363,0x000003BC,0x000022C6,0xFFFFF363,0x000003BC},
- {"0000001000010011111010101001010011011110001001000000100100100100",0x00002D47,0xFFFFEE01,0x00000477,0x000021CD,0xFFFFF36E,0x000003D6,0x000021CD,0xFFFFF36E,0x000003D6},
- {"0000001000010011111010101001010011011110000111100011000110100100",0x00001E7B,0xFFFFF733,0x00000339,0x00001668,0xFFFFFB29,0x000002BF,0x00001668,0xFFFFFB29,0x000002BF},
- {"0000001000010011111100001111110101000010110010100010100110000100",0x00002F7E,0xFFFFEAFF,0x000004FC,0x000018D4,0xFFFFF8BE,0x000002E8,0x000018D4,0xFFFFF8BE,0x000002E8},
- {"0000001000010011111010101001010011011110001100100011100010100100",0x00002635,0xFFFFF2E1,0x000003BC,0x000017A4,0xFFFFFA67,0x000002C3,0x000017A4,0xFFFFFA67,0x000002C3},
- {"0000001000010011111010101001010011011110000100100011000010100100",0x000026CA,0xFFFFF2C1,0x000003B2,0x00001C3E,0xFFFFF7AE,0x0000031F,0x00001C3E,0xFFFFF7AE,0x0000031F},
- {"0000001000010011111010101001010011011110000111000001000001100100",0x00002550,0xFFFFF380,0x000003B5,0x000019F5,0xFFFFF8E7,0x00000313,0x000019F5,0xFFFFF8E7,0x00000313},
- {"0000001000010011111100001111110101000010110010100100100100000100",0x00002FBC,0xFFFFEAF8,0x000004FA,0x000018CC,0xFFFFF8C6,0x000002E8,0x000018CC,0xFFFFF8C6,0x000002E8},
- {"0000001000010011111100001111110101000010110100000001100011100100",0x00002FCC,0xFFFFEB60,0x000004EA,0x00001EFF,0xFFFFF4DA,0x0000038F,0x00001EFF,0xFFFFF4DA,0x0000038F},
- {"0000001000010011111010101001010011011110000101100100000010000100",0x000023E6,0xFFFFF413,0x000003A1,0x00001544,0xFFFFFC16,0x0000028B,0x00001544,0xFFFFFC16,0x0000028B},
- {"0000001000010011111100001111110101000010110011100011000000100100",0x00003251,0xFFFFEAA2,0x000004F5,0x000025B0,0xFFFFF0DF,0x00000431,0x000025B0,0xFFFFF0DF,0x00000431},
- {"0000001000010011111100001111110101000010110100000011100110000100",0x00002F6F,0xFFFFEB67,0x000004E6,0x00002275,0xFFFFF249,0x000003FB,0x00002275,0xFFFFF249,0x000003FB},
- {"0000001000010011111010101001010011011110001100100010100101100100",0x00002597,0xFFFFF34A,0x000003B1,0x00001BCC,0xFFFFF822,0x0000031A,0x00001BCC,0xFFFFF822,0x0000031A},
- {"0000001000010011111100001111110101000010110001100011100001100100",0x00003B1D,0xFFFFE40E,0x0000060D,0x00001F61,0xFFFFF470,0x0000039F,0x00001F61,0xFFFFF470,0x0000039F},
- {"0000001000010011111100001111110101000010110001100100000101000100",0x0000379F,0xFFFFE6DB,0x0000058C,0x00002460,0xFFFFF170,0x00000415,0x00002460,0xFFFFF170,0x00000415},
- {"0000001000010011111010101001010011011110000101100101000101000100",0x00002442,0xFFFFF2FB,0x000003D9,0x00001414,0xFFFFFBDC,0x000002A2,0x00001414,0xFFFFFBDC,0x000002A2},
- {"0000001000010011111010101001010011011110000000100100000011000100",0x00003270,0xFFFFEA0D,0x0000051C,0x00001AFD,0xFFFFF783,0x00000328,0x00001AFD,0xFFFFF783,0x00000328},
- {"0000001000010011111010101001010011011110000101100001000100000100",0x00001B23,0xFFFFF94B,0x000002EB,0x000015F1,0xFFFFFB82,0x000002B4,0x000015F1,0xFFFFFB82,0x000002B4},
- {"0000001000010011111010101001010011011110001100100011100001000100",0x000026AE,0xFFFFF21A,0x000003DB,0x00001827,0xFFFFFA10,0x000002C8,0x00001827,0xFFFFFA10,0x000002C8},
- {"0000001000010011111100001111110101000010110010100100100010000100",0x00002DCF,0xFFFFEBD8,0x000004DB,0x00001A75,0xFFFFF719,0x0000033A,0x00001A75,0xFFFFF719,0x0000033A},
- {"0000001000010011111100001111110101000010110011100100000011100100",0x00003983,0xFFFFE500,0x000005EA,0x000022A6,0xFFFFF25F,0x000003F1,0x000022A6,0xFFFFF25F,0x000003F1},
- {"0000001000010011111010101001010011011110000100100001100011000100",0x00002AD5,0xFFFFF07A,0x00000406,0x000019FB,0xFFFFF961,0x000002D8,0x000019FB,0xFFFFF961,0x000002D8},
- {"0000001000010011111100001111110101000010110010100011100110100100",0x00002A43,0xFFFFEE43,0x00000474,0x00001D65,0xFFFFF538,0x00000387,0x00001D65,0xFFFFF538,0x00000387},
- {"0000001000010011111100001111110101000010110001100010000010000100",0x0000311E,0xFFFFEAF8,0x000004E8,0x00001959,0xFFFFF8E4,0x000002DC,0x00001959,0xFFFFF8E4,0x000002DC},
- {"0000001000010011111100001111110101000010110100000011000110100100",0x0000339A,0xFFFFE8A7,0x00000559,0x00001A04,0xFFFFF7E5,0x00000311,0x00001A04,0xFFFFF7E5,0x00000311},
- {"0000001000010011111010101001010011011110001000000100000101000100",0x000021B3,0xFFFFF50F,0x00000389,0x00001470,0xFFFFFBF7,0x000002A5,0x00001470,0xFFFFFBF7,0x000002A5},
- {"0000001000010011111010101001010011011110000000100001100010000100",0x00003417,0xFFFFE9A6,0x0000051D,0x000018A4,0xFFFFF984,0x000002CF,0x000018A4,0xFFFFF984,0x000002CF},
- {"0000001000010011111010101001010011011110001000000010100110000100",0x00001FED,0xFFFFF6A2,0x00000347,0x00001639,0xFFFFFB59,0x000002BB,0x00001639,0xFFFFFB59,0x000002BB},
- {"0000001000010011111010101001010011011110000100100001100010100100",0x000032D2,0xFFFFEB18,0x000004DC,0x00001A01,0xFFFFF95E,0x000002CF,0x00001A01,0xFFFFF95E,0x000002CF},
- {"0000001000010011111100001111110101000010110100000100000010000100",0x00003147,0xFFFFEA3B,0x00000518,0x0000241D,0xFFFFF11C,0x00000431,0x0000241D,0xFFFFF11C,0x00000431},
- {"0000001000010011111010101001010011011110000111000000100100000100",0x00001D44,0xFFFFF7E7,0x0000031A,0x0000153F,0xFFFFFBBC,0x000002A9,0x0000153F,0xFFFFFBBC,0x000002A9},
- {"0000001000010011111100001111110101000010110011000100000100000100",0x00003690,0xFFFFE6E3,0x000005A4,0x000018DE,0xFFFFF908,0x000002DD,0x000018DE,0xFFFFF908,0x000002DD},
- {"0000001000010011111100001111110101000010110011000010000110000100",0x00003561,0xFFFFE6F8,0x000005AB,0x000018B5,0xFFFFF8A0,0x000002F3,0x000018B5,0xFFFFF8A0,0x000002F3},
- {"0000001000010011111010101001010011011110001100100011000100100100",0x000028F4,0xFFFFF23A,0x000003CE,0x00001BC6,0xFFFFF881,0x00000311,0x00001BC6,0xFFFFF881,0x00000311},
- {"0000001000010011111100001111110101000010110100000011000110000100",0x000035D7,0xFFFFE71C,0x0000059B,0x00001D49,0xFFFFF5C8,0x00000368,0x00001D49,0xFFFFF5C8,0x00000368},
- {"0000001000010011111100001111110101000010110011100001100010100100",0x0000397E,0xFFFFE4CB,0x000005F4,0x00001989,0xFFFFF844,0x000002FD,0x00001989,0xFFFFF844,0x000002FD},
- {"0000001000010011111100001111110101000010110001100010000001100100",0x00003BAB,0xFFFFE332,0x0000063F,0x00001A69,0xFFFFF7B9,0x00000312,0x00001A69,0xFFFFF7B9,0x00000312},
- {"0000001000010011111100001111110101000010110100000011000001100100",0x00002F26,0xFFFFEB82,0x000004E8,0x00001D7D,0xFFFFF590,0x00000379,0x00001D7D,0xFFFFF590,0x00000379},
- {"0000001000010011111010101001010011011110000001100011000110100100",0x00002FDC,0xFFFFEBE0,0x000004C3,0x00001940,0xFFFFF8CC,0x000002EE,0x00001940,0xFFFFF8CC,0x000002EE},
- {"0000001000010011111010101001010011011110000111000000100011100100",0x000021B2,0xFFFFF558,0x00000379,0x00001643,0xFFFFFB1C,0x000002C3,0x00001643,0xFFFFFB1C,0x000002C3},
- {"0000001000010011111010101001010011011110001100100001100100000100",0x00002897,0xFFFFF181,0x000003F7,0x00001990,0xFFFFF994,0x000002E2,0x00001990,0xFFFFF994,0x000002E2},
- {"0000001000010011111010101001010011011110000111100000100100100100",0x00001D19,0xFFFFF829,0x0000031A,0x00001558,0xFFFFFBCA,0x000002AF,0x00001558,0xFFFFFBCA,0x000002AF},
- {"0000001000010011111010101001010011011110000001000011000101000100",0x00003311,0xFFFFEAD9,0x000004E1,0x00001BDC,0xFFFFF79E,0x0000031D,0x00001BDC,0xFFFFF79E,0x0000031D},
- {"0000001000010011111010101001010011011110000111100010100111000100",0x00001E54,0xFFFFF740,0x00000333,0x000016A1,0xFFFFFAF0,0x000002C4,0x000016A1,0xFFFFFAF0,0x000002C4},
- {"0000001000010011111100001111110101000010110011100011100101100100",0x00003266,0xFFFFE9A8,0x00000527,0x00002307,0xFFFFF219,0x000003FC,0x00002307,0xFFFFF219,0x000003FC},
- {"0000001000010011111010101001010011011110001100100001000101000100",0x00001D1F,0xFFFFF82B,0x000002F0,0x000013F0,0xFFFFFD0B,0x0000024E,0x000013F0,0xFFFFFD0B,0x0000024E},
- {"0000001000010011111100001111110101000010110001100100100010100100",0x0000312E,0xFFFFEA67,0x00000502,0x0000222A,0xFFFFF253,0x000003F9,0x0000222A,0xFFFFF253,0x000003F9},
- {"0000001000010011111100001111110101000010110010100100000100100100",0x000032B2,0xFFFFE9AD,0x00000523,0x00001E97,0xFFFFF527,0x0000037F,0x00001E97,0xFFFFF527,0x0000037F},
- {"0000001000010011111010101001010011011110000101100100000011100100",0x00001F6A,0xFFFFF6FC,0x00000338,0x0000164B,0xFFFFFB2C,0x000002C2,0x0000164B,0xFFFFFB2C,0x000002C2},
- {"0000001000010011111010101001010011011110000000100010100011000100",0x00002603,0xFFFFF386,0x00000392,0x00001EE0,0xFFFFF601,0x00000369,0x00001EE0,0xFFFFF601,0x00000369},
- {"0000001000010011111010101001010011011110001000000001000101100100",0x00001D0C,0xFFFFF803,0x00000317,0x00001345,0xFFFFFD52,0x00000260,0x00001345,0xFFFFFD52,0x00000260},
- {"0000001000010011111100001111110101000010110011000001100010000100",0x0000327A,0xFFFFE8E5,0x0000055C,0x00001680,0xFFFFFA2D,0x000002B2,0x00001680,0xFFFFFA2D,0x000002B2},
- {"0000001000010011111100001111110101000010110010100011100101100100",0x000032B8,0xFFFFE91A,0x0000054A,0x00001BAB,0xFFFFF6EC,0x00000338,0x00001BAB,0xFFFFF6EC,0x00000338},
- {"0000001000010011111100001111110101000010110011000011000001000100",0x00002F79,0xFFFFEB63,0x000004EF,0x000017BB,0xFFFFF9B1,0x000002CA,0x000017BB,0xFFFFF9B1,0x000002CA},
- {"0000001000010011111010101001010011011110000001000011100011100100",0x00002AE5,0xFFFFEFCB,0x0000041D,0x0000214A,0xFFFFF3A7,0x000003C7,0x0000214A,0xFFFFF3A7,0x000003C7},
- {"0000001000010011111010101001010011011110001100100010000001100100",0x0000212C,0xFFFFF5BC,0x0000034F,0x000017ED,0xFFFFFA4C,0x000002C1,0x000017ED,0xFFFFFA4C,0x000002C1},
- {"0000001000010011111010101001010011011110000100100001000100100100",0x00002BE7,0xFFFFEF40,0x0000043C,0x00001AE2,0xFFFFF8CF,0x000002E3,0x00001AE2,0xFFFFF8CF,0x000002E3},
- {"0000001000010011111100001111110101000010110100000101000101000100",0x000032DC,0xFFFFE90F,0x00000549,0x00002A2D,0xFFFFECC9,0x000004ED,0x00002A2D,0xFFFFECC9,0x000004ED},
- {"0000001000010011111010101001010011011110000101100001100010100100",0x00001DE3,0xFFFFF80D,0x00000319,0x000016FA,0xFFFFFB42,0x000002BC,0x000016FA,0xFFFFFB42,0x000002BC},
- {"0000001000010011111010101001010011011110000111100010100001000100",0x00001F1B,0xFFFFF6DE,0x00000346,0x00001502,0xFFFFFC23,0x00000298,0x00001502,0xFFFFFC23,0x00000298},
- {"0000001000010011111010101001010011011110000001100001100001100100",0x00003203,0xFFFFEA87,0x000004FE,0x0000194E,0xFFFFF8E3,0x000002EC,0x0000194E,0xFFFFF8E3,0x000002EC},
- {"0000001000010011111100001111110101000010110100000010000101000100",0x0000337A,0xFFFFE8DD,0x00000551,0x00001E3C,0xFFFFF534,0x00000385,0x00001E3C,0xFFFFF534,0x00000385},
- {"0000001000010011111100001111110101000010110010100100100001100100",0x000036F6,0xFFFFE62A,0x000005C5,0x000023C0,0xFFFFF117,0x00000435,0x000023C0,0xFFFFF117,0x00000435},
- {"0000001000010011111100001111110101000010110011000010000101000100",0x00003125,0xFFFFEA4E,0x0000051A,0x00001E6C,0xFFFFF503,0x0000038E,0x00001E6C,0xFFFFF503,0x0000038E},
- {"0000001000010011111010101001010011011110000111000000100010100100",0x00001CD4,0xFFFFF82D,0x0000030E,0x0000156D,0xFFFFFB64,0x000002B8,0x0000156D,0xFFFFFB64,0x000002B8},
- {"0000001000010011111010101001010011011110000000100100000010100100",0x00002F14,0xFFFFEC46,0x000004B8,0x000017F1,0xFFFFF977,0x000002D2,0x000017F1,0xFFFFF977,0x000002D2},
- {"0000001000010011111010101001010011011110000001100100000010100100",0x000031F1,0xFFFFEAD4,0x000004ED,0x0000184C,0xFFFFF983,0x000002D4,0x0000184C,0xFFFFF983,0x000002D4},
- {"0000001000010011111100001111110101000010110100000100100110000100",0x00002EA9,0xFFFFEBD7,0x000004D5,0x0000288D,0xFFFFEDDB,0x000004C0,0x0000288D,0xFFFFEDDB,0x000004C0},
- {"0000001000010011111100001111110101000010110010100011100110000100",0x0000335F,0xFFFFE82C,0x00000579,0x00001DBF,0xFFFFF512,0x0000038C,0x00001DBF,0xFFFFF512,0x0000038C},
- {"0000001000010011111010101001010011011110001000000001000110000100",0x0000224F,0xFFFFF4B5,0x00000391,0x0000138C,0xFFFFFCC3,0x0000027A,0x0000138C,0xFFFFFCC3,0x0000027A},
- {"0000001000010011111010101001010011011110000100100100000010100100",0x0000320D,0xFFFFEACD,0x000004F5,0x00001976,0xFFFFF913,0x000002E2,0x00001976,0xFFFFF913,0x000002E2},
- {"0000001000010011111010101001010011011110001000000010000100000100",0x00001BEB,0xFFFFF99C,0x000002E4,0x000016A4,0xFFFFFB77,0x000002C3,0x000016A4,0xFFFFFB77,0x000002C3},
- {"0000001000010011111010101001010011011110000001100011000001000100",0x0000396E,0xFFFFE616,0x000005A9,0x000018F4,0xFFFFF91A,0x000002E3,0x000018F4,0xFFFFF91A,0x000002E3},
- {"0000001000010011111010101001010011011110000000100010100001100100",0x00003251,0xFFFFEA8E,0x000004FA,0x000018EF,0xFFFFF910,0x000002E4,0x000018EF,0xFFFFF910,0x000002E4},
- {"0000001000010011111010101001010011011110000111000001100100100100",0x00001DAF,0xFFFFF857,0x0000030D,0x00001915,0xFFFFF9D8,0x000002F7,0x00001915,0xFFFFF9D8,0x000002F7},
- {"0000001000010011111010101001010011011110001000000100000110100100",0x000025B6,0xFFFFF26B,0x000003E5,0x00001531,0xFFFFFB68,0x000002AF,0x00001531,0xFFFFFB68,0x000002AF},
- {"0000001000010011111010101001010011011110000001100001100010000100",0x00002B2E,0xFFFFEF2E,0x00000440,0x00001968,0xFFFFF91A,0x000002DF,0x00001968,0xFFFFF91A,0x000002DF},
- {"0000001000010011111010101001010011011110000111000010000001100100",0x00002305,0xFFFFF528,0x00000377,0x000018A4,0xFFFFF9EB,0x000002F0,0x000018A4,0xFFFFF9EB,0x000002F0},
- {"0000001000010011111100001111110101000010110010100100000011000100",0x000032A1,0xFFFFE992,0x0000052E,0x00001A55,0xFFFFF826,0x000002FE,0x00001A55,0xFFFFF826,0x000002FE},
- {"0000001000010011111010101001010011011110000001000010000110000100",0x00002CCD,0xFFFFEE35,0x00000462,0x00001B09,0xFFFFF7E6,0x0000030F,0x00001B09,0xFFFFF7E6,0x0000030F},
- {"0000001000010011111010101001010011011110001100100011000010000100",0x00002602,0xFFFFF2CF,0x000003C5,0x000016EE,0xFFFFFAD4,0x000002B4,0x000016EE,0xFFFFFAD4,0x000002B4},
- {"0000001000010011111100001111110101000010110100000001100101100100",0x00003370,0xFFFFE891,0x00000560,0x000017F0,0xFFFFF930,0x000002DF,0x000017F0,0xFFFFF930,0x000002DF},
- {"0000001000010011111100001111110101000010110010100001100010000100",0x00002EDC,0xFFFFEB6D,0x000004EC,0x000016E6,0xFFFFF9ED,0x000002BC,0x000016E6,0xFFFFF9ED,0x000002BC},
- {"0000001000010011111010101001010011011110000100100010100011000100",0x00002A05,0xFFFFF13D,0x000003F0,0x00002065,0xFFFFF57B,0x00000378,0x00002065,0xFFFFF57B,0x00000378},
- {"0000001000010011111100001111110101000010110011100010000001000100",0x00002F8A,0xFFFFEB6E,0x000004E4,0x00001E3E,0xFFFFF50E,0x0000038D,0x00001E3E,0xFFFFF50E,0x0000038D},
- {"0000001000010011111100001111110101000010110010100011000001000100",0x00002BB5,0xFFFFED6A,0x000004A1,0x000017BF,0xFFFFF937,0x000002E5,0x000017BF,0xFFFFF937,0x000002E5},
- {"0000001000010011111010101001010011011110001000000001100101100100",0x0000202C,0xFFFFF6CE,0x0000033F,0x000015EE,0xFFFFFB83,0x000002B9,0x000015EE,0xFFFFFB83,0x000002B9},
- {"0000001000010011111010101001010011011110000000100010100010000100",0x00002C0C,0xFFFFEF10,0x0000043F,0x00001A73,0xFFFFF83E,0x0000030C,0x00001A73,0xFFFFF83E,0x0000030C},
- {"0000001000010011111010101001010011011110001100100100000100000100",0x0000234F,0xFFFFF460,0x00000385,0x000018C3,0xFFFFF9A5,0x000002DD,0x000018C3,0xFFFFF9A5,0x000002DD},
- {"0000001000010011111100001111110101000010110011100001100100000100",0x00003679,0xFFFFE704,0x00000595,0x00002177,0xFFFFF31A,0x000003D7,0x00002177,0xFFFFF31A,0x000003D7},
- {"0000001000010011111100001111110101000010110010100010100100100100",0x00003008,0xFFFFEBB8,0x000004D5,0x000024FF,0xFFFFF112,0x00000430,0x000024FF,0xFFFFF112,0x00000430},
- {"0000001000010011111100001111110101000010110001100100000110100100",0x00003848,0xFFFFE6A3,0x00000594,0x00002958,0xFFFFEE37,0x000004A0,0x00002958,0xFFFFEE37,0x000004A0},
- {"0000001000010011111100001111110101000010110011000001100100100100",0x00002FDF,0xFFFFEB08,0x000004FD,0x00001D77,0xFFFFF58B,0x0000037A,0x00001D77,0xFFFFF58B,0x0000037A},
- {"0000001000010011111010101001010011011110000001100011000001100100",0x00002EC8,0xFFFFED41,0x00000481,0x00001949,0xFFFFF91C,0x000002DF,0x00001949,0xFFFFF91C,0x000002DF},
- {"0000001000010011111100001111110101000010110100000100000110100100",0x000037C1,0xFFFFE5BA,0x000005D7,0x0000252C,0xFFFFF023,0x00000460,0x0000252C,0xFFFFF023,0x00000460},
- {"0000001000010011111100001111110101000010110011100010100101000100",0x00003716,0xFFFFE70C,0x0000058A,0x000028CC,0xFFFFEE57,0x0000049D,0x000028CC,0xFFFFEE57,0x0000049D},
- {"0000001000010011111100001111110101000010110010100100000011100100",0x000033D1,0xFFFFE8E8,0x00000547,0x00001AB1,0xFFFFF7E5,0x00000309,0x00001AB1,0xFFFFF7E5,0x00000309},
- {"0000001000010011111100001111110101000010110011000010100101000100",0x00002D72,0xFFFFED65,0x0000048E,0x00001E0D,0xFFFFF5A7,0x00000370,0x00001E0D,0xFFFFF5A7,0x00000370},
- {"0000001000010011111010101001010011011110000111000011100110100100",0x00002292,0xFFFFF49F,0x00000393,0x000017F4,0xFFFFF9CD,0x000002F5,0x000017F4,0xFFFFF9CD,0x000002F5},
- {"0000001000010011111010101001010011011110001001000011000001000100",0x000026EE,0xFFFFF18C,0x000003F7,0x000018A7,0xFFFFF95A,0x000002E5,0x000018A7,0xFFFFF95A,0x000002E5},
- {"0000001000010011111010101001010011011110000001000010000101100100",0x00002F62,0xFFFFEC9B,0x000004A4,0x0000194E,0xFFFFF932,0x000002D9,0x0000194E,0xFFFFF932,0x000002D9},
- {"0000001000010011111010101001010011011110000111100011100110000100",0x00001CE8,0xFFFFF7FA,0x0000031C,0x000014CE,0xFFFFFBD4,0x000002AB,0x000014CE,0xFFFFFBD4,0x000002AB},
- {"0000001000010011111010101001010011011110000100100001000011100100",0x00002E5A,0xFFFFEDAB,0x0000047C,0x00001A82,0xFFFFF8F7,0x000002DE,0x00001A82,0xFFFFF8F7,0x000002DE},
- {"0000001000010011111100001111110101000010110011000011000011100100",0x00003057,0xFFFFEC34,0x000004B9,0x00002296,0xFFFFF342,0x000003D0,0x00002296,0xFFFFF342,0x000003D0},
- {"0000001000010011111010101001010011011110000001000001100010100100",0x00002B0F,0xFFFFEF58,0x00000434,0x00001BFD,0xFFFFF721,0x00000330,0x00001BFD,0xFFFFF721,0x00000330},
- {"0000001000010011111010101001010011011110001000000001000010100100",0x00001F01,0xFFFFF751,0x0000032F,0x00001502,0xFFFFFC3E,0x00000296,0x00001502,0xFFFFFC3E,0x00000296},
- {"0000001000010011111100001111110101000010110010100011000001100100",0x00002FF4,0xFFFFEAE2,0x00000503,0x00001B36,0xFFFFF736,0x00000330,0x00001B36,0xFFFFF736,0x00000330},
- {"0000001000010011111100001111110101000010110011100010000001100100",0x00003762,0xFFFFE5AB,0x000005DE,0x000018CB,0xFFFFF896,0x000002F4,0x000018CB,0xFFFFF896,0x000002F4},
- {"0000001000010011111100001111110101000010110011000010000001100100",0x00002890,0xFFFFEF92,0x00000445,0x0000191D,0xFFFFF86F,0x00000302,0x0000191D,0xFFFFF86F,0x00000302},
- {"0000001000010011111010101001010011011110000001000011000001100100",0x00002F76,0xFFFFEC0E,0x000004BF,0x00001F7D,0xFFFFF41A,0x000003C0,0x00001F7D,0xFFFFF41A,0x000003C0},
- {"0000001000010011111010101001010011011110000111100000100010100100",0x00001D55,0xFFFFF7F8,0x0000031E,0x000015DF,0xFFFFFB79,0x000002B7,0x000015DF,0xFFFFFB79,0x000002B7},
- {"0000001000010011111010101001010011011110001000000100100100100100",0x00001FE9,0xFFFFF64A,0x00000353,0x000019E8,0xFFFFF882,0x0000032A,0x000019E8,0xFFFFF882,0x0000032A},
- {"0000001000010011111010101001010011011110000001100011100101100100",0x000030B5,0xFFFFEBB8,0x000004C4,0x00001857,0xFFFFF968,0x000002D8,0x00001857,0xFFFFF968,0x000002D8},
- {"0000001000010011111100001111110101000010110010100010100011000100",0x00003398,0xFFFFE9A3,0x00000524,0x00001FF9,0xFFFFF458,0x000003AD,0x00001FF9,0xFFFFF458,0x000003AD},
- {"0000001000010011111100001111110101000010110011100010100101100100",0x00003897,0xFFFFE5BD,0x000005C8,0x00002519,0xFFFFF0BA,0x00000438,0x00002519,0xFFFFF0BA,0x00000438},
- {"0000001000010011111100001111110101000010110100000100000001100100",0x00003234,0xFFFFE9B1,0x00000530,0x000022CC,0xFFFFF20E,0x00000409,0x000022CC,0xFFFFF20E,0x00000409},
- {"0000001000010011111010101001010011011110001000000101000100000100",0x00001FD2,0xFFFFF641,0x00000354,0x000017C9,0xFFFFF9C0,0x000002FB,0x000017C9,0xFFFFF9C0,0x000002FB},
- {"0000001000010011111100001111110101000010110011100100100011100100",0x00003234,0xFFFFE946,0x0000053D,0x00002267,0xFFFFF1F5,0x0000040D,0x00002267,0xFFFFF1F5,0x0000040D},
- {"0000001000010011111010101001010011011110001000000010100110100100",0x00002330,0xFFFFF474,0x00000399,0x00001490,0xFFFFFC67,0x00000288,0x00001490,0xFFFFFC67,0x00000288},
- {"0000001000010011111100001111110101000010110100000011100100100100",0x000032A3,0xFFFFE9EB,0x0000051B,0x0000234D,0xFFFFF23C,0x000003F7,0x0000234D,0xFFFFF23C,0x000003F7},
- {"0000001000010011111010101001010011011110001000000000100100000100",0x0000217E,0xFFFFF53A,0x00000384,0x00001511,0xFFFFFBF5,0x0000029E,0x00001511,0xFFFFFBF5,0x0000029E},
- {"0000001000010011111100001111110101000010110011100101000011100100",0x0000384F,0xFFFFE562,0x000005E2,0x0000295A,0xFFFFED53,0x000004D3,0x0000295A,0xFFFFED53,0x000004D3},
- {"0000001000010011111100001111110101000010110100000101000100100100",0x00003315,0xFFFFE8D1,0x00000552,0x000025D1,0xFFFFEFAF,0x00000471,0x000025D1,0xFFFFEFAF,0x00000471},
- {"0000001000010011111100001111110101000010110001100100100100100100",0x00004183,0xFFFFDF61,0x000006DA,0x0000193C,0xFFFFF88F,0x000002EC,0x0000193C,0xFFFFF88F,0x000002EC},
- {"0000001000010011111010101001010011011110001001000010000101100100",0x00002DFC,0xFFFFEDF2,0x0000047A,0x00001755,0xFFFFFAC2,0x000002AC,0x00001755,0xFFFFFAC2,0x000002AC},
- {"0000001000010011111100001111110101000010110010100011000110100100",0x000033FE,0xFFFFE774,0x0000059F,0x00001E70,0xFFFFF492,0x000003A0,0x00001E70,0xFFFFF492,0x000003A0},
- {"0000001000010011111100001111110101000010110001100010100110100100",0x000040D7,0xFFFFDFB8,0x000006CE,0x00001AC8,0xFFFFF773,0x0000031D,0x00001AC8,0xFFFFF773,0x0000031D},
- {"0000001000010011111010101001010011011110000111100001000101100100",0x00001D02,0xFFFFF803,0x00000322,0x000015FE,0xFFFFFB71,0x000002BB,0x000015FE,0xFFFFFB71,0x000002BB},
- {"0000001000010011111100001111110101000010110100000010100010000100",0x00002EB0,0xFFFFEC31,0x000004C4,0x00001B3C,0xFFFFF73B,0x00000330,0x00001B3C,0xFFFFF73B,0x00000330},
- {"0000001000010011111100001111110101000010110010100100100110000100",0x00002D9F,0xFFFFECBF,0x000004A8,0x000022B0,0xFFFFF23C,0x000003F9,0x000022B0,0xFFFFF23C,0x000003F9},
- {"0000001000010011111100001111110101000010110011000001100011100100",0x00002C6A,0xFFFFEDAC,0x00000488,0x00002419,0xFFFFF159,0x00000427,0x00002419,0xFFFFF159,0x00000427},
- {"0000001000010011111010101001010011011110000100100001000010100100",0x00002991,0xFFFFF06C,0x0000040E,0x00001AA9,0xFFFFF8D0,0x000002E1,0x00001AA9,0xFFFFF8D0,0x000002E1},
- {"0000001000010011111010101001010011011110000100100011100100000100",0x00002F8E,0xFFFFED1B,0x00000493,0x00001DE4,0xFFFFF69C,0x00000347,0x00001DE4,0xFFFFF69C,0x00000347},
- {"0000001000010011111010101001010011011110001000000100000110000100",0x00002136,0xFFFFF540,0x0000037C,0x000014FF,0xFFFFFB83,0x000002B2,0x000014FF,0xFFFFFB83,0x000002B2},
- {"0000001000010011111010101001010011011110000001100001100011100100",0x0000354C,0xFFFFE97D,0x0000051A,0x00001906,0xFFFFF965,0x000002DD,0x00001906,0xFFFFF965,0x000002DD},
- {"0000001000010011111100001111110101000010110001100010000011000100",0x0000348B,0xFFFFE94D,0x0000051F,0x0000285B,0xFFFFEF1A,0x00000473,0x0000285B,0xFFFFEF1A,0x00000473},
- {"0000001000010011111010101001010011011110001100100001100010100100",0x000026E6,0xFFFFF24E,0x000003D6,0x0000141F,0xFFFFFCCE,0x00000260,0x0000141F,0xFFFFFCCE,0x00000260},
- {"0000001000010011111100001111110101000010110001100100000101100100",0x00003CED,0xFFFFE2A5,0x0000064E,0x00002060,0xFFFFF3E0,0x000003B0,0x00002060,0xFFFFF3E0,0x000003B0},
- {"0000001000010011111010101001010011011110000000100001000010000100",0x000029D4,0xFFFFEFF7,0x00000426,0x00001976,0xFFFFF8E1,0x000002EE,0x00001976,0xFFFFF8E1,0x000002EE},
- {"0000001000010011111100001111110101000010110010100100000010100100",0x00003767,0xFFFFE601,0x000005CC,0x00001D22,0xFFFFF5F4,0x00000361,0x00001D22,0xFFFFF5F4,0x00000361},
- {"0000001000010011111100001111110101000010110001100101000011000100",0x00003CE8,0xFFFFE2E8,0x00000637,0x0000232C,0xFFFFF1E7,0x00000405,0x0000232C,0xFFFFF1E7,0x00000405},
- {"0000001000010011111010101001010011011110001000000001000001100100",0x000023A8,0xFFFFF4CD,0x00000386,0x00001944,0xFFFFF983,0x00000300,0x00001944,0xFFFFF983,0x00000300},
- {"0000001000010011111100001111110101000010110011000011000010100100",0x00003451,0xFFFFE8B9,0x00000551,0x00001AD7,0xFFFFF7BF,0x00000318,0x00001AD7,0xFFFFF7BF,0x00000318},
- {"0000001000010011111100001111110101000010110011100010100110000100",0x0000381B,0xFFFFE5A0,0x000005D0,0x00001E0F,0xFFFFF521,0x00000382,0x00001E0F,0xFFFFF521,0x00000382},
- {"0000001000010011111010101001010011011110001000000011100011000100",0x000023A4,0xFFFFF4A6,0x00000394,0x0000171F,0xFFFFFABB,0x000002D9,0x0000171F,0xFFFFFABB,0x000002D9},
- {"0000001000010011111100001111110101000010110001100010000010100100",0x00003C2B,0xFFFFE447,0x000005F0,0x0000207F,0xFFFFF44E,0x0000039A,0x0000207F,0xFFFFF44E,0x0000039A},
- {"0000001000010011111100001111110101000010110011000011100110000100",0x00002F07,0xFFFFEB70,0x000004E9,0x00001765,0xFFFFF9A5,0x000002C6,0x00001765,0xFFFFF9A5,0x000002C6},
- {"0000001000010011111100001111110101000010110001100010100110000100",0x00003A01,0xFFFFE4E0,0x000005E7,0x0000227A,0xFFFFF292,0x000003E5,0x0000227A,0xFFFFF292,0x000003E5},
- {"0000001000010011111100001111110101000010110011100010000010100100",0x0000376E,0xFFFFE686,0x000005A6,0x00001FCF,0xFFFFF43B,0x000003A8,0x00001FCF,0xFFFFF43B,0x000003A8},
- {"0000001000010011111100001111111111101111010110100100100110000100",0x0000485F,0xFFFFDCC1,0x00000713,0x00002CF8,0xFFFFEC45,0x000004DA,0x00002CF8,0xFFFFEC45,0x000004DA},
- {"0000001000010011111100001111111111101111010111000011000110000100",0x0000331C,0xFFFFE8FF,0x00000541,0x00002366,0xFFFFF19D,0x00000411,0x00002366,0xFFFFF19D,0x00000411},
- {"0000001000010011111100001111111111101111011001000011100001100100",0x00003CF3,0xFFFFE15A,0x00000694,0x00002FB3,0xFFFFE827,0x000005B9,0x00002FB3,0xFFFFE827,0x000005B9},
- {"0000001000010011111010101001010011011110001100100001000100000100",0x000023F3,0xFFFFF3EA,0x0000039A,0x00001345,0xFFFFFD6B,0x00000241,0x00001345,0xFFFFFD6B,0x00000241},
- {"0000001000010011111100001111111111101111010111000010100010100100",0x000038C0,0xFFFFE58A,0x000005CC,0x000023CA,0xFFFFF1AA,0x00000408,0x000023CA,0xFFFFF1AA,0x00000408},
- {"0000001000010011111100001111111111101111011001100010100101000100",0x00004976,0xFFFFDD6A,0x000006D7,0x000033C6,0xFFFFE8EB,0x0000054D,0x000033C6,0xFFFFE8EB,0x0000054D},
- {"0000001000010011111100001111111111101111011001000100100100000100",0x00004049,0xFFFFDF6D,0x000006D8,0x00003129,0xFFFFE716,0x000005E9,0x00003129,0xFFFFE716,0x000005E9},
- {"0000001000010011111100001111111111101111011001100001000101100100",0x000046C2,0xFFFFDCEB,0x0000071C,0x00002E6D,0xFFFFEA8F,0x0000052E,0x00002E6D,0xFFFFEA8F,0x0000052E},
- {"0000001000010011111100001111111111101111011000100011100010100100",0x00004080,0xFFFFE1E1,0x0000063A,0x0000396D,0xFFFFE40A,0x0000062C,0x0000396D,0xFFFFE40A,0x0000062C},
- {"0000001000010011111100001111111111101111010111100010000100100100",0x00003DE0,0xFFFFE358,0x0000060C,0x00002AA2,0xFFFFEDBF,0x000004A0,0x00002AA2,0xFFFFEDBF,0x000004A0},
- {"0000001000010011111100001111111111101111010111100011000101000100",0x00003FC0,0xFFFFE2A1,0x0000061A,0x000027D8,0xFFFFEFEC,0x0000043A,0x000027D8,0xFFFFEFEC,0x0000043A},
- {"0000001000010011111100001111111111101111011001100001100100100100",0x00003FBF,0xFFFFE2F5,0x00000603,0x000032D7,0xFFFFE900,0x00000552,0x000032D7,0xFFFFE900,0x00000552},
- {"0000001000010011111100001111111111101111010111000001000011100100",0x000035EE,0xFFFFE6CA,0x000005A2,0x0000247C,0xFFFFF088,0x00000446,0x0000247C,0xFFFFF088,0x00000446},
- {"0000001000010011111100001111111111101111011001000011100010000100",0x000039C8,0xFFFFE3AE,0x0000062A,0x000028AF,0xFFFFED24,0x000004DF,0x000028AF,0xFFFFED24,0x000004DF},
- {"0000001000010011111100001111111111101111010111000010100010000100",0x00003BDE,0xFFFFE33B,0x00000632,0x00001B6C,0xFFFFF720,0x00000326,0x00001B6C,0xFFFFF720,0x00000326},
- {"0000001000010011111100001111111111101111011100100001000010100100",0x00003818,0xFFFFE57D,0x000005D4,0x000020EF,0xFFFFF327,0x000003CE,0x000020EF,0xFFFFF327,0x000003CE},
- {"0000001000010011111100001111111111101111010111100001100110100100",0x000038DA,0xFFFFE561,0x000005D3,0x0000297D,0xFFFFED6D,0x000004C5,0x0000297D,0xFFFFED6D,0x000004C5},
- {"0000001000010011111100001111111111101111011010000100100010000100",0x000027AC,0xFFFFF0CE,0x00000417,0x00001F5F,0xFFFFF484,0x000003B2,0x00001F5F,0xFFFFF484,0x000003B2},
- {"0000001000010011111100001111111111101111011001100100100010100100",0x00003F02,0xFFFFE222,0x00000643,0x000026D4,0xFFFFF000,0x00000443,0x000026D4,0xFFFFF000,0x00000443},
- {"0000001000010011111100001111111111101111011000100100000101100100",0x00004303,0xFFFFDFE3,0x00000690,0x0000312C,0xFFFFE912,0x00000561,0x0000312C,0xFFFFE912,0x00000561},
- {"0000001000010011111100001111111111101111011000000000100100000100",0x000039E5,0xFFFFE31F,0x00000657,0x00001D23,0xFFFFF51F,0x00000386,0x00001D23,0xFFFFF51F,0x00000386},
- {"0000001000010011111100001111111111101111011001100001000101000100",0x000041FA,0xFFFFE01B,0x00000697,0x00002767,0xFFFFEF90,0x00000455,0x00002767,0xFFFFEF90,0x00000455},
- {"0000001000010011111100001111111111101111011010000011000010100100",0x00002888,0xFFFFF11C,0x00000403,0x00001864,0xFFFFF9D8,0x000002D3,0x00001864,0xFFFFF9D8,0x000002D3},
- {"0000001000010011111010101001010011011110001000000001100001100100",0x0000215C,0xFFFFF5B6,0x0000036D,0x000015C5,0xFFFFFB8A,0x000002B5,0x000015C5,0xFFFFFB8A,0x000002B5},
- {"0000001000010011111100001111111111101111011010000011100110000100",0x00002FAF,0xFFFFEC27,0x000004CA,0x00002184,0xFFFFF39C,0x000003CD,0x00002184,0xFFFFF39C,0x000003CD},
- {"0000001000010011111100001111111111101111010111100001000011000100",0x00004ACE,0xFFFFD9A3,0x000007BC,0x00001A5D,0xFFFFF7F6,0x000002FC,0x00001A5D,0xFFFFF7F6,0x000002FC},
- {"0000001000010011111100001111111111101111010110100011000001000100",0x00003763,0xFFFFE797,0x0000055F,0x000029B5,0xFFFFEEA1,0x00000474,0x000029B5,0xFFFFEEA1,0x00000474},
- {"0000001000010011111100001111111111101111010111100011000101100100",0x00003832,0xFFFFE6F9,0x00000575,0x00002C99,0xFFFFEC42,0x000004E3,0x00002C99,0xFFFFEC42,0x000004E3},
- {"0000001000010011111100001111111111101111011000000100000101100100",0x000041C9,0xFFFFDE33,0x0000071E,0x0000199D,0xFFFFF808,0x000002F9,0x0000199D,0xFFFFF808,0x000002F9},
- {"0000001000010011111100001111111111101111011001000001000101100100",0x0000474A,0xFFFFD96E,0x00000802,0x00002A30,0xFFFFEB57,0x0000053F,0x00002A30,0xFFFFEB57,0x0000053F},
- {"0000001000010011111100001111111111101111010111000011000111000100",0x0000312F,0xFFFFEA6A,0x00000508,0x000029D3,0xFFFFED38,0x000004D3,0x000029D3,0xFFFFED38,0x000004D3},
- {"0000001000010011111100001111111111101111011100100001000011000100",0x00003BD6,0xFFFFE2E7,0x00000644,0x00002093,0xFFFFF37B,0x000003BD,0x00002093,0xFFFFF37B,0x000003BD},
- {"0000001000010011111100001111111111101111011010000100000011100100",0x00002F94,0xFFFFECD4,0x000004A3,0x00002196,0xFFFFF40B,0x000003B5,0x00002196,0xFFFFF40B,0x000003B5},
- {"0000001000010011111100001111111111101111010111100001100101000100",0x0000369B,0xFFFFE762,0x00000571,0x00002726,0xFFFFEF99,0x00000459,0x00002726,0xFFFFEF99,0x00000459},
- {"0000001000010011111100001111111111101111011001000010000001100100",0x00003F57,0xFFFFDF47,0x000006F4,0x00002E5F,0xFFFFE8AE,0x000005AB,0x00002E5F,0xFFFFE8AE,0x000005AB},
- {"0000001000010011111010101001010011011110000010100100000011000100",0x00004313,0xFFFFDD81,0x0000072D,0x00002468,0xFFFFF068,0x00000440,0x00002468,0xFFFFF068,0x00000440},
- {"0000001000010011111100001111111111101111011010000011000001000100",0x00002A35,0xFFFFEFA8,0x00000441,0x00001F3F,0xFFFFF4F3,0x000003A0,0x00001F3F,0xFFFFF4F3,0x000003A0},
- {"0000001000010011111100001111111111101111011001100011000010100100",0x00003E33,0xFFFFE4B0,0x000005AF,0x00002802,0xFFFFF092,0x00000412,0x00002802,0xFFFFF092,0x00000412},
- {"0000001000010011111010101001010011011110001100100011100100000100",0x00002815,0xFFFFF20E,0x000003DD,0x00001C33,0xFFFFF7D5,0x0000032A,0x00001C33,0xFFFFF7D5,0x0000032A},
- {"0000001000010011111100001111111111101111010110100010000110000100",0x00003CC2,0xFFFFE43E,0x000005DE,0x00002C16,0xFFFFECED,0x000004BA,0x00002C16,0xFFFFECED,0x000004BA},
- {"0000001000010011111100001111111111101111010111000100000010000100",0x00003CFA,0xFFFFE1EE,0x00000673,0x00001F7D,0xFFFFF402,0x000003AE,0x00001F7D,0xFFFFF402,0x000003AE},
- {"0000001000010011111100001111111111101111011000100010000100000100",0x0000486E,0xFFFFDD43,0x000006EE,0x000036F0,0xFFFFE609,0x000005D5,0x000036F0,0xFFFFE609,0x000005D5},
- {"0000001000010011111100001111111111101111010111000100100101100100",0x000039FE,0xFFFFE41F,0x00000613,0x0000266C,0xFFFFEF35,0x0000047D,0x0000266C,0xFFFFEF35,0x0000047D},
- {"0000001000010011111010101001010011011110000100100011000100100100",0x00002EA4,0xFFFFEE3B,0x00000462,0x00002126,0xFFFFF4E2,0x0000038F,0x00002126,0xFFFFF4E2,0x0000038F},
- {"0000001000010011111100001111111111101111011010000011100101000100",0x00002D2E,0xFFFFEE7B,0x00000462,0x0000229D,0xFFFFF363,0x000003D4,0x0000229D,0xFFFFF363,0x000003D4},
- {"0000001000010011111100001111111111101111010111100010100001000100",0x0000375C,0xFFFFE695,0x0000059D,0x00002319,0xFFFFF237,0x000003EE,0x00002319,0xFFFFF237,0x000003EE},
- {"0000001000010011111100001111111111101111011100100101000011000100",0x00004522,0xFFFFDC71,0x0000075E,0x0000247E,0xFFFFF0A0,0x0000043C,0x0000247E,0xFFFFF0A0,0x0000043C},
- {"0000001000010011111010101001010011011110000100100100100011100100",0x00002E58,0xFFFFECB9,0x000004A9,0x0000199A,0xFFFFF8CF,0x000002E9,0x0000199A,0xFFFFF8CF,0x000002E9},
- {"0000001000010011111100001111111111101111011001000011100011100100",0x00003791,0xFFFFE5FE,0x000005B6,0x000029F5,0xFFFFED0D,0x000004CD,0x000029F5,0xFFFFED0D,0x000004CD},
- {"0000001000010011111010101001010011011110001001000100000101000100",0x00002E9E,0xFFFFEC8D,0x000004C1,0x000019D0,0xFFFFF869,0x0000030F,0x000019D0,0xFFFFF869,0x0000030F},
- {"0000001000010011111010101001010011011110001000000011100101100100",0x0000237C,0xFFFFF435,0x000003A6,0x000014EB,0xFFFFFBC4,0x000002AF,0x000014EB,0xFFFFFBC4,0x000002AF},
- {"0000001000010011111100001111111111101111011001100010100100100100",0x00003FE5,0xFFFFE4A2,0x000005A0,0x00003416,0xFFFFE995,0x00000523,0x00003416,0xFFFFE995,0x00000523},
- {"0000001000010011111100001111111111101111010111000000100100100100",0x00002B27,0xFFFFED51,0x000004A5,0x000025D1,0xFFFFEF18,0x00000492,0x000025D1,0xFFFFEF18,0x00000492},
- {"0000001000010011111100001111111111101111011010000100100100000100",0x00002D77,0xFFFFED79,0x00000494,0x00002196,0xFFFFF352,0x000003DE,0x00002196,0xFFFFF352,0x000003DE},
- {"0000001000010011111100001111111111101111010111000010000011000100",0x00003750,0xFFFFE6AC,0x00000596,0x00002524,0xFFFFF0B5,0x00000431,0x00002524,0xFFFFF0B5,0x00000431},
- {"0000001000010011111010101001010011011110000100100010100101000100",0x00002896,0xFFFFF1BB,0x000003D9,0x00001CE0,0xFFFFF753,0x0000032F,0x00001CE0,0xFFFFF753,0x0000032F},
- {"0000001000010011111100001111111111101111011001000001100110000100",0x00003CA7,0xFFFFE0F7,0x000006B1,0x00002CB8,0xFFFFE9AB,0x00000587,0x00002CB8,0xFFFFE9AB,0x00000587},
- {"0000001000010011111010101001010011011110001100100010100001100100",0x00002513,0xFFFFF323,0x000003BC,0x00001965,0xFFFFF93C,0x000002F0,0x00001965,0xFFFFF93C,0x000002F0},
- {"0000001000010011111100001111111111101111011001100010000101100100",0x00003914,0xFFFFE683,0x00000586,0x00003120,0xFFFFE9A6,0x00000543,0x00003120,0xFFFFE9A6,0x00000543},
- {"0000001000010011111100001111111111101111011001000011100100000100",0x000040D0,0xFFFFE007,0x000006AC,0x00002B9E,0xFFFFEBF5,0x000004FB,0x00002B9E,0xFFFFEBF5,0x000004FB},
- {"0000001000010011111100001111111111101111010110100100100010000100",0x00004412,0xFFFFDF5F,0x000006A9,0x00002A9E,0xFFFFEDCE,0x00000498,0x00002A9E,0xFFFFEDCE,0x00000498},
- {"0000001000010011111100001111111111101111011000100100100010000100",0x000042A6,0xFFFFDFEF,0x00000696,0x00002E65,0xFFFFEAAE,0x00000529,0x00002E65,0xFFFFEAAE,0x00000529},
- {"0000001000010011111010101001010011011110001100100010000100100100",0x000022E8,0xFFFFF565,0x0000035F,0x00001890,0xFFFFFA61,0x000002C6,0x00001890,0xFFFFFA61,0x000002C6},
- {"0000001000010011111100001111111111101111011000100011100110100100",0x00004637,0xFFFFDDD8,0x000006E9,0x0000349D,0xFFFFE6C8,0x000005C7,0x0000349D,0xFFFFE6C8,0x000005C7},
- {"0000001000010011111010101001010011011110001001100011100100000100",0x00004686,0xFFFFDC58,0x0000073D,0x00003972,0xFFFFE27B,0x0000068E,0x00003972,0xFFFFE27B,0x0000068E},
- {"0000001000010011111100001111111111101111011010000000100011100100",0x00002B35,0xFFFFEE9C,0x0000046C,0x00001F5B,0xFFFFF4A3,0x000003A9,0x00001F5B,0xFFFFF4A3,0x000003A9},
- {"0000001000010011111100001111111111101111011100100100000101000100",0x00003AC9,0xFFFFE3B2,0x0000061B,0x000023A1,0xFFFFF170,0x0000040F,0x000023A1,0xFFFFF170,0x0000040F},
- {"0000001000010011111100001111111111101111010111100001100010000100",0x00003C50,0xFFFFE37E,0x00000617,0x0000218F,0xFFFFF339,0x000003C4,0x0000218F,0xFFFFF339,0x000003C4},
- {"0000001000010011111100001111111111101111011001100011000001000100",0x00003793,0xFFFFE761,0x0000055D,0x000029C7,0xFFFFEE03,0x00000496,0x000029C7,0xFFFFEE03,0x00000496},
- {"0000001000010011111100001111111111101111011001000011100010100100",0x000040B5,0xFFFFDF78,0x000006DA,0x00002DED,0xFFFFEA20,0x00000551,0x00002DED,0xFFFFEA20,0x00000551},
- {"0000001000010011111100001111111111101111011000000001000101000100",0x000039D6,0xFFFFE37D,0x0000063C,0x00001AED,0xFFFFF6E2,0x00000331,0x00001AED,0xFFFFF6E2,0x00000331},
- {"0000001000010011111100001111111111101111011001100010000101000100",0x0000431F,0xFFFFE09B,0x0000066A,0x00002BDF,0xFFFFED93,0x00000496,0x00002BDF,0xFFFFED93,0x00000496},
- {"0000001000010011111100001111111111101111011000100011100001100100",0x00004887,0xFFFFDC65,0x00000721,0x00003669,0xFFFFE5C4,0x000005E9,0x00003669,0xFFFFE5C4,0x000005E9},
- {"0000001000010011111100001111111111101111011001000000100100100100",0x00004120,0xFFFFDDAE,0x00000748,0x0000303B,0xFFFFE70D,0x000005FC,0x0000303B,0xFFFFE70D,0x000005FC},
- {"0000001000010011111100001111111111101111010111100010100010100100",0x0000415D,0xFFFFE0BE,0x0000067B,0x00002FA7,0xFFFFEA28,0x00000538,0x00002FA7,0xFFFFEA28,0x00000538},
- {"0000001000010011111100001111111111101111011010000001100100000100",0x00002B12,0xFFFFEFF9,0x00000428,0x00001DDA,0xFFFFF693,0x00000356,0x00001DDA,0xFFFFF693,0x00000356},
- {"0000001000010011111100001111111111101111010111100011000110000100",0x00003ED3,0xFFFFE28D,0x0000062D,0x00002B00,0xFFFFED4E,0x000004B3,0x00002B00,0xFFFFED4E,0x000004B3},
- {"0000001000010011111100001111111111101111011000100101000010100100",0x00004218,0xFFFFE039,0x0000068F,0x00002F84,0xFFFFEA0C,0x00000541,0x00002F84,0xFFFFEA0C,0x00000541},
- {"0000001000010011111100001111111111101111010110100011100001000100",0x00003FF5,0xFFFFE2A3,0x00000617,0x00003017,0xFFFFEA7A,0x00000520,0x00003017,0xFFFFEA7A,0x00000520},
- {"0000001000010011111100001111111111101111010110100000100010100100",0x00004304,0xFFFFDFCC,0x0000069E,0x00002E0C,0xFFFFEB51,0x00000505,0x00002E0C,0xFFFFEB51,0x00000505},
- {"0000001000010011111100001111111111101111011001000001100101000100",0x00003D3A,0xFFFFE17F,0x00000687,0x0000284C,0xFFFFED83,0x000004CD,0x0000284C,0xFFFFED83,0x000004CD},
- {"0000001000010011111100001111111111101111010111100100000010100100",0x000042F5,0xFFFFDF76,0x000006B2,0x000027B6,0xFFFFEF72,0x00000455,0x000027B6,0xFFFFEF72,0x00000455},
- {"0000001000010011111100001111111111101111010111000011100011000100",0x00004267,0xFFFFDF29,0x000006D5,0x0000298F,0xFFFFEDBD,0x000004AC,0x0000298F,0xFFFFEDBD,0x000004AC},
- {"0000001000010011111010101001010011011110001001000000100100100100",0x0000303E,0xFFFFEC00,0x000004CB,0x000021CD,0xFFFFF36E,0x000003D6,0x000021CD,0xFFFFF36E,0x000003D6},
- {"0000001000010011111100001111111111101111010111100010100011000100",0x00003127,0xFFFFEBDB,0x000004A6,0x00002E95,0xFFFFEB78,0x000004F3,0x00002E95,0xFFFFEB78,0x000004F3},
- {"0000001000010011111010101001010011011110000111000001000001100100",0x00002655,0xFFFFF2D9,0x000003CF,0x000019F5,0xFFFFF8E7,0x00000313,0x000019F5,0xFFFFF8E7,0x00000313},
- {"0000001000010011111010101001010011011110000101100100000010000100",0x00002372,0xFFFFF449,0x0000039B,0x00001544,0xFFFFFC16,0x0000028B,0x00001544,0xFFFFFC16,0x0000028B},
- {"0000001000010011111100001111111111101111011001100010100011000100",0x0000348E,0xFFFFEB20,0x000004B2,0x00002BE8,0xFFFFEE80,0x00000467,0x00002BE8,0xFFFFEE80,0x00000467},
- {"0000001000010011111100001111111111101111010111100001000100000100",0x00004092,0xFFFFE073,0x0000069B,0x00002061,0xFFFFF403,0x000003A0,0x00002061,0xFFFFF403,0x000003A0},
- {"0000001000010011111100001111111111101111011100100010000011100100",0x000039D1,0xFFFFE55D,0x000005CC,0x000025CB,0xFFFFF0C0,0x00000428,0x000025CB,0xFFFFF0C0,0x00000428},
- {"0000001000010011111100001111111111101111010111100100100010000100",0x000042AA,0xFFFFDF68,0x000006C2,0x0000290B,0xFFFFEE78,0x00000485,0x0000290B,0xFFFFEE78,0x00000485},
- {"0000001000010011111100001111111111101111011100100001100011000100",0x0000356F,0xFFFFE7AC,0x0000056E,0x00001BE8,0xFFFFF6E3,0x0000032A,0x00001BE8,0xFFFFF6E3,0x0000032A},
- {"0000001000010011111100001111111111101111010111100001000101000100",0x00003525,0xFFFFE7FF,0x0000055D,0x0000242C,0xFFFFF12E,0x0000041D,0x0000242C,0xFFFFF12E,0x0000041D},
- {"0000001000010011111100001111111111101111010111000100100011000100",0x00003360,0xFFFFE895,0x00000550,0x00002175,0xFFFFF29E,0x000003E9,0x00002175,0xFFFFF29E,0x000003E9},
- {"0000001000010011111100001111111111101111011001000100000010100100",0x00003C94,0xFFFFE1C4,0x0000067E,0x00002E28,0xFFFFE964,0x0000057F,0x00002E28,0xFFFFE964,0x0000057F},
- {"0000001000010011111100001111111111101111011100100100000100100100",0x0000431C,0xFFFFDE4B,0x000006FF,0x00002270,0xFFFFF268,0x000003E5,0x00002270,0xFFFFF268,0x000003E5},
- {"0000001000010011111010101001010011011110000100100001100011000100",0x00002B67,0xFFFFF01D,0x00000414,0x000019FB,0xFFFFF961,0x000002D8,0x000019FB,0xFFFFF961,0x000002D8},
- {"0000001000010011111100001111111111101111010111100011100110000100",0x0000400B,0xFFFFE13D,0x0000066F,0x000024F3,0xFFFFF125,0x00000417,0x000024F3,0xFFFFF125,0x00000417},
- {"0000001000010011111100001111111111101111010110100010000010100100",0x00004460,0xFFFFE00E,0x0000067B,0x000023DF,0xFFFFF2E6,0x000003BB,0x000023DF,0xFFFFF2E6,0x000003BB},
- {"0000001000010011111100001111111111101111011001000001100001100100",0x00003AFB,0xFFFFE2C5,0x00000650,0x00002D46,0xFFFFE9C4,0x00000571,0x00002D46,0xFFFFE9C4,0x00000571},
- {"0000001000010011111100001111111111101111011000100010100100100100",0x00005482,0xFFFFD5BC,0x0000081A,0x00003250,0xFFFFE961,0x00000541,0x00003250,0xFFFFE961,0x00000541},
- {"0000001000010011111100001111111111101111010111000010100101000100",0x00003D27,0xFFFFE2FA,0x00000632,0x00002A4D,0xFFFFED6A,0x000004BB,0x00002A4D,0xFFFFED6A,0x000004BB},
- {"0000001000010011111100001111111111101111011000000001100010100100",0x00003E03,0xFFFFE142,0x00000690,0x00001E08,0xFFFFF555,0x0000036C,0x00001E08,0xFFFFF555,0x0000036C},
- {"0000001000010011111100001111111111101111010111000010000001100100",0x000031B5,0xFFFFE97D,0x00000535,0x0000232E,0xFFFFF166,0x00000422,0x0000232E,0xFFFFF166,0x00000422},
- {"0000001000010011111100001111111111101111010111100001100011100100",0x00003753,0xFFFFE724,0x00000575,0x0000281A,0xFFFFEF1A,0x0000046B,0x0000281A,0xFFFFEF1A,0x0000046B},
- {"0000001000010011111010101001010011011110001000000100000101000100",0x00002071,0xFFFFF5C9,0x0000036F,0x00001470,0xFFFFFBF7,0x000002A5,0x00001470,0xFFFFFBF7,0x000002A5},
- {"0000001000010011111100001111111111101111011010000011000101000100",0x00002799,0xFFFFF223,0x000003CF,0x00001CD3,0xFFFFF74A,0x00000333,0x00001CD3,0xFFFFF74A,0x00000333},
- {"0000001000010011111100001111111111101111011001100001000011000100",0x000040DF,0xFFFFE11C,0x00000664,0x000031D4,0xFFFFE8BC,0x0000056F,0x000031D4,0xFFFFE8BC,0x0000056F},
- {"0000001000010011111100001111111111101111011001000100000011000100",0x00003A4D,0xFFFFE3A6,0x00000627,0x00002871,0xFFFFEDA0,0x000004C0,0x00002871,0xFFFFEDA0,0x000004C0},
- {"0000001000010011111100001111111111101111011010000001100110000100",0x00002AF9,0xFFFFEED7,0x00000464,0x0000219B,0xFFFFF368,0x000003D6,0x0000219B,0xFFFFF368,0x000003D6},
- {"0000001000010011111010101001010011011110001100100011000100100100",0x000026D5,0xFFFFF36C,0x000003A3,0x00001BC6,0xFFFFF881,0x00000311,0x00001BC6,0xFFFFF881,0x00000311},
- {"0000001000010011111100001111111111101111010111100010000001000100",0x0000325D,0xFFFFEA07,0x0000050B,0x000026D1,0xFFFFEFB3,0x0000045A,0x000026D1,0xFFFFEFB3,0x0000045A},
- {"0000001000010011111100001111111111101111011010000010100001100100",0x00002F75,0xFFFFEC64,0x000004BE,0x00001EEB,0xFFFFF559,0x00000386,0x00001EEB,0xFFFFF559,0x00000386},
- {"0000001000010011111100001111111111101111010110100011100010100100",0x00003C2F,0xFFFFE541,0x000005A3,0x000025B6,0xFFFFF16F,0x000003FA,0x000025B6,0xFFFFF16F,0x000003FA},
- {"0000001000010011111100001111111111101111011010000100100100100100",0x00002BC2,0xFFFFEE89,0x0000046A,0x00001D04,0xFFFFF651,0x00000361,0x00001D04,0xFFFFF651,0x00000361},
- {"0000001000010011111100001111111111101111011010000010100110100100",0x00002DD0,0xFFFFED40,0x0000049F,0x00001C8C,0xFFFFF6B3,0x00000353,0x00001C8C,0xFFFFF6B3,0x00000353},
- {"0000001000010011111010101001010011011110000111000000100011100100",0x000021ED,0xFFFFF530,0x00000380,0x00001643,0xFFFFFB1C,0x000002C3,0x00001643,0xFFFFFB1C,0x000002C3},
- {"0000001000010011111010101001010011011110001100100001100100000100",0x000028C7,0xFFFFF160,0x000003FD,0x00001990,0xFFFFF994,0x000002E2,0x00001990,0xFFFFF994,0x000002E2},
- {"0000001000010011111100001111111111101111011001100001000010100100",0x0000431C,0xFFFFDF9D,0x000006A3,0x000034A6,0xFFFFE6B0,0x000005C9,0x000034A6,0xFFFFE6B0,0x000005C9},
- {"0000001000010011111010101001010011011110001001100011000010100100",0x00004115,0xFFFFE0D6,0x00000667,0x000031AD,0xFFFFE850,0x00000585,0x000031AD,0xFFFFE850,0x00000585},
- {"0000001000010011111100001111111111101111011001000011100100100100",0x0000424A,0xFFFFDEEC,0x000006E1,0x0000346A,0xFFFFE5EA,0x00000602,0x0000346A,0xFFFFE5EA,0x00000602},
- {"0000001000010011111100001111111111101111011001100001100110000100",0x00004990,0xFFFFDAFA,0x00000771,0x00002A9C,0xFFFFED37,0x000004BC,0x00002A9C,0xFFFFED37,0x000004BC},
- {"0000001000010011111100001111111111101111011001000010100010100100",0x00003858,0xFFFFE568,0x000005D2,0x00003030,0xFFFFE8B0,0x0000058E,0x00003030,0xFFFFE8B0,0x0000058E},
- {"0000001000010011111100001111111111101111011010000100000101100100",0x00001EDC,0xFFFFF6CD,0x00000322,0x00001FCA,0xFFFFF4BD,0x0000039E,0x00001FCA,0xFFFFF4BD,0x0000039E},
- {"0000001000010011111100001111111111101111011001100010000100100100",0x00004C88,0xFFFFDBA3,0x0000071B,0x000030C4,0xFFFFEAFD,0x000004F7,0x000030C4,0xFFFFEAFD,0x000004F7},
- {"0000001000010011111100001111111111101111011010000000100100000100",0x00002B9A,0xFFFFEE41,0x0000047D,0x00002131,0xFFFFF344,0x000003E5,0x00002131,0xFFFFF344,0x000003E5},
- {"0000001000010011111100001111111111101111011000100011100110000100",0x00003E4B,0xFFFFE33C,0x000005FA,0x00003877,0xFFFFE437,0x0000062E,0x00003877,0xFFFFE437,0x0000062E},
- {"0000001000010011111010101001010011011110001100100010000001100100",0x00002376,0xFFFFF444,0x0000038A,0x000017ED,0xFFFFFA4C,0x000002C1,0x000017ED,0xFFFFFA4C,0x000002C1},
- {"0000001000010011111100001111111111101111011001100001000010000100",0x00004517,0xFFFFDDF4,0x000006F2,0x000030DC,0xFFFFE8EF,0x00000571,0x000030DC,0xFFFFE8EF,0x00000571},
- {"0000001000010011111100001111111111101111011010000001100101000100",0x0000270C,0xFFFFF1F3,0x000003DF,0x0000207B,0xFFFFF474,0x000003AD,0x0000207B,0xFFFFF474,0x000003AD},
- {"0000001000010011111100001111111111101111011001000101000101000100",0x00004086,0xFFFFDF39,0x000006E3,0x00002A24,0xFFFFEC2B,0x000004FF,0x00002A24,0xFFFFEC2B,0x000004FF},
- {"0000001000010011111100001111111111101111010111000011000100100100",0x00003BDE,0xFFFFE45E,0x000005EB,0x00002CD5,0xFFFFEC45,0x000004DD,0x00002CD5,0xFFFFEC45,0x000004DD},
- {"0000001000010011111100001111111111101111011100100011000011100100",0x00003803,0xFFFFE714,0x00000579,0x0000288A,0xFFFFEF21,0x0000046B,0x0000288A,0xFFFFEF21,0x0000046B},
- {"0000001000010011111100001111111111101111011000000001000100000100",0x00003F50,0xFFFFE002,0x000006CD,0x00001AD4,0xFFFFF72E,0x0000031F,0x00001AD4,0xFFFFF72E,0x0000031F},
- {"0000001000010011111100001111111111101111011010000010000011100100",0x00002968,0xFFFFF100,0x00000402,0x00001FB5,0xFFFFF57C,0x0000037F,0x00001FB5,0xFFFFF57C,0x0000037F},
- {"0000001000010011111100001111111111101111011001100010000100000100",0x00004283,0xFFFFE2A7,0x000005F5,0x00003165,0xFFFFEB0C,0x000004EC,0x00003165,0xFFFFEB0C,0x000004EC},
- {"0000001000010011111100001111111111101111011001000011000110100100",0x00004253,0xFFFFDDA8,0x00000732,0x00002E5C,0xFFFFE90A,0x00000593,0x00002E5C,0xFFFFE90A,0x00000593},
- {"0000001000010011111100001111111111101111010111000101000010100100",0x00003551,0xFFFFE756,0x0000058D,0x000029A7,0xFFFFED0C,0x000004DE,0x000029A7,0xFFFFED0C,0x000004DE},
- {"0000001000010011111100001111111111101111011001000010100011000100",0x00003728,0xFFFFE604,0x000005C4,0x00002832,0xFFFFEE64,0x00000493,0x00002832,0xFFFFEE64,0x00000493},
- {"0000001000010011111100001111111111101111011000100011100101100100",0x00004796,0xFFFFDCC8,0x00000715,0x000032AB,0xFFFFE848,0x0000057C,0x000032AB,0xFFFFE848,0x0000057C},
- {"0000001000010011111100001111111111101111011000100001000011000100",0x000049DF,0xFFFFDB24,0x0000075F,0x00003076,0xFFFFE967,0x0000055C,0x00003076,0xFFFFE967,0x0000055C},
- {"0000001000010011111100001111111111101111011100100001000100000100",0x00003F13,0xFFFFE099,0x000006A8,0x00002279,0xFFFFF226,0x000003F3,0x00002279,0xFFFFF226,0x000003F3},
- {"0000001000010011111100001111111111101111011001000011000010100100",0x00003E03,0xFFFFE19F,0x00000674,0x00002D66,0xFFFFEAA7,0x00000537,0x00002D66,0xFFFFEAA7,0x00000537},
- {"0000001000010011111100001111111111101111010111000100000100000100",0x000037DA,0xFFFFE63F,0x000005A7,0x00002543,0xFFFFF0A0,0x00000431,0x00002543,0xFFFFF0A0,0x00000431},
- {"0000001000010011111100001111111111101111011000100100100101000100",0x00003D82,0xFFFFE3F5,0x000005D9,0x0000332F,0xFFFFE834,0x00000577,0x0000332F,0xFFFFE834,0x00000577},
- {"0000001000010011111010101001010011011110000100100010100011000100",0x00002915,0xFFFFF1E0,0x000003D4,0x00002065,0xFFFFF57B,0x00000378,0x00002065,0xFFFFF57B,0x00000378},
- {"0000001000010011111100001111111111101111010111100100100100000100",0x000036FC,0xFFFFE72D,0x00000577,0x00002811,0xFFFFEF30,0x00000464,0x00002811,0xFFFFEF30,0x00000464},
- {"0000001000010011111100001111111111101111011000100011000110000100",0x00004767,0xFFFFDD30,0x000006FD,0x00003703,0xFFFFE564,0x000005F8,0x00003703,0xFFFFE564,0x000005F8},
- {"0000001000010011111100001111111111101111011000000011000110000100",0x00003094,0xFFFFEAA9,0x000004F5,0x000022E7,0xFFFFF200,0x000003FB,0x000022E7,0xFFFFF200,0x000003FB},
- {"0000001000010011111100001111111111101111011001000001000101000100",0x00003EF0,0xFFFFDF83,0x000006ED,0x00002A27,0xFFFFEB7C,0x00000537,0x00002A27,0xFFFFEB7C,0x00000537},
- {"0000001000010011111100001111111111101111011010000001000100100100",0x0000243C,0xFFFFF358,0x000003AC,0x00001DC4,0xFFFFF5E9,0x00000372,0x00001DC4,0xFFFFF5E9,0x00000372},
- {"0000001000010011111100001111111111101111011100100010000101000100",0x0000284B,0xFFFFF036,0x0000040F,0x00001FCD,0xFFFFF445,0x00000395,0x00001FCD,0xFFFFF445,0x00000395},
- {"0000001000010011111100001111111111101111011010000100000011000100",0x00002611,0xFFFFF285,0x000003C7,0x00001CFE,0xFFFFF6A0,0x00000355,0x00001CFE,0xFFFFF6A0,0x00000355},
- {"0000001000010011111010101001010011011110000111000011100110100100",0x00002292,0xFFFFF49F,0x00000393,0x000017F4,0xFFFFF9CD,0x000002F5,0x000017F4,0xFFFFF9CD,0x000002F5},
- {"0000001000010011111100001111111111101111010111100011100010100100",0x000037F3,0xFFFFE68D,0x00000590,0x00002443,0xFFFFF1AD,0x000003FA,0x00002443,0xFFFFF1AD,0x000003FA},
- {"0000001000010011111100001111111111101111011010000010000101000100",0x00002C01,0xFFFFEF3F,0x00000444,0x0000210A,0xFFFFF475,0x000003A7,0x0000210A,0xFFFFF475,0x000003A7},
- {"0000001000010011111010101001010011011110000100100001000011100100",0x00002C0E,0xFFFFEF0F,0x00000446,0x00001A82,0xFFFFF8F7,0x000002DE,0x00001A82,0xFFFFF8F7,0x000002DE},
- {"0000001000010011111100001111111111101111010111100010000011000100",0x00003FA6,0xFFFFE20A,0x0000063F,0x00002E29,0xFFFFEB21,0x00000510,0x00002E29,0xFFFFEB21,0x00000510},
- {"0000001000010011111100001111111111101111010111000010000101100100",0x00003BCD,0xFFFFE31B,0x0000063C,0x000019AF,0xFFFFF83D,0x000002F8,0x000019AF,0xFFFFF83D,0x000002F8},
- {"0000001000010011111100001111111111101111011001100100000101100100",0x000044C8,0xFFFFDF08,0x000006B0,0x00002E2E,0xFFFFEB62,0x000004FD,0x00002E2E,0xFFFFEB62,0x000004FD},
- {"0000001000010011111100001111111111101111010111000001100010000100",0x00003790,0xFFFFE571,0x000005E3,0x00002042,0xFFFFF35D,0x000003CF,0x00002042,0xFFFFF35D,0x000003CF},
- {"0000001000010011111100001111111111101111011000000101000011100100",0x000038AC,0xFFFFE46C,0x00000609,0x0000215E,0xFFFFF22D,0x00000403,0x0000215E,0xFFFFF22D,0x00000403},
- {"0000001000010011111100001111111111101111010111100010100110100100",0x00003A1E,0xFFFFE536,0x000005C9,0x000024F3,0xFFFFF11A,0x0000041B,0x000024F3,0xFFFFF11A,0x0000041B},
- {"0000001000010011111100001111111111101111011001100101000011100100",0x0000431A,0xFFFFDF1B,0x000006C5,0x00002F34,0xFFFFEA02,0x00000545,0x00002F34,0xFFFFEA02,0x00000545},
- {"0000001000010011111100001111111111101111011001000001100100000100",0x000042DC,0xFFFFDE28,0x0000070C,0x00003B53,0xFFFFE0EA,0x000006E2,0x00003B53,0xFFFFE0EA,0x000006E2},
- {"0000001000010011111100001111111111101111011010000011000101100100",0x0000264B,0xFFFFF29A,0x000003C4,0x000021D0,0xFFFFF3CE,0x000003C4,0x000021D0,0xFFFFF3CE,0x000003C4},
- {"0000001000010011111100001111111111101111010110100100000001100100",0x00004225,0xFFFFE0E8,0x00000665,0x00002B53,0xFFFFED89,0x0000049F,0x00002B53,0xFFFFED89,0x0000049F},
- {"0000001000010011111010101001010011011110001000000100100100100100",0x00001FCC,0xFFFFF63F,0x00000358,0x000019E8,0xFFFFF882,0x0000032A,0x000019E8,0xFFFFF882,0x0000032A},
- {"0000001000010011111100001111111111101111011000100100000010100100",0x000045E0,0xFFFFDDD0,0x000006ED,0x00003193,0xFFFFE8BD,0x00000572,0x00003193,0xFFFFE8BD,0x00000572},
- {"0000001000010011111100001111111111101111011010000011100100100100",0x000024FC,0xFFFFF366,0x000003A6,0x00001FE8,0xFFFFF509,0x00000394,0x00001FE8,0xFFFFF509,0x00000394},
- {"0000001000010011111100001111111111101111010111000100100010000100",0x0000378F,0xFFFFE54B,0x000005F1,0x00001C9B,0xFFFFF5C7,0x00000368,0x00001C9B,0xFFFFF5C7,0x00000368},
- {"0000001000010011111100001111111111101111011001000001100010100100",0x00003CF3,0xFFFFE15A,0x00000694,0x00002CDD,0xFFFFEA44,0x00000557,0x00002CDD,0xFFFFEA44,0x00000557},
- {"0000001000010011111010101001010011011110001000000000100100000100",0x000021EC,0xFFFFF4F4,0x0000038F,0x00001511,0xFFFFFBF5,0x0000029E,0x00001511,0xFFFFFBF5,0x0000029E},
- {"0000001000010011111100001111111111101111011000000001000010100100",0x00003C8A,0xFFFFE1C1,0x00000685,0x000019C7,0xFFFFF7E2,0x00000301,0x000019C7,0xFFFFF7E2,0x00000301},
- {"0000001000010011111100001111111111101111010111100010000001100100",0x00003908,0xFFFFE5C7,0x000005B3,0x00002793,0xFFFFEF46,0x00000465,0x00002793,0xFFFFEF46,0x00000465},
- {"0000001000010011111100001111111111101111011000000101000100000100",0x000040A3,0xFFFFDE61,0x00000725,0x00002077,0xFFFFF2CE,0x000003E8,0x00002077,0xFFFFF2CE,0x000003E8},
- {"0000001000010011111100001111111111101111011001100100000101000100",0x00003DCA,0xFFFFE34D,0x00000608,0x00002D66,0xFFFFEBDF,0x000004E8,0x00002D66,0xFFFFEBDF,0x000004E8},
- {"0000001000010011111100001111111111101111010111100101000011000100",0x00003085,0xFFFFEB70,0x000004C8,0x000029B1,0xFFFFEDD9,0x000004A5,0x000029B1,0xFFFFEDD9,0x000004A5},
- {"0000001000010011111010101001010011011110000010000011100010000100",0x00004C73,0xFFFFD676,0x0000086C,0x0000280A,0xFFFFED89,0x000004C2,0x0000280A,0xFFFFED89,0x000004C2},
- {"0000001000010011111010101001010011011110001001000010000101100100",0x00002CE5,0xFFFFEE8C,0x00000466,0x00001755,0xFFFFFAC2,0x000002AC,0x00001755,0xFFFFFAC2,0x000002AC},
- {"0000001000010011111100001111111111101111011000100001000100100100",0x0000489F,0xFFFFDBF1,0x0000073E,0x0000332D,0xFFFFE786,0x000005AD,0x0000332D,0xFFFFE786,0x000005AD},
- {"0000001000010011111100001111111111101111011000000010100001100100",0x00003D09,0xFFFFE193,0x00000689,0x00001E82,0xFFFFF4C0,0x00000386,0x00001E82,0xFFFFF4C0,0x00000386},
- {"0000001000010011111100001111111111101111011001000100000100000100",0x00003E4C,0xFFFFE131,0x00000689,0x00002F4E,0xFFFFE925,0x0000057B,0x00002F4E,0xFFFFE925,0x0000057B},
- {"0000001000010011111100001111111111101111010110100100000010000100",0x00003B31,0xFFFFE53F,0x000005B3,0x0000248A,0xFFFFF211,0x000003DF,0x0000248A,0xFFFFF211,0x000003DF},
- {"0000001000010011111100001111111111101111011001000100000100100100",0x000038DD,0xFFFFE54A,0x000005C9,0x00002B6D,0xFFFFEBDF,0x00000502,0x00002B6D,0xFFFFEBDF,0x00000502},
- {"0000001000010011111100001111111111101111011010000100000001100100",0x00002698,0xFFFFF1A8,0x000003F2,0x00002163,0xFFFFF34B,0x000003E3,0x00002163,0xFFFFF34B,0x000003E3},
- {"0000001000010011111010101001010011011110001000000001000001100100",0x000023A8,0xFFFFF4CD,0x00000386,0x00001944,0xFFFFF983,0x00000300,0x00001944,0xFFFFF983,0x00000300},
- {"0000001000010011111100001111111111101111011001000001100011000100",0x00003EAF,0xFFFFE0C3,0x000006A0,0x000030AB,0xFFFFE829,0x000005A6,0x000030AB,0xFFFFE829,0x000005A6},
- {"0000001000010011111100001111111111101111011010000100100101000100",0x00002E89,0xFFFFECA6,0x000004B6,0x00001FA0,0xFFFFF4A8,0x000003A3,0x00001FA0,0xFFFFF4A8,0x000003A3},
- {"0000001000010011111100001111111111101111011010000010100010100100",0x000028A4,0xFFFFF112,0x00000402,0x00001F7C,0xFFFFF545,0x0000038A,0x00001F7C,0xFFFFF545,0x0000038A},
- {"0000001000010011111100001111111111101111011001100101000010100100",0x00004135,0xFFFFDFA2,0x000006C5,0x0000324C,0xFFFFE7AA,0x000005AF,0x0000324C,0xFFFFE7AA,0x000005AF},
- {"0000001000010011111010101001010011011110001000000011100011000100",0x00002012,0xFFFFF693,0x00000352,0x0000171F,0xFFFFFABB,0x000002D9,0x0000171F,0xFFFFFABB,0x000002D9},
- {"0000001000010011111100001111111111101111011001000011000010000100",0x00003D7C,0xFFFFE1BC,0x00000671,0x00002A45,0xFFFFEC84,0x000004EC,0x00002A45,0xFFFFEC84,0x000004EC},
- {"0000001000010011111100001111111111101111011100100011000001100100",0x00004172,0xFFFFDF58,0x000006DA,0x00002504,0xFFFFF0A6,0x00000431,0x00002504,0xFFFFF0A6,0x00000431},
- {"0000001000010011111100001111111010011001001010000001100101000100",0x000029C7,0xFFFFF087,0x00000414,0x00001DCB,0xFFFFF675,0x0000035F,0x00001DCB,0xFFFFF675,0x0000035F},
- {"0000001000010011111100001111111010011001001010100010100110100100",0x000027F0,0xFFFFF05A,0x00000432,0x00001707,0xFFFFFA0E,0x000002D1,0x00001707,0xFFFFFA0E,0x000002D1},
- {"0000001000010011111100001111111010011001001000100010000101000100",0x00003279,0xFFFFE9F7,0x00000511,0x00001B5E,0xFFFFF787,0x00000317,0x00001B5E,0xFFFFF787,0x00000317},
- {"0000001000010011111100001111111010011001001100100010000110000100",0x000030A5,0xFFFFEABC,0x000004FF,0x000019D1,0xFFFFF83C,0x00000304,0x000019D1,0xFFFFF83C,0x00000304},
- {"0000001000010011111100001111111010011001001010000010100001000100",0x0000283B,0xFFFFF122,0x00000402,0x000019C2,0xFFFFF8E9,0x000002FB,0x000019C2,0xFFFFF8E9,0x000002FB},
- {"0000001000010011111100001111111010011001001011000010000010000100",0x00003376,0xFFFFE9E1,0x00000510,0x000021A7,0xFFFFF39F,0x000003BF,0x000021A7,0xFFFFF39F,0x000003BF},
- {"0000001000010011111100001111111010011001001100100001100011000100",0x000031D2,0xFFFFEA9C,0x000004FC,0x00001F66,0xFFFFF4E4,0x00000390,0x00001F66,0xFFFFF4E4,0x00000390},
- {"0000001000010011111100001111111010011001000110100011100001100100",0x00003006,0xFFFFEB18,0x000004F2,0x000019B3,0xFFFFF84E,0x00000301,0x000019B3,0xFFFFF84E,0x00000301},
- {"0000001000010011111100001111111010011001001100000011100110100100",0x0000364F,0xFFFFE81F,0x00000556,0x00002AC9,0xFFFFED87,0x000004BD,0x00002AC9,0xFFFFED87,0x000004BD},
- {"0000001000010011111100001111111010011001001011100011100001000100",0x00003043,0xFFFFEBAE,0x000004CD,0x00001B0C,0xFFFFF7ED,0x0000030C,0x00001B0C,0xFFFFF7ED,0x0000030C},
- {"0000001000010011111100001111111010011001001100000100100010100100",0x000037CE,0xFFFFE69E,0x00000596,0x0000276B,0xFFFFEF65,0x0000046E,0x0000276B,0xFFFFEF65,0x0000046E},
- {"0000001000010011111100001111111010011001001011000011000100000100",0x00003063,0xFFFFED5E,0x0000046F,0x000024AE,0xFFFFF2C4,0x000003D8,0x000024AE,0xFFFFF2C4,0x000003D8},
- {"0000001000010011111100001111111010011001001011100000100010100100",0x00002F5D,0xFFFFEBDC,0x000004D3,0x00001EDB,0xFFFFF50F,0x0000038E,0x00001EDB,0xFFFFF50F,0x0000038E},
- {"0000001000010011111100001111111010011001001011100100100010100100",0x00003148,0xFFFFEA9A,0x000004FB,0x0000192D,0xFFFFF8E9,0x000002DF,0x0000192D,0xFFFFF8E9,0x000002DF},
- {"0000001000010011111100001111111010011001001011000010000001100100",0x00003682,0xFFFFE7E4,0x0000055C,0x0000250E,0xFFFFF150,0x0000041A,0x0000250E,0xFFFFF150,0x0000041A},
- {"0000001000010011111100001111111010011001001010100010000010000100",0x0000284E,0xFFFFF15A,0x000003F8,0x00001CE2,0xFFFFF6F9,0x0000034F,0x00001CE2,0xFFFFF6F9,0x0000034F},
- {"0000001000010011111100001111111010011001001100000001100010100100",0x00003171,0xFFFFEAE9,0x000004ED,0x00001F40,0xFFFFF513,0x00000384,0x00001F40,0xFFFFF513,0x00000384},
- {"0000001000010011111100001111111010011001001100100011000001000100",0x000031BD,0xFFFFEA64,0x0000050A,0x00001EFD,0xFFFFF4F7,0x00000390,0x00001EFD,0xFFFFF4F7,0x00000390},
- {"0000001000010011111100001111111010011001001011100101000011100100",0x00003050,0xFFFFEB29,0x000004EA,0x000019B3,0xFFFFF878,0x000002F9,0x000019B3,0xFFFFF878,0x000002F9},
- {"0000001000010011111100001111111010011001001011000001100100000100",0x00003400,0xFFFFE9A0,0x0000051A,0x00002460,0xFFFFF1DA,0x00000409,0x00002460,0xFFFFF1DA,0x00000409},
- {"0000001000010011111100001111111010011001001011000100100010000100",0x000034A1,0xFFFFE86F,0x00000558,0x0000255D,0xFFFFF09E,0x00000443,0x0000255D,0xFFFFF09E,0x00000443},
- {"0000001000010011111100001111111010011001001011100100100011100100",0x00003103,0xFFFFEAD7,0x000004F0,0x00001896,0xFFFFF95A,0x000002CC,0x00001896,0xFFFFF95A,0x000002CC},
- {"0000001000010011111100001111111010011001001100000001100011100100",0x00003120,0xFFFFEB9E,0x000004CB,0x000021E8,0xFFFFF3A2,0x000003C1,0x000021E8,0xFFFFF3A2,0x000003C1},
- {"0000001000010011111100001111111010011001000111000101000011100100",0x00003558,0xFFFFE812,0x00000565,0x0000256E,0xFFFFF097,0x00000447,0x0000256E,0xFFFFF097,0x00000447},
- {"0000001000010011111100001111111010011001000110100010100001000100",0x00002DA8,0xFFFFECA8,0x000004B7,0x0000180B,0xFFFFF96D,0x000002D8,0x0000180B,0xFFFFF96D,0x000002D8},
- {"0000001000010011111100001111111010011001001011100011000001100100",0x00003232,0xFFFFEA66,0x000004FF,0x00001DDE,0xFFFFF5FE,0x0000035A,0x00001DDE,0xFFFFF5FE,0x0000035A},
- {"0000001000010011111100001111111010011001001100000101000011100100",0x000034D2,0xFFFFE89F,0x00000548,0x0000246C,0xFFFFF17F,0x00000418,0x0000246C,0xFFFFF17F,0x00000418},
- {"0000001000010011111100001111111010011001001100000100100100000100",0x000033EC,0xFFFFE954,0x0000052A,0x00002323,0xFFFFF279,0x000003EE,0x00002323,0xFFFFF279,0x000003EE},
- {"0000001000010011111100001111111010011001001100000011100010000100",0x000033AA,0xFFFFE955,0x0000052D,0x0000229F,0xFFFFF2B2,0x000003E7,0x0000229F,0xFFFFF2B2,0x000003E7},
- {"0000001000010011111100001111111010011001001100100100100101100100",0x00003258,0xFFFFE9AA,0x0000052A,0x00001D5F,0xFFFFF5D1,0x0000036B,0x00001D5F,0xFFFFF5D1,0x0000036B},
- {"0000001000010011111100001111111010011001001100000010100110100100",0x0000323A,0xFFFFEA5F,0x00000504,0x00002108,0xFFFFF3D5,0x000003BA,0x00002108,0xFFFFF3D5,0x000003BA},
- {"0000001000010011111100001111111010011001001011000010000110000100",0x00003216,0xFFFFEA6B,0x000004FF,0x00001D6E,0xFFFFF640,0x00000350,0x00001D6E,0xFFFFF640,0x00000350},
- {"0000001000010011111100001111111010011001001100100001000011100100",0x000030C5,0xFFFFEAC4,0x000004FC,0x00001924,0xFFFFF8C2,0x000002EE,0x00001924,0xFFFFF8C2,0x000002EE},
- {"0000001000010011111100001111111010011001001100000101000100000100",0x000032BB,0xFFFFE9F1,0x00000515,0x00002211,0xFFFFF31B,0x000003D5,0x00002211,0xFFFFF31B,0x000003D5},
- {"0000001000010011111100001111111010011001001100000100100011000100",0x0000352C,0xFFFFE85B,0x00000553,0x00002410,0xFFFFF1B4,0x0000040F,0x00002410,0xFFFFF1B4,0x0000040F},
- {"0000001000010011111100001111111010011001001000100011100011000100",0x000036A0,0xFFFFE7E8,0x0000055D,0x00002901,0xFFFFEEB8,0x00000489,0x00002901,0xFFFFEEB8,0x00000489},
- {"0000001000010011111100001111111010011001001011000011000001000100",0x00003340,0xFFFFE9D9,0x00000516,0x00002332,0xFFFFF27A,0x000003F0,0x00002332,0xFFFFF27A,0x000003F0},
- {"0000001000010011111100001111111010011001000110100011100010100100",0x00003564,0xFFFFE86D,0x0000054E,0x00002613,0xFFFFF07C,0x00000444,0x00002613,0xFFFFF07C,0x00000444},
- {"0000001000010011111100001111111010011001001010000000100100000100",0x00002AD1,0xFFFFEF0B,0x0000045C,0x00001DEA,0xFFFFF5C8,0x00000381,0x00001DEA,0xFFFFF5C8,0x00000381},
- {"0000001000010011111100001111111010011001001000100010000011100100",0x000035B0,0xFFFFE846,0x00000555,0x000027BE,0xFFFFEF5D,0x00000474,0x000027BE,0xFFFFEF5D,0x00000474},
- {"0000001000010011111100001111111010011001001000100011100010100100",0x000032C4,0xFFFFEA48,0x00000502,0x000022C6,0xFFFFF2DF,0x000003DE,0x000022C6,0xFFFFF2DF,0x000003DE},
- {"0000001000010011111100001111111010011001001100000000100011000100",0x00003036,0xFFFFEB0D,0x000004F9,0x00001FE8,0xFFFFF41A,0x000003BC,0x00001FE8,0xFFFFF41A,0x000003BC},
- {"0000001000010011111100001111111010011001000110100000100100000100",0x000030F8,0xFFFFEA13,0x00000524,0x00001B6A,0xFFFFF6C9,0x0000034A,0x00001B6A,0xFFFFF6C9,0x0000034A},
- {"0000001000010011111100001111111010011001001100000001000010100100",0x00002EE2,0xFFFFEC0C,0x000004CB,0x00001A39,0xFFFFF814,0x0000030F,0x00001A39,0xFFFFF814,0x0000030F},
- {"0000001000010011111100001111111010011001000111000011000110000100",0x00003457,0xFFFFE924,0x0000052A,0x00001E9D,0xFFFFF59C,0x00000363,0x00001E9D,0xFFFFF59C,0x00000363},
- {"0000001000010011111100001111111010011001001100100010100001000100",0x000030BF,0xFFFFEB18,0x000004ED,0x00001D37,0xFFFFF636,0x0000035C,0x00001D37,0xFFFFF636,0x0000035C},
- {"0000001000010011111100001111111010011001001011100100000010000100",0x000031AF,0xFFFFEA75,0x000004FE,0x000019F2,0xFFFFF87A,0x000002F0,0x000019F2,0xFFFFF87A,0x000002F0},
- {"0000001000010011111100001111111010011001001100000010100010000100",0x00003642,0xFFFFE85B,0x00000547,0x00002975,0xFFFFEE98,0x0000048B,0x00002975,0xFFFFEE98,0x0000048B},
- {"0000001000010011111100001111111010011001001011100010100010000100",0x00002E8B,0xFFFFED1E,0x0000048E,0x000019C1,0xFFFFF917,0x000002D6,0x000019C1,0xFFFFF917,0x000002D6},
- {"0000001000010011111100001111111010011001001100100100000110100100",0x000033D9,0xFFFFE8E1,0x00000548,0x0000224B,0xFFFFF298,0x000003F4,0x0000224B,0xFFFFF298,0x000003F4},
- {"0000001000010011111100001111111010011001001011100010100011000100",0x000032BC,0xFFFFEB0F,0x000004D6,0x00002488,0xFFFFF240,0x000003F2,0x00002488,0xFFFFF240,0x000003F2},
- {"0000001000010011111100001111111010011001001100000100100101000100",0x000035FD,0xFFFFE838,0x00000553,0x00002762,0xFFFFEFBC,0x00000460,0x00002762,0xFFFFEFBC,0x00000460},
- {"0000001000010011111100001111111010011001001010000001100010100100",0x0000268B,0xFFFFF263,0x000003D1,0x00001914,0xFFFFF977,0x000002E8,0x00001914,0xFFFFF977,0x000002E8},
- {"0000001000010011111100001111111010011001001011000011000110000100",0x0000330B,0xFFFFEA1E,0x00000505,0x000020B1,0xFFFFF44D,0x0000039E,0x000020B1,0xFFFFF44D,0x0000039E},
- {"0000001000010011111100001111111010011001001000100010000010000100",0x0000326E,0xFFFFEA26,0x00000508,0x00001C17,0xFFFFF722,0x00000328,0x00001C17,0xFFFFF722,0x00000328},
- {"0000001000010011111100001111111010011001001010100011000110100100",0x00002A3F,0xFFFFEEE8,0x0000046D,0x00001B2B,0xFFFFF737,0x0000034D,0x00001B2B,0xFFFFF737,0x0000034D},
- {"0000001000010011111100001111111010011001001011000100000001100100",0x00003732,0xFFFFE765,0x00000574,0x00002A6D,0xFFFFEDA8,0x000004B7,0x00002A6D,0xFFFFEDA8,0x000004B7},
- {"0000001000010011111100001111111010011001001100000000100100100100",0x000034D3,0xFFFFE827,0x00000569,0x000027AA,0xFFFFEEE7,0x00000492,0x000027AA,0xFFFFEEE7,0x00000492},
- {"0000001000010011111100001111111010011001001011100100000011000100",0x00003306,0xFFFFEA39,0x000004FC,0x00001DCC,0xFFFFF655,0x00000344,0x00001DCC,0xFFFFF655,0x00000344},
- {"0000001000010011111100001111111010011001001010000010000001000100",0x00002A48,0xFFFFEFCA,0x00000439,0x00001DED,0xFFFFF60D,0x00000375,0x00001DED,0xFFFFF60D,0x00000375},
- {"0000001000010011111100001111111010011001001100000011100011000100",0x000033A3,0xFFFFEA36,0x000004F9,0x0000247C,0xFFFFF21F,0x000003F4,0x0000247C,0xFFFFF21F,0x000003F4},
- {"0000001000010011111100001111111010011001001011000011000101100100",0x0000311B,0xFFFFEB76,0x000004D1,0x00001EB1,0xFFFFF5B6,0x00000366,0x00001EB1,0xFFFFF5B6,0x00000366},
- {"0000001000010011111100001111111010011001001100100100000101100100",0x00003307,0xFFFFE97F,0x0000052A,0x00001E76,0xFFFFF54D,0x0000037C,0x00001E76,0xFFFFF54D,0x0000037C},
- {"0000001000010011111100001111111010011001000111000010000101000100",0x0000344B,0xFFFFE9C5,0x00000509,0x000020D6,0xFFFFF486,0x0000038F,0x000020D6,0xFFFFF486,0x0000038F},
- {"0000001000010011111100001111111010011001001011000011000101000100",0x000034B9,0xFFFFEA0B,0x000004F7,0x000027B3,0xFFFFF057,0x0000043A,0x000027B3,0xFFFFF057,0x0000043A},
- {"0000001000010011111100001111111010011001001100000001100101100100",0x00003360,0xFFFFE984,0x00000527,0x00002238,0xFFFFF2EE,0x000003E0,0x00002238,0xFFFFF2EE,0x000003E0},
- {"0000001000010011111100001111111010011001001100000010000100100100",0x0000315C,0xFFFFEC05,0x000004B1,0x000023C8,0xFFFFF2CC,0x000003DE,0x000023C8,0xFFFFF2CC,0x000003DE},
- {"0000001000010011111100001111111010011001001011000010100001100100",0x0000389B,0xFFFFE6D5,0x00000582,0x00002C6C,0xFFFFEC92,0x000004DE,0x00002C6C,0xFFFFEC92,0x000004DE},
- {"0000001000010011111100001111111010011001001011100001000100100100",0x00003058,0xFFFFEB30,0x000004E6,0x000019B5,0xFFFFF88B,0x000002F1,0x000019B5,0xFFFFF88B,0x000002F1},
- {"0000001000010011111100001111111010011001001011100000100100000100",0x00002F69,0xFFFFEB4A,0x000004F1,0x00001B82,0xFFFFF6EC,0x00000341,0x00001B82,0xFFFFF6EC,0x00000341},
- {"0000001000010011111100001111111010011001000110100001100011100100",0x000031EB,0xFFFFEA64,0x00000508,0x00002059,0xFFFFF427,0x000003B0,0x00002059,0xFFFFF427,0x000003B0},
- {"0000001000010011111100001111111010011001001000100100000100100100",0x000033E2,0xFFFFE94D,0x0000052A,0x000020BF,0xFFFFF40B,0x000003AB,0x000020BF,0xFFFFF40B,0x000003AB},
- {"0000001000010011111100001111111010011001001010000011000110000100",0x00002AF9,0xFFFFEFE9,0x00000427,0x00001F72,0xFFFFF57A,0x00000383,0x00001F72,0xFFFFF57A,0x00000383},
- {"0000001000010011111100001111111010011001001011000010100000100100",0x00003282,0xFFFFEA88,0x000004FA,0x00002561,0xFFFFF126,0x0000042B,0x00002561,0xFFFFF126,0x0000042B},
- {"0000001000010011111100001111111010011001001100000001000011100100",0x0000308A,0xFFFFEB5D,0x000004E0,0x00001E83,0xFFFFF577,0x00000378,0x00001E83,0xFFFFF577,0x00000378},
- {"0000001000010011111100001111111010011001001100100100100010000100",0x0000336E,0xFFFFE8C8,0x00000553,0x0000217C,0xFFFFF2E1,0x000003EB,0x0000217C,0xFFFFF2E1,0x000003EB},
- {"0000001000010011111100001111111010011001000110100010000101100100",0x000034A9,0xFFFFE838,0x00000561,0x000020CE,0xFFFFF38A,0x000003C7,0x000020CE,0xFFFFF38A,0x000003C7},
- {"0000001000010011111100001111111010011001001000100010000110000100",0x00003152,0xFFFFE9EB,0x00000522,0x00001755,0xFFFFF9A9,0x000002C6,0x00001755,0xFFFFF9A9,0x000002C6},
- {"0000001000010011111100001111111010011001001010000001100010000100",0x0000286E,0xFFFFF136,0x000003FD,0x00001BAB,0xFFFFF7C3,0x0000032C,0x00001BAB,0xFFFFF7C3,0x0000032C},
- {"0000001000010011111100001111111010011001001100000000100101000100",0x0000316B,0xFFFFEA02,0x00000528,0x00002247,0xFFFFF24E,0x00000408,0x00002247,0xFFFFF24E,0x00000408},
- {"0000001000010011111100001111111010011001001011000000100011100100",0x000034CF,0xFFFFE83D,0x00000562,0x00002458,0xFFFFF130,0x00000430,0x00002458,0xFFFFF130,0x00000430},
- {"0000001000010011111100001111111010011001001011000010100110000100",0x00003352,0xFFFFE9D1,0x00000515,0x0000212A,0xFFFFF3DC,0x000003B4,0x0000212A,0xFFFFF3DC,0x000003B4},
- {"0000001000010011111100001111111010011001001010000100000010100100",0x00002946,0xFFFFF09B,0x00000415,0x00001DC9,0xFFFFF650,0x00000366,0x00001DC9,0xFFFFF650,0x00000366},
- {"0000001000010011111100001111111010011001001100000001000100100100",0x00003080,0xFFFFEB47,0x000004E1,0x00001BD5,0xFFFFF73B,0x00000329,0x00001BD5,0xFFFFF73B,0x00000329},
- {"0000001000010011111100001111111010011001000110100001100010000100",0x00002FBD,0xFFFFEB7B,0x000004DD,0x000017FC,0xFFFFF99E,0x000002C7,0x000017FC,0xFFFFF99E,0x000002C7},
- {"0000001000010011111100001111111010011001001010000001000100100100",0x00002A28,0xFFFFF032,0x0000041F,0x00001B19,0xFFFFF83A,0x00000312,0x00001B19,0xFFFFF83A,0x00000312},
- {"0000001000010011111100001111111010011001001000100100000011000100",0x00003420,0xFFFFE936,0x00000530,0x000023C2,0xFFFFF203,0x00000406,0x000023C2,0xFFFFF203,0x00000406},
- {"0000001000010011111100001111111010011001001100000001000101000100",0x00002F7C,0xFFFFEBBA,0x000004D1,0x0000185D,0xFFFFF975,0x000002CA,0x0000185D,0xFFFFF975,0x000002CA},
- {"0000001000010011111100001111111010011001001011100010000001000100",0x00002C51,0xFFFFEE3B,0x0000046F,0x000019AA,0xFFFFF8DD,0x000002ED,0x000019AA,0xFFFFF8DD,0x000002ED},
- {"0000001000010011111100001111111010011001000110100100000101000100",0x000033D6,0xFFFFE8F2,0x0000053D,0x00001D73,0xFFFFF5FB,0x0000035B,0x00001D73,0xFFFFF5FB,0x0000035B},
- {"0000001000010011111100001111111010011001001100100011000010000100",0x000031D9,0xFFFFEAF7,0x000004E4,0x00001EBD,0xFFFFF5A6,0x00000368,0x00001EBD,0xFFFFF5A6,0x00000368},
- {"0000001000010011111100001111111010011001000110100010000010100100",0x00003386,0xFFFFE9CE,0x00000515,0x00002422,0xFFFFF1F3,0x00000405,0x00002422,0xFFFFF1F3,0x00000405},
- {"0000001000010011111100001111111010011001001011000101000011100100",0x000032FB,0xFFFFE9BC,0x00000520,0x00002301,0xFFFFF267,0x000003F7,0x00002301,0xFFFFF267,0x000003F7},
- {"0000001000010011111100001111111010011001001100100010100100100100",0x000032C2,0xFFFFEAC0,0x000004EA,0x0000250F,0xFFFFF1A2,0x00000413,0x0000250F,0xFFFFF1A2,0x00000413},
- {"0000001000010011111100001111111010011001000111000010100101000100",0x00003722,0xFFFFE8A6,0x00000527,0x000026E4,0xFFFFF0F5,0x0000041C,0x000026E4,0xFFFFF0F5,0x0000041C},
- {"0000001000010011111100001111111010011001001011000100100011000100",0x000035A4,0xFFFFE822,0x00000558,0x000022F2,0xFFFFF288,0x000003E8,0x000022F2,0xFFFFF288,0x000003E8},
- {"0000001000010011111100001111111010011001001010000000100100100100",0x00002CD1,0xFFFFEDC6,0x0000048C,0x00001EAF,0xFFFFF53D,0x00000396,0x00001EAF,0xFFFFF53D,0x00000396},
- {"0000001000010011111100001111111010011001001100000001000101100100",0x00003156,0xFFFFEA60,0x0000050B,0x00001BBC,0xFFFFF704,0x00000335,0x00001BBC,0xFFFFF704,0x00000335},
- {"0000001000010011111100001111111010011001001011000101000100000100",0x000034A1,0xFFFFE8C0,0x00000544,0x00002528,0xFFFFF105,0x0000042C,0x00002528,0xFFFFF105,0x0000042C},
- {"0000001000010011111100001111111010011001001100100011000001100100",0x000032CE,0xFFFFE9D3,0x00000520,0x000021FF,0xFFFFF2FD,0x000003E4,0x000021FF,0xFFFFF2FD,0x000003E4},
- {"0000001000010011111100001111111010011001000110100101000010100100",0x000034A0,0xFFFFE823,0x0000056D,0x0000256F,0xFFFFF047,0x0000045A,0x0000256F,0xFFFFF047,0x0000045A},
- {"0000001000010011111100001111111010011001001100000011100101000100",0x00003109,0xFFFFEBD6,0x000004BF,0x000022D4,0xFFFFF32D,0x000003D0,0x000022D4,0xFFFFF32D,0x000003D0},
- {"0000001000010011111100001111111010011001001011000001000101100100",0x000030B7,0xFFFFEAF0,0x000004F3,0x00001AEC,0xFFFFF7A9,0x0000031B,0x00001AEC,0xFFFFF7A9,0x0000031B},
- {"0000001000010011111100001111111010011001001011000011100110100100",0x00003078,0xFFFFEBA4,0x000004CF,0x00001E7A,0xFFFFF5AF,0x0000036B,0x00001E7A,0xFFFFF5AF,0x0000036B},
- {"0000001000010011111100001111111010011001001100000100000100100100",0x00003442,0xFFFFE998,0x00000518,0x000025EA,0xFFFFF0F3,0x0000042B,0x000025EA,0xFFFFF0F3,0x0000042B},
- {"0000001000010011111100001111111010011001001100000010000110100100",0x000031CB,0xFFFFEA80,0x00000501,0x000020A3,0xFFFFF403,0x000003B2,0x000020A3,0xFFFFF403,0x000003B2},
- {"0000001000010011111100001111111010011001001010100010100110000100",0x00002947,0xFFFFF018,0x00000433,0x00001BA5,0xFFFFF75C,0x00000340,0x00001BA5,0xFFFFF75C,0x00000340},
- {"0000001000010011111100001111111010011001001011000011100110000100",0x000033F9,0xFFFFE99D,0x00000518,0x00002231,0xFFFFF358,0x000003C5,0x00002231,0xFFFFF358,0x000003C5},
- {"0000001000010011111100001111111010011001001100100001000100100100",0x00003131,0xFFFFEA45,0x00000513,0x00001973,0xFFFFF85E,0x00000301,0x00001973,0xFFFFF85E,0x00000301},
- {"0000001000010011111100001111111010011001000111000010100110100100",0x00003571,0xFFFFE8AC,0x00000539,0x00002049,0xFFFFF49C,0x0000038D,0x00002049,0xFFFFF49C,0x0000038D},
- {"0000001000010011111100001111111010011001001011100011100001100100",0x0000309E,0xFFFFEB1D,0x000004E8,0x000019ED,0xFFFFF86E,0x000002F8,0x000019ED,0xFFFFF86E,0x000002F8},
- {"0000001000010011111100001111111010011001001100000010100110000100",0x00003091,0xFFFFEB9B,0x000004CC,0x00001D2C,0xFFFFF6A2,0x0000033D,0x00001D2C,0xFFFFF6A2,0x0000033D},
- {"0000001000010011111100001111111010011001001100000000100011100100",0x00003069,0xFFFFEAFD,0x000004F8,0x00001E82,0xFFFFF51C,0x0000038D,0x00001E82,0xFFFFF51C,0x0000038D},
- {"0000001000010011111100001111111010011001001000100001000010100100",0x00003459,0xFFFFE7F2,0x00000572,0x00001DA7,0xFFFFF552,0x0000037F,0x00001DA7,0xFFFFF552,0x0000037F},
- {"0000001000010011111100001111111010011001001100100001000100000100",0x0000304B,0xFFFFEAFB,0x000004F4,0x0000191E,0xFFFFF8BD,0x000002EE,0x0000191E,0xFFFFF8BD,0x000002EE},
- {"0000001000010011111100001111111010011001001100000010000011000100",0x0000346E,0xFFFFEA07,0x000004FD,0x00002767,0xFFFFF058,0x00000440,0x00002767,0xFFFFF058,0x00000440},
- {"0000001000010011111100001111111010011001001011100011000010000100",0x000030B5,0xFFFFEBC1,0x000004C1,0x00001B3C,0xFFFFF818,0x000002FD,0x00001B3C,0xFFFFF818,0x000002FD},
- {"0000001000010011111100001111111010011001001100000000100100000100",0x0000321F,0xFFFFE9EA,0x00000524,0x00002380,0xFFFFF1C2,0x0000041A,0x00002380,0xFFFFF1C2,0x0000041A},
- {"0000001000010011111100001111111010011001001011100011000001000100",0x000030DF,0xFFFFEB37,0x000004E2,0x00001E3C,0xFFFFF5BB,0x00000369,0x00001E3C,0xFFFFF5BB,0x00000369},
- {"0000001000010011111100001111111010011001001010000100100010100100",0x000027E0,0xFFFFF0E2,0x00000416,0x00001A6A,0xFFFFF820,0x00000321,0x00001A6A,0xFFFFF820,0x00000321},
- {"0000001000010011111100001111111010011001000110100001000010000100",0x00002FA1,0xFFFFEB63,0x000004E7,0x0000196B,0xFFFFF880,0x000002FB,0x0000196B,0xFFFFF880,0x000002FB},
- {"0000001000010011111100001111111010011001000111000001000010000100",0x0000310C,0xFFFFEAAF,0x000004FC,0x000019EF,0xFFFFF850,0x000002FD,0x000019EF,0xFFFFF850,0x000002FD},
- {"0000001000010011111100001111111010011001001100100011100100000100",0x0000334A,0xFFFFEA07,0x0000050B,0x00002380,0xFFFFF26F,0x000003F0,0x00002380,0xFFFFF26F,0x000003F0},
- {"0000001000010011111100001111111010011001001100000010100101000100",0x00002FF9,0xFFFFECDC,0x00000492,0x00002297,0xFFFFF394,0x000003BF,0x00002297,0xFFFFF394,0x000003BF},
- {"0000001000010011111100001111111010011001001011000010000101100100",0x0000354B,0xFFFFE894,0x00000546,0x000024C4,0xFFFFF16C,0x0000041B,0x000024C4,0xFFFFF16C,0x0000041B},
- {"0000001000010011111100001111111010011001001000100000100100100100",0x00003245,0xFFFFE92F,0x00000544,0x00001829,0xFFFFF8F1,0x000002EA,0x00001829,0xFFFFF8F1,0x000002EA},
- {"0000001000010011111100001111111010011001001011100100100010000100",0x0000302F,0xFFFFEB51,0x000004E3,0x0000199F,0xFFFFF894,0x000002F4,0x0000199F,0xFFFFF894,0x000002F4},
- {"0000001000010011111100001111111010011001001011100001100011000100",0x00002F54,0xFFFFEC86,0x000004A6,0x00001A6F,0xFFFFF891,0x000002EC,0x00001A6F,0xFFFFF891,0x000002EC},
- {"0000001000010011111100001111111010011001001010000100000101100100",0x00002908,0xFFFFF0D8,0x0000040A,0x00001C9B,0xFFFFF729,0x00000342,0x00001C9B,0xFFFFF729,0x00000342},
- {"0000001000010011111100001111111010011001001100000010100101100100",0x000031D9,0xFFFFEB40,0x000004D7,0x000023F5,0xFFFFF259,0x000003F4,0x000023F5,0xFFFFF259,0x000003F4},
- {"0000001000010011111100001111111010011001001100000100100011100100",0x000034C8,0xFFFFE8C6,0x0000053F,0x00002313,0xFFFFF280,0x000003EC,0x00002313,0xFFFFF280,0x000003EC},
- {"0000001000010011111100001111111010011001001100000101000011000100",0x000037D1,0xFFFFE6A1,0x0000059C,0x00002C6A,0xFFFFEBFF,0x00000504,0x00002C6A,0xFFFFEBFF,0x00000504},
- {"0000001000010011111100001111111010011001001100100001100101100100",0x000030E9,0xFFFFEA6B,0x0000050F,0x00001A2D,0xFFFFF7DF,0x00000316,0x00001A2D,0xFFFFF7DF,0x00000316},
- {"0000001000010011111100001111111010011001001100000010000010000100",0x0000323D,0xFFFFEA95,0x000004F4,0x00001ED2,0xFFFFF584,0x0000036C,0x00001ED2,0xFFFFF584,0x0000036C},
- {"0000001000010011111100001111111010011001001011000011000000100100",0x000033D6,0xFFFFE9DB,0x00000510,0x000027A7,0xFFFFEFC7,0x0000045E,0x000027A7,0xFFFFEFC7,0x0000045E},
- {"0000001000010011111100001111111010011001000111000011000101100100",0x00003444,0xFFFFE98A,0x00000517,0x000020FD,0xFFFFF43F,0x0000039D,0x000020FD,0xFFFFF43F,0x0000039D},
- {"0000001000010011111100001111111010011001001010000000100011100100",0x00002987,0xFFFFEFA1,0x0000044B,0x00001B06,0xFFFFF788,0x0000033C,0x00001B06,0xFFFFF788,0x0000033C},
- {"0000001000010011111100001111111010011001001011000010100011100100",0x0000311D,0xFFFFED20,0x00000474,0x000025DA,0xFFFFF223,0x000003F0,0x000025DA,0xFFFFF223,0x000003F0},
- {"0000001000010011111100001111111010011001001011000001000100100100",0x000032A2,0xFFFFEA0A,0x0000050D,0x00001D48,0xFFFFF659,0x0000034A,0x00001D48,0xFFFFF659,0x0000034A},
- {"0000001000010011111100001111111010011001001000100000100011100100",0x00003110,0xFFFFE9EA,0x00000529,0x00001786,0xFFFFF958,0x000002DB,0x00001786,0xFFFFF958,0x000002DB},
- {"0000001000010011111100001111111010011001001010000010000110100100",0x000027F2,0xFFFFF174,0x000003F7,0x00001C7A,0xFFFFF72A,0x00000348,0x00001C7A,0xFFFFF72A,0x00000348},
- {"0000001000010011111100001111111010011001000111000001000011100100",0x000031DB,0xFFFFEA7D,0x000004FB,0x000019C4,0xFFFFF8B1,0x000002E6,0x000019C4,0xFFFFF8B1,0x000002E6},
- {"0000001000010011111100001111111010011001001011000001000100000100",0x00003158,0xFFFFEAAC,0x000004FA,0x00001BC1,0xFFFFF737,0x0000032B,0x00001BC1,0xFFFFF737,0x0000032B},
- {"0000001000010011111100001111111010011001001100000001000011000100",0x00002F36,0xFFFFEBF9,0x000004CA,0x00001A2A,0xFFFFF83F,0x00000303,0x00001A2A,0xFFFFF83F,0x00000303},
- {"0000001000010011111100001111111010011001001100100011100010100100",0x000032B4,0xFFFFEA72,0x000004FA,0x000021FF,0xFFFFF378,0x000003C5,0x000021FF,0xFFFFF378,0x000003C5},
- {"0000001000010011111100001111111010011001001100000011000101100100",0x00003262,0xFFFFEAFA,0x000004DF,0x00002441,0xFFFFF237,0x000003F6,0x00002441,0xFFFFF237,0x000003F6},
- {"0000001000010011111100001111111010011001001100000011100100100100",0x0000336A,0xFFFFEAFB,0x000004D1,0x00002746,0xFFFFF0B8,0x0000042B,0x00002746,0xFFFFF0B8,0x0000042B},
- {"0000001000010011111100001111111010011001000110100100000010000100",0x000032E5,0xFFFFE923,0x00000541,0x00001DF0,0xFFFFF552,0x00000380,0x00001DF0,0xFFFFF552,0x00000380},
- {"0000001000010011111100001111111010011001001100000100000001100100",0x000035D1,0xFFFFE80B,0x0000055F,0x00002780,0xFFFFEF74,0x0000046F,0x00002780,0xFFFFEF74,0x0000046F},
- {"0000001000010011111100001111111010011001001100000010100010100100",0x000033EC,0xFFFFEA48,0x000004F4,0x0000269F,0xFFFFF0D8,0x0000042A,0x0000269F,0xFFFFF0D8,0x0000042A},
- {"0000001000010011111100001111111010011001001100100011100010000100",0x000030C4,0xFFFFEB39,0x000004E2,0x00001B44,0xFFFFF7AA,0x00000318,0x00001B44,0xFFFFF7AA,0x00000318},
- {"0000001000010011111100001111111010011001001010000001000101000100",0x00002926,0xFFFFF0AF,0x0000040E,0x0000194E,0xFFFFF959,0x000002E2,0x0000194E,0xFFFFF959,0x000002E2},
- {"0000001000010011111100001111111010011001001011000001000011000100",0x00003141,0xFFFFEAAF,0x000004F6,0x00001864,0xFFFFF97C,0x000002C6,0x00001864,0xFFFFF97C,0x000002C6},
- {"0000001000010011111100001111111010011001001100000001000001100100",0x000030B2,0xFFFFEB7C,0x000004DB,0x000022CE,0xFFFFF2B5,0x000003F0,0x000022CE,0xFFFFF2B5,0x000003F0},
- {"0000001000010011111100001111111010011001001100000001100101000100",0x0000318C,0xFFFFEAC7,0x000004F6,0x00002113,0xFFFFF3CA,0x000003BD,0x00002113,0xFFFFF3CA,0x000003BD},
- {"0000001000010011111100001111111010011001001011100001000100000100",0x00002FD2,0xFFFFEB8F,0x000004D9,0x00001996,0xFFFFF89F,0x000002F1,0x00001996,0xFFFFF89F,0x000002F1},
- {"0000001000010011111100001111111010011001000110100010100010100100",0x0000310D,0xFFFFEB25,0x000004E7,0x00001F67,0xFFFFF4EF,0x0000038E,0x00001F67,0xFFFFF4EF,0x0000038E},
- {"0000001000010011111100001111111010011001001010100100100101100100",0x00002BBC,0xFFFFEE68,0x00000477,0x00002050,0xFFFFF41D,0x000003C8,0x00002050,0xFFFFF41D,0x000003C8},
- {"0000001000010011111100001111111010011001001100000010000100000100",0x00003096,0xFFFFECED,0x00000486,0x000024C9,0xFFFFF278,0x000003E7,0x000024C9,0xFFFFF278,0x000003E7},
- {"0000001000010011111100001111111010011001001011000001000010100100",0x00003401,0xFFFFE8F1,0x0000053C,0x00001E75,0xFFFFF55C,0x00000376,0x00001E75,0xFFFFF55C,0x00000376},
- {"0000001000010011111100001111111010011001001100000010100001000100",0x0000319E,0xFFFFEAB1,0x000004F8,0x00001EA3,0xFFFFF567,0x00000378,0x00001EA3,0xFFFFF567,0x00000378},
- {"0000001000010011111100001111111010011001001100100010100101100100",0x000030FD,0xFFFFEB4C,0x000004DB,0x00001CA6,0xFFFFF6E8,0x00000335,0x00001CA6,0xFFFFF6E8,0x00000335},
- {"0000001000010011111100001111111010011001001011100100000010100100",0x000030D6,0xFFFFEB1A,0x000004E4,0x00001A0D,0xFFFFF87D,0x000002EF,0x00001A0D,0xFFFFF87D,0x000002EF},
- {"0000001000010011111100001111111010011001001011000010000100100100",0x0000324B,0xFFFFEB17,0x000004D9,0x00002225,0xFFFFF3A8,0x000003BA,0x00002225,0xFFFFF3A8,0x000003BA},
- {"0000001000010011111100001111111010011001001010000100000010000100",0x00002A00,0xFFFFF02E,0x00000424,0x00001E21,0xFFFFF61D,0x0000036C,0x00001E21,0xFFFFF61D,0x0000036C},
- {"0000001000010011111100001111111010011001001010100100100010100100",0x000029CF,0xFFFFEF53,0x00000457,0x00001B11,0xFFFFF772,0x0000033D,0x00001B11,0xFFFFF772,0x0000033D},
- {"0000001000010011111100001111111010011001000110100011000010100100",0x000032A1,0xFFFFEA63,0x000004FB,0x00001F83,0xFFFFF516,0x0000037E,0x00001F83,0xFFFFF516,0x0000037E},
- {"0000001000010011111100001111111010011001001011100010000011000100",0x0000305C,0xFFFFEC14,0x000004B5,0x00001D0B,0xFFFFF6ED,0x00000332,0x00001D0B,0xFFFFF6ED,0x00000332},
- {"0000001000010011111100001111111010011001001011000001000001100100",0x00003467,0xFFFFE8D5,0x00000543,0x0000243F,0xFFFFF190,0x00000418,0x0000243F,0xFFFFF190,0x00000418},
- {"0000001000010011111100001111111010011001001010100010000001100100",0x00002796,0xFFFFF133,0x00000409,0x00001903,0xFFFFF91C,0x000002FC,0x00001903,0xFFFFF91C,0x000002FC},
- {"0000001000010011111100001111111010011001001100000010000101100100",0x000031F6,0xFFFFEAB7,0x000004F5,0x000022B9,0xFFFFF2D0,0x000003E6,0x000022B9,0xFFFFF2D0,0x000003E6},
- {"0000001000010011111100001111111010011001001011100101000100000100",0x00003196,0xFFFFEA76,0x00000503,0x00001CC5,0xFFFFF67D,0x0000034A,0x00001CC5,0xFFFFF67D,0x0000034A},
- {"0000001000010011111100001111111010011001001100100001000101000100",0x00002F9E,0xFFFFEAD9,0x00000505,0x000017C1,0xFFFFF93D,0x000002DF,0x000017C1,0xFFFFF93D,0x000002DF},
- {"0000001000010011111100001111111010011001001011100010000100100100",0x00002FBC,0xFFFFEC75,0x000004A8,0x00001D6D,0xFFFFF6AC,0x0000033D,0x00001D6D,0xFFFFF6AC,0x0000033D},
- {"0000001000010011111100001111111010011001001011000011100010100100",0x00003541,0xFFFFE921,0x00000524,0x00002662,0xFFFFF0CB,0x0000042B,0x00002662,0xFFFFF0CB,0x0000042B},
- {"0000001000010011111100001111111010011001001010100010000110100100",0x00002953,0xFFFFEF76,0x00000459,0x00001C05,0xFFFFF6A0,0x00000368,0x00001C05,0xFFFFF6A0,0x00000368},
- {"0000001000010011111100001111111010011001001011000100100100100100",0x000034BC,0xFFFFE8DD,0x00000536,0x0000210E,0xFFFFF3F4,0x000003A8,0x0000210E,0xFFFFF3F4,0x000003A8},
- {"0000001000010011111100001111111010011001001011000010100110100100",0x000034BE,0xFFFFE916,0x0000052F,0x000024A1,0xFFFFF1A6,0x00000410,0x000024A1,0xFFFFF1A6,0x00000410},
- {"0000001000010011111100001111111010011001001100000100100101100100",0x000037B5,0xFFFFE7A9,0x0000055B,0x000028A1,0xFFFFEF51,0x00000467,0x000028A1,0xFFFFEF51,0x00000467},
- {"0000001000010011111100001111111010011001001100000001000100000100",0x00002FC5,0xFFFFEBBE,0x000004D1,0x00001BA5,0xFFFFF757,0x00000328,0x00001BA5,0xFFFFF757,0x00000328},
- {"0000001000010011111100001111111010011001001100000100000010100100",0x000033CB,0xFFFFE944,0x0000052B,0x00001FBE,0xFFFFF4B1,0x0000038C,0x00001FBE,0xFFFFF4B1,0x0000038C},
- {"0000001000010011111100001111111010011001001100000001100001000100",0x000030AE,0xFFFFEBA0,0x000004D3,0x00002268,0xFFFFF316,0x000003DD,0x00002268,0xFFFFF316,0x000003DD},
- {"0000001000010011111100001111111010011001001011000010000010100100",0x00002F90,0xFFFFEC5A,0x000004B0,0x00001C3A,0xFFFFF752,0x00000323,0x00001C3A,0xFFFFF752,0x00000323},
- {"0000001000010011111100001111111010011001001011100011100011100100",0x00003113,0xFFFFEB91,0x000004C8,0x00001E3C,0xFFFFF623,0x0000034E,0x00001E3C,0xFFFFF623,0x0000034E},
- {"0000001000010011111100001111111010011001001100100011100110000100",0x0000330B,0xFFFFE94B,0x00000539,0x000020E7,0xFFFFF37E,0x000003CD,0x000020E7,0xFFFFF37E,0x000003CD},
- {"0000001000010011111100001111111010011001001011100010100001100100",0x000031D1,0xFFFFEACB,0x000004ED,0x00001E82,0xFFFFF5B2,0x00000365,0x00001E82,0xFFFFF5B2,0x00000365},
- {"0000001000010011111100001111111010011001001010100011100110000100",0x00002CD5,0xFFFFEDC1,0x0000048D,0x000020F8,0xFFFFF3C1,0x000003D1,0x000020F8,0xFFFFF3C1,0x000003D1},
- { NULL ,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000}
+static const struct phm_fuses_default vega10_fuses_default[] = {
+ { 0x0213EA94DE0E4964, 0x00003C96, 0xFFFFE226, 0x00000656, 0x00002203, 0xFFFFF201, 0x000003FF, 0x00002203, 0xFFFFF201, 0x000003FF },
+ { 0x0213EA94DE0A1884, 0x00003CC5, 0xFFFFE23A, 0x0000064E, 0x00002258, 0xFFFFF1F7, 0x000003FC, 0x00002258, 0xFFFFF1F7, 0x000003FC },
+ { 0x0213EA94DE0E31A4, 0x00003CAF, 0xFFFFE36E, 0x00000602, 0x00001E98, 0xFFFFF569, 0x00000357, 0x00001E98, 0xFFFFF569, 0x00000357 },
+ { 0x0213EA94DE2C1144, 0x0000391A, 0xFFFFE548, 0x000005C9, 0x00001B98, 0xFFFFF707, 0x00000324, 0x00001B98, 0xFFFFF707, 0x00000324 },
+ { 0x0213EA94DE2C18C4, 0x00003821, 0xFFFFE674, 0x00000597, 0x00002196, 0xFFFFF361, 0x000003C0, 0x00002196, 0xFFFFF361, 0x000003C0 },
+ { 0x0213EA94DE263884, 0x000044A2, 0xFFFFDCB7, 0x00000738, 0x0000325C, 0xFFFFE6A7, 0x000005E6, 0x0000325C, 0xFFFFE6A7, 0x000005E6 },
+ { 0x0213EA94DE082924, 0x00004057, 0xFFFFE1CF, 0x0000063C, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00002E2E, 0xFFFFEB62, 0x000004FD },
+ { 0x0213EA94DE284924, 0x00003FD0, 0xFFFFDF0F, 0x000006E5, 0x0000267C, 0xFFFFEE2D, 0x000004AB, 0x0000267C, 0xFFFFEE2D, 0x000004AB },
+ { 0x0213EA94DE280904, 0x00003F13, 0xFFFFE010, 0x000006AD, 0x000020E7, 0xFFFFF266, 0x000003EC, 0x000020E7, 0xFFFFF266, 0x000003EC },
+ { 0x0213EA94DE082044, 0x00004088, 0xFFFFDFAB, 0x000006B6, 0x0000252B, 0xFFFFEFDB, 0x00000458, 0x0000252B, 0xFFFFEFDB, 0x00000458 },
+ { 0x0213EA94DE283884, 0x00003EF6, 0xFFFFE017, 0x000006AA, 0x00001F67, 0xFFFFF369, 0x000003BE, 0x00001F67, 0xFFFFF369, 0x000003BE },
+ { 0x0213EA94DE2C2184, 0x00003CDD, 0xFFFFE2A7, 0x0000063C, 0x000026C6, 0xFFFFEF38, 0x00000478, 0x000026C6, 0xFFFFEF38, 0x00000478 },
+ { 0x0213EA94DE105124, 0x00003FA8, 0xFFFFDF02, 0x000006F0, 0x000027FE, 0xFFFFECF6, 0x000004EA, 0x000027FE, 0xFFFFECF6, 0x000004EA },
+ { 0x0213EA94DE2638C4, 0x00004670, 0xFFFFDC40, 0x00000742, 0x00003A7A, 0xFFFFE1A7, 0x000006B6, 0x00003A7A, 0xFFFFE1A7, 0x000006B6 },
+ { 0x0213EA94DE2C3024, 0x00003CDC, 0xFFFFE18C, 0x00000683, 0x00002A69, 0xFFFFEBE7, 0x00000515, 0x00002A69, 0xFFFFEBE7, 0x00000515 },
+ { 0x0213EA94DE0E38C4, 0x00003CEC, 0xFFFFE38E, 0x00000601, 0x00002752, 0xFFFFEFA7, 0x00000453, 0x00002752, 0xFFFFEFA7, 0x00000453 },
+ { 0x0213EA94DE2C1124, 0x000037D0, 0xFFFFE634, 0x000005A7, 0x00001CD2, 0xFFFFF644, 0x00000348, 0x00001CD2, 0xFFFFF644, 0x00000348 },
+ { 0x0213EA94DE283964, 0x00003DF5, 0xFFFFE0A5, 0x00000698, 0x00001FD5, 0xFFFFF30E, 0x000003D1, 0x00001FD5, 0xFFFFF30E, 0x000003D1 },
+ { 0x0213EA94DE0828C4, 0x00004201, 0xFFFFE03E, 0x00000688, 0x00003206, 0xFFFFE852, 0x0000058A, 0x00003206, 0xFFFFE852, 0x0000058A },
+ { 0x0213EA94DE2C1864, 0x00003BED, 0xFFFFE2F5, 0x00000638, 0x0000270D, 0xFFFFEED0, 0x0000048E, 0x0000270D, 0xFFFFEED0, 0x0000048E },
+ { 0x0213EA94DE0A1904, 0x00003E82, 0xFFFFE1BE, 0x00000654, 0x000025FB, 0xFFFFEFFA, 0x00000448, 0x000025FB, 0xFFFFEFFA, 0x00000448 },
+ { 0x0213EA94DE2C40C4, 0x00003962, 0xFFFFE4B9, 0x000005EF, 0x00002385, 0xFFFFF156, 0x00000423, 0x00002385, 0xFFFFF156, 0x00000423 },
+ { 0x0213EA94DE2C0944, 0x00003D88, 0xFFFFE21A, 0x00000655, 0x0000295A, 0xFFFFED68, 0x000004C4, 0x0000295A, 0xFFFFED68, 0x000004C4 },
+ { 0x0213EA94DE2C1104, 0x00003AA4, 0xFFFFE4A3, 0x000005E0, 0x000022EF, 0xFFFFF250, 0x000003EB, 0x000022EF, 0xFFFFF250, 0x000003EB },
+ { 0x0213EA94DE0E29A4, 0x00003D97, 0xFFFFE30D, 0x0000060D, 0x0000205D, 0xFFFFF45D, 0x00000380, 0x0000205D, 0xFFFFF45D, 0x00000380 },
+ { 0x0213EA94DE2C40A4, 0x000039B6, 0xFFFFE446, 0x00000605, 0x00002325, 0xFFFFF16C, 0x0000041F, 0x00002325, 0xFFFFF16C, 0x0000041F },
+ { 0x0213EA94DE263904, 0x0000457E, 0xFFFFDCF6, 0x00000722, 0x00003972, 0xFFFFE27B, 0x0000068E, 0x00003972, 0xFFFFE27B, 0x0000068E },
+ { 0x0213EA94DE0A1924, 0x00003FB8, 0xFFFFE101, 0x00000670, 0x00002787, 0xFFFFEEF5, 0x00000471, 0x00002787, 0xFFFFEEF5, 0x00000471 },
+ { 0x0213EA94DE0E38A4, 0x00003BB2, 0xFFFFE430, 0x000005EA, 0x000024A5, 0xFFFFF162, 0x00000409, 0x000024A5, 0xFFFFF162, 0x00000409 },
+ { 0x0213EA94DE082144, 0x00003EC5, 0xFFFFE1BD, 0x0000064F, 0x000022F0, 0xFFFFF227, 0x000003E8, 0x000022F0, 0xFFFFF227, 0x000003E8 },
+ { 0x0213EA94DE2C3164, 0x000038A7, 0xFFFFE59F, 0x000005C1, 0x000021CC, 0xFFFFF2DF, 0x000003D9, 0x000021CC, 0xFFFFF2DF, 0x000003D9 },
+ { 0x0213EA94DE324184, 0x00002995, 0xFFFFEF7A, 0x0000044C, 0x00001552, 0xFFFFFB5D, 0x00000292, 0x00001552, 0xFFFFFB5D, 0x00000292 },
+ { 0x0213EA94DE2C4064, 0x00003B26, 0xFFFFE2D3, 0x00000649, 0x000023B4, 0xFFFFF09B, 0x00000449, 0x000023B4, 0xFFFFF09B, 0x00000449 },
+ { 0x0213EA94DE081124, 0x000040D2, 0xFFFFE00A, 0x00000696, 0x000022DA, 0xFFFFF1E9, 0x000003F2, 0x000022DA, 0xFFFFF1E9, 0x000003F2 },
+ { 0x0213EA94DE2C3924, 0x00003C98, 0xFFFFE365, 0x00000618, 0x00002D5D, 0xFFFFEB3A, 0x0000051D, 0x00002D5D, 0xFFFFEB3A, 0x0000051D },
+ { 0x0213EA94DE2C10A4, 0x00003BBD, 0xFFFFE37E, 0x00000617, 0x0000252E, 0xFFFFF06E, 0x00000441, 0x0000252E, 0xFFFFF06E, 0x00000441 },
+ { 0x0213EA94DE262924, 0x00004363, 0xFFFFDF7A, 0x000006A0, 0x000031F5, 0xFFFFE880, 0x0000057B, 0x000031F5, 0xFFFFE880, 0x0000057B },
+ { 0x0213EA94DE0E3844, 0x00003CFC, 0xFFFFE2AF, 0x0000062E, 0x0000212A, 0xFFFFF335, 0x000003BF, 0x0000212A, 0xFFFFF335, 0x000003BF },
+ { 0x0213EA94DE1C4924, 0x0000252D, 0xFFFFF31B, 0x000003C3, 0x00001A1A, 0xFFFFF882, 0x00000325, 0x00001A1A, 0xFFFFF882, 0x00000325 },
+ { 0x0213EA94DE0A29A4, 0x00003FE2, 0xFFFFDFEF, 0x000006AC, 0x000025A2, 0xFFFFEF84, 0x00000462, 0x000025A2, 0xFFFFEF84, 0x00000462 },
+ { 0x0213EA94DE0820E4, 0x000040A5, 0xFFFFE13B, 0x0000065B, 0x00002C13, 0xFFFFEC75, 0x000004D7, 0x00002C13, 0xFFFFEC75, 0x000004D7 },
+ { 0x0213EA94DE0E48A4, 0x00003E42, 0xFFFFE1B3, 0x00000657, 0x0000221D, 0xFFFFF273, 0x000003DE, 0x0000221D, 0xFFFFF273, 0x000003DE },
+ { 0x0213EA94DE0A20E4, 0x00003E7F, 0xFFFFE255, 0x00000638, 0x00002D30, 0xFFFFEB8A, 0x00000503, 0x00002D30, 0xFFFFEB8A, 0x00000503 },
+ { 0x0213EA94DE2C29C4, 0x00003E56, 0xFFFFE16D, 0x00000670, 0x000028DC, 0xFFFFEDA0, 0x000004BA, 0x000028DC, 0xFFFFEDA0, 0x000004BA },
+ { 0x0213EA94DE2630A4, 0x000044AD, 0xFFFFDE24, 0x000006DD, 0x000031AD, 0xFFFFE850, 0x00000585, 0x000031AD, 0xFFFFE850, 0x00000585 },
+ { 0x0213EA94DE2C20E4, 0x00003AF3, 0xFFFFE5B0, 0x000005A6, 0x00002CF6, 0xFFFFEC75, 0x000004DD, 0x00002CF6, 0xFFFFEC75, 0x000004DD },
+ { 0x0213EA94DE0A2084, 0x00003E66, 0xFFFFE19E, 0x0000065B, 0x00002332, 0xFFFFF1B9, 0x000003FD, 0x00002332, 0xFFFFF1B9, 0x000003FD },
+ { 0x0213EA94DE082884, 0x00003FB4, 0xFFFFE0A5, 0x00000686, 0x0000253E, 0xFFFFF02E, 0x00000444, 0x0000253E, 0xFFFFF02E, 0x00000444 },
+ { 0x0213EA94DE2818A4, 0x00003E28, 0xFFFFE14D, 0x0000066E, 0x00001FE2, 0xFFFFF39A, 0x000003B1, 0x00001FE2, 0xFFFFF39A, 0x000003B1 },
+ { 0x0213EA94DE2C0904, 0x000039E6, 0xFFFFE44B, 0x000005FE, 0x0000210C, 0xFFFFF2F4, 0x000003DA, 0x0000210C, 0xFFFFF2F4, 0x000003DA },
+ { 0x0213EA94DE2C5104, 0x00003A4D, 0xFFFFE252, 0x0000067A, 0x000027E2, 0xFFFFECED, 0x000004FA, 0x000027E2, 0xFFFFECED, 0x000004FA },
+ { 0x0213EA94DE0A2964, 0x00004065, 0xFFFFE02F, 0x0000069B, 0x0000299D, 0xFFFFED38, 0x000004C2, 0x0000299D, 0xFFFFED38, 0x000004C2 },
+ { 0x0213EA94DE0E20A4, 0x000039EE, 0xFFFFE603, 0x00000594, 0x0000214F, 0xFFFFF429, 0x0000038E, 0x0000214F, 0xFFFFF429, 0x0000038E },
+ { 0x0213EA94DE0E48E4, 0x00003BD2, 0xFFFFE351, 0x00000618, 0x000020B8, 0xFFFFF377, 0x000003B4, 0x000020B8, 0xFFFFF377, 0x000003B4 },
+ { 0x0213EA94DE0A3124, 0x00003FAA, 0xFFFFE183, 0x0000065E, 0x000032AE, 0xFFFFE7C2, 0x000005A6, 0x000032AE, 0xFFFFE7C2, 0x000005A6 },
+ { 0x0213EA94DE2C2984, 0x00003AFB, 0xFFFFE3E4, 0x00000608, 0x00002293, 0xFFFFF21F, 0x000003FA, 0x00002293, 0xFFFFF21F, 0x000003FA },
+ { 0x0213EA94DE262064, 0x0000448B, 0xFFFFDD5D, 0x0000070D, 0x00002E4E, 0xFFFFE9DF, 0x00000551, 0x00002E4E, 0xFFFFE9DF, 0x00000551 },
+ { 0x0213EA94DE0E2184, 0x00003D46, 0xFFFFE39B, 0x000005F3, 0x0000218E, 0xFFFFF3CD, 0x00000398, 0x0000218E, 0xFFFFF3CD, 0x00000398 },
+ { 0x0213EA94DE0848E4, 0x00003F01, 0xFFFFDFD9, 0x000006BF, 0x000023AF, 0xFFFFF04E, 0x0000044C, 0x000023AF, 0xFFFFF04E, 0x0000044C },
+ { 0x0213EA94DE1029A4, 0x0000403D, 0xFFFFDF6B, 0x000006C9, 0x0000270D, 0xFFFFEE4B, 0x0000049E, 0x0000270D, 0xFFFFEE4B, 0x0000049E },
+ { 0x0213EA94DE0E3964, 0x00003C11, 0xFFFFE35C, 0x00000613, 0x000020F9, 0xFFFFF365, 0x000003B9, 0x000020F9, 0xFFFFF365, 0x000003B9 },
+ { 0x0213EA94DE2C3884, 0x00003B58, 0xFFFFE37D, 0x0000061F, 0x00002698, 0xFFFFEF46, 0x00000478, 0x00002698, 0xFFFFEF46, 0x00000478 },
+ { 0x0213EA94DE2841A4, 0x00003EBC, 0xFFFFDF7A, 0x000006D6, 0x0000212B, 0xFFFFF195, 0x0000041B, 0x0000212B, 0xFFFFF195, 0x0000041B },
+ { 0x0213EA94DE0848C4, 0x00004050, 0xFFFFDEB3, 0x000006FE, 0x00002D6C, 0xFFFFE961, 0x00000582, 0x00002D6C, 0xFFFFE961, 0x00000582 },
+ { 0x0213EA94DE262044, 0x000043F0, 0xFFFFDD9C, 0x00000702, 0x00002B31, 0xFFFFEBEA, 0x000004F7, 0x00002B31, 0xFFFFEBEA, 0x000004F7 },
+ { 0x0213EA94DE100924, 0x00003EFA, 0xFFFFE093, 0x00000696, 0x000026DB, 0xFFFFEEB3, 0x00000489, 0x000026DB, 0xFFFFEEB3, 0x00000489 },
+ { 0x0213EA94DE082064, 0x0000425D, 0xFFFFDE8D, 0x000006E6, 0x00002CA4, 0xFFFFEAD2, 0x00000531, 0x00002CA4, 0xFFFFEAD2, 0x00000531 },
+ { 0x0213EA94DE2639A4, 0x000043B0, 0xFFFFDD03, 0x00000728, 0x00002946, 0xFFFFECA6, 0x000004DE, 0x00002946, 0xFFFFECA6, 0x000004DE },
+ { 0x0213EA94DE282864, 0x00003F6A, 0xFFFFE03A, 0x0000069D, 0x00002208, 0xFFFFF1F8, 0x000003F6, 0x00002208, 0xFFFFF1F8, 0x000003F6 },
+ { 0x0213EA94DE2C2964, 0x00003A94, 0xFFFFE4A7, 0x000005E2, 0x000024D0, 0xFFFFF100, 0x00000426, 0x000024D0, 0xFFFFF100, 0x00000426 },
+ { 0x0213EA94DE2810C4, 0x00003F2F, 0xFFFFE0A3, 0x00000688, 0x00002198, 0xFFFFF271, 0x000003E2, 0x00002198, 0xFFFFF271, 0x000003E2 },
+ { 0x0213EA94DE1048E4, 0x00003EA5, 0xFFFFE032, 0x000006AE, 0x0000227C, 0xFFFFF130, 0x00000426, 0x0000227C, 0xFFFFF130, 0x00000426 },
+ { 0x0213EA94DE264144, 0x0000442F, 0xFFFFDBC4, 0x0000078B, 0x00003CD6, 0xFFFFDE6C, 0x0000076C, 0x00003CD6, 0xFFFFDE6C, 0x0000076C },
+ { 0x0213EA94DE282884, 0x00003DDE, 0xFFFFE174, 0x00000668, 0x00001FF4, 0xFFFFF38F, 0x000003B1, 0x00001FF4, 0xFFFFF38F, 0x000003B1 },
+ { 0x0213EA94DE0A3144, 0x000040B0, 0xFFFFE016, 0x000006A0, 0x00002DBB, 0xFFFFEA7F, 0x00000537, 0x00002DBB, 0xFFFFEA7F, 0x00000537 },
+ { 0x0213EA94DE2C3104, 0x00003429, 0xFFFFEA97, 0x000004DD, 0x000024D5, 0xFFFFF26F, 0x000003DF, 0x000024D5, 0xFFFFF26F, 0x000003DF },
+ { 0x0213EA94DE0E1904, 0x00003AEB, 0xFFFFE590, 0x000005A3, 0x000022CB, 0xFFFFF347, 0x000003B2, 0x000022CB, 0xFFFFF347, 0x000003B2 },
+ { 0x0213EA94DE283904, 0x00003B8E, 0xFFFFE2EF, 0x00000636, 0x00002351, 0xFFFFF143, 0x0000041C, 0x00002351, 0xFFFFF143, 0x0000041C },
+ { 0x0213EA94DE3240C4, 0x00002926, 0xFFFFF0B0, 0x00000410, 0x0000194E, 0xFFFFF94E, 0x000002E9, 0x0000194E, 0xFFFFF94E, 0x000002E9 },
+ { 0x0213EA94DE283184, 0x0000402B, 0xFFFFDF78, 0x000006C2, 0x00002273, 0xFFFFF16C, 0x00000414, 0x00002273, 0xFFFFF16C, 0x00000414 },
+ { 0x0213EA94DE0A10A4, 0x00003D6A, 0xFFFFE1D3, 0x00000659, 0x00002006, 0xFFFFF394, 0x000003B1, 0x00002006, 0xFFFFF394, 0x000003B1 },
+ { 0x0213EA94DE284064, 0x00004042, 0xFFFFDFD8, 0x000006A8, 0x00002135, 0xFFFFF29F, 0x000003D9, 0x00002135, 0xFFFFF29F, 0x000003D9 },
+ { 0x0213EA94DE0820A4, 0x0000405B, 0xFFFFE093, 0x00000682, 0x0000288F, 0xFFFFEE3A, 0x00000491, 0x0000288F, 0xFFFFEE3A, 0x00000491 },
+ { 0x0213EA94DE2C48A4, 0x00003A49, 0xFFFFE30C, 0x00000648, 0x000023F9, 0xFFFFF02D, 0x00000460, 0x000023F9, 0xFFFFF02D, 0x00000460 },
+ { 0x0213EA94DE282964, 0x00003D59, 0xFFFFE1CC, 0x0000065B, 0x00002013, 0xFFFFF37D, 0x000003B6, 0x00002013, 0xFFFFF37D, 0x000003B6 },
+ { 0x0213EA94DE2C3984, 0x000040C1, 0xFFFFDF8C, 0x000006CA, 0x00003271, 0xFFFFE6CA, 0x000005EA, 0x00003271, 0xFFFFE6CA, 0x000005EA },
+ { 0x0213EA94DE2620E4, 0x000042E9, 0xFFFFDFDC, 0x0000068C, 0x00002ED9, 0xFFFFEAAF, 0x0000051B, 0x00002ED9, 0xFFFFEAAF, 0x0000051B },
+ { 0x0213EA94DE083084, 0x000042ED, 0xFFFFDE50, 0x000006F0, 0x00002FCF, 0xFFFFE8BB, 0x0000058C, 0x00002FCF, 0xFFFFE8BB, 0x0000058C },
+ { 0x0213EA94DE0A4104, 0x00003EBD, 0xFFFFE099, 0x00000698, 0x00002709, 0xFFFFEE7B, 0x00000495, 0x00002709, 0xFFFFEE7B, 0x00000495 },
+ { 0x0213EA94DE284904, 0x00003F71, 0xFFFFDF82, 0x000006C9, 0x0000219B, 0xFFFFF1AD, 0x0000040F, 0x0000219B, 0xFFFFF1AD, 0x0000040F },
+ { 0x0213EA94DE2808E4, 0x00003E73, 0xFFFFE080, 0x0000069B, 0x000020E7, 0xFFFFF273, 0x000003E9, 0x000020E7, 0xFFFFF273, 0x000003E9 },
+ { 0x0213EA94DE0E3184, 0x00003E14, 0xFFFFE278, 0x0000062C, 0x00002275, 0xFFFFF2B3, 0x000003CE, 0x00002275, 0xFFFFF2B3, 0x000003CE },
+ { 0x0213EA94DE2C21A4, 0x00003ABB, 0xFFFFE3B9, 0x00000615, 0x00002192, 0xFFFFF28F, 0x000003EB, 0x00002192, 0xFFFFF28F, 0x000003EB },
+ { 0x0213EA94DE283124, 0x00003D53, 0xFFFFE255, 0x00000643, 0x0000275B, 0xFFFFEEED, 0x00000479, 0x0000275B, 0xFFFFEEED, 0x00000479 },
+ { 0x0213EA94DE262864, 0x000043E3, 0xFFFFDDC3, 0x000006FB, 0x00002B6B, 0xFFFFEBD6, 0x000004FA, 0x00002B6B, 0xFFFFEBD6, 0x000004FA },
+ { 0x0213EA94DE0E2144, 0x00003BDE, 0xFFFFE507, 0x000005B4, 0x000022CE, 0xFFFFF358, 0x000003AB, 0x000022CE, 0xFFFFF358, 0x000003AB },
+ { 0x0213EA94DE323164, 0x00002460, 0xFFFFF3B5, 0x000003A2, 0x000014E7, 0xFFFFFC32, 0x0000027C, 0x000014E7, 0xFFFFFC32, 0x0000027C },
+ { 0x0213EA94DE2820C4, 0x00003D20, 0xFFFFE298, 0x0000062F, 0x00002080, 0xFFFFF3AF, 0x000003A8, 0x00002080, 0xFFFFF3AF, 0x000003A8 },
+ { 0x0213EA94DE081904, 0x00003E14, 0xFFFFE221, 0x00000641, 0x000021BB, 0xFFFFF2EA, 0x000003CA, 0x000021BB, 0xFFFFF2EA, 0x000003CA },
+ { 0x0213EA94DE0A40C4, 0x00003DE1, 0xFFFFE14E, 0x00000677, 0x00002468, 0xFFFFF068, 0x00000440, 0x00002468, 0xFFFFF068, 0x00000440 },
+ { 0x0213EA94DE261084, 0x00004372, 0xFFFFDDF8, 0x000006F5, 0x00002B3F, 0xFFFFEBE8, 0x000004F8, 0x00002B3F, 0xFFFFEBE8, 0x000004F8 },
+ { 0x0213EA94DE0A28C4, 0x00003E4F, 0xFFFFE2A3, 0x0000062B, 0x00002F5A, 0xFFFFEA37, 0x0000053B, 0x00002F5A, 0xFFFFEA37, 0x0000053B },
+ { 0x0213EA94DE2850E4, 0x00003E07, 0xFFFFE02F, 0x000006B6, 0x0000216B, 0xFFFFF1A3, 0x00000416, 0x0000216B, 0xFFFFF1A3, 0x00000416 },
+ { 0x0213EA94DE2838A4, 0x00003DAB, 0xFFFFE128, 0x0000067F, 0x0000216F, 0xFFFFF236, 0x000003F3, 0x0000216F, 0xFFFFF236, 0x000003F3 },
+ { 0x0213EA94DE2C2924, 0x0000364B, 0xFFFFE8CB, 0x0000052A, 0x00002568, 0xFFFFF1B2, 0x00000400, 0x00002568, 0xFFFFF1B2, 0x00000400 },
+ { 0x0213EA94DE261064, 0x00004219, 0xFFFFDE87, 0x000006E8, 0x00002C59, 0xFFFFEAEE, 0x00000529, 0x00002C59, 0xFFFFEAEE, 0x00000529 },
+ { 0x0213EA94DE0E1944, 0x000039A8, 0xFFFFE602, 0x00000594, 0x00001D06, 0xFFFFF6F0, 0x00000316, 0x00001D06, 0xFFFFF6F0, 0x00000316 },
+ { 0x0213EA94DE2610E4, 0x00004052, 0xFFFFE01C, 0x00000698, 0x00002310, 0xFFFFF1A1, 0x000003FE, 0x00002310, 0xFFFFF1A1, 0x000003FE },
+ { 0x0213EA94DE0E2824, 0x00003C1C, 0xFFFFE3EB, 0x000005F1, 0x00002289, 0xFFFFF2CF, 0x000003C9, 0x00002289, 0xFFFFF2CF, 0x000003C9 },
+ { 0x0213EA94DE0E5124, 0x00003F19, 0xFFFFE085, 0x0000069E, 0x00002B94, 0xFFFFEB72, 0x0000051D, 0x00002B94, 0xFFFFEB72, 0x0000051D },
+ { 0x0213EA94DE0E41A4, 0x00003C51, 0xFFFFE2AD, 0x00000638, 0x0000206B, 0xFFFFF361, 0x000003BE, 0x0000206B, 0xFFFFF361, 0x000003BE },
+ { 0x0213EA94DE2610C4, 0x000040B9, 0xFFFFDFBB, 0x000006AB, 0x0000241F, 0xFFFFF0CC, 0x00000425, 0x0000241F, 0xFFFFF0CC, 0x00000425 },
+ { 0x0213EA94DE0A2064, 0x00003E62, 0xFFFFE12C, 0x00000678, 0x00002445, 0xFFFFF09E, 0x00000435, 0x00002445, 0xFFFFF09E, 0x00000435 },
+ { 0x0213EA94DE0E1984, 0x00003C97, 0xFFFFE399, 0x000005FB, 0x0000209D, 0xFFFFF41D, 0x0000038F, 0x0000209D, 0xFFFFF41D, 0x0000038F },
+ { 0x0213EA94DE0E3144, 0x00003FF9, 0xFFFFE1E9, 0x0000063E, 0x00002E96, 0xFFFFEAF5, 0x00000516, 0x00002E96, 0xFFFFEAF5, 0x00000516 },
+ { 0x0213EA94DE0A3084, 0x00003F04, 0xFFFFE109, 0x0000067A, 0x000026E1, 0xFFFFEF0B, 0x00000476, 0x000026E1, 0xFFFFEF0B, 0x00000476 },
+ { 0x0213EA94DE101124, 0x00003E3E, 0xFFFFE187, 0x00000660, 0x00002049, 0xFFFFF38D, 0x000003B0, 0x00002049, 0xFFFFF38D, 0x000003B0 },
+ { 0x0213EA94DE282944, 0x00003D58, 0xFFFFE253, 0x0000063D, 0x00002158, 0xFFFFF308, 0x000003C3, 0x00002158, 0xFFFFF308, 0x000003C3 },
+ { 0x0213EA94DE0840C4, 0x00004074, 0xFFFFDF8D, 0x000006C0, 0x00002799, 0xFFFFEE19, 0x000004A5, 0x00002799, 0xFFFFEE19, 0x000004A5 },
+ { 0x0213EA94DE281924, 0x00003DAF, 0xFFFFE1C9, 0x00000659, 0x000020E5, 0xFFFFF313, 0x000003C6, 0x000020E5, 0xFFFFF313, 0x000003C6 },
+ { 0x0213EA94DE0A3964, 0x000041DD, 0xFFFFDDFA, 0x0000071B, 0x0000348D, 0xFFFFE4B4, 0x0000064C, 0x0000348D, 0xFFFFE4B4, 0x0000064C },
+ { 0x0213EA94DE2C2884, 0x00003947, 0xFFFFE5AE, 0x000005B8, 0x000024A6, 0xFFFFF140, 0x0000041D, 0x000024A6, 0xFFFFF140, 0x0000041D },
+ { 0x0213EA94DE101844, 0x00003D35, 0xFFFFE197, 0x0000066E, 0x00002248, 0xFFFFF1BC, 0x00000408, 0x00002248, 0xFFFFF1BC, 0x00000408 },
+ { 0x0213EA94DE0A18E4, 0x00003F4F, 0xFFFFE13E, 0x0000066D, 0x00002AF0, 0xFFFFEC99, 0x000004DB, 0x00002AF0, 0xFFFFEC99, 0x000004DB },
+ { 0x0213EA94DE263944, 0x0000430F, 0xFFFFDDFB, 0x000006FC, 0x00002D4D, 0xFFFFEA55, 0x00000540, 0x00002D4D, 0xFFFFEA55, 0x00000540 },
+ { 0x0213EA94DE0E2944, 0x00003B22, 0xFFFFE543, 0x000005B1, 0x000022E1, 0xFFFFF31B, 0x000003B9, 0x000022E1, 0xFFFFF31B, 0x000003B9 },
+ { 0x0213EA94DE0E2084, 0x00003978, 0xFFFFE611, 0x00000592, 0x00001C36, 0xFFFFF771, 0x00000302, 0x00001C36, 0xFFFFF771, 0x00000302 },
+ { 0x0213EA94DE262164, 0x000044DF, 0xFFFFDDAB, 0x000006F2, 0x00002CEA, 0xFFFFEB47, 0x00000507, 0x00002CEA, 0xFFFFEB47, 0x00000507 },
+ { 0x0213EA94DE0A38C4, 0x00003E9B, 0xFFFFE12C, 0x0000067C, 0x00002B79, 0xFFFFEBD9, 0x00000503, 0x00002B79, 0xFFFFEBD9, 0x00000503 },
+ { 0x0213EA94DE263044, 0x00004464, 0xFFFFDCD3, 0x00000731, 0x00002D14, 0xFFFFEA2D, 0x0000054E, 0x00002D14, 0xFFFFEA2D, 0x0000054E },
+ { 0x0213EA94DE281124, 0x00003FB3, 0xFFFFE052, 0x00000693, 0x000020AC, 0xFFFFF311, 0x000003C6, 0x000020AC, 0xFFFFF311, 0x000003C6 },
+ { 0x0213EA94DE2C1084, 0x00003BDA, 0xFFFFE2FB, 0x00000636, 0x0000261E, 0xFFFFEF72, 0x00000471, 0x0000261E, 0xFFFFEF72, 0x00000471 },
+ { 0x0213EA94DE2C1964, 0x00003D72, 0xFFFFE28A, 0x0000063E, 0x000029D8, 0xFFFFED54, 0x000004C7, 0x000029D8, 0xFFFFED54, 0x000004C7 },
+ { 0x0213EA94DE2C2824, 0x00003E26, 0xFFFFE102, 0x00000694, 0x00002DD1, 0xFFFFE9CA, 0x0000056D, 0x00002DD1, 0xFFFFE9CA, 0x0000056D },
+ { 0x0213EA94DE104124, 0x000041CD, 0xFFFFDE97, 0x000006ED, 0x00002DE5, 0xFFFFE9B9, 0x00000565, 0x00002DE5, 0xFFFFE9B9, 0x00000565 },
+ { 0x0213EA94DE0A2984, 0x00003F30, 0xFFFFE06E, 0x00000698, 0x000024FF, 0xFFFFEFFC, 0x0000044F, 0x000024FF, 0xFFFFEFFC, 0x0000044F },
+ { 0x0213EA94DE2C38C4, 0x0000378B, 0xFFFFE6B4, 0x00000594, 0x000023A7, 0xFFFFF1DC, 0x00000407, 0x000023A7, 0xFFFFF1DC, 0x00000407 },
+ { 0x0213EA94DE0E4164, 0x00003CD7, 0xFFFFE28D, 0x00000636, 0x00002036, 0xFFFFF3B5, 0x000003AA, 0x00002036, 0xFFFFF3B5, 0x000003AA },
+ { 0x0213EA94DE0A3884, 0x00003EF9, 0xFFFFE0AA, 0x0000068D, 0x000024D3, 0xFFFFF02F, 0x00000445, 0x000024D3, 0xFFFFF02F, 0x00000445 },
+ { 0x0213EA94DE283944, 0x00003D08, 0xFFFFE1BB, 0x00000665, 0x00002159, 0xFFFFF26F, 0x000003E6, 0x00002159, 0xFFFFF26F, 0x000003E6 },
+ { 0x0213EA94DE2C20C4, 0x000038A9, 0xFFFFE6CA, 0x00000580, 0x000025D3, 0xFFFFF101, 0x00000421, 0x000025D3, 0xFFFFF101, 0x00000421 },
+ { 0x0213EA94DE0A20A4, 0x00003E45, 0xFFFFE1F8, 0x0000064D, 0x000027E3, 0xFFFFEEBB, 0x0000047F, 0x000027E3, 0xFFFFEEBB, 0x0000047F },
+ { 0x0213EA94DE0E3864, 0x00003F76, 0xFFFFE128, 0x0000066E, 0x0000286B, 0xFFFFEE4C, 0x00000493, 0x0000286B, 0xFFFFEE4C, 0x00000493 },
+ { 0x0213EA94DE264104, 0x0000440D, 0xFFFFDCA2, 0x0000074F, 0x00003817, 0xFFFFE256, 0x000006AF, 0x00003817, 0xFFFFE256, 0x000006AF },
+ { 0x0213EA94DE105104, 0x00003EE1, 0xFFFFDFA7, 0x000006D4, 0x000027EA, 0xFFFFED2B, 0x000004DE, 0x000027EA, 0xFFFFED2B, 0x000004DE },
+ { 0x0213EA94DE2C3864, 0x00003C62, 0xFFFFE285, 0x0000064A, 0x00002520, 0xFFFFF001, 0x0000045C, 0x00002520, 0xFFFFF001, 0x0000045C },
+ { 0x0213EA94DE323964, 0x0000272E, 0xFFFFF17A, 0x000003FA, 0x0000150B, 0xFFFFFBD5, 0x00000284, 0x0000150B, 0xFFFFFBD5, 0x00000284 },
+ { 0x0213EA94DE261924, 0x00004275, 0xFFFFDF69, 0x000006A5, 0x000025AA, 0xFFFFF05C, 0x0000042B, 0x000025AA, 0xFFFFF05C, 0x0000042B },
+ { 0x0213EA94DE0E40E4, 0x00003CAA, 0xFFFFE392, 0x000005FF, 0x000023A8, 0xFFFFF20E, 0x000003E9, 0x000023A8, 0xFFFFF20E, 0x000003E9 },
+ { 0x0213EA94DE2C50C4, 0x00003CF8, 0xFFFFE0FB, 0x000006A6, 0x00002CA7, 0xFFFFE9FF, 0x0000056E, 0x00002CA7, 0xFFFFE9FF, 0x0000056E },
+ { 0x0213EA94DE282124, 0x00003D00, 0xFFFFE296, 0x00000633, 0x000021C1, 0xFFFFF2C8, 0x000003CF, 0x000021C1, 0xFFFFF2C8, 0x000003CF },
+ { 0x0213EA94DE2838E4, 0x00003B46, 0xFFFFE301, 0x00000632, 0x0000204C, 0xFFFFF33B, 0x000003C8, 0x0000204C, 0xFFFFF33B, 0x000003C8 },
+ { 0x0213EA94DE204164, 0x00002026, 0xFFFFF5CE, 0x00000368, 0x00001598, 0xFFFFFB29, 0x000002C3, 0x00001598, 0xFFFFFB29, 0x000002C3 },
+ { 0x0213EA94DE283164, 0x00003DCA, 0xFFFFE178, 0x00000668, 0x00001FDB, 0xFFFFF39D, 0x000003AF, 0x00001FDB, 0xFFFFF39D, 0x000003AF },
+ { 0x0213EA94DE2C48C4, 0x00003A59, 0xFFFFE327, 0x00000642, 0x000024B9, 0xFFFFEFC4, 0x00000471, 0x000024B9, 0xFFFFEFC4, 0x00000471 },
+ { 0x0213EA94DE2C2944, 0x00003C26, 0xFFFFE440, 0x000005EB, 0x00002C0F, 0xFFFFEC88, 0x000004E0, 0x00002C0F, 0xFFFFEC88, 0x000004E0 },
+ { 0x0213EA94DE083884, 0x00004149, 0xFFFFDEB8, 0x000006E7, 0x0000280A, 0xFFFFED89, 0x000004C2, 0x0000280A, 0xFFFFED89, 0x000004C2 },
+ { 0x0213EA94DE0E4124, 0x00003EB4, 0xFFFFE1E5, 0x0000064D, 0x0000299F, 0xFFFFEDB3, 0x000004A9, 0x0000299F, 0xFFFFEDB3, 0x000004A9 },
+ { 0x0213EA94DE2C39A4, 0x00003BBF, 0xFFFFE268, 0x0000065A, 0x00002504, 0xFFFFEFB0, 0x00000470, 0x00002504, 0xFFFFEFB0, 0x00000470 },
+ { 0x0213EA94DE084904, 0x00004203, 0xFFFFDDC6, 0x00000720, 0x0000303B, 0xFFFFE78F, 0x000005D0, 0x0000303B, 0xFFFFE78F, 0x000005D0 },
+ { 0x0213EA94DE0E3984, 0x00003DA3, 0xFFFFE244, 0x0000063E, 0x000021B4, 0xFFFFF2DA, 0x000003CD, 0x000021B4, 0xFFFFF2DA, 0x000003CD },
+ { 0x0213EA94DE0A38E4, 0x00004035, 0xFFFFE065, 0x0000069B, 0x00003323, 0xFFFFE6D6, 0x000005D8, 0x00003323, 0xFFFFE6D6, 0x000005D8 },
+ { 0x0213EA94DE2C1164, 0x00003944, 0xFFFFE4E5, 0x000005E2, 0x00001F3C, 0xFFFFF456, 0x0000039D, 0x00001F3C, 0xFFFFF456, 0x0000039D },
+ { 0x0213EA94DE061904, 0x000032D8, 0xFFFFEAE8, 0x000004E6, 0x00001812, 0xFFFFFA1C, 0x000002BC, 0x00001812, 0xFFFFFA1C, 0x000002BC },
+ { 0x0213F0FD42D22944, 0x000041F6, 0xFFFFE025, 0x0000069A, 0x0000241E, 0xFFFFF1B4, 0x00000402, 0x0000241E, 0xFFFFF1B4, 0x00000402 },
+ { 0x0213F0FE990C30A4, 0x00003300, 0xFFFFEB60, 0x000004C1, 0x00001E15, 0xFFFFF6A6, 0x0000033B, 0x00001E15, 0xFFFFF6A6, 0x0000033B },
+ { 0x0213EA94DE0408A4, 0x000037F0, 0xFFFFE68F, 0x0000059B, 0x00001F8A, 0xFFFFF467, 0x000003A3, 0x00001F8A, 0xFFFFF467, 0x000003A3 },
+ { 0x0213F0FE99182984, 0x000025D8, 0xFFFFF2AA, 0x000003C3, 0x000018A8, 0xFFFFF9BE, 0x000002D2, 0x000018A8, 0xFFFFF9BE, 0x000002D2 },
+ { 0x0213F0FE990620C4, 0x0000364F, 0xFFFFE988, 0x000004FC, 0x00001E51, 0xFFFFF633, 0x0000034F, 0x00001E51, 0xFFFFF633, 0x0000034F },
+ { 0x0213EA94DE061144, 0x00002288, 0xFFFFF483, 0x0000036C, 0x0000280F, 0xFFFFEF39, 0x0000047B, 0x0000280F, 0xFFFFEF39, 0x0000047B },
+ { 0x0213F0FE99082084, 0x00003322, 0xFFFFEA7E, 0x000004ED, 0x00001DAD, 0xFFFFF62B, 0x00000355, 0x00001DAD, 0xFFFFF62B, 0x00000355 },
+ { 0x0213EA94DE0250E4, 0x00002B7B, 0xFFFFEE4F, 0x0000045B, 0x00001AA2, 0xFFFFF710, 0x0000033E, 0x00001AA2, 0xFFFFF710, 0x0000033E },
+ { 0x0213F0FE990420C4, 0x000034CC, 0xFFFFEA79, 0x000004E4, 0x00001B05, 0xFFFFF8B3, 0x000002EC, 0x00001B05, 0xFFFFF8B3, 0x000002EC },
+ { 0x0213F0FD42DC2864, 0x00003837, 0xFFFFE5ED, 0x000005C3, 0x00001ACB, 0xFFFFF7B2, 0x00000314, 0x00001ACB, 0xFFFFF7B2, 0x00000314 },
+ { 0x0213F0FE99044164, 0x0000352D, 0xFFFFE88F, 0x00000548, 0x000021E6, 0xFFFFF3B5, 0x000003AA, 0x000021E6, 0xFFFFF3B5, 0x000003AA },
+ { 0x0213F0FE990A4884, 0x00003300, 0xFFFFE835, 0x0000057B, 0x00001A85, 0xFFFFF715, 0x00000336, 0x00001A85, 0xFFFFF715, 0x00000336 },
+ { 0x0213EA94DE0448A4, 0x000033FA, 0xFFFFE851, 0x00000565, 0x00001A8E, 0xFFFFF727, 0x0000033B, 0x00001A8E, 0xFFFFF727, 0x0000033B },
+ { 0x0213F0FD42DA3924, 0x000039D3, 0xFFFFE5D3, 0x000005B0, 0x00001888, 0xFFFFF978, 0x000002C8, 0x00001888, 0xFFFFF978, 0x000002C8 },
+ { 0x0213F0FE990E4864, 0x00002F6B, 0xFFFFEC53, 0x000004B9, 0x00001C15, 0xFFFFF71B, 0x00000337, 0x00001C15, 0xFFFFF71B, 0x00000337 },
+ { 0x0213F0FE99064144, 0x0000384D, 0xFFFFE737, 0x00000569, 0x00001D2D, 0xFFFFF673, 0x00000343, 0x00001D2D, 0xFFFFF673, 0x00000343 },
+ { 0x0213F0FE990620A4, 0x00003A49, 0xFFFFE70B, 0x0000055F, 0x00001A63, 0xFFFFF8CD, 0x000002E2, 0x00001A63, 0xFFFFF8CD, 0x000002E2 },
+ { 0x0213F0FE99042984, 0x0000311E, 0xFFFFEB97, 0x000004C6, 0x00001EAE, 0xFFFFF5A9, 0x00000367, 0x00001EAE, 0xFFFFF5A9, 0x00000367 },
+ { 0x0213F0FE990E1124, 0x000027D3, 0xFFFFF075, 0x00000417, 0x00002001, 0xFFFFF44A, 0x000003A2, 0x00002001, 0xFFFFF44A, 0x000003A2 },
+ { 0x0213F0FE99064904, 0x00003B72, 0xFFFFE4BD, 0x000005DC, 0x00001D76, 0xFFFFF606, 0x0000035A, 0x00001D76, 0xFFFFF606, 0x0000035A },
+ { 0x0213F0FE99101124, 0x00002E0F, 0xFFFFECA7, 0x000004AE, 0x00001DC6, 0xFFFFF5BF, 0x0000036A, 0x00001DC6, 0xFFFFF5BF, 0x0000036A },
+ { 0x0213F0FE990238A4, 0x000032C7, 0xFFFFEA7A, 0x000004F0, 0x00001A7B, 0xFFFFF827, 0x00000301, 0x00001A7B, 0xFFFFF827, 0x00000301 },
+ { 0x0213EA94DE044884, 0x0000312D, 0xFFFFEA39, 0x00000515, 0x00001948, 0xFFFFF800, 0x00000318, 0x00001948, 0xFFFFF800, 0x00000318 },
+ { 0x0213EA94DE062084, 0x00003611, 0xFFFFE8D7, 0x00000533, 0x00001929, 0xFFFFF965, 0x000002D2, 0x00001929, 0xFFFFF965, 0x000002D2 },
+ { 0x0213F0FE992C30E4, 0x00002FE2, 0xFFFFED89, 0x00000470, 0x00001A3C, 0xFFFFF955, 0x000002D5, 0x00001A3C, 0xFFFFF955, 0x000002D5 },
+ { 0x0213EA94DE0208A4, 0x000035FF, 0xFFFFE884, 0x00000548, 0x0000182A, 0xFFFFF9AB, 0x000002CF, 0x0000182A, 0xFFFFF9AB, 0x000002CF },
+ { 0x0213F0FE990220E4, 0x00003597, 0xFFFFE904, 0x00000528, 0x00001A94, 0xFFFFF840, 0x00000300, 0x00001A94, 0xFFFFF840, 0x00000300 },
+ { 0x0213F0FE99181944, 0x000026CB, 0xFFFFF1FB, 0x000003E4, 0x000017CC, 0xFFFFFA25, 0x000002C8, 0x000017CC, 0xFFFFFA25, 0x000002C8 },
+ { 0x0213EA94DE0608C4, 0x00003274, 0xFFFFEA39, 0x0000050C, 0x00001B20, 0xFFFFF7C1, 0x00000314, 0x00001B20, 0xFFFFF7C1, 0x00000314 },
+ { 0x0213F0FD42D82924, 0x0000280B, 0xFFFFF283, 0x000003B5, 0x000018D0, 0xFFFFF992, 0x000002EC, 0x000018D0, 0xFFFFF992, 0x000002EC },
+ { 0x0213F0FE99062104, 0x000033AB, 0xFFFFEB1B, 0x000004C4, 0x00001FEE, 0xFFFFF53A, 0x00000378, 0x00001FEE, 0xFFFFF53A, 0x00000378 },
+ { 0x0213F0FE990A3964, 0x00002F79, 0xFFFFEB0C, 0x000004FA, 0x00001E57, 0xFFFFF4BF, 0x0000039B, 0x00001E57, 0xFFFFF4BF, 0x0000039B },
+ { 0x0213F0FE990448E4, 0x00003487, 0xFFFFE8F2, 0x00000539, 0x0000185B, 0xFFFFF9AE, 0x000002BA, 0x0000185B, 0xFFFFF9AE, 0x000002BA },
+ { 0x0213F0FE990A18A4, 0x00003500, 0xFFFFE793, 0x0000058A, 0x00001AA2, 0xFFFFF792, 0x0000031D, 0x00001AA2, 0xFFFFF792, 0x0000031D },
+ { 0x0213F0FE99081164, 0x00003943, 0xFFFFE54D, 0x000005D9, 0x00001BC8, 0xFFFFF6E0, 0x00000339, 0x00001BC8, 0xFFFFF6E0, 0x00000339 },
+ { 0x0213EA94DE0430A4, 0x0000306D, 0xFFFFEC5E, 0x000004A5, 0x00001A3A, 0xFFFFF85F, 0x00000304, 0x00001A3A, 0xFFFFF85F, 0x00000304 },
+ { 0x0213F0FD42D83084, 0x00002BA4, 0xFFFFEE8D, 0x0000046A, 0x0000198C, 0xFFFFF88E, 0x00000307, 0x0000198C, 0xFFFFF88E, 0x00000307 },
+ { 0x0213F0FD42D218E4, 0x00003D30, 0xFFFFE2F6, 0x0000062A, 0x000025DC, 0xFFFFF074, 0x00000435, 0x000025DC, 0xFFFFF074, 0x00000435 },
+ { 0x0213F0FD42D83964, 0x00002CD6, 0xFFFFED79, 0x0000049B, 0x000016D0, 0xFFFFFA53, 0x000002BB, 0x000016D0, 0xFFFFFA53, 0x000002BB },
+ { 0x0213F0FE99163164, 0x00002484, 0xFFFFF3BD, 0x000003A0, 0x000015B8, 0xFFFFFB6B, 0x000002A4, 0x000015B8, 0xFFFFFB6B, 0x000002A4 },
+ { 0x0213F0FE990E3944, 0x000038AE, 0xFFFFE6D1, 0x00000587, 0x00001A2A, 0xFFFFF8F1, 0x000002D4, 0x00001A2A, 0xFFFFF8F1, 0x000002D4 },
+ { 0x0213F0FE99044944, 0x000036FD, 0xFFFFE76C, 0x00000576, 0x00001EE4, 0xFFFFF58D, 0x00000361, 0x00001EE4, 0xFFFFF58D, 0x00000361 },
+ { 0x0213F0FD42D830A4, 0x00002BCF, 0xFFFFEF28, 0x00000448, 0x00001B93, 0xFFFFF7BA, 0x00000327, 0x00001B93, 0xFFFFF7BA, 0x00000327 },
+ { 0x0213F0FE99062884, 0x00003834, 0xFFFFE818, 0x0000053B, 0x00001AFE, 0xFFFFF85C, 0x000002F3, 0x00001AFE, 0xFFFFF85C, 0x000002F3 },
+ { 0x0213F0FE993231A4, 0x00002EF7, 0xFFFFEBFC, 0x000004CE, 0x00001897, 0xFFFFF8EF, 0x000002EC, 0x00001897, 0xFFFFF8EF, 0x000002EC },
+ { 0x0213F0FE992C18C4, 0x000035BD, 0xFFFFE8BB, 0x0000053B, 0x00001F22, 0xFFFFF561, 0x00000373, 0x00001F22, 0xFFFFF561, 0x00000373 },
+ { 0x0213F0FE99183984, 0x00002D42, 0xFFFFEE1D, 0x00000478, 0x000016F0, 0xFFFFFAAE, 0x000002B3, 0x000016F0, 0xFFFFFAAE, 0x000002B3 },
+ { 0x0213EA94DE045124, 0x00002F98, 0xFFFFEB3C, 0x000004F0, 0x00001903, 0xFFFFF818, 0x00000319, 0x00001903, 0xFFFFF818, 0x00000319 },
+ { 0x0213F0FD42D42144, 0x00004081, 0xFFFFDF13, 0x000006F3, 0x00002A6D, 0xFFFFEC1B, 0x00000509, 0x00002A6D, 0xFFFFEC1B, 0x00000509 },
+ { 0x0213EA94DE040904, 0x00002D68, 0xFFFFED21, 0x00000498, 0x00001FF6, 0xFFFFF427, 0x000003B0, 0x00001FF6, 0xFFFFF427, 0x000003B0 },
+ { 0x0213F0FE99023884, 0x00003243, 0xFFFFEA5C, 0x000004FD, 0x000020FB, 0xFFFFF39E, 0x000003C0, 0x000020FB, 0xFFFFF39E, 0x000003C0 },
+ { 0x0213F0FD42D848A4, 0x00002F20, 0xFFFFEC19, 0x000004C6, 0x00001748, 0xFFFFF99F, 0x000002DA, 0x00001748, 0xFFFFF99F, 0x000002DA },
+ { 0x0213F0FE99103984, 0x00002D68, 0xFFFFED21, 0x00000498, 0x00001A43, 0xFFFFF843, 0x000002F9, 0x00001A43, 0xFFFFF843, 0x000002F9 },
+ { 0x0213F0FE990220A4, 0x0000396E, 0xFFFFE616, 0x000005A9, 0x00001A51, 0xFFFFF850, 0x000002FA, 0x00001A51, 0xFFFFF850, 0x000002FA },
+ { 0x0213F0FE99043144, 0x0000305C, 0xFFFFED4B, 0x0000046C, 0x00001CF9, 0xFFFFF7BA, 0x00000304, 0x00001CF9, 0xFFFFF7BA, 0x00000304 },
+ { 0x0213F0FD42DA4164, 0x0000343C, 0xFFFFE869, 0x00000559, 0x00001CE2, 0xFFFFF614, 0x00000359, 0x00001CE2, 0xFFFFF614, 0x00000359 },
+ { 0x0213F0FE99183964, 0x00002782, 0xFFFFF1FE, 0x000003D9, 0x000015DC, 0xFFFFFB8B, 0x00000290, 0x000015DC, 0xFFFFFB8B, 0x00000290 },
+ { 0x0213F0FE991818C4, 0x00002B9C, 0xFFFFEF63, 0x00000443, 0x00001369, 0xFFFFFD51, 0x00000244, 0x00001369, 0xFFFFFD51, 0x00000244 },
+ { 0x0213F0FE990A2084, 0x000035F8, 0xFFFFE743, 0x00000592, 0x000018D8, 0xFFFFF8EE, 0x000002E4, 0x000018D8, 0xFFFFF8EE, 0x000002E4 },
+ { 0x0213EA94DE062844, 0x00002B72, 0xFFFFEF1E, 0x0000043C, 0x00002647, 0xFFFFF092, 0x0000043E, 0x00002647, 0xFFFFF092, 0x0000043E },
+ { 0x0213F0FE99102184, 0x00002EC9, 0xFFFFEC5F, 0x000004B8, 0x000018B6, 0xFFFFF936, 0x000002D8, 0x000018B6, 0xFFFFF936, 0x000002D8 },
+ { 0x0213F0FE99064084, 0x000038A7, 0xFFFFE6AC, 0x00000589, 0x00001C42, 0xFFFFF70B, 0x00000329, 0x00001C42, 0xFFFFF70B, 0x00000329 },
+ { 0x0213F0FE993008A4, 0x00002F6B, 0xFFFFEBF6, 0x000004CF, 0x000018AE, 0xFFFFF928, 0x000002E3, 0x000018AE, 0xFFFFF928, 0x000002E3 },
+ { 0x0213F0FD42DA5104, 0x000029CD, 0xFFFFEEE1, 0x00000459, 0x00001AB5, 0xFFFFF76F, 0x00000324, 0x00001AB5, 0xFFFFF76F, 0x00000324 },
+ { 0x0213EA94DE0638C4, 0x00003921, 0xFFFFE71D, 0x00000577, 0x00001646, 0xFFFFFB24, 0x00000293, 0x00001646, 0xFFFFFB24, 0x00000293 },
+ { 0x0213EA94DE044164, 0x00003940, 0xFFFFE521, 0x000005E8, 0x00001947, 0xFFFFF839, 0x0000030D, 0x00001947, 0xFFFFF839, 0x0000030D },
+ { 0x0213F0FD42D24164, 0x00003DCA, 0xFFFFE211, 0x00000659, 0x0000250E, 0xFFFFF072, 0x00000443, 0x0000250E, 0xFFFFF072, 0x00000443 },
+ { 0x0213F0FE990C0904, 0x00002E95, 0xFFFFEC20, 0x000004C9, 0x000015B4, 0xFFFFFAD3, 0x0000029D, 0x000015B4, 0xFFFFFAD3, 0x0000029D },
+ { 0x0213F0FE99041084, 0x00002C11, 0xFFFFEE6E, 0x00000468, 0x00001901, 0xFFFFF924, 0x000002E7, 0x00001901, 0xFFFFF924, 0x000002E7 },
+ { 0x0213EA94DE062104, 0x0000293F, 0xFFFFF158, 0x000003E6, 0x0000183F, 0xFFFFF9F6, 0x000002D2, 0x0000183F, 0xFFFFF9F6, 0x000002D2 },
+ { 0x0213F0FE990E1104, 0x00002A67, 0xFFFFEF34, 0x0000043E, 0x00001C6F, 0xFFFFF6F1, 0x0000032B, 0x00001C6F, 0xFFFFF6F1, 0x0000032B },
+ { 0x0213EA94DE065124, 0x00002F8D, 0xFFFFEB77, 0x000004DA, 0x00001C0D, 0xFFFFF627, 0x00000365, 0x00001C0D, 0xFFFFF627, 0x00000365 },
+ { 0x0213F0FE990C38C4, 0x00003476, 0xFFFFEA5B, 0x000004E7, 0x00001DBF, 0xFFFFF6C7, 0x00000333, 0x00001DBF, 0xFFFFF6C7, 0x00000333 },
+ { 0x0213F0FE990E0944, 0x00003336, 0xFFFFE92F, 0x00000546, 0x00001614, 0xFFFFFAE0, 0x00000296, 0x00001614, 0xFFFFFAE0, 0x00000296 },
+ { 0x0213F0FE99162164, 0x00002513, 0xFFFFF323, 0x000003BC, 0x000016DB, 0xFFFFFA79, 0x000002CD, 0x000016DB, 0xFFFFFA79, 0x000002CD },
+ { 0x0213F0FE990A2944, 0x000035A7, 0xFFFFE78E, 0x00000584, 0x00001B0D, 0xFFFFF77D, 0x0000031F, 0x00001B0D, 0xFFFFF77D, 0x0000031F },
+ { 0x0213F0FE993238E4, 0x00003171, 0xFFFFEB98, 0x000004C6, 0x00001C76, 0xFFFFF71F, 0x0000032F, 0x00001C76, 0xFFFFF71F, 0x0000032F },
+ { 0x0213F0FD42DA1084, 0x00002C52, 0xFFFFED2E, 0x000004A7, 0x00002182, 0xFFFFF2F4, 0x000003E4, 0x00002182, 0xFFFFF2F4, 0x000003E4 },
+ { 0x0213F0FE99102924, 0x000032E1, 0xFFFFEB39, 0x000004D0, 0x00001B55, 0xFFFFF859, 0x000002FA, 0x00001B55, 0xFFFFF859, 0x000002FA },
+ { 0x0213F0FE991848A4, 0x000029B6, 0xFFFFEFF7, 0x00000430, 0x0000151B, 0xFFFFFBC6, 0x0000027F, 0x0000151B, 0xFFFFFBC6, 0x0000027F },
+ { 0x0213F0FD42DA1964, 0x00002FF7, 0xFFFFEB67, 0x000004DA, 0x000020E9, 0xFFFFF363, 0x000003CE, 0x000020E9, 0xFFFFF363, 0x000003CE },
+ { 0x0213F0FD42DA5124, 0x00003CDD, 0xFFFFE2B2, 0x00000649, 0x00001B18, 0xFFFFF739, 0x00000329, 0x00001B18, 0xFFFFF739, 0x00000329 },
+ { 0x0213F0FE990628A4, 0x00003C82, 0xFFFFE5C6, 0x0000058E, 0x00001F3F, 0xFFFFF5AD, 0x00000361, 0x00001F3F, 0xFFFFF5AD, 0x00000361 },
+ { 0x0213F0FD42DC4084, 0x0000319B, 0xFFFFEA15, 0x0000051B, 0x00001CC9, 0xFFFFF62E, 0x00000358, 0x00001CC9, 0xFFFFF62E, 0x00000358 },
+ { 0x0213EA94DE0638E4, 0x000032B6, 0xFFFFEB2B, 0x000004D6, 0x000018E0, 0xFFFFF966, 0x000002DE, 0x000018E0, 0xFFFFF966, 0x000002DE },
+ { 0x0213EA94DE023984, 0x0000300A, 0xFFFFEBA6, 0x000004D1, 0x00001CFD, 0xFFFFF5F6, 0x0000036D, 0x00001CFD, 0xFFFFF5F6, 0x0000036D },
+ { 0x0213F0FD42D82984, 0x000026A9, 0xFFFFF15D, 0x00000400, 0x00001561, 0xFFFFFB1F, 0x000002A0, 0x00001561, 0xFFFFFB1F, 0x000002A0 },
+ { 0x0213F0FE990E5124, 0x00003123, 0xFFFFEAD2, 0x000004FA, 0x000018CB, 0xFFFFF8F5, 0x000002EC, 0x000018CB, 0xFFFFF8F5, 0x000002EC },
+ { 0x0213F0FE991840C4, 0x00003577, 0xFFFFE935, 0x00000533, 0x000016CD, 0xFFFFFB44, 0x00000289, 0x000016CD, 0xFFFFFB44, 0x00000289 },
+ { 0x0213F0FE99282184, 0x00002875, 0xFFFFF170, 0x000003F3, 0x00001567, 0xFFFFFBD5, 0x00000289, 0x00001567, 0xFFFFFBD5, 0x00000289 },
+ { 0x0213F0FE99084084, 0x00003AE2, 0xFFFFE538, 0x000005C1, 0x00001CB4, 0xFFFFF6A3, 0x0000033C, 0x00001CB4, 0xFFFFF6A3, 0x0000033C },
+ { 0x0213F0FE990C38E4, 0x000031DF, 0xFFFFEC2A, 0x000004A3, 0x00001EF0, 0xFFFFF626, 0x00000352, 0x00001EF0, 0xFFFFF626, 0x00000352 },
+ { 0x0213F0FD42D25144, 0x00004A6A, 0xFFFFDB15, 0x00000758, 0x000027F3, 0xFFFFEEEE, 0x00000479, 0x000027F3, 0xFFFFEEEE, 0x00000479 },
+ { 0x0213EA94DE063904, 0x00002BB9, 0xFFFFEF5D, 0x00000433, 0x00001589, 0xFFFFFB57, 0x00000295, 0x00001589, 0xFFFFFB57, 0x00000295 },
+ { 0x0213F0FE99042164, 0x000033A0, 0xFFFFE98F, 0x00000528, 0x00001CB4, 0xFFFFF706, 0x0000032D, 0x00001CB4, 0xFFFFF706, 0x0000032D },
+ { 0x0213F0FE99163064, 0x0000248E, 0xFFFFF380, 0x000003AC, 0x000016EA, 0xFFFFFA6C, 0x000002CE, 0x000016EA, 0xFFFFFA6C, 0x000002CE },
+ { 0x0213F0FE990221A4, 0x00002FE2, 0xFFFFEB2F, 0x000004E9, 0x00001D4E, 0xFFFFF56B, 0x00000380, 0x00001D4E, 0xFFFFF56B, 0x00000380 },
+ { 0x0213F0FE990A2884, 0x00003283, 0xFFFFE9E7, 0x0000051D, 0x00000694, 0xFFFFFD32, 0x000003C3, 0x00000694, 0xFFFFFD32, 0x000003C3 },
+ { 0x0213F0FD42D850C4, 0x00002EE4, 0xFFFFEBFD, 0x000004D3, 0x0000151A, 0xFFFFFAF6, 0x000002A4, 0x0000151A, 0xFFFFFAF6, 0x000002A4 },
+ { 0x0213F0FD42DC18E4, 0x0000302D, 0xFFFFEB7F, 0x000004DA, 0x00001E6D, 0xFFFFF54B, 0x00000380, 0x00001E6D, 0xFFFFF54B, 0x00000380 },
+ { 0x0213F0FD42DA50C4, 0x000033DA, 0xFFFFE7FB, 0x0000057F, 0x00001DED, 0xFFFFF50E, 0x0000038D, 0x00001DED, 0xFFFFF50E, 0x0000038D },
+ { 0x0213F0FE992C4084, 0x000030B5, 0xFFFFEBB8, 0x000004C4, 0x00001C3F, 0xFFFFF726, 0x0000032A, 0x00001C3F, 0xFFFFF726, 0x0000032A },
+ { 0x0213F0FE990831C4, 0x00003BBD, 0xFFFFE55C, 0x000005B8, 0x000019DB, 0xFFFFF8BB, 0x000002EF, 0x000019DB, 0xFFFFF8BB, 0x000002EF },
+ { 0x0213F0FE990E3884, 0x00002964, 0xFFFFF051, 0x0000040E, 0x000025CD, 0xFFFFF11B, 0x0000041F, 0x000025CD, 0xFFFFF11B, 0x0000041F },
+ { 0x0213F0FD42DC4884, 0x000033F5, 0xFFFFE863, 0x00000560, 0x00001BCE, 0xFFFFF689, 0x0000034B, 0x00001BCE, 0xFFFFF689, 0x0000034B },
+ { 0x0213F0FE990A2864, 0x00003294, 0xFFFFE924, 0x00000548, 0x00001D41, 0xFFFFF580, 0x0000037D, 0x00001D41, 0xFFFFF580, 0x0000037D },
+ { 0x0213F0FD42DC39A4, 0x000034FB, 0xFFFFE7FE, 0x0000056D, 0x00001CB1, 0xFFFFF635, 0x00000357, 0x00001CB1, 0xFFFFF635, 0x00000357 },
+ { 0x0213F0FE990A10A4, 0x00002E28, 0xFFFFEBB9, 0x000004E0, 0x00001B20, 0xFFFFF6E3, 0x0000033C, 0x00001B20, 0xFFFFF6E3, 0x0000033C },
+ { 0x0213F0FD42DA1904, 0x00002799, 0xFFFFF0F4, 0x000003FC, 0x00001C9D, 0xFFFFF6A1, 0x00000345, 0x00001C9D, 0xFFFFF6A1, 0x00000345 },
+ { 0x0213F0FE99064104, 0x00003AEA, 0xFFFFE5DB, 0x0000059D, 0x00001B61, 0xFFFFF7F0, 0x00000301, 0x00001B61, 0xFFFFF7F0, 0x00000301 },
+ { 0x0213EA94DE041984, 0x000031F6, 0xFFFFEAB8, 0x000004F3, 0x00001D90, 0xFFFFF622, 0x00000359, 0x00001D90, 0xFFFFF622, 0x00000359 },
+ { 0x0213F0FE990C4064, 0x000031B8, 0xFFFFEA61, 0x0000050F, 0x0000199D, 0xFFFFF87C, 0x000002FD, 0x0000199D, 0xFFFFF87C, 0x000002FD },
+ { 0x0213F0FD42D23144, 0x00004514, 0xFFFFDDFF, 0x000006F6, 0x000022CD, 0xFFFFF29F, 0x000003D9, 0x000022CD, 0xFFFFF29F, 0x000003D9 },
+ { 0x0213EA94DE043164, 0x00002F30, 0xFFFFECB8, 0x000004A0, 0x00001B07, 0xFFFFF7E2, 0x00000313, 0x00001B07, 0xFFFFF7E2, 0x00000313 },
+ { 0x0213F0FD42DC30A4, 0x0000383B, 0xFFFFE702, 0x00000581, 0x00001A08, 0xFFFFF8CA, 0x000002E2, 0x00001A08, 0xFFFFF8CA, 0x000002E2 },
+ { 0x0213F0FE99022164, 0x00002CC5, 0xFFFFEDF8, 0x00000465, 0x00001F47, 0xFFFFF4B2, 0x00000393, 0x00001F47, 0xFFFFF4B2, 0x00000393 },
+ { 0x0213F0FE991621C4, 0x00002304, 0xFFFFF453, 0x00000384, 0x0000170A, 0xFFFFFA3F, 0x000002CE, 0x0000170A, 0xFFFFFA3F, 0x000002CE },
+ { 0x0213F0FE990A5124, 0x0000337E, 0xFFFFE850, 0x0000056E, 0x00001BDD, 0xFFFFF668, 0x00000353, 0x00001BDD, 0xFFFFF668, 0x00000353 },
+ { 0x0213F0FE990E4924, 0x00002E2F, 0xFFFFEC9B, 0x000004AE, 0x00001C4D, 0xFFFFF6D3, 0x00000338, 0x00001C4D, 0xFFFFF6D3, 0x00000338 },
+ { 0x0213EA94DE061124, 0x00002DDD, 0xFFFFEDA4, 0x00000477, 0x00002010, 0xFFFFF4BB, 0x00000390, 0x00002010, 0xFFFFF4BB, 0x00000390 },
+ { 0x0213F0FD42DA48E4, 0x0000290C, 0xFFFFEF61, 0x00000445, 0x00002133, 0xFFFFF324, 0x000003D8, 0x00002133, 0xFFFFF324, 0x000003D8 },
+ { 0x0213F0FE99062924, 0x0000371E, 0xFFFFE8D5, 0x00000524, 0x00001C3A, 0xFFFFF7AE, 0x00000314, 0x00001C3A, 0xFFFFF7AE, 0x00000314 },
+ { 0x0213F0FD42D838E4, 0x00002A58, 0xFFFFF007, 0x00000429, 0x000018A6, 0xFFFFF98F, 0x000002E1, 0x000018A6, 0xFFFFF98F, 0x000002E1 },
+ { 0x0213F0FE99023084, 0x00002FED, 0xFFFFEC48, 0x000004AA, 0x00001E9D, 0xFFFFF584, 0x00000370, 0x00001E9D, 0xFFFFF584, 0x00000370 },
+ { 0x0213F0FE99181884, 0x00002829, 0xFFFFF15F, 0x000003F7, 0x0000157E, 0xFFFFFBD4, 0x00000282, 0x0000157E, 0xFFFFFBD4, 0x00000282 },
+ { 0x0213F0FE99101924, 0x000030CF, 0xFFFFEB8D, 0x000004CE, 0x00001A4C, 0xFFFFF868, 0x000002F7, 0x00001A4C, 0xFFFFF868, 0x000002F7 },
+ { 0x0213F0FD42DA2084, 0x00002C8F, 0xFFFFEDD2, 0x0000047D, 0x00001CCE, 0xFFFFF6A1, 0x00000343, 0x00001CCE, 0xFFFFF6A1, 0x00000343 },
+ { 0x0213F0FE99182164, 0x00002A84, 0xFFFFEFBA, 0x0000043E, 0x000015EF, 0xFFFFFB4B, 0x0000029E, 0x000015EF, 0xFFFFFB4B, 0x0000029E },
+ { 0x0213F0FE990C28A4, 0x000034CA, 0xFFFFEA08, 0x000004FF, 0x00001C19, 0xFFFFF7ED, 0x00000309, 0x00001C19, 0xFFFFF7ED, 0x00000309 },
+ { 0x0213F0FE991639A4, 0x00002187, 0xFFFFF4B0, 0x0000037E, 0x0000154A, 0xFFFFFB0C, 0x000002AE, 0x0000154A, 0xFFFFFB0C, 0x000002AE },
+ { 0x0213F0FD42DA3844, 0x00002F4F, 0xFFFFEB3C, 0x000004F8, 0x0000181F, 0xFFFFF92D, 0x000002DF, 0x0000181F, 0xFFFFF92D, 0x000002DF },
+ { 0x0213F0FE990410E4, 0x0000290C, 0xFFFFF0B1, 0x000003FC, 0x00001DB0, 0xFFFFF636, 0x00000355, 0x00001DB0, 0xFFFFF636, 0x00000355 },
+ { 0x0213F0FE990A1064, 0x000034C1, 0xFFFFE888, 0x0000055A, 0x000019BF, 0xFFFFF881, 0x000002FB, 0x000019BF, 0xFFFFF881, 0x000002FB },
+ { 0x0213F0FD42DC18C4, 0x00003139, 0xFFFFEA98, 0x00000504, 0x000019F2, 0xFFFFF820, 0x0000030B, 0x000019F2, 0xFFFFF820, 0x0000030B },
+ { 0x0213F0FD42D83144, 0x00002CAC, 0xFFFFEEB2, 0x00000458, 0x0000152C, 0xFFFFFBEF, 0x0000027B, 0x0000152C, 0xFFFFFBEF, 0x0000027B },
+ { 0x0213F0FE992C38E4, 0x00003577, 0xFFFFE99C, 0x0000050D, 0x00001E64, 0xFFFFF679, 0x0000033F, 0x00001E64, 0xFFFFF679, 0x0000033F },
+ { 0x0213F0FD42DA4104, 0x0000263A, 0xFFFFF1E4, 0x000003D4, 0x00001F68, 0xFFFFF4ED, 0x00000386, 0x00001F68, 0xFFFFF4ED, 0x00000386 },
+ { 0x0213F0FD42D81984, 0x00002CE9, 0xFFFFED63, 0x00000497, 0x00001810, 0xFFFFF94D, 0x000002E3, 0x00001810, 0xFFFFF94D, 0x000002E3 },
+ { 0x0213EA94DE044104, 0x0000318A, 0xFFFFEAC8, 0x000004F5, 0x0000195C, 0xFFFFF896, 0x000002FB, 0x0000195C, 0xFFFFF896, 0x000002FB },
+ { 0x0213F0FD42D83904, 0x00002C41, 0xFFFFEEC6, 0x0000045D, 0x000017DD, 0xFFFFFA16, 0x000002CB, 0x000017DD, 0xFFFFFA16, 0x000002CB },
+ { 0x0213F0FE990231A4, 0x00002DD4, 0xFFFFEC98, 0x000004AD, 0x00001BD7, 0xFFFFF69F, 0x00000347, 0x00001BD7, 0xFFFFF69F, 0x00000347 },
+ { 0x0213F0FD42DA3944, 0x00003351, 0xFFFFE9B2, 0x0000051A, 0x00001CA1, 0xFFFFF6A4, 0x00000341, 0x00001CA1, 0xFFFFF6A4, 0x00000341 },
+ { 0x0213F0FE99021104, 0x0000322D, 0xFFFFE9BE, 0x00000527, 0x00001CF9, 0xFFFFF5EB, 0x00000366, 0x00001CF9, 0xFFFFF5EB, 0x00000366 },
+ { 0x0213F0FE990C28C4, 0x00003678, 0xFFFFE9A8, 0x00000503, 0x00001AD4, 0xFFFFF8F6, 0x000002E3, 0x00001AD4, 0xFFFFF8F6, 0x000002E3 },
+ { 0x0213F0FE99161924, 0x0000260E, 0xFFFFF2C1, 0x000003CA, 0x00001139, 0xFFFFFE48, 0x00000236, 0x00001139, 0xFFFFFE48, 0x00000236 },
+ { 0x0213F0FE990A2164, 0x000033D3, 0xFFFFE872, 0x00000565, 0x00001B72, 0xFFFFF713, 0x00000332, 0x00001B72, 0xFFFFF713, 0x00000332 },
+ { 0x0213F0FE99323844, 0x0000309B, 0xFFFFEB42, 0x000004E4, 0x00001918, 0xFFFFF8C8, 0x000002F2, 0x00001918, 0xFFFFF8C8, 0x000002F2 },
+ { 0x0213F0FE99182864, 0x000028B8, 0xFFFFF105, 0x00000402, 0x000018BB, 0xFFFFF9BC, 0x000002D3, 0x000018BB, 0xFFFFF9BC, 0x000002D3 },
+ { 0x0213F0FE990A1884, 0x00003123, 0xFFFFE9D1, 0x00000534, 0x00001B19, 0xFFFFF6FE, 0x0000033C, 0x00001B19, 0xFFFFF6FE, 0x0000033C },
+ { 0x0213F0FE99022144, 0x00003216, 0xFFFFEA8E, 0x000004F6, 0x00001F72, 0xFFFFF4CE, 0x0000038B, 0x00001F72, 0xFFFFF4CE, 0x0000038B },
+ { 0x0213F0FE99162964, 0x00002564, 0xFFFFF32D, 0x000003B6, 0x00001685, 0xFFFFFADB, 0x000002BB, 0x00001685, 0xFFFFFADB, 0x000002BB },
+ { 0x0213F0FD42DA2924, 0x00002E60, 0xFFFFED13, 0x00000497, 0x00001CA5, 0xFFFFF6B9, 0x00000346, 0x00001CA5, 0xFFFFF6B9, 0x00000346 },
+ { 0x0213F0FE990E39A4, 0x0000336D, 0xFFFFE934, 0x0000053B, 0x00001B3E, 0xFFFFF763, 0x00000327, 0x00001B3E, 0xFFFFF763, 0x00000327 },
+ { 0x0213F0FE99101084, 0x0000274A, 0xFFFFF119, 0x000003FA, 0x00001D75, 0xFFFFF5CD, 0x0000036F, 0x00001D75, 0xFFFFF5CD, 0x0000036F },
+ { 0x0213F0FD42DA2164, 0x0000366B, 0xFFFFE70A, 0x0000059A, 0x00001ED8, 0xFFFFF501, 0x00000389, 0x00001ED8, 0xFFFFF501, 0x00000389 },
+ { 0x0213F0FE99223964, 0x00003164, 0xFFFFEAB4, 0x000004FA, 0x00001C52, 0xFFFFF6E0, 0x00000336, 0x00001C52, 0xFFFFF6E0, 0x00000336 },
+ { 0x0213F0FD42D23064, 0x00004224, 0xFFFFDF7F, 0x000006C1, 0x00002A52, 0xFFFFED5E, 0x000004BB, 0x00002A52, 0xFFFFED5E, 0x000004BB },
+ { 0x0213F0FE99102864, 0x000030E3, 0xFFFFEB07, 0x000004ED, 0x00001FD3, 0xFFFFF46D, 0x000003A1, 0x00001FD3, 0xFFFFF46D, 0x000003A1 },
+ { 0x0213F0FD42D82884, 0x00002AEB, 0xFFFFEF1B, 0x00000454, 0x00001829, 0xFFFFF995, 0x000002DD, 0x00001829, 0xFFFFF995, 0x000002DD },
+ { 0x0213F0FD42DC50E4, 0x0000346B, 0xFFFFE7A2, 0x0000058B, 0x000020C5, 0xFFFFF2E8, 0x000003EC, 0x000020C5, 0xFFFFF2E8, 0x000003EC },
+ { 0x0213F0FD42DC4164, 0x000039CF, 0xFFFFE5D7, 0x000005A9, 0x00001D66, 0xFFFFF5D6, 0x00000366, 0x00001D66, 0xFFFFF5D6, 0x00000366 },
+ { 0x0213F0FE990418E4, 0x000034AC, 0xFFFFE9AE, 0x00000515, 0x00001A28, 0xFFFFF904, 0x000002DC, 0x00001A28, 0xFFFFF904, 0x000002DC },
+ { 0x0213F0FD42DC2084, 0x00002D68, 0xFFFFED21, 0x00000498, 0x00001C6F, 0xFFFFF686, 0x0000034C, 0x00001C6F, 0xFFFFF686, 0x0000034C },
+ { 0x0213F0FE990820C4, 0x0000328B, 0xFFFFEBA1, 0x000004B4, 0x00001DA3, 0xFFFFF683, 0x00000349, 0x00001DA3, 0xFFFFF683, 0x00000349 },
+ { 0x0213F0FE991828C4, 0x000027DC, 0xFFFFF295, 0x000003BF, 0x000019C1, 0xFFFFF98E, 0x000002E8, 0x000019C1, 0xFFFFF98E, 0x000002E8 },
+ { 0x0213F0FE99184084, 0x00002756, 0xFFFFF1D7, 0x000003DF, 0x000015D9, 0xFFFFFB51, 0x00000298, 0x000015D9, 0xFFFFFB51, 0x00000298 },
+ { 0x0213F0FE99083884, 0x00003526, 0xFFFFE907, 0x00000526, 0x000017AB, 0xFFFFFA12, 0x000002AB, 0x000017AB, 0xFFFFFA12, 0x000002AB },
+ { 0x0213F0FD42DA18E4, 0x0000351B, 0xFFFFE8B7, 0x00000540, 0x00001A86, 0xFFFFF821, 0x00000303, 0x00001A86, 0xFFFFF821, 0x00000303 },
+ { 0x0213F0FE99164144, 0x000024B2, 0xFFFFF34E, 0x000003B1, 0x000018E2, 0xFFFFF926, 0x000002FC, 0x000018E2, 0xFFFFF926, 0x000002FC },
+ { 0x0213F0FD42D828A4, 0x00002F36, 0xFFFFED5D, 0x00000486, 0x0000157A, 0xFFFFFB85, 0x00000293, 0x0000157A, 0xFFFFFB85, 0x00000293 },
+ { 0x0213F0FD42DC50C4, 0x00003A6E, 0xFFFFE456, 0x000005FD, 0x00001F68, 0xFFFFF3D1, 0x000003C3, 0x00001F68, 0xFFFFF3D1, 0x000003C3 },
+ { 0x0213F0FE990A31A4, 0x00002BC3, 0xFFFFED2D, 0x000004A7, 0x00001C3F, 0xFFFFF609, 0x00000364, 0x00001C3F, 0xFFFFF609, 0x00000364 },
+ { 0x0213F0FE990E2084, 0x000032E1, 0xFFFFEA83, 0x000004F6, 0x00001B37, 0xFFFFF842, 0x000002F5, 0x00001B37, 0xFFFFF842, 0x000002F5 },
+ { 0x0213F0FD42D83184, 0x000028E3, 0xFFFFF07F, 0x00000412, 0x00001676, 0xFFFFFA68, 0x000002BE, 0x00001676, 0xFFFFFA68, 0x000002BE },
+ { 0x0213F0FD42D21104, 0x0000444C, 0xFFFFDDAD, 0x00000712, 0x00002634, 0xFFFFEF89, 0x0000046C, 0x00002634, 0xFFFFEF89, 0x0000046C },
+ { 0x0213F0FE990418C4, 0x00003121, 0xFFFFEBBB, 0x000004C6, 0x00001C98, 0xFFFFF72B, 0x0000032D, 0x00001C98, 0xFFFFF72B, 0x0000032D },
+ { 0x0213F0FD42D840A4, 0x00002C31, 0xFFFFEDC4, 0x00000490, 0x0000162D, 0xFFFFFA8E, 0x000002B4, 0x0000162D, 0xFFFFFA8E, 0x000002B4 },
+ { 0x0213F0FD42DA18C4, 0x00002749, 0xFFFFF112, 0x000003FC, 0x00001C85, 0xFFFFF6B8, 0x00000342, 0x00001C85, 0xFFFFF6B8, 0x00000342 },
+ { 0x0213F0FE99044104, 0x00003159, 0xFFFFEB99, 0x000004C2, 0x00001BD0, 0xFFFFF7CA, 0x00000307, 0x00001BD0, 0xFFFFF7CA, 0x00000307 },
+ { 0x0213F0FE99164164, 0x00002610, 0xFFFFF1FD, 0x000003EC, 0x000016BE, 0xFFFFFA53, 0x000002CB, 0x000016BE, 0xFFFFFA53, 0x000002CB },
+ { 0x0213F0FE99023184, 0x000037B5, 0xFFFFE63D, 0x000005B5, 0x00002285, 0xFFFFF25D, 0x000003F7, 0x00002285, 0xFFFFF25D, 0x000003F7 },
+ { 0x0213F0FE990A28A4, 0x00002FEE, 0xFFFFEB47, 0x000004EF, 0x00001CBE, 0xFFFFF64E, 0x00000358, 0x00001CBE, 0xFFFFF64E, 0x00000358 },
+ { 0x0213F0FE99105104, 0x00002E90, 0xFFFFEC48, 0x000004C0, 0x00001A47, 0xFFFFF7D1, 0x0000031A, 0x00001A47, 0xFFFFF7D1, 0x0000031A },
+ { 0x0213F0FD42DA4084, 0x000034AB, 0xFFFFE84A, 0x00000559, 0x00001A72, 0xFFFFF79A, 0x0000031C, 0x00001A72, 0xFFFFF79A, 0x0000031C },
+ { 0x0213F0FE99183884, 0x00002F7B, 0xFFFFECFC, 0x0000049C, 0x00001814, 0xFFFFFA22, 0x000002C2, 0x00001814, 0xFFFFFA22, 0x000002C2 },
+ { 0x0213F0FE99021964, 0x00003618, 0xFFFFE709, 0x00000596, 0x00001EBF, 0xFFFFF482, 0x000003A5, 0x00001EBF, 0xFFFFF482, 0x000003A5 },
+ { 0x0213EA94DE024904, 0x0000341B, 0xFFFFE8B2, 0x0000054F, 0x00001D26, 0xFFFFF578, 0x00000388, 0x00001D26, 0xFFFFF578, 0x00000388 },
+ { 0x0213F0FE99102144, 0x000030F6, 0xFFFFEB89, 0x000004CD, 0x000019C0, 0xFFFFF8CC, 0x000002E6, 0x000019C0, 0xFFFFF8CC, 0x000002E6 },
+ { 0x0213F0FE992841A4, 0x00002B76, 0xFFFFEF6C, 0x00000444, 0x00001563, 0xFFFFFBBE, 0x0000028D, 0x00001563, 0xFFFFFBBE, 0x0000028D },
+ { 0x0213F0FD42D81864, 0x00002BA2, 0xFFFFEE31, 0x0000047F, 0x00001A3D, 0xFFFFF7F3, 0x00000320, 0x00001A3D, 0xFFFFF7F3, 0x00000320 },
+ { 0x0213F0FE992C48E4, 0x00003545, 0xFFFFE87A, 0x0000054A, 0x00001B5A, 0xFFFFF7B0, 0x0000030C, 0x00001B5A, 0xFFFFF7B0, 0x0000030C },
+ { 0x0213EA94DE042944, 0x00003879, 0xFFFFE73F, 0x00000578, 0x00001649, 0xFFFFFB57, 0x00000283, 0x00001649, 0xFFFFFB57, 0x00000283 },
+ { 0x0213F0FD42D840C4, 0x00002772, 0xFFFFF0F1, 0x00000410, 0x0000142F, 0xFFFFFBCF, 0x00000287, 0x0000142F, 0xFFFFFBCF, 0x00000287 },
+ { 0x0213F0FD42DA3184, 0x00003228, 0xFFFFE98E, 0x00000535, 0x00001F48, 0xFFFFF495, 0x00000399, 0x00001F48, 0xFFFFF495, 0x00000399 },
+ { 0x0213F0FE990E40E4, 0x00002887, 0xFFFFF119, 0x000003E8, 0x000021AA, 0xFFFFF3F5, 0x000003A5, 0x000021AA, 0xFFFFF3F5, 0x000003A5 },
+ { 0x0213F0FD42DA28A4, 0x0000301F, 0xFFFFEBB2, 0x000004D2, 0x00001C02, 0xFFFFF736, 0x0000032B, 0x00001C02, 0xFFFFF736, 0x0000032B },
+ { 0x0213F0FE991820A4, 0x00002E13, 0xFFFFEE3F, 0x00000468, 0x000016AC, 0xFFFFFB32, 0x0000029E, 0x000016AC, 0xFFFFFB32, 0x0000029E },
+ { 0x0213F0FE99044924, 0x00003478, 0xFFFFE8F9, 0x00000538, 0x00001DAB, 0xFFFFF645, 0x00000345, 0x00001DAB, 0xFFFFF645, 0x00000345 },
+ { 0x0213F0FE990608C4, 0x000030C6, 0xFFFFEB6C, 0x000004D4, 0x0000184A, 0xFFFFF934, 0x000002E1, 0x0000184A, 0xFFFFF934, 0x000002E1 },
+ { 0x0213F0FE990A2044, 0x00002F1B, 0xFFFFEBD3, 0x000004D3, 0x000019E7, 0xFFFFF813, 0x0000030D, 0x000019E7, 0xFFFFF813, 0x0000030D },
+ { 0x0213F0FE99023904, 0x00003214, 0xFFFFEAE9, 0x000004E0, 0x0000178F, 0xFFFFFA1C, 0x000002B1, 0x0000178F, 0xFFFFFA1C, 0x000002B1 },
+ { 0x0213F0FD42DC3144, 0x0000399C, 0xFFFFE738, 0x0000055E, 0x00001EA1, 0xFFFFF5E7, 0x0000035A, 0x00001EA1, 0xFFFFF5E7, 0x0000035A },
+ { 0x0213F0FE990650C4, 0x00003A01, 0xFFFFE5B2, 0x000005B6, 0x00001D95, 0xFFFFF5D2, 0x0000036A, 0x00001D95, 0xFFFFF5D2, 0x0000036A },
+ { 0x0213F0FE99043884, 0x0000310D, 0xFFFFEB78, 0x000004D0, 0x00001C06, 0xFFFFF76E, 0x0000031A, 0x00001C06, 0xFFFFF76E, 0x0000031A },
+ { 0x0213F0FE99063864, 0x00003CD1, 0xFFFFE42F, 0x000005EB, 0x00001933, 0xFFFFF91F, 0x000002D4, 0x00001933, 0xFFFFF91F, 0x000002D4 },
+ { 0x0213F0FD42DA3164, 0x00003119, 0xFFFFEB1B, 0x000004E1, 0x00001FC7, 0xFFFFF46A, 0x000003A2, 0x00001FC7, 0xFFFFF46A, 0x000003A2 },
+ { 0x0213EA94DE0648A4, 0x0000390D, 0xFFFFE566, 0x000005D8, 0x00001EC6, 0xFFFFF4DC, 0x00000391, 0x00001EC6, 0xFFFFF4DC, 0x00000391 },
+ { 0x0213F0FD42DA10C4, 0x00003446, 0xFFFFE858, 0x00000561, 0x00001FDB, 0xFFFFF3FF, 0x000003B9, 0x00001FDB, 0xFFFFF3FF, 0x000003B9 },
+ { 0x0213F0FE99044904, 0x000032BA, 0xFFFFEA07, 0x00000511, 0x00001B25, 0xFFFFF7C9, 0x0000030D, 0x00001B25, 0xFFFFF7C9, 0x0000030D },
+ { 0x0213F0FE990E1864, 0x00002CCF, 0xFFFFEDE5, 0x00000478, 0x00001BC8, 0xFFFFF761, 0x00000326, 0x00001BC8, 0xFFFFF761, 0x00000326 },
+ { 0x0213F0FE99062984, 0x0000400E, 0xFFFFE1CB, 0x00000652, 0x00001AF8, 0xFFFFF7B9, 0x00000312, 0x00001AF8, 0xFFFFF7B9, 0x00000312 },
+ { 0x0213F0FE990408E4, 0x00002F24, 0xFFFFEC2A, 0x000004C7, 0x00001B94, 0xFFFFF748, 0x00000333, 0x00001B94, 0xFFFFF748, 0x00000333 },
+ { 0x0213F0FD42D21924, 0x00003FDA, 0xFFFFE1C1, 0x0000064B, 0x00002427, 0xFFFFF180, 0x0000040C, 0x00002427, 0xFFFFF180, 0x0000040C },
+ { 0x0213F0FE990A18C4, 0x00002F6B, 0xFFFFEBA7, 0x000004DD, 0x00001C25, 0xFFFFF6C1, 0x00000344, 0x00001C25, 0xFFFFF6C1, 0x00000344 },
+ { 0x0213F0FE99182104, 0x00002A53, 0xFFFFF0EE, 0x00000402, 0x000017C6, 0xFFFFFAA0, 0x000002BF, 0x000017C6, 0xFFFFFAA0, 0x000002BF },
+ { 0x0213F0FE99105144, 0x000031F4, 0xFFFFEA34, 0x00000517, 0x000016FF, 0xFFFFFA4E, 0x000002AC, 0x000016FF, 0xFFFFFA4E, 0x000002AC },
+ { 0x0213F0FE99322144, 0x00002E24, 0xFFFFED46, 0x00000489, 0x00001712, 0xFFFFFA5D, 0x000002AC, 0x00001712, 0xFFFFFA5D, 0x000002AC },
+ { 0x0213F0FE99182824, 0x000028CD, 0xFFFFF0E3, 0x0000040E, 0x00001606, 0xFFFFFB37, 0x000002A4, 0x00001606, 0xFFFFFB37, 0x000002A4 },
+ { 0x0213F0FE990220C4, 0x00003184, 0xFFFFEB88, 0x000004C3, 0x000018DA, 0xFFFFF939, 0x000002DB, 0x000018DA, 0xFFFFF939, 0x000002DB },
+ { 0x0213F0FE99162124, 0x0000239B, 0xFFFFF470, 0x00000386, 0x00001714, 0xFFFFFA9F, 0x000002C8, 0x00001714, 0xFFFFFA9F, 0x000002C8 },
+ { 0x0213F0FD42DC38E4, 0x00003641, 0xFFFFE92B, 0x00000515, 0x00001BE2, 0xFFFFF795, 0x0000031B, 0x00001BE2, 0xFFFFF795, 0x0000031B },
+ { 0x0213F0FE992C1144, 0x00003278, 0xFFFFEA17, 0x00000510, 0x00001B71, 0xFFFFF778, 0x0000031D, 0x00001B71, 0xFFFFF778, 0x0000031D },
+ { 0x0213F0FE99062844, 0x000035B9, 0xFFFFE8DA, 0x0000052D, 0x00001A6A, 0xFFFFF83B, 0x000002FF, 0x00001A6A, 0xFFFFF83B, 0x000002FF },
+ { 0x0213F0FE990E18C4, 0x00002E5E, 0xFFFFED32, 0x0000048B, 0x00001E7D, 0xFFFFF60E, 0x0000034E, 0x00001E7D, 0xFFFFF60E, 0x0000034E },
+ { 0x0213F0FE991019A4, 0x00003178, 0xFFFFEA52, 0x00000513, 0x00001AD0, 0xFFFFF793, 0x0000031F, 0x00001AD0, 0xFFFFF793, 0x0000031F },
+ { 0x0213F0FD42D44104, 0x00003A2C, 0xFFFFE346, 0x00000641, 0x000023D0, 0xFFFFF0CE, 0x00000433, 0x000023D0, 0xFFFFF0CE, 0x00000433 },
+ { 0x0213F0FD42D818C4, 0x000028FD, 0xFFFFF02A, 0x0000042B, 0x0000152B, 0xFFFFFB90, 0x00000289, 0x0000152B, 0xFFFFFB90, 0x00000289 },
+ { 0x0213F0FE990E3084, 0x000030DE, 0xFFFFEBDF, 0x000004BE, 0x00001CDC, 0xFFFFF747, 0x0000031C, 0x00001CDC, 0xFFFFF747, 0x0000031C },
+ { 0x0213F0FE99021944, 0x000036CB, 0xFFFFE6EE, 0x00000596, 0x00002096, 0xFFFFF3C2, 0x000003BB, 0x00002096, 0xFFFFF3C2, 0x000003BB },
+ { 0x0213F0FE990C48C4, 0x00003172, 0xFFFFEAC1, 0x000004F4, 0x00001C87, 0xFFFFF6CD, 0x00000337, 0x00001C87, 0xFFFFF6CD, 0x00000337 },
+ { 0x0213F0FD42D24864, 0x00004A18, 0xFFFFDB34, 0x00000758, 0x0000213C, 0xFFFFF3A2, 0x000003AC, 0x0000213C, 0xFFFFF3A2, 0x000003AC },
+ { 0x0213F0FE99022104, 0x000031F3, 0xFFFFEB73, 0x000004C6, 0x00001B23, 0xFFFFF7CB, 0x0000031A, 0x00001B23, 0xFFFFF7CB, 0x0000031A },
+ { 0x0213F0FE990A2924, 0x000031C0, 0xFFFFEABA, 0x000004F7, 0x00001A5A, 0xFFFFF845, 0x000002FF, 0x00001A5A, 0xFFFFF845, 0x000002FF },
+ { 0x0213F0FE99104944, 0x00003B77, 0xFFFFE3B3, 0x00000623, 0x00001BCA, 0xFFFFF6F8, 0x00000333, 0x00001BCA, 0xFFFFF6F8, 0x00000333 },
+ { 0x0213F0FE990A3944, 0x000035AF, 0xFFFFE76D, 0x00000588, 0x00001C16, 0xFFFFF6AB, 0x00000341, 0x00001C16, 0xFFFFF6AB, 0x00000341 },
+ { 0x0213EA94DE0438C4, 0x000032AD, 0xFFFFEA8E, 0x000004F8, 0x00001A3A, 0xFFFFF832, 0x0000030E, 0x00001A3A, 0xFFFFF832, 0x0000030E },
+ { 0x0213F0FE99104884, 0x00002E92, 0xFFFFEBD2, 0x000004DA, 0x00001E04, 0xFFFFF51E, 0x0000038A, 0x00001E04, 0xFFFFF51E, 0x0000038A },
+ { 0x0213F0FD42D440A4, 0x00003E57, 0xFFFFE0F7, 0x0000068F, 0x000021F1, 0xFFFFF1C6, 0x00000411, 0x000021F1, 0xFFFFF1C6, 0x00000411 },
+ { 0x0213F0FE990821A4, 0x00003598, 0xFFFFE8BB, 0x00000535, 0x00001B62, 0xFFFFF764, 0x00000326, 0x00001B62, 0xFFFFF764, 0x00000326 },
+ { 0x0213F0FE990A3884, 0x00002B15, 0xFFFFEDEC, 0x00000487, 0x00001E8B, 0xFFFFF4AB, 0x0000039F, 0x00001E8B, 0xFFFFF4AB, 0x0000039F },
+ { 0x0213EA94DE060904, 0x0000267E, 0xFFFFF1A7, 0x000003E1, 0x000021C1, 0xFFFFF2E9, 0x000003EA, 0x000021C1, 0xFFFFF2E9, 0x000003EA },
+ { 0x0213EA94DE0239A4, 0x00002ED7, 0xFFFFEC88, 0x000004A6, 0x00001DEC, 0xFFFFF57C, 0x00000378, 0x00001DEC, 0xFFFFF57C, 0x00000378 },
+ { 0x0213EA94DE0441A4, 0x00003365, 0xFFFFE946, 0x00000536, 0x000019E9, 0xFFFFF7E0, 0x0000031D, 0x000019E9, 0xFFFFF7E0, 0x0000031D },
+ { 0x0213F0FE991818E4, 0x000029A4, 0xFFFFF0FD, 0x000003FE, 0x0000163F, 0xFFFFFB68, 0x00000299, 0x0000163F, 0xFFFFFB68, 0x00000299 },
+ { 0x0213EA94DE021904, 0x0000348D, 0xFFFFE9F7, 0x00000509, 0x000017A0, 0xFFFFFA59, 0x000002B6, 0x000017A0, 0xFFFFFA59, 0x000002B6 },
+ { 0x0213F0FE990610C4, 0x00003144, 0xFFFFEB23, 0x000004D9, 0x00001C9B, 0xFFFFF664, 0x00000351, 0x00001C9B, 0xFFFFF664, 0x00000351 },
+ { 0x0213EA94DE0620E4, 0x00002E95, 0xFFFFEE1A, 0x00000463, 0x00001707, 0xFFFFFAB7, 0x000002B3, 0x00001707, 0xFFFFFAB7, 0x000002B3 },
+ { 0x0213F0FD42D41864, 0x0000489C, 0xFFFFDA43, 0x000007AC, 0x00002866, 0xFFFFED6B, 0x000004D0, 0x00002866, 0xFFFFED6B, 0x000004D0 },
+ { 0x0213F0FE99161844, 0x00002895, 0xFFFFF10A, 0x0000040A, 0x000013E9, 0xFFFFFC9F, 0x0000026E, 0x000013E9, 0xFFFFFC9F, 0x0000026E },
+ { 0x0213F0FE99061964, 0x000033A0, 0xFFFFE9B1, 0x00000510, 0x00001D96, 0xFFFFF5AE, 0x0000036F, 0x00001D96, 0xFFFFF5AE, 0x0000036F },
+ { 0x0213F0FE99083984, 0x0000327C, 0xFFFFEAEA, 0x000004DD, 0x00001D45, 0xFFFFF649, 0x00000356, 0x00001D45, 0xFFFFF649, 0x00000356 },
+ { 0x0213EA94DE0248A4, 0x000031DF, 0xFFFFE9AB, 0x0000052F, 0x000019C8, 0xFFFFF7B7, 0x00000321, 0x000019C8, 0xFFFFF7B7, 0x00000321 },
+ { 0x0213F0FE991640A4, 0x00002BCC, 0xFFFFEEF4, 0x0000045C, 0x000015CD, 0xFFFFFB58, 0x0000029E, 0x000015CD, 0xFFFFFB58, 0x0000029E },
+ { 0x0213F0FE990638E4, 0x00003534, 0xFFFFEA10, 0x000004EB, 0x00001BB6, 0xFFFFF7B9, 0x00000314, 0x00001BB6, 0xFFFFF7B9, 0x00000314 },
+ { 0x0213F0FE99041984, 0x00002F4F, 0xFFFFEC35, 0x000004B9, 0x0000205D, 0xFFFFF47F, 0x00000392, 0x0000205D, 0xFFFFF47F, 0x00000392 },
+ { 0x0213F0FE990C20A4, 0x00003295, 0xFFFFEB1C, 0x000004D6, 0x000019C1, 0xFFFFF931, 0x000002D5, 0x000019C1, 0xFFFFF931, 0x000002D5 },
+ { 0x0213F0FE99024144, 0x00003557, 0xFFFFE7F7, 0x00000568, 0x00002342, 0xFFFFF1F9, 0x00000405, 0x00002342, 0xFFFFF1F9, 0x00000405 },
+ { 0x0213F0FE990450C4, 0x00003487, 0xFFFFE872, 0x0000055D, 0x000019D7, 0xFFFFF823, 0x0000030C, 0x000019D7, 0xFFFFF823, 0x0000030C },
+ { 0x0213F0FE992C3944, 0x0000378F, 0xFFFFE7A6, 0x00000566, 0x00001875, 0xFFFFFA04, 0x000002AF, 0x00001875, 0xFFFFFA04, 0x000002AF },
+ { 0x0213EA94DE0230E4, 0x00002A67, 0xFFFFF157, 0x000003DD, 0x000017BD, 0xFFFFFA53, 0x000002D1, 0x000017BD, 0xFFFFFA53, 0x000002D1 },
+ { 0x0213F0FD42D220E4, 0x000030B5, 0xFFFFEB32, 0x000004D9, 0x00002129, 0xFFFFF38A, 0x000003BB, 0x00002129, 0xFFFFF38A, 0x000003BB },
+ { 0x0213F0FE990610A4, 0x00003786, 0xFFFFE703, 0x00000584, 0x00001D63, 0xFFFFF5DC, 0x00000367, 0x00001D63, 0xFFFFF5DC, 0x00000367 },
+ { 0x0213F0FD42DA20C4, 0x0000346A, 0xFFFFE93E, 0x0000052C, 0x00001B27, 0xFFFFF79D, 0x0000031F, 0x00001B27, 0xFFFFF79D, 0x0000031F },
+ { 0x0213F0FE990E3024, 0x0000294E, 0xFFFFF0A5, 0x00000409, 0x00001928, 0xFFFFF93B, 0x000002E6, 0x00001928, 0xFFFFF93B, 0x000002E6 },
+ { 0x0213F0FD42D410C4, 0x00003E09, 0xFFFFE0FF, 0x00000694, 0x000025A0, 0xFFFFEF0F, 0x0000048F, 0x000025A0, 0xFFFFEF0F, 0x0000048F },
+ { 0x0213F0FE990A2964, 0x00003197, 0xFFFFEA06, 0x00000520, 0x00001B42, 0xFFFFF73B, 0x0000032A, 0x00001B42, 0xFFFFF73B, 0x0000032A },
+ { 0x0213F0FE99161864, 0x000022CB, 0xFFFFF3FC, 0x000003A3, 0x00001449, 0xFFFFFBD0, 0x00000297, 0x00001449, 0xFFFFFBD0, 0x00000297 },
+ { 0x0213F0FD42D82944, 0x00002A79, 0xFFFFEFD2, 0x00000433, 0x00001585, 0xFFFFFB92, 0x0000028E, 0x00001585, 0xFFFFFB92, 0x0000028E },
+ { 0x0213F0FE990C4184, 0x00003249, 0xFFFFEA92, 0x000004F4, 0x000019CB, 0xFFFFF8CF, 0x000002E1, 0x000019CB, 0xFFFFF8CF, 0x000002E1 },
+ { 0x0213EA94DE0218A4, 0x00002CEA, 0xFFFFEE46, 0x00000463, 0x00001A5E, 0xFFFFF83C, 0x0000030D, 0x00001A5E, 0xFFFFF83C, 0x0000030D },
+ { 0x0213F0FD42DC5144, 0x00003AE2, 0xFFFFE422, 0x00000600, 0x00001C65, 0xFFFFF62F, 0x0000034B, 0x00001C65, 0xFFFFF62F, 0x0000034B },
+ { 0x0213F0FE99181184, 0x000026A0, 0xFFFFF1C2, 0x000003F8, 0x000010E5, 0xFFFFFE56, 0x0000022A, 0x000010E5, 0xFFFFFE56, 0x0000022A },
+ { 0x0213F0FE992829A4, 0x00002A7B, 0xFFFFF063, 0x00000417, 0x000016FC, 0xFFFFFAD7, 0x000002B1, 0x000016FC, 0xFFFFFAD7, 0x000002B1 },
+ { 0x0213F0FE993210C4, 0x00003092, 0xFFFFEAB9, 0x00000507, 0x00001AE3, 0xFFFFF783, 0x00000323, 0x00001AE3, 0xFFFFF783, 0x00000323 },
+ { 0x0213F0FE990438E4, 0x00003265, 0xFFFFEBE8, 0x000004AA, 0x00001D65, 0xFFFFF73F, 0x00000321, 0x00001D65, 0xFFFFF73F, 0x00000321 },
+ { 0x0213EA94DE023084, 0x00002F14, 0xFFFFECC2, 0x000004A4, 0x00001A8D, 0xFFFFF7F3, 0x0000031D, 0x00001A8D, 0xFFFFF7F3, 0x0000031D },
+ { 0x0213F0FD42DC10E4, 0x000035FB, 0xFFFFE6D3, 0x000005AC, 0x00001B19, 0xFFFFF712, 0x00000338, 0x00001B19, 0xFFFFF712, 0x00000338 },
+ { 0x0213F0FD42DA2124, 0x00003519, 0xFFFFE8CC, 0x0000053A, 0x00001A0F, 0xFFFFF86E, 0x000002F5, 0x00001A0F, 0xFFFFF86E, 0x000002F5 },
+ { 0x0213F0FE992C2144, 0x0000364C, 0xFFFFE879, 0x00000541, 0x00001A42, 0xFFFFF8BA, 0x000002E2, 0x00001A42, 0xFFFFF8BA, 0x000002E2 },
+ { 0x0213EA94DE0218C4, 0x000029BA, 0xFFFFF09A, 0x00000408, 0x00001986, 0xFFFFF8D9, 0x000002FE, 0x00001986, 0xFFFFF8D9, 0x000002FE },
+ { 0x0213F0FD42DA38E4, 0x00003507, 0xFFFFE961, 0x00000518, 0x00001B79, 0xFFFFF775, 0x00000325, 0x00001B79, 0xFFFFF775, 0x00000325 },
+ { 0x0213F0FD42DC3184, 0x00003AD5, 0xFFFFE415, 0x00000613, 0x00001CB4, 0xFFFFF66D, 0x00000348, 0x00001CB4, 0xFFFFF66D, 0x00000348 },
+ { 0x0213F0FE991640E4, 0x000023D1, 0xFFFFF42B, 0x0000038F, 0x00001546, 0xFFFFFBA0, 0x0000029F, 0x00001546, 0xFFFFFBA0, 0x0000029F },
+ { 0x0213F0FE990A1924, 0x0000399E, 0xFFFFE518, 0x000005E7, 0x00001990, 0xFFFFF871, 0x000002FB, 0x00001990, 0xFFFFF871, 0x000002FB },
+ { 0x0213F0FD42D82964, 0x00002EDE, 0xFFFFEC93, 0x000004B8, 0x0000152C, 0xFFFFFBB3, 0x0000027E, 0x0000152C, 0xFFFFFBB3, 0x0000027E },
+ { 0x0213EA94DE042964, 0x00003140, 0xFFFFEBC9, 0x000004BB, 0x000016BE, 0xFFFFFB0A, 0x00000288, 0x000016BE, 0xFFFFFB0A, 0x00000288 },
+ { 0x0213F0FE99064064, 0x000030F6, 0xFFFFEB89, 0x000004CD, 0x0000185D, 0xFFFFF95A, 0x000002D9, 0x0000185D, 0xFFFFF95A, 0x000002D9 },
+ { 0x0213F0FE99023844, 0x0000389C, 0xFFFFE65A, 0x000005A2, 0x0000195D, 0xFFFFF8C8, 0x000002E8, 0x0000195D, 0xFFFFF8C8, 0x000002E8 },
+ { 0x0213F0FE99042104, 0x0000362B, 0xFFFFE9EC, 0x000004F6, 0x00001605, 0xFFFFFC1C, 0x00000263, 0x00001605, 0xFFFFFC1C, 0x00000263 },
+ { 0x0213F0FE992A1964, 0x00002946, 0xFFFFF04F, 0x00000426, 0x000015BA, 0xFFFFFB2F, 0x000002A3, 0x000015BA, 0xFFFFFB2F, 0x000002A3 },
+ { 0x0213F0FE99082184, 0x0000368E, 0xFFFFE837, 0x0000054A, 0x000017D7, 0xFFFFF9EB, 0x000002BA, 0x000017D7, 0xFFFFF9EB, 0x000002BA },
+ { 0x0213F0FD42DA2844, 0x00002E74, 0xFFFFEBE8, 0x000004DA, 0x00001DD6, 0xFFFFF57E, 0x00000379, 0x00001DD6, 0xFFFFF57E, 0x00000379 },
+ { 0x0213F0FE99041944, 0x0000322D, 0xFFFFEAA8, 0x000004F5, 0x00001B55, 0xFFFFF7DD, 0x0000030B, 0x00001B55, 0xFFFFF7DD, 0x0000030B },
+ { 0x0213F0FE99181904, 0x00002A29, 0xFFFFF07B, 0x00000416, 0x00001671, 0xFFFFFB3E, 0x0000029F, 0x00001671, 0xFFFFFB3E, 0x0000029F },
+ { 0x0213F0FD42DA2104, 0x000030F6, 0xFFFFEB89, 0x000004CD, 0x00001815, 0xFFFFF9AE, 0x000002C9, 0x00001815, 0xFFFFF9AE, 0x000002C9 },
+ { 0x0213F0FE990E10E4, 0x0000265F, 0xFFFFF1CB, 0x000003D5, 0x00001ED2, 0xFFFFF539, 0x0000037A, 0x00001ED2, 0xFFFFF539, 0x0000037A },
+ { 0x0213F0FE99162184, 0x000027A8, 0xFFFFF10D, 0x00000413, 0x000014B5, 0xFFFFFBA1, 0x00000299, 0x000014B5, 0xFFFFFBA1, 0x00000299 },
+ { 0x0213F0FE99043064, 0x00002CEE, 0xFFFFEDF6, 0x00000476, 0x00001A99, 0xFFFFF83E, 0x00000305, 0x00001A99, 0xFFFFF83E, 0x00000305 },
+ { 0x0213F0FE990640C4, 0x0000346C, 0xFFFFEA17, 0x000004EF, 0x00001D38, 0xFFFFF69F, 0x0000033D, 0x00001D38, 0xFFFFF69F, 0x0000033D },
+ { 0x0213F0FD42DA2944, 0x00002DBB, 0xFFFFED35, 0x00000490, 0x000018C1, 0xFFFFF930, 0x000002DA, 0x000018C1, 0xFFFFF930, 0x000002DA },
+ { 0x0213F0FE99042924, 0x000038DF, 0xFFFFE8A7, 0x0000051E, 0x00001B59, 0xFFFFF915, 0x000002D3, 0x00001B59, 0xFFFFF915, 0x000002D3 },
+ { 0x0213F0FE99080944, 0x00003384, 0xFFFFE979, 0x00000524, 0x00001AF3, 0xFFFFF74C, 0x0000032F, 0x00001AF3, 0xFFFFF74C, 0x0000032F },
+ { 0x0213F0FE99181864, 0x0000258B, 0xFFFFF2AE, 0x000003CB, 0x0000190C, 0xFFFFF93E, 0x000002EF, 0x0000190C, 0xFFFFF93E, 0x000002EF },
+ { 0x0213F0FE99103884, 0x000034F1, 0xFFFFE84B, 0x0000055E, 0x00001CB8, 0xFFFFF670, 0x0000034A, 0x00001CB8, 0xFFFFF670, 0x0000034A },
+ { 0x0213F0FE990C2104, 0x000030FB, 0xFFFFECD2, 0x00000488, 0x00001BF4, 0xFFFFF821, 0x00000302, 0x00001BF4, 0xFFFFF821, 0x00000302 },
+ { 0x0213F0FE99063044, 0x000036A6, 0xFFFFE815, 0x00000556, 0x000018FD, 0xFFFFF925, 0x000002DF, 0x000018FD, 0xFFFFF925, 0x000002DF },
+ { 0x0213EA94DE023044, 0x0000302A, 0xFFFFEB79, 0x000004E0, 0x00001C11, 0xFFFFF694, 0x00000358, 0x00001C11, 0xFFFFF694, 0x00000358 },
+ { 0x0213F0FE99181124, 0x00002555, 0xFFFFF2C4, 0x000003CB, 0x000017E3, 0xFFFFFA1F, 0x000002CB, 0x000017E3, 0xFFFFFA1F, 0x000002CB },
+ { 0x0213F0FE990A3164, 0x000032A3, 0xFFFFE933, 0x00000544, 0x000019D3, 0xFFFFF81A, 0x00000306, 0x000019D3, 0xFFFFF81A, 0x00000306 },
+ { 0x0213F0FD42D85104, 0x00002B91, 0xFFFFED81, 0x000004A9, 0x0000158B, 0xFFFFFAB9, 0x000002AC, 0x0000158B, 0xFFFFFAB9, 0x000002AC },
+ { 0x0213F0FE990E20C4, 0x00003537, 0xFFFFE912, 0x0000052C, 0x00001C8A, 0xFFFFF754, 0x0000031B, 0x00001C8A, 0xFFFFF754, 0x0000031B },
+ { 0x0213EA94DE063184, 0x000032E1, 0xFFFFEA5A, 0x000004F9, 0x000017B4, 0xFFFFF9D9, 0x000002C2, 0x000017B4, 0xFFFFF9D9, 0x000002C2 },
+ { 0x0213F0FD42D210C4, 0x00003B76, 0xFFFFE330, 0x00000636, 0x000026FB, 0xFFFFEF06, 0x00000481, 0x000026FB, 0xFFFFEF06, 0x00000481 },
+ { 0x0213F0FE99042144, 0x0000320C, 0xFFFFEB84, 0x000004C3, 0x00001A3A, 0xFFFFF8E9, 0x000002DF, 0x00001A3A, 0xFFFFF8E9, 0x000002DF },
+ { 0x0213F0FE99023984, 0x0000317D, 0xFFFFEA1F, 0x00000515, 0x00002100, 0xFFFFF31B, 0x000003DD, 0x00002100, 0xFFFFF31B, 0x000003DD },
+ { 0x0213F0FD42D43164, 0x00003DCB, 0xFFFFE0B4, 0x000006B4, 0x00002160, 0xFFFFF269, 0x000003F0, 0x00002160, 0xFFFFF269, 0x000003F0 },
+ { 0x0213F0FE991618C4, 0x00002737, 0xFFFFF218, 0x000003E1, 0x000015B5, 0xFFFFFB8F, 0x0000029C, 0x000015B5, 0xFFFFFB8F, 0x0000029C },
+ { 0x0213EA94DE023184, 0x0000318F, 0xFFFFEB3F, 0x000004D8, 0x00001938, 0xFFFFF8E9, 0x000002EB, 0x00001938, 0xFFFFF8E9, 0x000002EB },
+ { 0x0213F0FE991048C4, 0x000031BD, 0xFFFFE9DE, 0x00000527, 0x000018A7, 0xFFFFF8CA, 0x000002ED, 0x000018A7, 0xFFFFF8CA, 0x000002ED },
+ { 0x0213F0FD42DA3884, 0x00002F77, 0xFFFFEC2F, 0x000004B4, 0x00001D25, 0xFFFFF61B, 0x0000035D, 0x00001D25, 0xFFFFF61B, 0x0000035D },
+ { 0x0213F0FE990E4904, 0x00002CCA, 0xFFFFEDB3, 0x0000047C, 0x00001FBD, 0xFFFFF4A7, 0x00000391, 0x00001FBD, 0xFFFFF4A7, 0x00000391 },
+ { 0x0213F0FD42D438A4, 0x00003FF6, 0xFFFFE058, 0x000006A2, 0x000024CD, 0xFFFFF026, 0x00000452, 0x000024CD, 0xFFFFF026, 0x00000452 },
+ { 0x0213F0FE990A38E4, 0x00003161, 0xFFFFEAC8, 0x000004F3, 0x00001BB6, 0xFFFFF72A, 0x0000032B, 0x00001BB6, 0xFFFFF72A, 0x0000032B },
+ { 0x0213F0FD42D838A4, 0x00002EA0, 0xFFFFECA6, 0x000004B7, 0x000018C2, 0xFFFFF94E, 0x000002E1, 0x000018C2, 0xFFFFF94E, 0x000002E1 },
+ { 0x0213F0FE99182184, 0x00002F62, 0xFFFFEC9E, 0x000004B8, 0x00001531, 0xFFFFFBCD, 0x00000285, 0x00001531, 0xFFFFFBCD, 0x00000285 },
+ { 0x0213F0FE990440A4, 0x00003013, 0xFFFFEBD6, 0x000004C2, 0x00001B01, 0xFFFFF802, 0x000002FF, 0x00001B01, 0xFFFFF802, 0x000002FF },
+ { 0x0213F0FE99183064, 0x00002972, 0xFFFFF08D, 0x00000417, 0x00001A32, 0xFFFFF8A4, 0x00000305, 0x00001A32, 0xFFFFF8A4, 0x00000305 },
+ { 0x0213F0FD42D820E4, 0x00002E95, 0xFFFFED94, 0x00000487, 0x00001529, 0xFFFFFC26, 0x00000271, 0x00001529, 0xFFFFFC26, 0x00000271 },
+ { 0x0213F0FE990A1084, 0x00002D6A, 0xFFFFEC79, 0x000004C1, 0x00001AE2, 0xFFFFF725, 0x00000337, 0x00001AE2, 0xFFFFF725, 0x00000337 },
+ { 0x0213F0FE99021884, 0x000036B4, 0xFFFFE704, 0x00000591, 0x00001E7E, 0xFFFFF51C, 0x00000383, 0x00001E7E, 0xFFFFF51C, 0x00000383 },
+ { 0x0213F0FE99041844, 0x00002A6F, 0xFFFFEF70, 0x00000443, 0x00001BAA, 0xFFFFF752, 0x00000336, 0x00001BAA, 0xFFFFF752, 0x00000336 },
+ { 0x0213F0FE99183944, 0x00002C66, 0xFFFFEF5F, 0x0000043A, 0x000019F7, 0xFFFFF931, 0x000002EC, 0x000019F7, 0xFFFFF931, 0x000002EC },
+ { 0x0213EA94DE0631C4, 0x00003852, 0xFFFFE6AB, 0x00000590, 0x000019C1, 0xFFFFF8B1, 0x000002E5, 0x000019C1, 0xFFFFF8B1, 0x000002E5 },
+ { 0x0213F0FD42DA3124, 0x00003521, 0xFFFFE932, 0x00000523, 0x000018A9, 0xFFFFF96B, 0x000002D0, 0x000018A9, 0xFFFFF96B, 0x000002D0 },
+ { 0x0213F0FE99062164, 0x000031B9, 0xFFFFEB36, 0x000004D0, 0x00001D65, 0xFFFFF612, 0x0000035D, 0x00001D65, 0xFFFFF612, 0x0000035D },
+ { 0x0213F0FD42D41064, 0x00003ED0, 0xFFFFE135, 0x00000679, 0x00002351, 0xFFFFF0FE, 0x00000433, 0x00002351, 0xFFFFF0FE, 0x00000433 },
+ { 0x0213F0FE990A20E4, 0x000033ED, 0xFFFFE91A, 0x00000541, 0x00001C93, 0xFFFFF6A0, 0x0000034A, 0x00001C93, 0xFFFFF6A0, 0x0000034A },
+ { 0x0213EA94DE021844, 0x0000356F, 0xFFFFE8F7, 0x00000530, 0x000016BF, 0xFFFFFA85, 0x000002AB, 0x000016BF, 0xFFFFFA85, 0x000002AB },
+ { 0x0213F0FE991840E4, 0x00002304, 0xFFFFF4F3, 0x00000364, 0x000017CC, 0xFFFFFA41, 0x000002CA, 0x000017CC, 0xFFFFFA41, 0x000002CA },
+ { 0x0213F0FE99161164, 0x00002887, 0xFFFFEFD7, 0x00000450, 0x00001474, 0xFFFFFB94, 0x00000299, 0x00001474, 0xFFFFFB94, 0x00000299 },
+ { 0x0213F0FE99063064, 0x00003D0B, 0xFFFFE416, 0x000005EF, 0x00001C7E, 0xFFFFF71D, 0x00000325, 0x00001C7E, 0xFFFFF71D, 0x00000325 },
+ { 0x0213F0FE990810E4, 0x00003185, 0xFFFFEAFA, 0x000004E4, 0x00001A12, 0xFFFFF83C, 0x00000303, 0x00001A12, 0xFFFFF83C, 0x00000303 },
+ { 0x0213F0FE990A1944, 0x00003032, 0xFFFFEAE6, 0x000004FC, 0x00001B2A, 0xFFFFF73F, 0x0000032B, 0x00001B2A, 0xFFFFF73F, 0x0000032B },
+ { 0x0213F0FD42D838C4, 0x00002691, 0xFFFFF22D, 0x000003D6, 0x00001700, 0xFFFFFA6E, 0x000002C0, 0x00001700, 0xFFFFFA6E, 0x000002C0 },
+ { 0x0213F0FE990218A4, 0x00002B2F, 0xFFFFEEC4, 0x0000044B, 0x0000215F, 0xFFFFF33F, 0x000003D2, 0x0000215F, 0xFFFFF33F, 0x000003D2 },
+ { 0x0213F0FE990A4184, 0x000034AA, 0xFFFFE706, 0x000005B1, 0x00001B28, 0xFFFFF6B5, 0x00000349, 0x00001B28, 0xFFFFF6B5, 0x00000349 },
+ { 0x0213F0FD42DA2964, 0x0000307E, 0xFFFFEB38, 0x000004E6, 0x00001A22, 0xFFFFF83F, 0x00000300, 0x00001A22, 0xFFFFF83F, 0x00000300 },
+ { 0x0213F0FE990618A4, 0x000038D6, 0xFFFFE6D8, 0x0000057C, 0x00001B24, 0xFFFFF7E4, 0x00000307, 0x00001B24, 0xFFFFF7E4, 0x00000307 },
+ { 0x0213F0FE99183044, 0x00002757, 0xFFFFF1E8, 0x000003DD, 0x000017F5, 0xFFFFFA15, 0x000002C8, 0x000017F5, 0xFFFFFA15, 0x000002C8 },
+ { 0x0213F0FE99083184, 0x000031FC, 0xFFFFEB3E, 0x000004CE, 0x00001B4C, 0xFFFFF7AD, 0x00000319, 0x00001B4C, 0xFFFFF7AD, 0x00000319 },
+ { 0x0213F0FE99301864, 0x00002933, 0xFFFFF073, 0x0000040E, 0x00001C3C, 0xFFFFF701, 0x0000033C, 0x00001C3C, 0xFFFFF701, 0x0000033C },
+ { 0x0213F0FD42D218A4, 0x000040BB, 0xFFFFE066, 0x0000069A, 0x0000257F, 0xFFFFF08A, 0x00000435, 0x0000257F, 0xFFFFF08A, 0x00000435 },
+ { 0x0213F0FE991010A4, 0x0000305B, 0xFFFFEB9B, 0x000004CB, 0x00001996, 0xFFFFF846, 0x00000308, 0x00001996, 0xFFFFF846, 0x00000308 },
+ { 0x0213F0FE99064884, 0x000039C0, 0xFFFFE5D3, 0x000005B0, 0x00001A8D, 0xFFFFF7DA, 0x00000313, 0x00001A8D, 0xFFFFF7DA, 0x00000313 },
+ { 0x0213EA94DE0210A4, 0x00002E23, 0xFFFFED3F, 0x0000048F, 0x0000189D, 0xFFFFF94C, 0x000002DE, 0x0000189D, 0xFFFFF94C, 0x000002DE },
+ { 0x0213EA94DE021984, 0x0000332B, 0xFFFFE9F1, 0x00000516, 0x000018E6, 0xFFFFF8FE, 0x000002EC, 0x000018E6, 0xFFFFF8FE, 0x000002EC },
+ { 0x0213F0FE990838C4, 0x000034A0, 0xFFFFEA44, 0x000004E4, 0x00001ECD, 0xFFFFF5B4, 0x00000364, 0x00001ECD, 0xFFFFF5B4, 0x00000364 },
+ { 0x0213F0FD42D24104, 0x0000448C, 0xFFFFDF34, 0x000006A8, 0x0000231C, 0xFFFFF286, 0x000003D9, 0x0000231C, 0xFFFFF286, 0x000003D9 },
+ { 0x0213EA94DE062144, 0x00002D8C, 0xFFFFEE65, 0x00000456, 0x000018B1, 0xFFFFF9C8, 0x000002C8, 0x000018B1, 0xFFFFF9C8, 0x000002C8 },
+ { 0x0213F0FE99061904, 0x00003527, 0xFFFFE9BF, 0x000004FD, 0x00001D23, 0xFFFFF69F, 0x00000342, 0x00001D23, 0xFFFFF69F, 0x00000342 },
+ { 0x0213F0FD42DC38A4, 0x00002C51, 0xFFFFEDC3, 0x00000483, 0x00001BE0, 0xFFFFF720, 0x0000032D, 0x00001BE0, 0xFFFFF720, 0x0000032D },
+ { 0x0213F0FE990A3044, 0x00002C6C, 0xFFFFECEB, 0x000004B7, 0x00001C86, 0xFFFFF5E7, 0x00000371, 0x00001C86, 0xFFFFF5E7, 0x00000371 },
+ { 0x0213F0FE99045144, 0x000037CF, 0xFFFFE6BE, 0x00000599, 0x000018CD, 0xFFFFF967, 0x000002C7, 0x000018CD, 0xFFFFF967, 0x000002C7 },
+ { 0x0213F0FE99103164, 0x00002E6F, 0xFFFFED1D, 0x0000048E, 0x00001ADC, 0xFFFFF7F4, 0x0000030E, 0x00001ADC, 0xFFFFF7F4, 0x0000030E },
+ { 0x0213F0FD42D42984, 0x00003FF3, 0xFFFFDF13, 0x000006F9, 0x000025BF, 0xFFFFEEEE, 0x00000497, 0x000025BF, 0xFFFFEEEE, 0x00000497 },
+ { 0x0213F0FD42DC5104, 0x00004135, 0xFFFFDF97, 0x000006CC, 0x00001D52, 0xFFFFF541, 0x00000383, 0x00001D52, 0xFFFFF541, 0x00000383 },
+ { 0x0213F0FD42DC20E4, 0x00002EA9, 0xFFFFEDDB, 0x0000045F, 0x0000197C, 0xFFFFF8E1, 0x000002F0, 0x0000197C, 0xFFFFF8E1, 0x000002F0 },
+ { 0x0213EA94DE043084, 0x0000345C, 0xFFFFE922, 0x00000532, 0x00001922, 0xFFFFF8C7, 0x000002F1, 0x00001922, 0xFFFFF8C7, 0x000002F1 },
+ { 0x0213F0FE99064124, 0x000035C4, 0xFFFFE8FE, 0x00000521, 0x00001C87, 0xFFFFF6F3, 0x00000330, 0x00001C87, 0xFFFFF6F3, 0x00000330 },
+ { 0x0213F0FD42D83164, 0x00002888, 0xFFFFF08A, 0x0000041E, 0x0000150F, 0xFFFFFB87, 0x00000291, 0x0000150F, 0xFFFFFB87, 0x00000291 },
+ { 0x0213F0FE990A1124, 0x000035E9, 0xFFFFE657, 0x000005CC, 0x00001BD6, 0xFFFFF664, 0x00000355, 0x00001BD6, 0xFFFFF664, 0x00000355 },
+ { 0x0213F0FE991648E4, 0x00002F94, 0xFFFFEBD0, 0x000004E5, 0x00001333, 0xFFFFFCA7, 0x00000266, 0x00001333, 0xFFFFFCA7, 0x00000266 },
+ { 0x0213F0FE99181964, 0x000029E7, 0xFFFFF009, 0x00000433, 0x0000144A, 0xFFFFFC37, 0x0000027D, 0x0000144A, 0xFFFFFC37, 0x0000027D },
+ { 0x0213F0FE992C1944, 0x00003418, 0xFFFFE979, 0x00000521, 0x00001D33, 0xFFFFF66B, 0x0000034A, 0x00001D33, 0xFFFFF66B, 0x0000034A },
+ { 0x0213EA94DE0440E4, 0x00003656, 0xFFFFE79D, 0x0000057A, 0x000017C2, 0xFFFFF992, 0x000002D4, 0x000017C2, 0xFFFFF992, 0x000002D4 },
+ { 0x0213F0FE990C40C4, 0x00002EB2, 0xFFFFECFE, 0x00000493, 0x00001F2A, 0xFFFFF543, 0x0000037B, 0x00001F2A, 0xFFFFF543, 0x0000037B },
+ { 0x0213F0FE99021124, 0x00002FC1, 0xFFFFEB3F, 0x000004E8, 0x00001CD0, 0xFFFFF5F7, 0x00000364, 0x00001CD0, 0xFFFFF5F7, 0x00000364 },
+ { 0x0213F0FE990C1124, 0x0000307B, 0xFFFFEB66, 0x000004DE, 0x00001953, 0xFFFFF8ED, 0x000002E4, 0x00001953, 0xFFFFF8ED, 0x000002E4 },
+ { 0x0213F0FD42DA1884, 0x00002CAA, 0xFFFFED07, 0x000004AC, 0x0000251C, 0xFFFFF086, 0x0000044D, 0x0000251C, 0xFFFFF086, 0x0000044D },
+ { 0x0213EA94DE043944, 0x00002C94, 0xFFFFEE5F, 0x0000045B, 0x000018D7, 0xFFFFF900, 0x000002EB, 0x000018D7, 0xFFFFF900, 0x000002EB },
+ { 0x0213F0FE99021864, 0x000031F1, 0xFFFFE9BE, 0x0000052E, 0x00001DDF, 0xFFFFF558, 0x00000380, 0x00001DDF, 0xFFFFF558, 0x00000380 },
+ { 0x0213F0FE990E50C4, 0x00002603, 0xFFFFF1E9, 0x000003DA, 0x00001B37, 0xFFFFF75A, 0x0000032F, 0x00001B37, 0xFFFFF75A, 0x0000032F },
+ { 0x0213F0FD42DA3044, 0x00003992, 0xFFFFE4F9, 0x000005EB, 0x00001775, 0xFFFFF9B8, 0x000002C2, 0x00001775, 0xFFFFF9B8, 0x000002C2 },
+ { 0x0213F0FE99184964, 0x000029DA, 0xFFFFF052, 0x0000041F, 0x000016E2, 0xFFFFFA99, 0x000002BB, 0x000016E2, 0xFFFFFA99, 0x000002BB },
+ { 0x0213F0FE99101064, 0x00002FF2, 0xFFFFEB8F, 0x000004DF, 0x00001AF6, 0xFFFFF7A1, 0x00000321, 0x00001AF6, 0xFFFFF7A1, 0x00000321 },
+ { 0x0213F0FE991608E4, 0x00002590, 0xFFFFF222, 0x000003EE, 0x0000130B, 0xFFFFFCC9, 0x00000268, 0x0000130B, 0xFFFFFCC9, 0x00000268 },
+ { 0x0213F0FE99024064, 0x000038A2, 0xFFFFE65F, 0x000005A2, 0x000018B1, 0xFFFFF917, 0x000002E1, 0x000018B1, 0xFFFFF917, 0x000002E1 },
+ { 0x0213F0FD42DC48E4, 0x000035FD, 0xFFFFE73C, 0x0000058D, 0x00001BB3, 0xFFFFF6E1, 0x00000337, 0x00001BB3, 0xFFFFF6E1, 0x00000337 },
+ { 0x0213F0FE991038C4, 0x00002AB7, 0xFFFFEF98, 0x00000429, 0x00001F35, 0xFFFFF539, 0x0000037C, 0x00001F35, 0xFFFFF539, 0x0000037C },
+ { 0x0213F0FE990A0944, 0x000034BA, 0xFFFFE73D, 0x000005A6, 0x000018A6, 0xFFFFF888, 0x000002FB, 0x000018A6, 0xFFFFF888, 0x000002FB },
+ { 0x0213F0FE99063844, 0x000032EA, 0xFFFFEA78, 0x000004F4, 0x00001AB6, 0xFFFFF812, 0x00000308, 0x00001AB6, 0xFFFFF812, 0x00000308 },
+ { 0x0213F0FE990C3044, 0x00002BE9, 0xFFFFEE9A, 0x00000457, 0x00001942, 0xFFFFF8D2, 0x000002F2, 0x00001942, 0xFFFFF8D2, 0x000002F2 },
+ { 0x0213F0FE99105124, 0x00002FAB, 0xFFFFEB76, 0x000004E1, 0x00001DCA, 0xFFFFF57D, 0x00000378, 0x00001DCA, 0xFFFFF57D, 0x00000378 },
+ { 0x0213F0FE992E2844, 0x0000330A, 0xFFFFE9E1, 0x0000051B, 0x00001CC4, 0xFFFFF6DF, 0x00000335, 0x00001CC4, 0xFFFFF6DF, 0x00000335 },
+ { 0x0213F0FE991828A4, 0x000027D8, 0xFFFFF276, 0x000003BF, 0x0000178A, 0xFFFFFABF, 0x000002B5, 0x0000178A, 0xFFFFFABF, 0x000002B5 },
+ { 0x0213F0FD42DC3864, 0x0000340A, 0xFFFFE86D, 0x00000562, 0x00001B85, 0xFFFFF719, 0x0000032F, 0x00001B85, 0xFFFFF719, 0x0000032F },
+ { 0x0213EA94DE063084, 0x00003879, 0xFFFFE73F, 0x00000578, 0x0000161C, 0xFFFFFB6B, 0x00000281, 0x0000161C, 0xFFFFFB6B, 0x00000281 },
+ { 0x0213F0FE99184064, 0x00002879, 0xFFFFF0F8, 0x0000040A, 0x00001749, 0xFFFFFA37, 0x000002CC, 0x00001749, 0xFFFFFA37, 0x000002CC },
+ { 0x0213F0FE99043964, 0x00002C3A, 0xFFFFEEA0, 0x0000044F, 0x00001D57, 0xFFFFF6C2, 0x00000332, 0x00001D57, 0xFFFFF6C2, 0x00000332 },
+ { 0x0213EA94DE021964, 0x000035BB, 0xFFFFE90D, 0x0000052A, 0x000017D9, 0xFFFFF9F5, 0x000002C3, 0x000017D9, 0xFFFFF9F5, 0x000002C3 },
+ { 0x0213EA94DE041124, 0x000031F1, 0xFFFFEAD4, 0x000004ED, 0x00001F10, 0xFFFFF539, 0x0000037D, 0x00001F10, 0xFFFFF539, 0x0000037D },
+ { 0x0213F0FE99102824, 0x00002A1A, 0xFFFFEFAD, 0x00000430, 0x00001D47, 0xFFFFF62F, 0x0000035E, 0x00001D47, 0xFFFFF62F, 0x0000035E },
+ { 0x0213F0FE99164924, 0x00002AF0, 0xFFFFEEDC, 0x00000465, 0x0000145F, 0xFFFFFBEB, 0x00000281, 0x0000145F, 0xFFFFFBEB, 0x00000281 },
+ { 0x0213F0FE99183164, 0x00002657, 0xFFFFF2E0, 0x000003B6, 0x00001664, 0xFFFFFB37, 0x000002A2, 0x00001664, 0xFFFFFB37, 0x000002A2 },
+ { 0x0213F0FD42D03864, 0x00003183, 0xFFFFE9F1, 0x0000052B, 0x00002020, 0xFFFFF3CE, 0x000003C1, 0x00002020, 0xFFFFF3CE, 0x000003C1 },
+ { 0x0213F0FD42C628E4, 0x00003240, 0xFFFFEB65, 0x000004C7, 0x00002425, 0xFFFFF245, 0x000003F3, 0x00002425, 0xFFFFF245, 0x000003F3 },
+ { 0x0213EA94DE321104, 0x000023D0, 0xFFFFF400, 0x00000397, 0x00001345, 0xFFFFFD6B, 0x00000241, 0x00001345, 0xFFFFFD6B, 0x00000241 },
+ { 0x0213F0FD42CE38A4, 0x00003440, 0xFFFFE872, 0x0000055B, 0x00002247, 0xFFFFF296, 0x000003E8, 0x00002247, 0xFFFFF296, 0x000003E8 },
+ { 0x0213F0FD42D04904, 0x00003275, 0xFFFFE970, 0x00000538, 0x00001F94, 0xFFFFF429, 0x000003AD, 0x00001F94, 0xFFFFF429, 0x000003AD },
+ { 0x0213F0FD42C640A4, 0x00003918, 0xFFFFE5DA, 0x000005B6, 0x000024FC, 0xFFFFF106, 0x00000426, 0x000024FC, 0xFFFFF106, 0x00000426 },
+ { 0x0213EA94DE062044, 0x0000334B, 0xFFFFEA39, 0x000004FD, 0x00001983, 0xFFFFF8F6, 0x000002E2, 0x00001983, 0xFFFFF8F6, 0x000002E2 },
+ { 0x0213F0FD42C64984, 0x00003B59, 0xFFFFE4D0, 0x000005DA, 0x00002605, 0xFFFFF090, 0x00000439, 0x00002605, 0xFFFFF090, 0x00000439 },
+ { 0x0213F0FD42D03124, 0x00003251, 0xFFFFEA46, 0x00000511, 0x00002781, 0xFFFFEF84, 0x00000470, 0x00002781, 0xFFFFEF84, 0x00000470 },
+ { 0x0213F0FD42CA3164, 0x00003304, 0xFFFFE926, 0x00000542, 0x00001EE9, 0xFFFFF4E4, 0x0000038B, 0x00001EE9, 0xFFFFF4E4, 0x0000038B },
+ { 0x0213F0FD42CC38C4, 0x00002F4C, 0xFFFFEC0C, 0x000004C4, 0x00001E49, 0xFFFFF578, 0x00000374, 0x00001E49, 0xFFFFF578, 0x00000374 },
+ { 0x0213EA94DE1C2164, 0x00002034, 0xFFFFF692, 0x0000034C, 0x000014B8, 0xFFFFFC5B, 0x00000294, 0x000014B8, 0xFFFFFC5B, 0x00000294 },
+ { 0x0213F0FD42CE4924, 0x0000385F, 0xFFFFE513, 0x000005F3, 0x000024E7, 0xFFFFF053, 0x00000450, 0x000024E7, 0xFFFFF053, 0x00000450 },
+ { 0x0213EA94DE1C40E4, 0x00001D70, 0xFFFFF821, 0x0000030F, 0x00001541, 0xFFFFFBB4, 0x000002B0, 0x00001541, 0xFFFFFBB4, 0x000002B0 },
+ { 0x0213F0FD42D02084, 0x000034EB, 0xFFFFE7FF, 0x00000575, 0x000019B4, 0xFFFFF836, 0x00000308, 0x000019B4, 0xFFFFF836, 0x00000308 },
+ { 0x0213F0FD42D050E4, 0x000037C9, 0xFFFFE5D4, 0x000005CD, 0x000026A1, 0xFFFFEF0C, 0x00000491, 0x000026A1, 0xFFFFEF0C, 0x00000491 },
+ { 0x0213EA94DE121944, 0x00002918, 0xFFFFF148, 0x000003E9, 0x00001A49, 0xFFFFF94C, 0x000002CF, 0x00001A49, 0xFFFFF94C, 0x000002CF },
+ { 0x0213F0FD42CA4064, 0x00002F90, 0xFFFFEAB5, 0x00000514, 0x00001707, 0xFFFFF9C7, 0x000002C4, 0x00001707, 0xFFFFF9C7, 0x000002C4 },
+ { 0x0213EA94DE062064, 0x0000327E, 0xFFFFEA99, 0x000004F4, 0x0000194F, 0xFFFFF929, 0x000002DC, 0x0000194F, 0xFFFFF929, 0x000002DC },
+ { 0x0213F0FD42C64084, 0x0000326F, 0xFFFFE9CF, 0x00000519, 0x00002240, 0xFFFFF299, 0x000003E7, 0x00002240, 0xFFFFF299, 0x000003E7 },
+ { 0x0213EA94DE321124, 0x000022FB, 0xFFFFF4C6, 0x00000371, 0x00001506, 0xFFFFFC73, 0x00000265, 0x00001506, 0xFFFFFC73, 0x00000265 },
+ { 0x0213F0FD42CA3924, 0x00003AD6, 0xFFFFE470, 0x000005FE, 0x00001F03, 0xFFFFF4F3, 0x00000387, 0x00001F03, 0xFFFFF4F3, 0x00000387 },
+ { 0x0213EA94DE201124, 0x00001F11, 0xFFFFF756, 0x00000332, 0x00001666, 0xFFFFFB8A, 0x000002B2, 0x00001666, 0xFFFFFB8A, 0x000002B2 },
+ { 0x0213EA94DE0238A4, 0x00002A5F, 0xFFFFEFA7, 0x00000430, 0x00001943, 0xFFFFF8C6, 0x000002F7, 0x00001943, 0xFFFFF8C6, 0x000002F7 },
+ { 0x0213EA94DE1650E4, 0x0000235E, 0xFFFFF3B4, 0x000003B3, 0x00001489, 0xFFFFFBCF, 0x0000029B, 0x00001489, 0xFFFFFBCF, 0x0000029B },
+ { 0x0213F0FD42CC38A4, 0x00003570, 0xFFFFE780, 0x0000058D, 0x00001B1D, 0xFFFFF767, 0x00000325, 0x00001B1D, 0xFFFFF767, 0x00000325 },
+ { 0x0213EA94DE042064, 0x00003678, 0xFFFFE7C3, 0x00000569, 0x00001831, 0xFFFFF98E, 0x000002C8, 0x00001831, 0xFFFFF98E, 0x000002C8 },
+ { 0x0213EA94DE201864, 0x000020B9, 0xFFFFF625, 0x0000035A, 0x000015C5, 0xFFFFFB8A, 0x000002B5, 0x000015C5, 0xFFFFFB8A, 0x000002B5 },
+ { 0x0213F0FD42C63184, 0x00003985, 0xFFFFE529, 0x000005DD, 0x00002165, 0xFFFFF351, 0x000003C5, 0x00002165, 0xFFFFF351, 0x000003C5 },
+ { 0x0213F0FD42D02064, 0x0000322A, 0xFFFFE99D, 0x00000535, 0x000019A1, 0xFFFFF844, 0x00000305, 0x000019A1, 0xFFFFF844, 0x00000305 },
+ { 0x0213F0FD42D05104, 0x000033ED, 0xFFFFE834, 0x00000571, 0x00002094, 0xFFFFF33A, 0x000003DB, 0x00002094, 0xFFFFF33A, 0x000003DB },
+ { 0x0213EA94DE2040C4, 0x00001D10, 0xFFFFF84D, 0x0000030B, 0x00001659, 0xFFFFFB0A, 0x000002CB, 0x00001659, 0xFFFFFB0A, 0x000002CB },
+ { 0x0213EA94DE1C1124, 0x0000210F, 0xFFFFF644, 0x00000355, 0x00001A4A, 0xFFFFF90F, 0x00000310, 0x00001A4A, 0xFFFFF90F, 0x00000310 },
+ { 0x0213EA94DE164164, 0x00001CA8, 0xFFFFF813, 0x00000316, 0x00001440, 0xFFFFFC1C, 0x0000029D, 0x00001440, 0xFFFFFC1C, 0x0000029D },
+ { 0x0213EA94DE3210C4, 0x00002864, 0xFFFFF15A, 0x000003FA, 0x0000137F, 0xFFFFFD43, 0x00000248, 0x0000137F, 0xFFFFFD43, 0x00000248 },
+ { 0x0213F0FD42D04184, 0x00002CDB, 0xFFFFECFD, 0x000004A7, 0x00002472, 0xFFFFF0E1, 0x00000437, 0x00002472, 0xFFFFF0E1, 0x00000437 },
+ { 0x0213F0FD42CC5104, 0x00003348, 0xFFFFE8CA, 0x00000554, 0x00001E91, 0xFFFFF4D4, 0x00000392, 0x00001E91, 0xFFFFF4D4, 0x00000392 },
+ { 0x0213F0FD42C64944, 0x00003989, 0xFFFFE4BB, 0x000005F8, 0x00001ACB, 0xFFFFF780, 0x00000319, 0x00001ACB, 0xFFFFF780, 0x00000319 },
+ { 0x0213F0FD42CA2104, 0x00003238, 0xFFFFEA09, 0x0000051E, 0x00001F08, 0xFFFFF4F4, 0x0000038C, 0x00001F08, 0xFFFFF4F4, 0x0000038C },
+ { 0x0213EA94DE120904, 0x00002453, 0xFFFFF3B0, 0x0000038D, 0x00001AED, 0xFFFFF8A2, 0x000002EA, 0x00001AED, 0xFFFFF8A2, 0x000002EA },
+ { 0x0213EA94DE1C3024, 0x00002459, 0xFFFFF409, 0x000003A8, 0x000017B5, 0xFFFFFA53, 0x000002E1, 0x000017B5, 0xFFFFFA53, 0x000002E1 },
+ { 0x0213EA94DE021184, 0x0000310D, 0xFFFFEB78, 0x000004D0, 0x00001DC9, 0xFFFFF5D5, 0x00000368, 0x00001DC9, 0xFFFFF5D5, 0x00000368 },
+ { 0x0213EA94DE023104, 0x000031BF, 0xFFFFECA3, 0x00000498, 0x00001DC9, 0xFFFFF717, 0x00000336, 0x00001DC9, 0xFFFFF717, 0x00000336 },
+ { 0x0213F0FD42CE2104, 0x00003896, 0xFFFFE5DD, 0x000005C5, 0x000023E2, 0xFFFFF1A1, 0x00000416, 0x000023E2, 0xFFFFF1A1, 0x00000416 },
+ { 0x0213EA94DE323904, 0x000023CB, 0xFFFFF4C8, 0x00000372, 0x00001C33, 0xFFFFF7D5, 0x0000032A, 0x00001C33, 0xFFFFF7D5, 0x0000032A },
+ { 0x0213F0FD42D020C4, 0x00002F6B, 0xFFFFEBF0, 0x000004CE, 0x00001C89, 0xFFFFF689, 0x0000034D, 0x00001C89, 0xFFFFF689, 0x0000034D },
+ { 0x0213F0FD42CE3904, 0x00003E72, 0xFFFFE211, 0x0000065D, 0x0000218D, 0xFFFFF309, 0x000003DC, 0x0000218D, 0xFFFFF309, 0x000003DC },
+ { 0x0213EA94DE022084, 0x00002612, 0xFFFFF2C3, 0x000003AD, 0x000019F7, 0xFFFFF891, 0x000002FE, 0x000019F7, 0xFFFFF891, 0x000002FE },
+ { 0x0213EA94DE164184, 0x0000205D, 0xFFFFF59F, 0x00000372, 0x000012E6, 0xFFFFFD0A, 0x00000270, 0x000012E6, 0xFFFFFD0A, 0x00000270 },
+ { 0x0213F0FD42CA2124, 0x00002ECB, 0xFFFFEC47, 0x000004BD, 0x00001936, 0xFFFFF8D9, 0x000002E4, 0x00001936, 0xFFFFF8D9, 0x000002E4 },
+ { 0x0213EA94DE064904, 0x00002BDB, 0xFFFFEE6D, 0x00000458, 0x00001852, 0xFFFFF943, 0x000002D9, 0x00001852, 0xFFFFF943, 0x000002D9 },
+ { 0x0213EA94DE124904, 0x00003387, 0xFFFFE958, 0x00000534, 0x00001932, 0xFFFFF8FA, 0x000002E4, 0x00001932, 0xFFFFF8FA, 0x000002E4 },
+ { 0x0213EA94DE0208C4, 0x00002E3C, 0xFFFFED26, 0x00000495, 0x00001858, 0xFFFFF990, 0x000002D1, 0x00001858, 0xFFFFF990, 0x000002D1 },
+ { 0x0213EA94DE022964, 0x000033B8, 0xFFFFEA5C, 0x000004F9, 0x00001BD1, 0xFFFFF76A, 0x0000032E, 0x00001BD1, 0xFFFFF76A, 0x0000032E },
+ { 0x0213EA94DE062984, 0x00002BCE, 0xFFFFEEE9, 0x00000443, 0x00001982, 0xFFFFF90D, 0x000002DF, 0x00001982, 0xFFFFF90D, 0x000002DF },
+ { 0x0213F0FD42D048E4, 0x00003495, 0xFFFFE7D9, 0x0000057B, 0x00001D2A, 0xFFFFF5A5, 0x00000372, 0x00001D2A, 0xFFFFF5A5, 0x00000372 },
+ { 0x0213F0FD42CA38E4, 0x000034B1, 0xFFFFE88D, 0x00000556, 0x00002014, 0xFFFFF43A, 0x000003AA, 0x00002014, 0xFFFFF43A, 0x000003AA },
+ { 0x0213F0FD42CC3124, 0x00002F96, 0xFFFFEC84, 0x000004AD, 0x000024A2, 0xFFFFF1CE, 0x0000040A, 0x000024A2, 0xFFFFF1CE, 0x0000040A },
+ { 0x0213EA94DE161064, 0x0000203B, 0xFFFFF640, 0x00000359, 0x000014EC, 0xFFFFFC14, 0x0000029C, 0x000014EC, 0xFFFFFC14, 0x0000029C },
+ { 0x0213F0FD42D02984, 0x000034E2, 0xFFFFE7B8, 0x00000582, 0x00001938, 0xFFFFF872, 0x000002FA, 0x00001938, 0xFFFFF872, 0x000002FA },
+ { 0x0213EA94DE063124, 0x00002AC7, 0xFFFFF0C1, 0x000003F5, 0x00002268, 0xFFFFF39C, 0x000003C9, 0x00002268, 0xFFFFF39C, 0x000003C9 },
+ { 0x0213F0FD42C63144, 0x000036F6, 0xFFFFE77F, 0x00000571, 0x000027D9, 0xFFFFEF6F, 0x00000461, 0x000027D9, 0xFFFFEF6F, 0x00000461 },
+ { 0x0213EA94DE123124, 0x00002BAB, 0xFFFFF018, 0x00000419, 0x00002126, 0xFFFFF4E2, 0x0000038F, 0x00002126, 0xFFFFF4E2, 0x0000038F },
+ { 0x0213EA94DE323924, 0x000028C4, 0xFFFFF161, 0x000003F8, 0x0000180C, 0xFFFFFA4B, 0x000002C8, 0x0000180C, 0xFFFFFA4B, 0x000002C8 },
+ { 0x0213F0FD42CA2864, 0x00002F48, 0xFFFFEB62, 0x000004EE, 0x00001912, 0xFFFFF8C8, 0x000002EA, 0x00001912, 0xFFFFF8C8, 0x000002EA },
+ { 0x0213F0FD42CE2864, 0x000032DF, 0xFFFFE911, 0x00000545, 0x00001F06, 0xFFFFF485, 0x0000039C, 0x00001F06, 0xFFFFF485, 0x0000039C },
+ { 0x0213F0FD42D04144, 0x000035B8, 0xFFFFE74F, 0x00000590, 0x00001FD7, 0xFFFFF410, 0x000003AF, 0x00001FD7, 0xFFFFF410, 0x000003AF },
+ { 0x0213F0FD42D050C4, 0x00003608, 0xFFFFE6D7, 0x000005A9, 0x000024A6, 0xFFFFF075, 0x00000450, 0x000024A6, 0xFFFFF075, 0x00000450 },
+ { 0x0213F0FD42CA3884, 0x000030AB, 0xFFFFEAED, 0x000004F5, 0x000019EE, 0xFFFFF84E, 0x000002FC, 0x000019EE, 0xFFFFF84E, 0x000002FC },
+ { 0x0213EA94DE0620C4, 0x000030C6, 0xFFFFEC92, 0x0000049E, 0x000019BB, 0xFFFFF8F1, 0x000002F3, 0x000019BB, 0xFFFFF8F1, 0x000002F3 },
+ { 0x0213F0FD42C630A4, 0x00003B27, 0xFFFFE544, 0x000005C1, 0x00002697, 0xFFFFF072, 0x00000438, 0x00002697, 0xFFFFF072, 0x00000438 },
+ { 0x0213EA94DE1248E4, 0x00002F23, 0xFFFFEC48, 0x000004B9, 0x0000199A, 0xFFFFF8CF, 0x000002E9, 0x0000199A, 0xFFFFF8CF, 0x000002E9 },
+ { 0x0213EA94DE0629A4, 0x00002BD7, 0xFFFFEEAC, 0x00000450, 0x00001991, 0xFFFFF8F4, 0x000002E2, 0x00001991, 0xFFFFF8F4, 0x000002E2 },
+ { 0x0213EA94DE022024, 0x00003210, 0xFFFFEB24, 0x000004DE, 0x00001BDF, 0xFFFFF744, 0x00000333, 0x00001BDF, 0xFFFFF744, 0x00000333 },
+ { 0x0213EA94DE244144, 0x00002DDC, 0xFFFFED0D, 0x000004AC, 0x000019D0, 0xFFFFF869, 0x0000030F, 0x000019D0, 0xFFFFF869, 0x0000030F },
+ { 0x0213EA94DE203964, 0x000023E6, 0xFFFFF40C, 0x000003A9, 0x000014EB, 0xFFFFFBC4, 0x000002AF, 0x000014EB, 0xFFFFFBC4, 0x000002AF },
+ { 0x0213F0FD42CA29A4, 0x000030CE, 0xFFFFE9A5, 0x0000053C, 0x00001C45, 0xFFFFF60E, 0x0000035D, 0x00001C45, 0xFFFFF60E, 0x0000035D },
+ { 0x0213EA94DE161084, 0x00001E89, 0xFFFFF73A, 0x00000337, 0x0000157C, 0xFFFFFBC0, 0x000002AA, 0x0000157C, 0xFFFFFBC0, 0x000002AA },
+ { 0x0213F0FD42D04124, 0x000036C6, 0xFFFFE6CF, 0x000005A1, 0x00002457, 0xFFFFF11D, 0x0000042D, 0x00002457, 0xFFFFF11D, 0x0000042D },
+ { 0x0213EA94DE321944, 0x00002815, 0xFFFFF19A, 0x000003F2, 0x000016D2, 0xFFFFFB40, 0x00000299, 0x000016D2, 0xFFFFFB40, 0x00000299 },
+ { 0x0213EA94DE1C19A4, 0x00001FE2, 0xFFFFF660, 0x00000354, 0x000015A7, 0xFFFFFB47, 0x000002C1, 0x000015A7, 0xFFFFFB47, 0x000002C1 },
+ { 0x0213EA94DE161964, 0x00002114, 0xFFFFF634, 0x00000356, 0x000016C1, 0xFFFFFB43, 0x000002B8, 0x000016C1, 0xFFFFFB43, 0x000002B8 },
+ { 0x0213F0FD42CC28C4, 0x000028E3, 0xFFFFF075, 0x00000414, 0x0000203C, 0xFFFFF438, 0x000003B3, 0x0000203C, 0xFFFFF438, 0x000003B3 },
+ { 0x0213EA94DE1C3924, 0x00001EEB, 0xFFFFF7BB, 0x0000031A, 0x00001580, 0xFFFFFBD7, 0x000002AD, 0x00001580, 0xFFFFFBD7, 0x000002AD },
+ { 0x0213EA94DE2408C4, 0x00002BB2, 0xFFFFEE72, 0x00000470, 0x0000192C, 0xFFFFF91E, 0x000002E7, 0x0000192C, 0xFFFFF91E, 0x000002E7 },
+ { 0x0213EA94DE0650E4, 0x00003A3D, 0xFFFFE49D, 0x000005F5, 0x00001A3B, 0xFFFFF7B1, 0x00000320, 0x00001A3B, 0xFFFFF7B1, 0x00000320 },
+ { 0x0213F0FD42CE3164, 0x00002E93, 0xFFFFEC5A, 0x000004B4, 0x000025EB, 0xFFFFF03C, 0x0000044A, 0x000025EB, 0xFFFFF03C, 0x0000044A },
+ { 0x0213F0FD42CA20C4, 0x0000331F, 0xFFFFE97A, 0x00000531, 0x00001A06, 0xFFFFF850, 0x000002FD, 0x00001A06, 0xFFFFF850, 0x000002FD },
+ { 0x0213F0FD42C63964, 0x00003937, 0xFFFFE5A0, 0x000005C7, 0x0000235E, 0xFFFFF234, 0x000003F2, 0x0000235E, 0xFFFFF234, 0x000003F2 },
+ { 0x0213EA94DE1E3924, 0x00001DD0, 0xFFFFF80E, 0x00000319, 0x000015C7, 0xFFFFFB91, 0x000002BC, 0x000015C7, 0xFFFFFB91, 0x000002BC },
+ { 0x0213F0FD42D03964, 0x00003328, 0xFFFFE905, 0x0000054A, 0x00002054, 0xFFFFF3BF, 0x000003C0, 0x00002054, 0xFFFFF3BF, 0x000003C0 },
+ { 0x0213F0FD42CC1104, 0x00002FE5, 0xFFFFEA65, 0x00000520, 0x0000188B, 0xFFFFF8A7, 0x000002F5, 0x0000188B, 0xFFFFF8A7, 0x000002F5 },
+ { 0x0213F0FD42CA38A4, 0x00002ED3, 0xFFFFEC51, 0x000004B9, 0x00001888, 0xFFFFF96A, 0x000002CA, 0x00001888, 0xFFFFF96A, 0x000002CA },
+ { 0x0213F0FD42D03084, 0x00002FCC, 0xFFFFEB60, 0x000004EA, 0x00001F8D, 0xFFFFF436, 0x000003B4, 0x00001F8D, 0xFFFFF436, 0x000003B4 },
+ { 0x0213F0FD42CE4084, 0x0000329F, 0xFFFFE8F7, 0x0000054F, 0x000023DB, 0xFFFFF0EE, 0x0000043A, 0x000023DB, 0xFFFFF0EE, 0x0000043A },
+ { 0x0213EA94DE0438A4, 0x000030B5, 0xFFFFEBB8, 0x000004C4, 0x00001AFD, 0xFFFFF781, 0x00000329, 0x00001AFD, 0xFFFFF781, 0x00000329 },
+ { 0x0213EA94DE1E19A4, 0x00001BBF, 0xFFFFF8E2, 0x000002F7, 0x00001722, 0xFFFFFA85, 0x000002DB, 0x00001722, 0xFFFFFA85, 0x000002DB },
+ { 0x0213EA94DE022044, 0x000030E4, 0xFFFFEBE6, 0x000004BB, 0x00001C80, 0xFFFFF6E1, 0x0000033E, 0x00001C80, 0xFFFFF6E1, 0x0000033E },
+ { 0x0213EA94DE122944, 0x000030E2, 0xFFFFECD0, 0x00000492, 0x00001CE0, 0xFFFFF753, 0x0000032F, 0x00001CE0, 0xFFFFF753, 0x0000032F },
+ { 0x0213EA94DE322864, 0x00002513, 0xFFFFF323, 0x000003BC, 0x00001965, 0xFFFFF93C, 0x000002F0, 0x00001965, 0xFFFFF93C, 0x000002F0 },
+ { 0x0213EA94DE1610A4, 0x00002147, 0xFFFFF585, 0x0000037A, 0x000014CC, 0xFFFFFC3B, 0x00000296, 0x000014CC, 0xFFFFFC3B, 0x00000296 },
+ { 0x0213EA94DE322124, 0x00002507, 0xFFFFF432, 0x0000038A, 0x00001890, 0xFFFFFA61, 0x000002C6, 0x00001890, 0xFFFFFA61, 0x000002C6 },
+ { 0x0213EA94DE0638A4, 0x0000339B, 0xFFFFEA7D, 0x000004F0, 0x0000191E, 0xFFFFF944, 0x000002DF, 0x0000191E, 0xFFFFF944, 0x000002DF },
+ { 0x0213F0FD42CC28A4, 0x00002842, 0xFFFFF043, 0x00000427, 0x00001988, 0xFFFFF892, 0x000002F7, 0x00001988, 0xFFFFF892, 0x000002F7 },
+ { 0x0213F0FD42C618A4, 0x0000389D, 0xFFFFE5D8, 0x000005BF, 0x00001EE1, 0xFFFFF4EF, 0x00000387, 0x00001EE1, 0xFFFFF4EF, 0x00000387 },
+ { 0x0213F0FD42CE3184, 0x0000396D, 0xFFFFE4D7, 0x000005F2, 0x000020DA, 0xFFFFF34E, 0x000003CD, 0x000020DA, 0xFFFFF34E, 0x000003CD },
+ { 0x0213F0FD42CA3104, 0x0000355F, 0xFFFFE85A, 0x0000055F, 0x0000281F, 0xFFFFEF28, 0x0000047D, 0x0000281F, 0xFFFFEF28, 0x0000047D },
+ { 0x0213EA94DE1C50E4, 0x00002284, 0xFFFFF46E, 0x00000399, 0x00001498, 0xFFFFFBE3, 0x0000029C, 0x00001498, 0xFFFFFBE3, 0x0000029C },
+ { 0x0213EA94DE023944, 0x000031B6, 0xFFFFEB42, 0x000004D9, 0x00001F54, 0xFFFFF4D2, 0x00000399, 0x00001F54, 0xFFFFF4D2, 0x00000399 },
+ { 0x0213F0FD42C63064, 0x000035CE, 0xFFFFE79D, 0x00000578, 0x00001C78, 0xFFFFF68C, 0x00000344, 0x00001C78, 0xFFFFF68C, 0x00000344 },
+ { 0x0213EA94DE1E4964, 0x00001C0A, 0xFFFFF81B, 0x00000318, 0x00001492, 0xFFFFFBCC, 0x000002A5, 0x00001492, 0xFFFFFBCC, 0x000002A5 },
+ { 0x0213EA94DE022184, 0x00003492, 0xFFFFE95C, 0x00000526, 0x00001A97, 0xFFFFF81B, 0x0000030B, 0x00001A97, 0xFFFFF81B, 0x0000030B },
+ { 0x0213EA94DE163164, 0x00001E89, 0xFFFFF7D0, 0x0000031A, 0x000017A5, 0xFFFFFA99, 0x000002D9, 0x000017A5, 0xFFFFFA99, 0x000002D9 },
+ { 0x0213F0FD42CA48C4, 0x00002DCC, 0xFFFFEBE0, 0x000004DE, 0x000019BA, 0xFFFFF7F5, 0x0000030D, 0x000019BA, 0xFFFFF7F5, 0x0000030D },
+ { 0x0213EA94DE042984, 0x000030EF, 0xFFFFEBC1, 0x000004C0, 0x00001AA9, 0xFFFFF814, 0x0000030A, 0x00001AA9, 0xFFFFF814, 0x0000030A },
+ { 0x0213EA94DE245124, 0x00002EA3, 0xFFFFEBF6, 0x000004D8, 0x00001DCF, 0xFFFFF521, 0x00000399, 0x00001DCF, 0xFFFFF521, 0x00000399 },
+ { 0x0213EA94DE324164, 0x00002B5F, 0xFFFFEEA1, 0x0000046C, 0x000017EB, 0xFFFFF9C9, 0x000002D4, 0x000017EB, 0xFFFFF9C9, 0x000002D4 },
+ { 0x0213EA94DE024104, 0x00002C63, 0xFFFFEE82, 0x00000455, 0x00002268, 0xFFFFF29D, 0x000003F6, 0x00002268, 0xFFFFF29D, 0x000003F6 },
+ { 0x0213EA94DE121904, 0x00002B1A, 0xFFFFF016, 0x0000041C, 0x000019AA, 0xFFFFF988, 0x000002D2, 0x000019AA, 0xFFFFF988, 0x000002D2 },
+ { 0x0213F0FD42CA2964, 0x0000332F, 0xFFFFE934, 0x0000053B, 0x00001E47, 0xFFFFF566, 0x00000374, 0x00001E47, 0xFFFFF566, 0x00000374 },
+ { 0x0213F0FD42CA48E4, 0x00002995, 0xFFFFEEC1, 0x00000465, 0x0000178F, 0xFFFFF995, 0x000002C5, 0x0000178F, 0xFFFFF995, 0x000002C5 },
+ { 0x0213EA94DE201884, 0x00001C2E, 0xFFFFF932, 0x000002E9, 0x000015C2, 0xFFFFFBC5, 0x000002AD, 0x000015C2, 0xFFFFFBC5, 0x000002AD },
+ { 0x0213F0FD42C640E4, 0x00003B08, 0xFFFFE4E8, 0x000005D8, 0x0000209D, 0xFFFFF444, 0x00000398, 0x0000209D, 0xFFFFF444, 0x00000398 },
+ { 0x0213EA94DE0450E4, 0x00002F1F, 0xFFFFEB74, 0x000004EB, 0x00001F4C, 0xFFFFF3D4, 0x000003CE, 0x00001F4C, 0xFFFFF3D4, 0x000003CE },
+ { 0x0213EA94DE043884, 0x00003415, 0xFFFFE89F, 0x00000553, 0x0000186B, 0xFFFFF8E1, 0x000002EF, 0x0000186B, 0xFFFFF8E1, 0x000002EF },
+ { 0x0213F0FD42CC10C4, 0x00003441, 0xFFFFE779, 0x0000059D, 0x000019EA, 0xFFFFF7B2, 0x0000031F, 0x000019EA, 0xFFFFF7B2, 0x0000031F },
+ { 0x0213EA94DE164064, 0x00002174, 0xFFFFF546, 0x00000378, 0x00001456, 0xFFFFFC5F, 0x00000284, 0x00001456, 0xFFFFFC5F, 0x00000284 },
+ { 0x0213F0FD42CE40C4, 0x00003788, 0xFFFFE61E, 0x000005BF, 0x00001DF4, 0xFFFFF562, 0x00000374, 0x00001DF4, 0xFFFFF562, 0x00000374 },
+ { 0x0213EA94DE1E1844, 0x00001C41, 0xFFFFF8C1, 0x000002FC, 0x0000171E, 0xFFFFFA93, 0x000002DE, 0x0000171E, 0xFFFFFA93, 0x000002DE },
+ { 0x0213F0FD42CA3864, 0x00002B15, 0xFFFFEDEC, 0x00000487, 0x000017E4, 0xFFFFF934, 0x000002DF, 0x000017E4, 0xFFFFF934, 0x000002DF },
+ { 0x0213F0FD42CC3144, 0x0000327A, 0xFFFFEA71, 0x000004FF, 0x00001D96, 0xFFFFF63B, 0x00000351, 0x00001D96, 0xFFFFF63B, 0x00000351 },
+ { 0x0213EA94DE1E4064, 0x000023C6, 0xFFFFF3E5, 0x000003B6, 0x000014DE, 0xFFFFFC29, 0x00000294, 0x000014DE, 0xFFFFFC29, 0x00000294 },
+ { 0x0213EA94DE164944, 0x00001F96, 0xFFFFF5FA, 0x00000364, 0x00001397, 0xFFFFFC9D, 0x0000027D, 0x00001397, 0xFFFFFC9D, 0x0000027D },
+ { 0x0213EA94DE063144, 0x00002B51, 0xFFFFEFB5, 0x00000420, 0x00001ACA, 0xFFFFF824, 0x0000030D, 0x00001ACA, 0xFFFFF824, 0x0000030D },
+ { 0x0213EA94DE1E4944, 0x000020DB, 0xFFFFF55B, 0x0000037C, 0x0000153D, 0xFFFFFB5F, 0x000002BA, 0x0000153D, 0xFFFFFB5F, 0x000002BA },
+ { 0x0213EA94DE0221A4, 0x000030BB, 0xFFFFEBDA, 0x000004BC, 0x00001B0E, 0xFFFFF7A8, 0x0000031E, 0x00001B0E, 0xFFFFF7A8, 0x0000031E },
+ { 0x0213F0FD42C62904, 0x000033C4, 0xFFFFEA41, 0x000004FA, 0x000022C6, 0xFFFFF363, 0x000003BC, 0x000022C6, 0xFFFFF363, 0x000003BC },
+ { 0x0213EA94DE240924, 0x00002D47, 0xFFFFEE01, 0x00000477, 0x000021CD, 0xFFFFF36E, 0x000003D6, 0x000021CD, 0xFFFFF36E, 0x000003D6 },
+ { 0x0213EA94DE1E31A4, 0x00001E7B, 0xFFFFF733, 0x00000339, 0x00001668, 0xFFFFFB29, 0x000002BF, 0x00001668, 0xFFFFFB29, 0x000002BF },
+ { 0x0213F0FD42CA2984, 0x00002F7E, 0xFFFFEAFF, 0x000004FC, 0x000018D4, 0xFFFFF8BE, 0x000002E8, 0x000018D4, 0xFFFFF8BE, 0x000002E8 },
+ { 0x0213EA94DE3238A4, 0x00002635, 0xFFFFF2E1, 0x000003BC, 0x000017A4, 0xFFFFFA67, 0x000002C3, 0x000017A4, 0xFFFFFA67, 0x000002C3 },
+ { 0x0213EA94DE1230A4, 0x000026CA, 0xFFFFF2C1, 0x000003B2, 0x00001C3E, 0xFFFFF7AE, 0x0000031F, 0x00001C3E, 0xFFFFF7AE, 0x0000031F },
+ { 0x0213EA94DE1C1064, 0x00002550, 0xFFFFF380, 0x000003B5, 0x000019F5, 0xFFFFF8E7, 0x00000313, 0x000019F5, 0xFFFFF8E7, 0x00000313 },
+ { 0x0213F0FD42CA4904, 0x00002FBC, 0xFFFFEAF8, 0x000004FA, 0x000018CC, 0xFFFFF8C6, 0x000002E8, 0x000018CC, 0xFFFFF8C6, 0x000002E8 },
+ { 0x0213F0FD42D018E4, 0x00002FCC, 0xFFFFEB60, 0x000004EA, 0x00001EFF, 0xFFFFF4DA, 0x0000038F, 0x00001EFF, 0xFFFFF4DA, 0x0000038F },
+ { 0x0213EA94DE164084, 0x000023E6, 0xFFFFF413, 0x000003A1, 0x00001544, 0xFFFFFC16, 0x0000028B, 0x00001544, 0xFFFFFC16, 0x0000028B },
+ { 0x0213F0FD42CE3024, 0x00003251, 0xFFFFEAA2, 0x000004F5, 0x000025B0, 0xFFFFF0DF, 0x00000431, 0x000025B0, 0xFFFFF0DF, 0x00000431 },
+ { 0x0213F0FD42D03984, 0x00002F6F, 0xFFFFEB67, 0x000004E6, 0x00002275, 0xFFFFF249, 0x000003FB, 0x00002275, 0xFFFFF249, 0x000003FB },
+ { 0x0213EA94DE322964, 0x00002597, 0xFFFFF34A, 0x000003B1, 0x00001BCC, 0xFFFFF822, 0x0000031A, 0x00001BCC, 0xFFFFF822, 0x0000031A },
+ { 0x0213F0FD42C63864, 0x00003B1D, 0xFFFFE40E, 0x0000060D, 0x00001F61, 0xFFFFF470, 0x0000039F, 0x00001F61, 0xFFFFF470, 0x0000039F },
+ { 0x0213F0FD42C64144, 0x0000379F, 0xFFFFE6DB, 0x0000058C, 0x00002460, 0xFFFFF170, 0x00000415, 0x00002460, 0xFFFFF170, 0x00000415 },
+ { 0x0213EA94DE165144, 0x00002442, 0xFFFFF2FB, 0x000003D9, 0x00001414, 0xFFFFFBDC, 0x000002A2, 0x00001414, 0xFFFFFBDC, 0x000002A2 },
+ { 0x0213EA94DE0240C4, 0x00003270, 0xFFFFEA0D, 0x0000051C, 0x00001AFD, 0xFFFFF783, 0x00000328, 0x00001AFD, 0xFFFFF783, 0x00000328 },
+ { 0x0213EA94DE161104, 0x00001B23, 0xFFFFF94B, 0x000002EB, 0x000015F1, 0xFFFFFB82, 0x000002B4, 0x000015F1, 0xFFFFFB82, 0x000002B4 },
+ { 0x0213EA94DE323844, 0x000026AE, 0xFFFFF21A, 0x000003DB, 0x00001827, 0xFFFFFA10, 0x000002C8, 0x00001827, 0xFFFFFA10, 0x000002C8 },
+ { 0x0213F0FD42CA4884, 0x00002DCF, 0xFFFFEBD8, 0x000004DB, 0x00001A75, 0xFFFFF719, 0x0000033A, 0x00001A75, 0xFFFFF719, 0x0000033A },
+ { 0x0213F0FD42CE40E4, 0x00003983, 0xFFFFE500, 0x000005EA, 0x000022A6, 0xFFFFF25F, 0x000003F1, 0x000022A6, 0xFFFFF25F, 0x000003F1 },
+ { 0x0213EA94DE1218C4, 0x00002AD5, 0xFFFFF07A, 0x00000406, 0x000019FB, 0xFFFFF961, 0x000002D8, 0x000019FB, 0xFFFFF961, 0x000002D8 },
+ { 0x0213F0FD42CA39A4, 0x00002A43, 0xFFFFEE43, 0x00000474, 0x00001D65, 0xFFFFF538, 0x00000387, 0x00001D65, 0xFFFFF538, 0x00000387 },
+ { 0x0213F0FD42C62084, 0x0000311E, 0xFFFFEAF8, 0x000004E8, 0x00001959, 0xFFFFF8E4, 0x000002DC, 0x00001959, 0xFFFFF8E4, 0x000002DC },
+ { 0x0213F0FD42D031A4, 0x0000339A, 0xFFFFE8A7, 0x00000559, 0x00001A04, 0xFFFFF7E5, 0x00000311, 0x00001A04, 0xFFFFF7E5, 0x00000311 },
+ { 0x0213EA94DE204144, 0x000021B3, 0xFFFFF50F, 0x00000389, 0x00001470, 0xFFFFFBF7, 0x000002A5, 0x00001470, 0xFFFFFBF7, 0x000002A5 },
+ { 0x0213EA94DE021884, 0x00003417, 0xFFFFE9A6, 0x0000051D, 0x000018A4, 0xFFFFF984, 0x000002CF, 0x000018A4, 0xFFFFF984, 0x000002CF },
+ { 0x0213EA94DE202984, 0x00001FED, 0xFFFFF6A2, 0x00000347, 0x00001639, 0xFFFFFB59, 0x000002BB, 0x00001639, 0xFFFFFB59, 0x000002BB },
+ { 0x0213EA94DE1218A4, 0x000032D2, 0xFFFFEB18, 0x000004DC, 0x00001A01, 0xFFFFF95E, 0x000002CF, 0x00001A01, 0xFFFFF95E, 0x000002CF },
+ { 0x0213F0FD42D04084, 0x00003147, 0xFFFFEA3B, 0x00000518, 0x0000241D, 0xFFFFF11C, 0x00000431, 0x0000241D, 0xFFFFF11C, 0x00000431 },
+ { 0x0213EA94DE1C0904, 0x00001D44, 0xFFFFF7E7, 0x0000031A, 0x0000153F, 0xFFFFFBBC, 0x000002A9, 0x0000153F, 0xFFFFFBBC, 0x000002A9 },
+ { 0x0213F0FD42CC4104, 0x00003690, 0xFFFFE6E3, 0x000005A4, 0x000018DE, 0xFFFFF908, 0x000002DD, 0x000018DE, 0xFFFFF908, 0x000002DD },
+ { 0x0213F0FD42CC2184, 0x00003561, 0xFFFFE6F8, 0x000005AB, 0x000018B5, 0xFFFFF8A0, 0x000002F3, 0x000018B5, 0xFFFFF8A0, 0x000002F3 },
+ { 0x0213EA94DE323124, 0x000028F4, 0xFFFFF23A, 0x000003CE, 0x00001BC6, 0xFFFFF881, 0x00000311, 0x00001BC6, 0xFFFFF881, 0x00000311 },
+ { 0x0213F0FD42D03184, 0x000035D7, 0xFFFFE71C, 0x0000059B, 0x00001D49, 0xFFFFF5C8, 0x00000368, 0x00001D49, 0xFFFFF5C8, 0x00000368 },
+ { 0x0213F0FD42CE18A4, 0x0000397E, 0xFFFFE4CB, 0x000005F4, 0x00001989, 0xFFFFF844, 0x000002FD, 0x00001989, 0xFFFFF844, 0x000002FD },
+ { 0x0213F0FD42C62064, 0x00003BAB, 0xFFFFE332, 0x0000063F, 0x00001A69, 0xFFFFF7B9, 0x00000312, 0x00001A69, 0xFFFFF7B9, 0x00000312 },
+ { 0x0213F0FD42D03064, 0x00002F26, 0xFFFFEB82, 0x000004E8, 0x00001D7D, 0xFFFFF590, 0x00000379, 0x00001D7D, 0xFFFFF590, 0x00000379 },
+ { 0x0213EA94DE0631A4, 0x00002FDC, 0xFFFFEBE0, 0x000004C3, 0x00001940, 0xFFFFF8CC, 0x000002EE, 0x00001940, 0xFFFFF8CC, 0x000002EE },
+ { 0x0213EA94DE1C08E4, 0x000021B2, 0xFFFFF558, 0x00000379, 0x00001643, 0xFFFFFB1C, 0x000002C3, 0x00001643, 0xFFFFFB1C, 0x000002C3 },
+ { 0x0213EA94DE321904, 0x00002897, 0xFFFFF181, 0x000003F7, 0x00001990, 0xFFFFF994, 0x000002E2, 0x00001990, 0xFFFFF994, 0x000002E2 },
+ { 0x0213EA94DE1E0924, 0x00001D19, 0xFFFFF829, 0x0000031A, 0x00001558, 0xFFFFFBCA, 0x000002AF, 0x00001558, 0xFFFFFBCA, 0x000002AF },
+ { 0x0213EA94DE043144, 0x00003311, 0xFFFFEAD9, 0x000004E1, 0x00001BDC, 0xFFFFF79E, 0x0000031D, 0x00001BDC, 0xFFFFF79E, 0x0000031D },
+ { 0x0213EA94DE1E29C4, 0x00001E54, 0xFFFFF740, 0x00000333, 0x000016A1, 0xFFFFFAF0, 0x000002C4, 0x000016A1, 0xFFFFFAF0, 0x000002C4 },
+ { 0x0213F0FD42CE3964, 0x00003266, 0xFFFFE9A8, 0x00000527, 0x00002307, 0xFFFFF219, 0x000003FC, 0x00002307, 0xFFFFF219, 0x000003FC },
+ { 0x0213EA94DE321144, 0x00001D1F, 0xFFFFF82B, 0x000002F0, 0x000013F0, 0xFFFFFD0B, 0x0000024E, 0x000013F0, 0xFFFFFD0B, 0x0000024E },
+ { 0x0213F0FD42C648A4, 0x0000312E, 0xFFFFEA67, 0x00000502, 0x0000222A, 0xFFFFF253, 0x000003F9, 0x0000222A, 0xFFFFF253, 0x000003F9 },
+ { 0x0213F0FD42CA4124, 0x000032B2, 0xFFFFE9AD, 0x00000523, 0x00001E97, 0xFFFFF527, 0x0000037F, 0x00001E97, 0xFFFFF527, 0x0000037F },
+ { 0x0213EA94DE1640E4, 0x00001F6A, 0xFFFFF6FC, 0x00000338, 0x0000164B, 0xFFFFFB2C, 0x000002C2, 0x0000164B, 0xFFFFFB2C, 0x000002C2 },
+ { 0x0213EA94DE0228C4, 0x00002603, 0xFFFFF386, 0x00000392, 0x00001EE0, 0xFFFFF601, 0x00000369, 0x00001EE0, 0xFFFFF601, 0x00000369 },
+ { 0x0213EA94DE201164, 0x00001D0C, 0xFFFFF803, 0x00000317, 0x00001345, 0xFFFFFD52, 0x00000260, 0x00001345, 0xFFFFFD52, 0x00000260 },
+ { 0x0213F0FD42CC1884, 0x0000327A, 0xFFFFE8E5, 0x0000055C, 0x00001680, 0xFFFFFA2D, 0x000002B2, 0x00001680, 0xFFFFFA2D, 0x000002B2 },
+ { 0x0213F0FD42CA3964, 0x000032B8, 0xFFFFE91A, 0x0000054A, 0x00001BAB, 0xFFFFF6EC, 0x00000338, 0x00001BAB, 0xFFFFF6EC, 0x00000338 },
+ { 0x0213F0FD42CC3044, 0x00002F79, 0xFFFFEB63, 0x000004EF, 0x000017BB, 0xFFFFF9B1, 0x000002CA, 0x000017BB, 0xFFFFF9B1, 0x000002CA },
+ { 0x0213EA94DE0438E4, 0x00002AE5, 0xFFFFEFCB, 0x0000041D, 0x0000214A, 0xFFFFF3A7, 0x000003C7, 0x0000214A, 0xFFFFF3A7, 0x000003C7 },
+ { 0x0213EA94DE322064, 0x0000212C, 0xFFFFF5BC, 0x0000034F, 0x000017ED, 0xFFFFFA4C, 0x000002C1, 0x000017ED, 0xFFFFFA4C, 0x000002C1 },
+ { 0x0213EA94DE121124, 0x00002BE7, 0xFFFFEF40, 0x0000043C, 0x00001AE2, 0xFFFFF8CF, 0x000002E3, 0x00001AE2, 0xFFFFF8CF, 0x000002E3 },
+ { 0x0213F0FD42D05144, 0x000032DC, 0xFFFFE90F, 0x00000549, 0x00002A2D, 0xFFFFECC9, 0x000004ED, 0x00002A2D, 0xFFFFECC9, 0x000004ED },
+ { 0x0213EA94DE1618A4, 0x00001DE3, 0xFFFFF80D, 0x00000319, 0x000016FA, 0xFFFFFB42, 0x000002BC, 0x000016FA, 0xFFFFFB42, 0x000002BC },
+ { 0x0213EA94DE1E2844, 0x00001F1B, 0xFFFFF6DE, 0x00000346, 0x00001502, 0xFFFFFC23, 0x00000298, 0x00001502, 0xFFFFFC23, 0x00000298 },
+ { 0x0213EA94DE061864, 0x00003203, 0xFFFFEA87, 0x000004FE, 0x0000194E, 0xFFFFF8E3, 0x000002EC, 0x0000194E, 0xFFFFF8E3, 0x000002EC },
+ { 0x0213F0FD42D02144, 0x0000337A, 0xFFFFE8DD, 0x00000551, 0x00001E3C, 0xFFFFF534, 0x00000385, 0x00001E3C, 0xFFFFF534, 0x00000385 },
+ { 0x0213F0FD42CA4864, 0x000036F6, 0xFFFFE62A, 0x000005C5, 0x000023C0, 0xFFFFF117, 0x00000435, 0x000023C0, 0xFFFFF117, 0x00000435 },
+ { 0x0213F0FD42CC2144, 0x00003125, 0xFFFFEA4E, 0x0000051A, 0x00001E6C, 0xFFFFF503, 0x0000038E, 0x00001E6C, 0xFFFFF503, 0x0000038E },
+ { 0x0213EA94DE1C08A4, 0x00001CD4, 0xFFFFF82D, 0x0000030E, 0x0000156D, 0xFFFFFB64, 0x000002B8, 0x0000156D, 0xFFFFFB64, 0x000002B8 },
+ { 0x0213EA94DE0240A4, 0x00002F14, 0xFFFFEC46, 0x000004B8, 0x000017F1, 0xFFFFF977, 0x000002D2, 0x000017F1, 0xFFFFF977, 0x000002D2 },
+ { 0x0213EA94DE0640A4, 0x000031F1, 0xFFFFEAD4, 0x000004ED, 0x0000184C, 0xFFFFF983, 0x000002D4, 0x0000184C, 0xFFFFF983, 0x000002D4 },
+ { 0x0213F0FD42D04984, 0x00002EA9, 0xFFFFEBD7, 0x000004D5, 0x0000288D, 0xFFFFEDDB, 0x000004C0, 0x0000288D, 0xFFFFEDDB, 0x000004C0 },
+ { 0x0213F0FD42CA3984, 0x0000335F, 0xFFFFE82C, 0x00000579, 0x00001DBF, 0xFFFFF512, 0x0000038C, 0x00001DBF, 0xFFFFF512, 0x0000038C },
+ { 0x0213EA94DE201184, 0x0000224F, 0xFFFFF4B5, 0x00000391, 0x0000138C, 0xFFFFFCC3, 0x0000027A, 0x0000138C, 0xFFFFFCC3, 0x0000027A },
+ { 0x0213EA94DE1240A4, 0x0000320D, 0xFFFFEACD, 0x000004F5, 0x00001976, 0xFFFFF913, 0x000002E2, 0x00001976, 0xFFFFF913, 0x000002E2 },
+ { 0x0213EA94DE202104, 0x00001BEB, 0xFFFFF99C, 0x000002E4, 0x000016A4, 0xFFFFFB77, 0x000002C3, 0x000016A4, 0xFFFFFB77, 0x000002C3 },
+ { 0x0213EA94DE063044, 0x0000396E, 0xFFFFE616, 0x000005A9, 0x000018F4, 0xFFFFF91A, 0x000002E3, 0x000018F4, 0xFFFFF91A, 0x000002E3 },
+ { 0x0213EA94DE022864, 0x00003251, 0xFFFFEA8E, 0x000004FA, 0x000018EF, 0xFFFFF910, 0x000002E4, 0x000018EF, 0xFFFFF910, 0x000002E4 },
+ { 0x0213EA94DE1C1924, 0x00001DAF, 0xFFFFF857, 0x0000030D, 0x00001915, 0xFFFFF9D8, 0x000002F7, 0x00001915, 0xFFFFF9D8, 0x000002F7 },
+ { 0x0213EA94DE2041A4, 0x000025B6, 0xFFFFF26B, 0x000003E5, 0x00001531, 0xFFFFFB68, 0x000002AF, 0x00001531, 0xFFFFFB68, 0x000002AF },
+ { 0x0213EA94DE061884, 0x00002B2E, 0xFFFFEF2E, 0x00000440, 0x00001968, 0xFFFFF91A, 0x000002DF, 0x00001968, 0xFFFFF91A, 0x000002DF },
+ { 0x0213EA94DE1C2064, 0x00002305, 0xFFFFF528, 0x00000377, 0x000018A4, 0xFFFFF9EB, 0x000002F0, 0x000018A4, 0xFFFFF9EB, 0x000002F0 },
+ { 0x0213F0FD42CA40C4, 0x000032A1, 0xFFFFE992, 0x0000052E, 0x00001A55, 0xFFFFF826, 0x000002FE, 0x00001A55, 0xFFFFF826, 0x000002FE },
+ { 0x0213EA94DE042184, 0x00002CCD, 0xFFFFEE35, 0x00000462, 0x00001B09, 0xFFFFF7E6, 0x0000030F, 0x00001B09, 0xFFFFF7E6, 0x0000030F },
+ { 0x0213EA94DE323084, 0x00002602, 0xFFFFF2CF, 0x000003C5, 0x000016EE, 0xFFFFFAD4, 0x000002B4, 0x000016EE, 0xFFFFFAD4, 0x000002B4 },
+ { 0x0213F0FD42D01964, 0x00003370, 0xFFFFE891, 0x00000560, 0x000017F0, 0xFFFFF930, 0x000002DF, 0x000017F0, 0xFFFFF930, 0x000002DF },
+ { 0x0213F0FD42CA1884, 0x00002EDC, 0xFFFFEB6D, 0x000004EC, 0x000016E6, 0xFFFFF9ED, 0x000002BC, 0x000016E6, 0xFFFFF9ED, 0x000002BC },
+ { 0x0213EA94DE1228C4, 0x00002A05, 0xFFFFF13D, 0x000003F0, 0x00002065, 0xFFFFF57B, 0x00000378, 0x00002065, 0xFFFFF57B, 0x00000378 },
+ { 0x0213F0FD42CE2044, 0x00002F8A, 0xFFFFEB6E, 0x000004E4, 0x00001E3E, 0xFFFFF50E, 0x0000038D, 0x00001E3E, 0xFFFFF50E, 0x0000038D },
+ { 0x0213F0FD42CA3044, 0x00002BB5, 0xFFFFED6A, 0x000004A1, 0x000017BF, 0xFFFFF937, 0x000002E5, 0x000017BF, 0xFFFFF937, 0x000002E5 },
+ { 0x0213EA94DE201964, 0x0000202C, 0xFFFFF6CE, 0x0000033F, 0x000015EE, 0xFFFFFB83, 0x000002B9, 0x000015EE, 0xFFFFFB83, 0x000002B9 },
+ { 0x0213EA94DE022884, 0x00002C0C, 0xFFFFEF10, 0x0000043F, 0x00001A73, 0xFFFFF83E, 0x0000030C, 0x00001A73, 0xFFFFF83E, 0x0000030C },
+ { 0x0213EA94DE324104, 0x0000234F, 0xFFFFF460, 0x00000385, 0x000018C3, 0xFFFFF9A5, 0x000002DD, 0x000018C3, 0xFFFFF9A5, 0x000002DD },
+ { 0x0213F0FD42CE1904, 0x00003679, 0xFFFFE704, 0x00000595, 0x00002177, 0xFFFFF31A, 0x000003D7, 0x00002177, 0xFFFFF31A, 0x000003D7 },
+ { 0x0213F0FD42CA2924, 0x00003008, 0xFFFFEBB8, 0x000004D5, 0x000024FF, 0xFFFFF112, 0x00000430, 0x000024FF, 0xFFFFF112, 0x00000430 },
+ { 0x0213F0FD42C641A4, 0x00003848, 0xFFFFE6A3, 0x00000594, 0x00002958, 0xFFFFEE37, 0x000004A0, 0x00002958, 0xFFFFEE37, 0x000004A0 },
+ { 0x0213F0FD42CC1924, 0x00002FDF, 0xFFFFEB08, 0x000004FD, 0x00001D77, 0xFFFFF58B, 0x0000037A, 0x00001D77, 0xFFFFF58B, 0x0000037A },
+ { 0x0213EA94DE063064, 0x00002EC8, 0xFFFFED41, 0x00000481, 0x00001949, 0xFFFFF91C, 0x000002DF, 0x00001949, 0xFFFFF91C, 0x000002DF },
+ { 0x0213F0FD42D041A4, 0x000037C1, 0xFFFFE5BA, 0x000005D7, 0x0000252C, 0xFFFFF023, 0x00000460, 0x0000252C, 0xFFFFF023, 0x00000460 },
+ { 0x0213F0FD42CE2944, 0x00003716, 0xFFFFE70C, 0x0000058A, 0x000028CC, 0xFFFFEE57, 0x0000049D, 0x000028CC, 0xFFFFEE57, 0x0000049D },
+ { 0x0213F0FD42CA40E4, 0x000033D1, 0xFFFFE8E8, 0x00000547, 0x00001AB1, 0xFFFFF7E5, 0x00000309, 0x00001AB1, 0xFFFFF7E5, 0x00000309 },
+ { 0x0213F0FD42CC2944, 0x00002D72, 0xFFFFED65, 0x0000048E, 0x00001E0D, 0xFFFFF5A7, 0x00000370, 0x00001E0D, 0xFFFFF5A7, 0x00000370 },
+ { 0x0213EA94DE1C39A4, 0x00002292, 0xFFFFF49F, 0x00000393, 0x000017F4, 0xFFFFF9CD, 0x000002F5, 0x000017F4, 0xFFFFF9CD, 0x000002F5 },
+ { 0x0213EA94DE243044, 0x000026EE, 0xFFFFF18C, 0x000003F7, 0x000018A7, 0xFFFFF95A, 0x000002E5, 0x000018A7, 0xFFFFF95A, 0x000002E5 },
+ { 0x0213EA94DE042164, 0x00002F62, 0xFFFFEC9B, 0x000004A4, 0x0000194E, 0xFFFFF932, 0x000002D9, 0x0000194E, 0xFFFFF932, 0x000002D9 },
+ { 0x0213EA94DE1E3984, 0x00001CE8, 0xFFFFF7FA, 0x0000031C, 0x000014CE, 0xFFFFFBD4, 0x000002AB, 0x000014CE, 0xFFFFFBD4, 0x000002AB },
+ { 0x0213EA94DE1210E4, 0x00002E5A, 0xFFFFEDAB, 0x0000047C, 0x00001A82, 0xFFFFF8F7, 0x000002DE, 0x00001A82, 0xFFFFF8F7, 0x000002DE },
+ { 0x0213F0FD42CC30E4, 0x00003057, 0xFFFFEC34, 0x000004B9, 0x00002296, 0xFFFFF342, 0x000003D0, 0x00002296, 0xFFFFF342, 0x000003D0 },
+ { 0x0213EA94DE0418A4, 0x00002B0F, 0xFFFFEF58, 0x00000434, 0x00001BFD, 0xFFFFF721, 0x00000330, 0x00001BFD, 0xFFFFF721, 0x00000330 },
+ { 0x0213EA94DE2010A4, 0x00001F01, 0xFFFFF751, 0x0000032F, 0x00001502, 0xFFFFFC3E, 0x00000296, 0x00001502, 0xFFFFFC3E, 0x00000296 },
+ { 0x0213F0FD42CA3064, 0x00002FF4, 0xFFFFEAE2, 0x00000503, 0x00001B36, 0xFFFFF736, 0x00000330, 0x00001B36, 0xFFFFF736, 0x00000330 },
+ { 0x0213F0FD42CE2064, 0x00003762, 0xFFFFE5AB, 0x000005DE, 0x000018CB, 0xFFFFF896, 0x000002F4, 0x000018CB, 0xFFFFF896, 0x000002F4 },
+ { 0x0213F0FD42CC2064, 0x00002890, 0xFFFFEF92, 0x00000445, 0x0000191D, 0xFFFFF86F, 0x00000302, 0x0000191D, 0xFFFFF86F, 0x00000302 },
+ { 0x0213EA94DE043064, 0x00002F76, 0xFFFFEC0E, 0x000004BF, 0x00001F7D, 0xFFFFF41A, 0x000003C0, 0x00001F7D, 0xFFFFF41A, 0x000003C0 },
+ { 0x0213EA94DE1E08A4, 0x00001D55, 0xFFFFF7F8, 0x0000031E, 0x000015DF, 0xFFFFFB79, 0x000002B7, 0x000015DF, 0xFFFFFB79, 0x000002B7 },
+ { 0x0213EA94DE204924, 0x00001FE9, 0xFFFFF64A, 0x00000353, 0x000019E8, 0xFFFFF882, 0x0000032A, 0x000019E8, 0xFFFFF882, 0x0000032A },
+ { 0x0213EA94DE063964, 0x000030B5, 0xFFFFEBB8, 0x000004C4, 0x00001857, 0xFFFFF968, 0x000002D8, 0x00001857, 0xFFFFF968, 0x000002D8 },
+ { 0x0213F0FD42CA28C4, 0x00003398, 0xFFFFE9A3, 0x00000524, 0x00001FF9, 0xFFFFF458, 0x000003AD, 0x00001FF9, 0xFFFFF458, 0x000003AD },
+ { 0x0213F0FD42CE2964, 0x00003897, 0xFFFFE5BD, 0x000005C8, 0x00002519, 0xFFFFF0BA, 0x00000438, 0x00002519, 0xFFFFF0BA, 0x00000438 },
+ { 0x0213F0FD42D04064, 0x00003234, 0xFFFFE9B1, 0x00000530, 0x000022CC, 0xFFFFF20E, 0x00000409, 0x000022CC, 0xFFFFF20E, 0x00000409 },
+ { 0x0213EA94DE205104, 0x00001FD2, 0xFFFFF641, 0x00000354, 0x000017C9, 0xFFFFF9C0, 0x000002FB, 0x000017C9, 0xFFFFF9C0, 0x000002FB },
+ { 0x0213F0FD42CE48E4, 0x00003234, 0xFFFFE946, 0x0000053D, 0x00002267, 0xFFFFF1F5, 0x0000040D, 0x00002267, 0xFFFFF1F5, 0x0000040D },
+ { 0x0213EA94DE2029A4, 0x00002330, 0xFFFFF474, 0x00000399, 0x00001490, 0xFFFFFC67, 0x00000288, 0x00001490, 0xFFFFFC67, 0x00000288 },
+ { 0x0213F0FD42D03924, 0x000032A3, 0xFFFFE9EB, 0x0000051B, 0x0000234D, 0xFFFFF23C, 0x000003F7, 0x0000234D, 0xFFFFF23C, 0x000003F7 },
+ { 0x0213EA94DE200904, 0x0000217E, 0xFFFFF53A, 0x00000384, 0x00001511, 0xFFFFFBF5, 0x0000029E, 0x00001511, 0xFFFFFBF5, 0x0000029E },
+ { 0x0213F0FD42CE50E4, 0x0000384F, 0xFFFFE562, 0x000005E2, 0x0000295A, 0xFFFFED53, 0x000004D3, 0x0000295A, 0xFFFFED53, 0x000004D3 },
+ { 0x0213F0FD42D05124, 0x00003315, 0xFFFFE8D1, 0x00000552, 0x000025D1, 0xFFFFEFAF, 0x00000471, 0x000025D1, 0xFFFFEFAF, 0x00000471 },
+ { 0x0213F0FD42C64924, 0x00004183, 0xFFFFDF61, 0x000006DA, 0x0000193C, 0xFFFFF88F, 0x000002EC, 0x0000193C, 0xFFFFF88F, 0x000002EC },
+ { 0x0213EA94DE242164, 0x00002DFC, 0xFFFFEDF2, 0x0000047A, 0x00001755, 0xFFFFFAC2, 0x000002AC, 0x00001755, 0xFFFFFAC2, 0x000002AC },
+ { 0x0213F0FD42CA31A4, 0x000033FE, 0xFFFFE774, 0x0000059F, 0x00001E70, 0xFFFFF492, 0x000003A0, 0x00001E70, 0xFFFFF492, 0x000003A0 },
+ { 0x0213F0FD42C629A4, 0x000040D7, 0xFFFFDFB8, 0x000006CE, 0x00001AC8, 0xFFFFF773, 0x0000031D, 0x00001AC8, 0xFFFFF773, 0x0000031D },
+ { 0x0213EA94DE1E1164, 0x00001D02, 0xFFFFF803, 0x00000322, 0x000015FE, 0xFFFFFB71, 0x000002BB, 0x000015FE, 0xFFFFFB71, 0x000002BB },
+ { 0x0213F0FD42D02884, 0x00002EB0, 0xFFFFEC31, 0x000004C4, 0x00001B3C, 0xFFFFF73B, 0x00000330, 0x00001B3C, 0xFFFFF73B, 0x00000330 },
+ { 0x0213F0FD42CA4984, 0x00002D9F, 0xFFFFECBF, 0x000004A8, 0x000022B0, 0xFFFFF23C, 0x000003F9, 0x000022B0, 0xFFFFF23C, 0x000003F9 },
+ { 0x0213F0FD42CC18E4, 0x00002C6A, 0xFFFFEDAC, 0x00000488, 0x00002419, 0xFFFFF159, 0x00000427, 0x00002419, 0xFFFFF159, 0x00000427 },
+ { 0x0213EA94DE1210A4, 0x00002991, 0xFFFFF06C, 0x0000040E, 0x00001AA9, 0xFFFFF8D0, 0x000002E1, 0x00001AA9, 0xFFFFF8D0, 0x000002E1 },
+ { 0x0213EA94DE123904, 0x00002F8E, 0xFFFFED1B, 0x00000493, 0x00001DE4, 0xFFFFF69C, 0x00000347, 0x00001DE4, 0xFFFFF69C, 0x00000347 },
+ { 0x0213EA94DE204184, 0x00002136, 0xFFFFF540, 0x0000037C, 0x000014FF, 0xFFFFFB83, 0x000002B2, 0x000014FF, 0xFFFFFB83, 0x000002B2 },
+ { 0x0213EA94DE0618E4, 0x0000354C, 0xFFFFE97D, 0x0000051A, 0x00001906, 0xFFFFF965, 0x000002DD, 0x00001906, 0xFFFFF965, 0x000002DD },
+ { 0x0213F0FD42C620C4, 0x0000348B, 0xFFFFE94D, 0x0000051F, 0x0000285B, 0xFFFFEF1A, 0x00000473, 0x0000285B, 0xFFFFEF1A, 0x00000473 },
+ { 0x0213EA94DE3218A4, 0x000026E6, 0xFFFFF24E, 0x000003D6, 0x0000141F, 0xFFFFFCCE, 0x00000260, 0x0000141F, 0xFFFFFCCE, 0x00000260 },
+ { 0x0213F0FD42C64164, 0x00003CED, 0xFFFFE2A5, 0x0000064E, 0x00002060, 0xFFFFF3E0, 0x000003B0, 0x00002060, 0xFFFFF3E0, 0x000003B0 },
+ { 0x0213EA94DE021084, 0x000029D4, 0xFFFFEFF7, 0x00000426, 0x00001976, 0xFFFFF8E1, 0x000002EE, 0x00001976, 0xFFFFF8E1, 0x000002EE },
+ { 0x0213F0FD42CA40A4, 0x00003767, 0xFFFFE601, 0x000005CC, 0x00001D22, 0xFFFFF5F4, 0x00000361, 0x00001D22, 0xFFFFF5F4, 0x00000361 },
+ { 0x0213F0FD42C650C4, 0x00003CE8, 0xFFFFE2E8, 0x00000637, 0x0000232C, 0xFFFFF1E7, 0x00000405, 0x0000232C, 0xFFFFF1E7, 0x00000405 },
+ { 0x0213EA94DE201064, 0x000023A8, 0xFFFFF4CD, 0x00000386, 0x00001944, 0xFFFFF983, 0x00000300, 0x00001944, 0xFFFFF983, 0x00000300 },
+ { 0x0213F0FD42CC30A4, 0x00003451, 0xFFFFE8B9, 0x00000551, 0x00001AD7, 0xFFFFF7BF, 0x00000318, 0x00001AD7, 0xFFFFF7BF, 0x00000318 },
+ { 0x0213F0FD42CE2984, 0x0000381B, 0xFFFFE5A0, 0x000005D0, 0x00001E0F, 0xFFFFF521, 0x00000382, 0x00001E0F, 0xFFFFF521, 0x00000382 },
+ { 0x0213EA94DE2038C4, 0x000023A4, 0xFFFFF4A6, 0x00000394, 0x0000171F, 0xFFFFFABB, 0x000002D9, 0x0000171F, 0xFFFFFABB, 0x000002D9 },
+ { 0x0213F0FD42C620A4, 0x00003C2B, 0xFFFFE447, 0x000005F0, 0x0000207F, 0xFFFFF44E, 0x0000039A, 0x0000207F, 0xFFFFF44E, 0x0000039A },
+ { 0x0213F0FD42CC3984, 0x00002F07, 0xFFFFEB70, 0x000004E9, 0x00001765, 0xFFFFF9A5, 0x000002C6, 0x00001765, 0xFFFFF9A5, 0x000002C6 },
+ { 0x0213F0FD42C62984, 0x00003A01, 0xFFFFE4E0, 0x000005E7, 0x0000227A, 0xFFFFF292, 0x000003E5, 0x0000227A, 0xFFFFF292, 0x000003E5 },
+ { 0x0213F0FD42CE20A4, 0x0000376E, 0xFFFFE686, 0x000005A6, 0x00001FCF, 0xFFFFF43B, 0x000003A8, 0x00001FCF, 0xFFFFF43B, 0x000003A8 },
+ { 0x0213F0FFEF5A4984, 0x0000485F, 0xFFFFDCC1, 0x00000713, 0x00002CF8, 0xFFFFEC45, 0x000004DA, 0x00002CF8, 0xFFFFEC45, 0x000004DA },
+ { 0x0213F0FFEF5C3184, 0x0000331C, 0xFFFFE8FF, 0x00000541, 0x00002366, 0xFFFFF19D, 0x00000411, 0x00002366, 0xFFFFF19D, 0x00000411 },
+ { 0x0213F0FFEF643864, 0x00003CF3, 0xFFFFE15A, 0x00000694, 0x00002FB3, 0xFFFFE827, 0x000005B9, 0x00002FB3, 0xFFFFE827, 0x000005B9 },
+ { 0x0213EA94DE321104, 0x000023F3, 0xFFFFF3EA, 0x0000039A, 0x00001345, 0xFFFFFD6B, 0x00000241, 0x00001345, 0xFFFFFD6B, 0x00000241 },
+ { 0x0213F0FFEF5C28A4, 0x000038C0, 0xFFFFE58A, 0x000005CC, 0x000023CA, 0xFFFFF1AA, 0x00000408, 0x000023CA, 0xFFFFF1AA, 0x00000408 },
+ { 0x0213F0FFEF662944, 0x00004976, 0xFFFFDD6A, 0x000006D7, 0x000033C6, 0xFFFFE8EB, 0x0000054D, 0x000033C6, 0xFFFFE8EB, 0x0000054D },
+ { 0x0213F0FFEF644904, 0x00004049, 0xFFFFDF6D, 0x000006D8, 0x00003129, 0xFFFFE716, 0x000005E9, 0x00003129, 0xFFFFE716, 0x000005E9 },
+ { 0x0213F0FFEF661164, 0x000046C2, 0xFFFFDCEB, 0x0000071C, 0x00002E6D, 0xFFFFEA8F, 0x0000052E, 0x00002E6D, 0xFFFFEA8F, 0x0000052E },
+ { 0x0213F0FFEF6238A4, 0x00004080, 0xFFFFE1E1, 0x0000063A, 0x0000396D, 0xFFFFE40A, 0x0000062C, 0x0000396D, 0xFFFFE40A, 0x0000062C },
+ { 0x0213F0FFEF5E2124, 0x00003DE0, 0xFFFFE358, 0x0000060C, 0x00002AA2, 0xFFFFEDBF, 0x000004A0, 0x00002AA2, 0xFFFFEDBF, 0x000004A0 },
+ { 0x0213F0FFEF5E3144, 0x00003FC0, 0xFFFFE2A1, 0x0000061A, 0x000027D8, 0xFFFFEFEC, 0x0000043A, 0x000027D8, 0xFFFFEFEC, 0x0000043A },
+ { 0x0213F0FFEF661924, 0x00003FBF, 0xFFFFE2F5, 0x00000603, 0x000032D7, 0xFFFFE900, 0x00000552, 0x000032D7, 0xFFFFE900, 0x00000552 },
+ { 0x0213F0FFEF5C10E4, 0x000035EE, 0xFFFFE6CA, 0x000005A2, 0x0000247C, 0xFFFFF088, 0x00000446, 0x0000247C, 0xFFFFF088, 0x00000446 },
+ { 0x0213F0FFEF643884, 0x000039C8, 0xFFFFE3AE, 0x0000062A, 0x000028AF, 0xFFFFED24, 0x000004DF, 0x000028AF, 0xFFFFED24, 0x000004DF },
+ { 0x0213F0FFEF5C2884, 0x00003BDE, 0xFFFFE33B, 0x00000632, 0x00001B6C, 0xFFFFF720, 0x00000326, 0x00001B6C, 0xFFFFF720, 0x00000326 },
+ { 0x0213F0FFEF7210A4, 0x00003818, 0xFFFFE57D, 0x000005D4, 0x000020EF, 0xFFFFF327, 0x000003CE, 0x000020EF, 0xFFFFF327, 0x000003CE },
+ { 0x0213F0FFEF5E19A4, 0x000038DA, 0xFFFFE561, 0x000005D3, 0x0000297D, 0xFFFFED6D, 0x000004C5, 0x0000297D, 0xFFFFED6D, 0x000004C5 },
+ { 0x0213F0FFEF684884, 0x000027AC, 0xFFFFF0CE, 0x00000417, 0x00001F5F, 0xFFFFF484, 0x000003B2, 0x00001F5F, 0xFFFFF484, 0x000003B2 },
+ { 0x0213F0FFEF6648A4, 0x00003F02, 0xFFFFE222, 0x00000643, 0x000026D4, 0xFFFFF000, 0x00000443, 0x000026D4, 0xFFFFF000, 0x00000443 },
+ { 0x0213F0FFEF624164, 0x00004303, 0xFFFFDFE3, 0x00000690, 0x0000312C, 0xFFFFE912, 0x00000561, 0x0000312C, 0xFFFFE912, 0x00000561 },
+ { 0x0213F0FFEF600904, 0x000039E5, 0xFFFFE31F, 0x00000657, 0x00001D23, 0xFFFFF51F, 0x00000386, 0x00001D23, 0xFFFFF51F, 0x00000386 },
+ { 0x0213F0FFEF661144, 0x000041FA, 0xFFFFE01B, 0x00000697, 0x00002767, 0xFFFFEF90, 0x00000455, 0x00002767, 0xFFFFEF90, 0x00000455 },
+ { 0x0213F0FFEF6830A4, 0x00002888, 0xFFFFF11C, 0x00000403, 0x00001864, 0xFFFFF9D8, 0x000002D3, 0x00001864, 0xFFFFF9D8, 0x000002D3 },
+ { 0x0213EA94DE201864, 0x0000215C, 0xFFFFF5B6, 0x0000036D, 0x000015C5, 0xFFFFFB8A, 0x000002B5, 0x000015C5, 0xFFFFFB8A, 0x000002B5 },
+ { 0x0213F0FFEF683984, 0x00002FAF, 0xFFFFEC27, 0x000004CA, 0x00002184, 0xFFFFF39C, 0x000003CD, 0x00002184, 0xFFFFF39C, 0x000003CD },
+ { 0x0213F0FFEF5E10C4, 0x00004ACE, 0xFFFFD9A3, 0x000007BC, 0x00001A5D, 0xFFFFF7F6, 0x000002FC, 0x00001A5D, 0xFFFFF7F6, 0x000002FC },
+ { 0x0213F0FFEF5A3044, 0x00003763, 0xFFFFE797, 0x0000055F, 0x000029B5, 0xFFFFEEA1, 0x00000474, 0x000029B5, 0xFFFFEEA1, 0x00000474 },
+ { 0x0213F0FFEF5E3164, 0x00003832, 0xFFFFE6F9, 0x00000575, 0x00002C99, 0xFFFFEC42, 0x000004E3, 0x00002C99, 0xFFFFEC42, 0x000004E3 },
+ { 0x0213F0FFEF604164, 0x000041C9, 0xFFFFDE33, 0x0000071E, 0x0000199D, 0xFFFFF808, 0x000002F9, 0x0000199D, 0xFFFFF808, 0x000002F9 },
+ { 0x0213F0FFEF641164, 0x0000474A, 0xFFFFD96E, 0x00000802, 0x00002A30, 0xFFFFEB57, 0x0000053F, 0x00002A30, 0xFFFFEB57, 0x0000053F },
+ { 0x0213F0FFEF5C31C4, 0x0000312F, 0xFFFFEA6A, 0x00000508, 0x000029D3, 0xFFFFED38, 0x000004D3, 0x000029D3, 0xFFFFED38, 0x000004D3 },
+ { 0x0213F0FFEF7210C4, 0x00003BD6, 0xFFFFE2E7, 0x00000644, 0x00002093, 0xFFFFF37B, 0x000003BD, 0x00002093, 0xFFFFF37B, 0x000003BD },
+ { 0x0213F0FFEF6840E4, 0x00002F94, 0xFFFFECD4, 0x000004A3, 0x00002196, 0xFFFFF40B, 0x000003B5, 0x00002196, 0xFFFFF40B, 0x000003B5 },
+ { 0x0213F0FFEF5E1944, 0x0000369B, 0xFFFFE762, 0x00000571, 0x00002726, 0xFFFFEF99, 0x00000459, 0x00002726, 0xFFFFEF99, 0x00000459 },
+ { 0x0213F0FFEF642064, 0x00003F57, 0xFFFFDF47, 0x000006F4, 0x00002E5F, 0xFFFFE8AE, 0x000005AB, 0x00002E5F, 0xFFFFE8AE, 0x000005AB },
+ { 0x0213EA94DE0A40C4, 0x00004313, 0xFFFFDD81, 0x0000072D, 0x00002468, 0xFFFFF068, 0x00000440, 0x00002468, 0xFFFFF068, 0x00000440 },
+ { 0x0213F0FFEF683044, 0x00002A35, 0xFFFFEFA8, 0x00000441, 0x00001F3F, 0xFFFFF4F3, 0x000003A0, 0x00001F3F, 0xFFFFF4F3, 0x000003A0 },
+ { 0x0213F0FFEF6630A4, 0x00003E33, 0xFFFFE4B0, 0x000005AF, 0x00002802, 0xFFFFF092, 0x00000412, 0x00002802, 0xFFFFF092, 0x00000412 },
+ { 0x0213EA94DE323904, 0x00002815, 0xFFFFF20E, 0x000003DD, 0x00001C33, 0xFFFFF7D5, 0x0000032A, 0x00001C33, 0xFFFFF7D5, 0x0000032A },
+ { 0x0213F0FFEF5A2184, 0x00003CC2, 0xFFFFE43E, 0x000005DE, 0x00002C16, 0xFFFFECED, 0x000004BA, 0x00002C16, 0xFFFFECED, 0x000004BA },
+ { 0x0213F0FFEF5C4084, 0x00003CFA, 0xFFFFE1EE, 0x00000673, 0x00001F7D, 0xFFFFF402, 0x000003AE, 0x00001F7D, 0xFFFFF402, 0x000003AE },
+ { 0x0213F0FFEF622104, 0x0000486E, 0xFFFFDD43, 0x000006EE, 0x000036F0, 0xFFFFE609, 0x000005D5, 0x000036F0, 0xFFFFE609, 0x000005D5 },
+ { 0x0213F0FFEF5C4964, 0x000039FE, 0xFFFFE41F, 0x00000613, 0x0000266C, 0xFFFFEF35, 0x0000047D, 0x0000266C, 0xFFFFEF35, 0x0000047D },
+ { 0x0213EA94DE123124, 0x00002EA4, 0xFFFFEE3B, 0x00000462, 0x00002126, 0xFFFFF4E2, 0x0000038F, 0x00002126, 0xFFFFF4E2, 0x0000038F },
+ { 0x0213F0FFEF683944, 0x00002D2E, 0xFFFFEE7B, 0x00000462, 0x0000229D, 0xFFFFF363, 0x000003D4, 0x0000229D, 0xFFFFF363, 0x000003D4 },
+ { 0x0213F0FFEF5E2844, 0x0000375C, 0xFFFFE695, 0x0000059D, 0x00002319, 0xFFFFF237, 0x000003EE, 0x00002319, 0xFFFFF237, 0x000003EE },
+ { 0x0213F0FFEF7250C4, 0x00004522, 0xFFFFDC71, 0x0000075E, 0x0000247E, 0xFFFFF0A0, 0x0000043C, 0x0000247E, 0xFFFFF0A0, 0x0000043C },
+ { 0x0213EA94DE1248E4, 0x00002E58, 0xFFFFECB9, 0x000004A9, 0x0000199A, 0xFFFFF8CF, 0x000002E9, 0x0000199A, 0xFFFFF8CF, 0x000002E9 },
+ { 0x0213F0FFEF6438E4, 0x00003791, 0xFFFFE5FE, 0x000005B6, 0x000029F5, 0xFFFFED0D, 0x000004CD, 0x000029F5, 0xFFFFED0D, 0x000004CD },
+ { 0x0213EA94DE244144, 0x00002E9E, 0xFFFFEC8D, 0x000004C1, 0x000019D0, 0xFFFFF869, 0x0000030F, 0x000019D0, 0xFFFFF869, 0x0000030F },
+ { 0x0213EA94DE203964, 0x0000237C, 0xFFFFF435, 0x000003A6, 0x000014EB, 0xFFFFFBC4, 0x000002AF, 0x000014EB, 0xFFFFFBC4, 0x000002AF },
+ { 0x0213F0FFEF662924, 0x00003FE5, 0xFFFFE4A2, 0x000005A0, 0x00003416, 0xFFFFE995, 0x00000523, 0x00003416, 0xFFFFE995, 0x00000523 },
+ { 0x0213F0FFEF5C0924, 0x00002B27, 0xFFFFED51, 0x000004A5, 0x000025D1, 0xFFFFEF18, 0x00000492, 0x000025D1, 0xFFFFEF18, 0x00000492 },
+ { 0x0213F0FFEF684904, 0x00002D77, 0xFFFFED79, 0x00000494, 0x00002196, 0xFFFFF352, 0x000003DE, 0x00002196, 0xFFFFF352, 0x000003DE },
+ { 0x0213F0FFEF5C20C4, 0x00003750, 0xFFFFE6AC, 0x00000596, 0x00002524, 0xFFFFF0B5, 0x00000431, 0x00002524, 0xFFFFF0B5, 0x00000431 },
+ { 0x0213EA94DE122944, 0x00002896, 0xFFFFF1BB, 0x000003D9, 0x00001CE0, 0xFFFFF753, 0x0000032F, 0x00001CE0, 0xFFFFF753, 0x0000032F },
+ { 0x0213F0FFEF641984, 0x00003CA7, 0xFFFFE0F7, 0x000006B1, 0x00002CB8, 0xFFFFE9AB, 0x00000587, 0x00002CB8, 0xFFFFE9AB, 0x00000587 },
+ { 0x0213EA94DE322864, 0x00002513, 0xFFFFF323, 0x000003BC, 0x00001965, 0xFFFFF93C, 0x000002F0, 0x00001965, 0xFFFFF93C, 0x000002F0 },
+ { 0x0213F0FFEF662164, 0x00003914, 0xFFFFE683, 0x00000586, 0x00003120, 0xFFFFE9A6, 0x00000543, 0x00003120, 0xFFFFE9A6, 0x00000543 },
+ { 0x0213F0FFEF643904, 0x000040D0, 0xFFFFE007, 0x000006AC, 0x00002B9E, 0xFFFFEBF5, 0x000004FB, 0x00002B9E, 0xFFFFEBF5, 0x000004FB },
+ { 0x0213F0FFEF5A4884, 0x00004412, 0xFFFFDF5F, 0x000006A9, 0x00002A9E, 0xFFFFEDCE, 0x00000498, 0x00002A9E, 0xFFFFEDCE, 0x00000498 },
+ { 0x0213F0FFEF624884, 0x000042A6, 0xFFFFDFEF, 0x00000696, 0x00002E65, 0xFFFFEAAE, 0x00000529, 0x00002E65, 0xFFFFEAAE, 0x00000529 },
+ { 0x0213EA94DE322124, 0x000022E8, 0xFFFFF565, 0x0000035F, 0x00001890, 0xFFFFFA61, 0x000002C6, 0x00001890, 0xFFFFFA61, 0x000002C6 },
+ { 0x0213F0FFEF6239A4, 0x00004637, 0xFFFFDDD8, 0x000006E9, 0x0000349D, 0xFFFFE6C8, 0x000005C7, 0x0000349D, 0xFFFFE6C8, 0x000005C7 },
+ { 0x0213EA94DE263904, 0x00004686, 0xFFFFDC58, 0x0000073D, 0x00003972, 0xFFFFE27B, 0x0000068E, 0x00003972, 0xFFFFE27B, 0x0000068E },
+ { 0x0213F0FFEF6808E4, 0x00002B35, 0xFFFFEE9C, 0x0000046C, 0x00001F5B, 0xFFFFF4A3, 0x000003A9, 0x00001F5B, 0xFFFFF4A3, 0x000003A9 },
+ { 0x0213F0FFEF724144, 0x00003AC9, 0xFFFFE3B2, 0x0000061B, 0x000023A1, 0xFFFFF170, 0x0000040F, 0x000023A1, 0xFFFFF170, 0x0000040F },
+ { 0x0213F0FFEF5E1884, 0x00003C50, 0xFFFFE37E, 0x00000617, 0x0000218F, 0xFFFFF339, 0x000003C4, 0x0000218F, 0xFFFFF339, 0x000003C4 },
+ { 0x0213F0FFEF663044, 0x00003793, 0xFFFFE761, 0x0000055D, 0x000029C7, 0xFFFFEE03, 0x00000496, 0x000029C7, 0xFFFFEE03, 0x00000496 },
+ { 0x0213F0FFEF6438A4, 0x000040B5, 0xFFFFDF78, 0x000006DA, 0x00002DED, 0xFFFFEA20, 0x00000551, 0x00002DED, 0xFFFFEA20, 0x00000551 },
+ { 0x0213F0FFEF601144, 0x000039D6, 0xFFFFE37D, 0x0000063C, 0x00001AED, 0xFFFFF6E2, 0x00000331, 0x00001AED, 0xFFFFF6E2, 0x00000331 },
+ { 0x0213F0FFEF662144, 0x0000431F, 0xFFFFE09B, 0x0000066A, 0x00002BDF, 0xFFFFED93, 0x00000496, 0x00002BDF, 0xFFFFED93, 0x00000496 },
+ { 0x0213F0FFEF623864, 0x00004887, 0xFFFFDC65, 0x00000721, 0x00003669, 0xFFFFE5C4, 0x000005E9, 0x00003669, 0xFFFFE5C4, 0x000005E9 },
+ { 0x0213F0FFEF640924, 0x00004120, 0xFFFFDDAE, 0x00000748, 0x0000303B, 0xFFFFE70D, 0x000005FC, 0x0000303B, 0xFFFFE70D, 0x000005FC },
+ { 0x0213F0FFEF5E28A4, 0x0000415D, 0xFFFFE0BE, 0x0000067B, 0x00002FA7, 0xFFFFEA28, 0x00000538, 0x00002FA7, 0xFFFFEA28, 0x00000538 },
+ { 0x0213F0FFEF681904, 0x00002B12, 0xFFFFEFF9, 0x00000428, 0x00001DDA, 0xFFFFF693, 0x00000356, 0x00001DDA, 0xFFFFF693, 0x00000356 },
+ { 0x0213F0FFEF5E3184, 0x00003ED3, 0xFFFFE28D, 0x0000062D, 0x00002B00, 0xFFFFED4E, 0x000004B3, 0x00002B00, 0xFFFFED4E, 0x000004B3 },
+ { 0x0213F0FFEF6250A4, 0x00004218, 0xFFFFE039, 0x0000068F, 0x00002F84, 0xFFFFEA0C, 0x00000541, 0x00002F84, 0xFFFFEA0C, 0x00000541 },
+ { 0x0213F0FFEF5A3844, 0x00003FF5, 0xFFFFE2A3, 0x00000617, 0x00003017, 0xFFFFEA7A, 0x00000520, 0x00003017, 0xFFFFEA7A, 0x00000520 },
+ { 0x0213F0FFEF5A08A4, 0x00004304, 0xFFFFDFCC, 0x0000069E, 0x00002E0C, 0xFFFFEB51, 0x00000505, 0x00002E0C, 0xFFFFEB51, 0x00000505 },
+ { 0x0213F0FFEF641944, 0x00003D3A, 0xFFFFE17F, 0x00000687, 0x0000284C, 0xFFFFED83, 0x000004CD, 0x0000284C, 0xFFFFED83, 0x000004CD },
+ { 0x0213F0FFEF5E40A4, 0x000042F5, 0xFFFFDF76, 0x000006B2, 0x000027B6, 0xFFFFEF72, 0x00000455, 0x000027B6, 0xFFFFEF72, 0x00000455 },
+ { 0x0213F0FFEF5C38C4, 0x00004267, 0xFFFFDF29, 0x000006D5, 0x0000298F, 0xFFFFEDBD, 0x000004AC, 0x0000298F, 0xFFFFEDBD, 0x000004AC },
+ { 0x0213EA94DE240924, 0x0000303E, 0xFFFFEC00, 0x000004CB, 0x000021CD, 0xFFFFF36E, 0x000003D6, 0x000021CD, 0xFFFFF36E, 0x000003D6 },
+ { 0x0213F0FFEF5E28C4, 0x00003127, 0xFFFFEBDB, 0x000004A6, 0x00002E95, 0xFFFFEB78, 0x000004F3, 0x00002E95, 0xFFFFEB78, 0x000004F3 },
+ { 0x0213EA94DE1C1064, 0x00002655, 0xFFFFF2D9, 0x000003CF, 0x000019F5, 0xFFFFF8E7, 0x00000313, 0x000019F5, 0xFFFFF8E7, 0x00000313 },
+ { 0x0213EA94DE164084, 0x00002372, 0xFFFFF449, 0x0000039B, 0x00001544, 0xFFFFFC16, 0x0000028B, 0x00001544, 0xFFFFFC16, 0x0000028B },
+ { 0x0213F0FFEF6628C4, 0x0000348E, 0xFFFFEB20, 0x000004B2, 0x00002BE8, 0xFFFFEE80, 0x00000467, 0x00002BE8, 0xFFFFEE80, 0x00000467 },
+ { 0x0213F0FFEF5E1104, 0x00004092, 0xFFFFE073, 0x0000069B, 0x00002061, 0xFFFFF403, 0x000003A0, 0x00002061, 0xFFFFF403, 0x000003A0 },
+ { 0x0213F0FFEF7220E4, 0x000039D1, 0xFFFFE55D, 0x000005CC, 0x000025CB, 0xFFFFF0C0, 0x00000428, 0x000025CB, 0xFFFFF0C0, 0x00000428 },
+ { 0x0213F0FFEF5E4884, 0x000042AA, 0xFFFFDF68, 0x000006C2, 0x0000290B, 0xFFFFEE78, 0x00000485, 0x0000290B, 0xFFFFEE78, 0x00000485 },
+ { 0x0213F0FFEF7218C4, 0x0000356F, 0xFFFFE7AC, 0x0000056E, 0x00001BE8, 0xFFFFF6E3, 0x0000032A, 0x00001BE8, 0xFFFFF6E3, 0x0000032A },
+ { 0x0213F0FFEF5E1144, 0x00003525, 0xFFFFE7FF, 0x0000055D, 0x0000242C, 0xFFFFF12E, 0x0000041D, 0x0000242C, 0xFFFFF12E, 0x0000041D },
+ { 0x0213F0FFEF5C48C4, 0x00003360, 0xFFFFE895, 0x00000550, 0x00002175, 0xFFFFF29E, 0x000003E9, 0x00002175, 0xFFFFF29E, 0x000003E9 },
+ { 0x0213F0FFEF6440A4, 0x00003C94, 0xFFFFE1C4, 0x0000067E, 0x00002E28, 0xFFFFE964, 0x0000057F, 0x00002E28, 0xFFFFE964, 0x0000057F },
+ { 0x0213F0FFEF724124, 0x0000431C, 0xFFFFDE4B, 0x000006FF, 0x00002270, 0xFFFFF268, 0x000003E5, 0x00002270, 0xFFFFF268, 0x000003E5 },
+ { 0x0213EA94DE1218C4, 0x00002B67, 0xFFFFF01D, 0x00000414, 0x000019FB, 0xFFFFF961, 0x000002D8, 0x000019FB, 0xFFFFF961, 0x000002D8 },
+ { 0x0213F0FFEF5E3984, 0x0000400B, 0xFFFFE13D, 0x0000066F, 0x000024F3, 0xFFFFF125, 0x00000417, 0x000024F3, 0xFFFFF125, 0x00000417 },
+ { 0x0213F0FFEF5A20A4, 0x00004460, 0xFFFFE00E, 0x0000067B, 0x000023DF, 0xFFFFF2E6, 0x000003BB, 0x000023DF, 0xFFFFF2E6, 0x000003BB },
+ { 0x0213F0FFEF641864, 0x00003AFB, 0xFFFFE2C5, 0x00000650, 0x00002D46, 0xFFFFE9C4, 0x00000571, 0x00002D46, 0xFFFFE9C4, 0x00000571 },
+ { 0x0213F0FFEF622924, 0x00005482, 0xFFFFD5BC, 0x0000081A, 0x00003250, 0xFFFFE961, 0x00000541, 0x00003250, 0xFFFFE961, 0x00000541 },
+ { 0x0213F0FFEF5C2944, 0x00003D27, 0xFFFFE2FA, 0x00000632, 0x00002A4D, 0xFFFFED6A, 0x000004BB, 0x00002A4D, 0xFFFFED6A, 0x000004BB },
+ { 0x0213F0FFEF6018A4, 0x00003E03, 0xFFFFE142, 0x00000690, 0x00001E08, 0xFFFFF555, 0x0000036C, 0x00001E08, 0xFFFFF555, 0x0000036C },
+ { 0x0213F0FFEF5C2064, 0x000031B5, 0xFFFFE97D, 0x00000535, 0x0000232E, 0xFFFFF166, 0x00000422, 0x0000232E, 0xFFFFF166, 0x00000422 },
+ { 0x0213F0FFEF5E18E4, 0x00003753, 0xFFFFE724, 0x00000575, 0x0000281A, 0xFFFFEF1A, 0x0000046B, 0x0000281A, 0xFFFFEF1A, 0x0000046B },
+ { 0x0213EA94DE204144, 0x00002071, 0xFFFFF5C9, 0x0000036F, 0x00001470, 0xFFFFFBF7, 0x000002A5, 0x00001470, 0xFFFFFBF7, 0x000002A5 },
+ { 0x0213F0FFEF683144, 0x00002799, 0xFFFFF223, 0x000003CF, 0x00001CD3, 0xFFFFF74A, 0x00000333, 0x00001CD3, 0xFFFFF74A, 0x00000333 },
+ { 0x0213F0FFEF6610C4, 0x000040DF, 0xFFFFE11C, 0x00000664, 0x000031D4, 0xFFFFE8BC, 0x0000056F, 0x000031D4, 0xFFFFE8BC, 0x0000056F },
+ { 0x0213F0FFEF6440C4, 0x00003A4D, 0xFFFFE3A6, 0x00000627, 0x00002871, 0xFFFFEDA0, 0x000004C0, 0x00002871, 0xFFFFEDA0, 0x000004C0 },
+ { 0x0213F0FFEF681984, 0x00002AF9, 0xFFFFEED7, 0x00000464, 0x0000219B, 0xFFFFF368, 0x000003D6, 0x0000219B, 0xFFFFF368, 0x000003D6 },
+ { 0x0213EA94DE323124, 0x000026D5, 0xFFFFF36C, 0x000003A3, 0x00001BC6, 0xFFFFF881, 0x00000311, 0x00001BC6, 0xFFFFF881, 0x00000311 },
+ { 0x0213F0FFEF5E2044, 0x0000325D, 0xFFFFEA07, 0x0000050B, 0x000026D1, 0xFFFFEFB3, 0x0000045A, 0x000026D1, 0xFFFFEFB3, 0x0000045A },
+ { 0x0213F0FFEF682864, 0x00002F75, 0xFFFFEC64, 0x000004BE, 0x00001EEB, 0xFFFFF559, 0x00000386, 0x00001EEB, 0xFFFFF559, 0x00000386 },
+ { 0x0213F0FFEF5A38A4, 0x00003C2F, 0xFFFFE541, 0x000005A3, 0x000025B6, 0xFFFFF16F, 0x000003FA, 0x000025B6, 0xFFFFF16F, 0x000003FA },
+ { 0x0213F0FFEF684924, 0x00002BC2, 0xFFFFEE89, 0x0000046A, 0x00001D04, 0xFFFFF651, 0x00000361, 0x00001D04, 0xFFFFF651, 0x00000361 },
+ { 0x0213F0FFEF6829A4, 0x00002DD0, 0xFFFFED40, 0x0000049F, 0x00001C8C, 0xFFFFF6B3, 0x00000353, 0x00001C8C, 0xFFFFF6B3, 0x00000353 },
+ { 0x0213EA94DE1C08E4, 0x000021ED, 0xFFFFF530, 0x00000380, 0x00001643, 0xFFFFFB1C, 0x000002C3, 0x00001643, 0xFFFFFB1C, 0x000002C3 },
+ { 0x0213EA94DE321904, 0x000028C7, 0xFFFFF160, 0x000003FD, 0x00001990, 0xFFFFF994, 0x000002E2, 0x00001990, 0xFFFFF994, 0x000002E2 },
+ { 0x0213F0FFEF6610A4, 0x0000431C, 0xFFFFDF9D, 0x000006A3, 0x000034A6, 0xFFFFE6B0, 0x000005C9, 0x000034A6, 0xFFFFE6B0, 0x000005C9 },
+ { 0x0213EA94DE2630A4, 0x00004115, 0xFFFFE0D6, 0x00000667, 0x000031AD, 0xFFFFE850, 0x00000585, 0x000031AD, 0xFFFFE850, 0x00000585 },
+ { 0x0213F0FFEF643924, 0x0000424A, 0xFFFFDEEC, 0x000006E1, 0x0000346A, 0xFFFFE5EA, 0x00000602, 0x0000346A, 0xFFFFE5EA, 0x00000602 },
+ { 0x0213F0FFEF661984, 0x00004990, 0xFFFFDAFA, 0x00000771, 0x00002A9C, 0xFFFFED37, 0x000004BC, 0x00002A9C, 0xFFFFED37, 0x000004BC },
+ { 0x0213F0FFEF6428A4, 0x00003858, 0xFFFFE568, 0x000005D2, 0x00003030, 0xFFFFE8B0, 0x0000058E, 0x00003030, 0xFFFFE8B0, 0x0000058E },
+ { 0x0213F0FFEF684164, 0x00001EDC, 0xFFFFF6CD, 0x00000322, 0x00001FCA, 0xFFFFF4BD, 0x0000039E, 0x00001FCA, 0xFFFFF4BD, 0x0000039E },
+ { 0x0213F0FFEF662124, 0x00004C88, 0xFFFFDBA3, 0x0000071B, 0x000030C4, 0xFFFFEAFD, 0x000004F7, 0x000030C4, 0xFFFFEAFD, 0x000004F7 },
+ { 0x0213F0FFEF680904, 0x00002B9A, 0xFFFFEE41, 0x0000047D, 0x00002131, 0xFFFFF344, 0x000003E5, 0x00002131, 0xFFFFF344, 0x000003E5 },
+ { 0x0213F0FFEF623984, 0x00003E4B, 0xFFFFE33C, 0x000005FA, 0x00003877, 0xFFFFE437, 0x0000062E, 0x00003877, 0xFFFFE437, 0x0000062E },
+ { 0x0213EA94DE322064, 0x00002376, 0xFFFFF444, 0x0000038A, 0x000017ED, 0xFFFFFA4C, 0x000002C1, 0x000017ED, 0xFFFFFA4C, 0x000002C1 },
+ { 0x0213F0FFEF661084, 0x00004517, 0xFFFFDDF4, 0x000006F2, 0x000030DC, 0xFFFFE8EF, 0x00000571, 0x000030DC, 0xFFFFE8EF, 0x00000571 },
+ { 0x0213F0FFEF681944, 0x0000270C, 0xFFFFF1F3, 0x000003DF, 0x0000207B, 0xFFFFF474, 0x000003AD, 0x0000207B, 0xFFFFF474, 0x000003AD },
+ { 0x0213F0FFEF645144, 0x00004086, 0xFFFFDF39, 0x000006E3, 0x00002A24, 0xFFFFEC2B, 0x000004FF, 0x00002A24, 0xFFFFEC2B, 0x000004FF },
+ { 0x0213F0FFEF5C3124, 0x00003BDE, 0xFFFFE45E, 0x000005EB, 0x00002CD5, 0xFFFFEC45, 0x000004DD, 0x00002CD5, 0xFFFFEC45, 0x000004DD },
+ { 0x0213F0FFEF7230E4, 0x00003803, 0xFFFFE714, 0x00000579, 0x0000288A, 0xFFFFEF21, 0x0000046B, 0x0000288A, 0xFFFFEF21, 0x0000046B },
+ { 0x0213F0FFEF601104, 0x00003F50, 0xFFFFE002, 0x000006CD, 0x00001AD4, 0xFFFFF72E, 0x0000031F, 0x00001AD4, 0xFFFFF72E, 0x0000031F },
+ { 0x0213F0FFEF6820E4, 0x00002968, 0xFFFFF100, 0x00000402, 0x00001FB5, 0xFFFFF57C, 0x0000037F, 0x00001FB5, 0xFFFFF57C, 0x0000037F },
+ { 0x0213F0FFEF662104, 0x00004283, 0xFFFFE2A7, 0x000005F5, 0x00003165, 0xFFFFEB0C, 0x000004EC, 0x00003165, 0xFFFFEB0C, 0x000004EC },
+ { 0x0213F0FFEF6431A4, 0x00004253, 0xFFFFDDA8, 0x00000732, 0x00002E5C, 0xFFFFE90A, 0x00000593, 0x00002E5C, 0xFFFFE90A, 0x00000593 },
+ { 0x0213F0FFEF5C50A4, 0x00003551, 0xFFFFE756, 0x0000058D, 0x000029A7, 0xFFFFED0C, 0x000004DE, 0x000029A7, 0xFFFFED0C, 0x000004DE },
+ { 0x0213F0FFEF6428C4, 0x00003728, 0xFFFFE604, 0x000005C4, 0x00002832, 0xFFFFEE64, 0x00000493, 0x00002832, 0xFFFFEE64, 0x00000493 },
+ { 0x0213F0FFEF623964, 0x00004796, 0xFFFFDCC8, 0x00000715, 0x000032AB, 0xFFFFE848, 0x0000057C, 0x000032AB, 0xFFFFE848, 0x0000057C },
+ { 0x0213F0FFEF6210C4, 0x000049DF, 0xFFFFDB24, 0x0000075F, 0x00003076, 0xFFFFE967, 0x0000055C, 0x00003076, 0xFFFFE967, 0x0000055C },
+ { 0x0213F0FFEF721104, 0x00003F13, 0xFFFFE099, 0x000006A8, 0x00002279, 0xFFFFF226, 0x000003F3, 0x00002279, 0xFFFFF226, 0x000003F3 },
+ { 0x0213F0FFEF6430A4, 0x00003E03, 0xFFFFE19F, 0x00000674, 0x00002D66, 0xFFFFEAA7, 0x00000537, 0x00002D66, 0xFFFFEAA7, 0x00000537 },
+ { 0x0213F0FFEF5C4104, 0x000037DA, 0xFFFFE63F, 0x000005A7, 0x00002543, 0xFFFFF0A0, 0x00000431, 0x00002543, 0xFFFFF0A0, 0x00000431 },
+ { 0x0213F0FFEF624944, 0x00003D82, 0xFFFFE3F5, 0x000005D9, 0x0000332F, 0xFFFFE834, 0x00000577, 0x0000332F, 0xFFFFE834, 0x00000577 },
+ { 0x0213EA94DE1228C4, 0x00002915, 0xFFFFF1E0, 0x000003D4, 0x00002065, 0xFFFFF57B, 0x00000378, 0x00002065, 0xFFFFF57B, 0x00000378 },
+ { 0x0213F0FFEF5E4904, 0x000036FC, 0xFFFFE72D, 0x00000577, 0x00002811, 0xFFFFEF30, 0x00000464, 0x00002811, 0xFFFFEF30, 0x00000464 },
+ { 0x0213F0FFEF623184, 0x00004767, 0xFFFFDD30, 0x000006FD, 0x00003703, 0xFFFFE564, 0x000005F8, 0x00003703, 0xFFFFE564, 0x000005F8 },
+ { 0x0213F0FFEF603184, 0x00003094, 0xFFFFEAA9, 0x000004F5, 0x000022E7, 0xFFFFF200, 0x000003FB, 0x000022E7, 0xFFFFF200, 0x000003FB },
+ { 0x0213F0FFEF641144, 0x00003EF0, 0xFFFFDF83, 0x000006ED, 0x00002A27, 0xFFFFEB7C, 0x00000537, 0x00002A27, 0xFFFFEB7C, 0x00000537 },
+ { 0x0213F0FFEF681124, 0x0000243C, 0xFFFFF358, 0x000003AC, 0x00001DC4, 0xFFFFF5E9, 0x00000372, 0x00001DC4, 0xFFFFF5E9, 0x00000372 },
+ { 0x0213F0FFEF722144, 0x0000284B, 0xFFFFF036, 0x0000040F, 0x00001FCD, 0xFFFFF445, 0x00000395, 0x00001FCD, 0xFFFFF445, 0x00000395 },
+ { 0x0213F0FFEF6840C4, 0x00002611, 0xFFFFF285, 0x000003C7, 0x00001CFE, 0xFFFFF6A0, 0x00000355, 0x00001CFE, 0xFFFFF6A0, 0x00000355 },
+ { 0x0213EA94DE1C39A4, 0x00002292, 0xFFFFF49F, 0x00000393, 0x000017F4, 0xFFFFF9CD, 0x000002F5, 0x000017F4, 0xFFFFF9CD, 0x000002F5 },
+ { 0x0213F0FFEF5E38A4, 0x000037F3, 0xFFFFE68D, 0x00000590, 0x00002443, 0xFFFFF1AD, 0x000003FA, 0x00002443, 0xFFFFF1AD, 0x000003FA },
+ { 0x0213F0FFEF682144, 0x00002C01, 0xFFFFEF3F, 0x00000444, 0x0000210A, 0xFFFFF475, 0x000003A7, 0x0000210A, 0xFFFFF475, 0x000003A7 },
+ { 0x0213EA94DE1210E4, 0x00002C0E, 0xFFFFEF0F, 0x00000446, 0x00001A82, 0xFFFFF8F7, 0x000002DE, 0x00001A82, 0xFFFFF8F7, 0x000002DE },
+ { 0x0213F0FFEF5E20C4, 0x00003FA6, 0xFFFFE20A, 0x0000063F, 0x00002E29, 0xFFFFEB21, 0x00000510, 0x00002E29, 0xFFFFEB21, 0x00000510 },
+ { 0x0213F0FFEF5C2164, 0x00003BCD, 0xFFFFE31B, 0x0000063C, 0x000019AF, 0xFFFFF83D, 0x000002F8, 0x000019AF, 0xFFFFF83D, 0x000002F8 },
+ { 0x0213F0FFEF664164, 0x000044C8, 0xFFFFDF08, 0x000006B0, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00002E2E, 0xFFFFEB62, 0x000004FD },
+ { 0x0213F0FFEF5C1884, 0x00003790, 0xFFFFE571, 0x000005E3, 0x00002042, 0xFFFFF35D, 0x000003CF, 0x00002042, 0xFFFFF35D, 0x000003CF },
+ { 0x0213F0FFEF6050E4, 0x000038AC, 0xFFFFE46C, 0x00000609, 0x0000215E, 0xFFFFF22D, 0x00000403, 0x0000215E, 0xFFFFF22D, 0x00000403 },
+ { 0x0213F0FFEF5E29A4, 0x00003A1E, 0xFFFFE536, 0x000005C9, 0x000024F3, 0xFFFFF11A, 0x0000041B, 0x000024F3, 0xFFFFF11A, 0x0000041B },
+ { 0x0213F0FFEF6650E4, 0x0000431A, 0xFFFFDF1B, 0x000006C5, 0x00002F34, 0xFFFFEA02, 0x00000545, 0x00002F34, 0xFFFFEA02, 0x00000545 },
+ { 0x0213F0FFEF641904, 0x000042DC, 0xFFFFDE28, 0x0000070C, 0x00003B53, 0xFFFFE0EA, 0x000006E2, 0x00003B53, 0xFFFFE0EA, 0x000006E2 },
+ { 0x0213F0FFEF683164, 0x0000264B, 0xFFFFF29A, 0x000003C4, 0x000021D0, 0xFFFFF3CE, 0x000003C4, 0x000021D0, 0xFFFFF3CE, 0x000003C4 },
+ { 0x0213F0FFEF5A4064, 0x00004225, 0xFFFFE0E8, 0x00000665, 0x00002B53, 0xFFFFED89, 0x0000049F, 0x00002B53, 0xFFFFED89, 0x0000049F },
+ { 0x0213EA94DE204924, 0x00001FCC, 0xFFFFF63F, 0x00000358, 0x000019E8, 0xFFFFF882, 0x0000032A, 0x000019E8, 0xFFFFF882, 0x0000032A },
+ { 0x0213F0FFEF6240A4, 0x000045E0, 0xFFFFDDD0, 0x000006ED, 0x00003193, 0xFFFFE8BD, 0x00000572, 0x00003193, 0xFFFFE8BD, 0x00000572 },
+ { 0x0213F0FFEF683924, 0x000024FC, 0xFFFFF366, 0x000003A6, 0x00001FE8, 0xFFFFF509, 0x00000394, 0x00001FE8, 0xFFFFF509, 0x00000394 },
+ { 0x0213F0FFEF5C4884, 0x0000378F, 0xFFFFE54B, 0x000005F1, 0x00001C9B, 0xFFFFF5C7, 0x00000368, 0x00001C9B, 0xFFFFF5C7, 0x00000368 },
+ { 0x0213F0FFEF6418A4, 0x00003CF3, 0xFFFFE15A, 0x00000694, 0x00002CDD, 0xFFFFEA44, 0x00000557, 0x00002CDD, 0xFFFFEA44, 0x00000557 },
+ { 0x0213EA94DE200904, 0x000021EC, 0xFFFFF4F4, 0x0000038F, 0x00001511, 0xFFFFFBF5, 0x0000029E, 0x00001511, 0xFFFFFBF5, 0x0000029E },
+ { 0x0213F0FFEF6010A4, 0x00003C8A, 0xFFFFE1C1, 0x00000685, 0x000019C7, 0xFFFFF7E2, 0x00000301, 0x000019C7, 0xFFFFF7E2, 0x00000301 },
+ { 0x0213F0FFEF5E2064, 0x00003908, 0xFFFFE5C7, 0x000005B3, 0x00002793, 0xFFFFEF46, 0x00000465, 0x00002793, 0xFFFFEF46, 0x00000465 },
+ { 0x0213F0FFEF605104, 0x000040A3, 0xFFFFDE61, 0x00000725, 0x00002077, 0xFFFFF2CE, 0x000003E8, 0x00002077, 0xFFFFF2CE, 0x000003E8 },
+ { 0x0213F0FFEF664144, 0x00003DCA, 0xFFFFE34D, 0x00000608, 0x00002D66, 0xFFFFEBDF, 0x000004E8, 0x00002D66, 0xFFFFEBDF, 0x000004E8 },
+ { 0x0213F0FFEF5E50C4, 0x00003085, 0xFFFFEB70, 0x000004C8, 0x000029B1, 0xFFFFEDD9, 0x000004A5, 0x000029B1, 0xFFFFEDD9, 0x000004A5 },
+ { 0x0213EA94DE083884, 0x00004C73, 0xFFFFD676, 0x0000086C, 0x0000280A, 0xFFFFED89, 0x000004C2, 0x0000280A, 0xFFFFED89, 0x000004C2 },
+ { 0x0213EA94DE242164, 0x00002CE5, 0xFFFFEE8C, 0x00000466, 0x00001755, 0xFFFFFAC2, 0x000002AC, 0x00001755, 0xFFFFFAC2, 0x000002AC },
+ { 0x0213F0FFEF621124, 0x0000489F, 0xFFFFDBF1, 0x0000073E, 0x0000332D, 0xFFFFE786, 0x000005AD, 0x0000332D, 0xFFFFE786, 0x000005AD },
+ { 0x0213F0FFEF602864, 0x00003D09, 0xFFFFE193, 0x00000689, 0x00001E82, 0xFFFFF4C0, 0x00000386, 0x00001E82, 0xFFFFF4C0, 0x00000386 },
+ { 0x0213F0FFEF644104, 0x00003E4C, 0xFFFFE131, 0x00000689, 0x00002F4E, 0xFFFFE925, 0x0000057B, 0x00002F4E, 0xFFFFE925, 0x0000057B },
+ { 0x0213F0FFEF5A4084, 0x00003B31, 0xFFFFE53F, 0x000005B3, 0x0000248A, 0xFFFFF211, 0x000003DF, 0x0000248A, 0xFFFFF211, 0x000003DF },
+ { 0x0213F0FFEF644124, 0x000038DD, 0xFFFFE54A, 0x000005C9, 0x00002B6D, 0xFFFFEBDF, 0x00000502, 0x00002B6D, 0xFFFFEBDF, 0x00000502 },
+ { 0x0213F0FFEF684064, 0x00002698, 0xFFFFF1A8, 0x000003F2, 0x00002163, 0xFFFFF34B, 0x000003E3, 0x00002163, 0xFFFFF34B, 0x000003E3 },
+ { 0x0213EA94DE201064, 0x000023A8, 0xFFFFF4CD, 0x00000386, 0x00001944, 0xFFFFF983, 0x00000300, 0x00001944, 0xFFFFF983, 0x00000300 },
+ { 0x0213F0FFEF6418C4, 0x00003EAF, 0xFFFFE0C3, 0x000006A0, 0x000030AB, 0xFFFFE829, 0x000005A6, 0x000030AB, 0xFFFFE829, 0x000005A6 },
+ { 0x0213F0FFEF684944, 0x00002E89, 0xFFFFECA6, 0x000004B6, 0x00001FA0, 0xFFFFF4A8, 0x000003A3, 0x00001FA0, 0xFFFFF4A8, 0x000003A3 },
+ { 0x0213F0FFEF6828A4, 0x000028A4, 0xFFFFF112, 0x00000402, 0x00001F7C, 0xFFFFF545, 0x0000038A, 0x00001F7C, 0xFFFFF545, 0x0000038A },
+ { 0x0213F0FFEF6650A4, 0x00004135, 0xFFFFDFA2, 0x000006C5, 0x0000324C, 0xFFFFE7AA, 0x000005AF, 0x0000324C, 0xFFFFE7AA, 0x000005AF },
+ { 0x0213EA94DE2038C4, 0x00002012, 0xFFFFF693, 0x00000352, 0x0000171F, 0xFFFFFABB, 0x000002D9, 0x0000171F, 0xFFFFFABB, 0x000002D9 },
+ { 0x0213F0FFEF643084, 0x00003D7C, 0xFFFFE1BC, 0x00000671, 0x00002A45, 0xFFFFEC84, 0x000004EC, 0x00002A45, 0xFFFFEC84, 0x000004EC },
+ { 0x0213F0FFEF723064, 0x00004172, 0xFFFFDF58, 0x000006DA, 0x00002504, 0xFFFFF0A6, 0x00000431, 0x00002504, 0xFFFFF0A6, 0x00000431 },
+ { 0x0213F0FE99281944, 0x000029C7, 0xFFFFF087, 0x00000414, 0x00001DCB, 0xFFFFF675, 0x0000035F, 0x00001DCB, 0xFFFFF675, 0x0000035F },
+ { 0x0213F0FE992A29A4, 0x000027F0, 0xFFFFF05A, 0x00000432, 0x00001707, 0xFFFFFA0E, 0x000002D1, 0x00001707, 0xFFFFFA0E, 0x000002D1 },
+ { 0x0213F0FE99222144, 0x00003279, 0xFFFFE9F7, 0x00000511, 0x00001B5E, 0xFFFFF787, 0x00000317, 0x00001B5E, 0xFFFFF787, 0x00000317 },
+ { 0x0213F0FE99322184, 0x000030A5, 0xFFFFEABC, 0x000004FF, 0x000019D1, 0xFFFFF83C, 0x00000304, 0x000019D1, 0xFFFFF83C, 0x00000304 },
+ { 0x0213F0FE99282844, 0x0000283B, 0xFFFFF122, 0x00000402, 0x000019C2, 0xFFFFF8E9, 0x000002FB, 0x000019C2, 0xFFFFF8E9, 0x000002FB },
+ { 0x0213F0FE992C2084, 0x00003376, 0xFFFFE9E1, 0x00000510, 0x000021A7, 0xFFFFF39F, 0x000003BF, 0x000021A7, 0xFFFFF39F, 0x000003BF },
+ { 0x0213F0FE993218C4, 0x000031D2, 0xFFFFEA9C, 0x000004FC, 0x00001F66, 0xFFFFF4E4, 0x00000390, 0x00001F66, 0xFFFFF4E4, 0x00000390 },
+ { 0x0213F0FE991A3864, 0x00003006, 0xFFFFEB18, 0x000004F2, 0x000019B3, 0xFFFFF84E, 0x00000301, 0x000019B3, 0xFFFFF84E, 0x00000301 },
+ { 0x0213F0FE993039A4, 0x0000364F, 0xFFFFE81F, 0x00000556, 0x00002AC9, 0xFFFFED87, 0x000004BD, 0x00002AC9, 0xFFFFED87, 0x000004BD },
+ { 0x0213F0FE992E3844, 0x00003043, 0xFFFFEBAE, 0x000004CD, 0x00001B0C, 0xFFFFF7ED, 0x0000030C, 0x00001B0C, 0xFFFFF7ED, 0x0000030C },
+ { 0x0213F0FE993048A4, 0x000037CE, 0xFFFFE69E, 0x00000596, 0x0000276B, 0xFFFFEF65, 0x0000046E, 0x0000276B, 0xFFFFEF65, 0x0000046E },
+ { 0x0213F0FE992C3104, 0x00003063, 0xFFFFED5E, 0x0000046F, 0x000024AE, 0xFFFFF2C4, 0x000003D8, 0x000024AE, 0xFFFFF2C4, 0x000003D8 },
+ { 0x0213F0FE992E08A4, 0x00002F5D, 0xFFFFEBDC, 0x000004D3, 0x00001EDB, 0xFFFFF50F, 0x0000038E, 0x00001EDB, 0xFFFFF50F, 0x0000038E },
+ { 0x0213F0FE992E48A4, 0x00003148, 0xFFFFEA9A, 0x000004FB, 0x0000192D, 0xFFFFF8E9, 0x000002DF, 0x0000192D, 0xFFFFF8E9, 0x000002DF },
+ { 0x0213F0FE992C2064, 0x00003682, 0xFFFFE7E4, 0x0000055C, 0x0000250E, 0xFFFFF150, 0x0000041A, 0x0000250E, 0xFFFFF150, 0x0000041A },
+ { 0x0213F0FE992A2084, 0x0000284E, 0xFFFFF15A, 0x000003F8, 0x00001CE2, 0xFFFFF6F9, 0x0000034F, 0x00001CE2, 0xFFFFF6F9, 0x0000034F },
+ { 0x0213F0FE993018A4, 0x00003171, 0xFFFFEAE9, 0x000004ED, 0x00001F40, 0xFFFFF513, 0x00000384, 0x00001F40, 0xFFFFF513, 0x00000384 },
+ { 0x0213F0FE99323044, 0x000031BD, 0xFFFFEA64, 0x0000050A, 0x00001EFD, 0xFFFFF4F7, 0x00000390, 0x00001EFD, 0xFFFFF4F7, 0x00000390 },
+ { 0x0213F0FE992E50E4, 0x00003050, 0xFFFFEB29, 0x000004EA, 0x000019B3, 0xFFFFF878, 0x000002F9, 0x000019B3, 0xFFFFF878, 0x000002F9 },
+ { 0x0213F0FE992C1904, 0x00003400, 0xFFFFE9A0, 0x0000051A, 0x00002460, 0xFFFFF1DA, 0x00000409, 0x00002460, 0xFFFFF1DA, 0x00000409 },
+ { 0x0213F0FE992C4884, 0x000034A1, 0xFFFFE86F, 0x00000558, 0x0000255D, 0xFFFFF09E, 0x00000443, 0x0000255D, 0xFFFFF09E, 0x00000443 },
+ { 0x0213F0FE992E48E4, 0x00003103, 0xFFFFEAD7, 0x000004F0, 0x00001896, 0xFFFFF95A, 0x000002CC, 0x00001896, 0xFFFFF95A, 0x000002CC },
+ { 0x0213F0FE993018E4, 0x00003120, 0xFFFFEB9E, 0x000004CB, 0x000021E8, 0xFFFFF3A2, 0x000003C1, 0x000021E8, 0xFFFFF3A2, 0x000003C1 },
+ { 0x0213F0FE991C50E4, 0x00003558, 0xFFFFE812, 0x00000565, 0x0000256E, 0xFFFFF097, 0x00000447, 0x0000256E, 0xFFFFF097, 0x00000447 },
+ { 0x0213F0FE991A2844, 0x00002DA8, 0xFFFFECA8, 0x000004B7, 0x0000180B, 0xFFFFF96D, 0x000002D8, 0x0000180B, 0xFFFFF96D, 0x000002D8 },
+ { 0x0213F0FE992E3064, 0x00003232, 0xFFFFEA66, 0x000004FF, 0x00001DDE, 0xFFFFF5FE, 0x0000035A, 0x00001DDE, 0xFFFFF5FE, 0x0000035A },
+ { 0x0213F0FE993050E4, 0x000034D2, 0xFFFFE89F, 0x00000548, 0x0000246C, 0xFFFFF17F, 0x00000418, 0x0000246C, 0xFFFFF17F, 0x00000418 },
+ { 0x0213F0FE99304904, 0x000033EC, 0xFFFFE954, 0x0000052A, 0x00002323, 0xFFFFF279, 0x000003EE, 0x00002323, 0xFFFFF279, 0x000003EE },
+ { 0x0213F0FE99303884, 0x000033AA, 0xFFFFE955, 0x0000052D, 0x0000229F, 0xFFFFF2B2, 0x000003E7, 0x0000229F, 0xFFFFF2B2, 0x000003E7 },
+ { 0x0213F0FE99324964, 0x00003258, 0xFFFFE9AA, 0x0000052A, 0x00001D5F, 0xFFFFF5D1, 0x0000036B, 0x00001D5F, 0xFFFFF5D1, 0x0000036B },
+ { 0x0213F0FE993029A4, 0x0000323A, 0xFFFFEA5F, 0x00000504, 0x00002108, 0xFFFFF3D5, 0x000003BA, 0x00002108, 0xFFFFF3D5, 0x000003BA },
+ { 0x0213F0FE992C2184, 0x00003216, 0xFFFFEA6B, 0x000004FF, 0x00001D6E, 0xFFFFF640, 0x00000350, 0x00001D6E, 0xFFFFF640, 0x00000350 },
+ { 0x0213F0FE993210E4, 0x000030C5, 0xFFFFEAC4, 0x000004FC, 0x00001924, 0xFFFFF8C2, 0x000002EE, 0x00001924, 0xFFFFF8C2, 0x000002EE },
+ { 0x0213F0FE99305104, 0x000032BB, 0xFFFFE9F1, 0x00000515, 0x00002211, 0xFFFFF31B, 0x000003D5, 0x00002211, 0xFFFFF31B, 0x000003D5 },
+ { 0x0213F0FE993048C4, 0x0000352C, 0xFFFFE85B, 0x00000553, 0x00002410, 0xFFFFF1B4, 0x0000040F, 0x00002410, 0xFFFFF1B4, 0x0000040F },
+ { 0x0213F0FE992238C4, 0x000036A0, 0xFFFFE7E8, 0x0000055D, 0x00002901, 0xFFFFEEB8, 0x00000489, 0x00002901, 0xFFFFEEB8, 0x00000489 },
+ { 0x0213F0FE992C3044, 0x00003340, 0xFFFFE9D9, 0x00000516, 0x00002332, 0xFFFFF27A, 0x000003F0, 0x00002332, 0xFFFFF27A, 0x000003F0 },
+ { 0x0213F0FE991A38A4, 0x00003564, 0xFFFFE86D, 0x0000054E, 0x00002613, 0xFFFFF07C, 0x00000444, 0x00002613, 0xFFFFF07C, 0x00000444 },
+ { 0x0213F0FE99280904, 0x00002AD1, 0xFFFFEF0B, 0x0000045C, 0x00001DEA, 0xFFFFF5C8, 0x00000381, 0x00001DEA, 0xFFFFF5C8, 0x00000381 },
+ { 0x0213F0FE992220E4, 0x000035B0, 0xFFFFE846, 0x00000555, 0x000027BE, 0xFFFFEF5D, 0x00000474, 0x000027BE, 0xFFFFEF5D, 0x00000474 },
+ { 0x0213F0FE992238A4, 0x000032C4, 0xFFFFEA48, 0x00000502, 0x000022C6, 0xFFFFF2DF, 0x000003DE, 0x000022C6, 0xFFFFF2DF, 0x000003DE },
+ { 0x0213F0FE993008C4, 0x00003036, 0xFFFFEB0D, 0x000004F9, 0x00001FE8, 0xFFFFF41A, 0x000003BC, 0x00001FE8, 0xFFFFF41A, 0x000003BC },
+ { 0x0213F0FE991A0904, 0x000030F8, 0xFFFFEA13, 0x00000524, 0x00001B6A, 0xFFFFF6C9, 0x0000034A, 0x00001B6A, 0xFFFFF6C9, 0x0000034A },
+ { 0x0213F0FE993010A4, 0x00002EE2, 0xFFFFEC0C, 0x000004CB, 0x00001A39, 0xFFFFF814, 0x0000030F, 0x00001A39, 0xFFFFF814, 0x0000030F },
+ { 0x0213F0FE991C3184, 0x00003457, 0xFFFFE924, 0x0000052A, 0x00001E9D, 0xFFFFF59C, 0x00000363, 0x00001E9D, 0xFFFFF59C, 0x00000363 },
+ { 0x0213F0FE99322844, 0x000030BF, 0xFFFFEB18, 0x000004ED, 0x00001D37, 0xFFFFF636, 0x0000035C, 0x00001D37, 0xFFFFF636, 0x0000035C },
+ { 0x0213F0FE992E4084, 0x000031AF, 0xFFFFEA75, 0x000004FE, 0x000019F2, 0xFFFFF87A, 0x000002F0, 0x000019F2, 0xFFFFF87A, 0x000002F0 },
+ { 0x0213F0FE99302884, 0x00003642, 0xFFFFE85B, 0x00000547, 0x00002975, 0xFFFFEE98, 0x0000048B, 0x00002975, 0xFFFFEE98, 0x0000048B },
+ { 0x0213F0FE992E2884, 0x00002E8B, 0xFFFFED1E, 0x0000048E, 0x000019C1, 0xFFFFF917, 0x000002D6, 0x000019C1, 0xFFFFF917, 0x000002D6 },
+ { 0x0213F0FE993241A4, 0x000033D9, 0xFFFFE8E1, 0x00000548, 0x0000224B, 0xFFFFF298, 0x000003F4, 0x0000224B, 0xFFFFF298, 0x000003F4 },
+ { 0x0213F0FE992E28C4, 0x000032BC, 0xFFFFEB0F, 0x000004D6, 0x00002488, 0xFFFFF240, 0x000003F2, 0x00002488, 0xFFFFF240, 0x000003F2 },
+ { 0x0213F0FE99304944, 0x000035FD, 0xFFFFE838, 0x00000553, 0x00002762, 0xFFFFEFBC, 0x00000460, 0x00002762, 0xFFFFEFBC, 0x00000460 },
+ { 0x0213F0FE992818A4, 0x0000268B, 0xFFFFF263, 0x000003D1, 0x00001914, 0xFFFFF977, 0x000002E8, 0x00001914, 0xFFFFF977, 0x000002E8 },
+ { 0x0213F0FE992C3184, 0x0000330B, 0xFFFFEA1E, 0x00000505, 0x000020B1, 0xFFFFF44D, 0x0000039E, 0x000020B1, 0xFFFFF44D, 0x0000039E },
+ { 0x0213F0FE99222084, 0x0000326E, 0xFFFFEA26, 0x00000508, 0x00001C17, 0xFFFFF722, 0x00000328, 0x00001C17, 0xFFFFF722, 0x00000328 },
+ { 0x0213F0FE992A31A4, 0x00002A3F, 0xFFFFEEE8, 0x0000046D, 0x00001B2B, 0xFFFFF737, 0x0000034D, 0x00001B2B, 0xFFFFF737, 0x0000034D },
+ { 0x0213F0FE992C4064, 0x00003732, 0xFFFFE765, 0x00000574, 0x00002A6D, 0xFFFFEDA8, 0x000004B7, 0x00002A6D, 0xFFFFEDA8, 0x000004B7 },
+ { 0x0213F0FE99300924, 0x000034D3, 0xFFFFE827, 0x00000569, 0x000027AA, 0xFFFFEEE7, 0x00000492, 0x000027AA, 0xFFFFEEE7, 0x00000492 },
+ { 0x0213F0FE992E40C4, 0x00003306, 0xFFFFEA39, 0x000004FC, 0x00001DCC, 0xFFFFF655, 0x00000344, 0x00001DCC, 0xFFFFF655, 0x00000344 },
+ { 0x0213F0FE99282044, 0x00002A48, 0xFFFFEFCA, 0x00000439, 0x00001DED, 0xFFFFF60D, 0x00000375, 0x00001DED, 0xFFFFF60D, 0x00000375 },
+ { 0x0213F0FE993038C4, 0x000033A3, 0xFFFFEA36, 0x000004F9, 0x0000247C, 0xFFFFF21F, 0x000003F4, 0x0000247C, 0xFFFFF21F, 0x000003F4 },
+ { 0x0213F0FE992C3164, 0x0000311B, 0xFFFFEB76, 0x000004D1, 0x00001EB1, 0xFFFFF5B6, 0x00000366, 0x00001EB1, 0xFFFFF5B6, 0x00000366 },
+ { 0x0213F0FE99324164, 0x00003307, 0xFFFFE97F, 0x0000052A, 0x00001E76, 0xFFFFF54D, 0x0000037C, 0x00001E76, 0xFFFFF54D, 0x0000037C },
+ { 0x0213F0FE991C2144, 0x0000344B, 0xFFFFE9C5, 0x00000509, 0x000020D6, 0xFFFFF486, 0x0000038F, 0x000020D6, 0xFFFFF486, 0x0000038F },
+ { 0x0213F0FE992C3144, 0x000034B9, 0xFFFFEA0B, 0x000004F7, 0x000027B3, 0xFFFFF057, 0x0000043A, 0x000027B3, 0xFFFFF057, 0x0000043A },
+ { 0x0213F0FE99301964, 0x00003360, 0xFFFFE984, 0x00000527, 0x00002238, 0xFFFFF2EE, 0x000003E0, 0x00002238, 0xFFFFF2EE, 0x000003E0 },
+ { 0x0213F0FE99302124, 0x0000315C, 0xFFFFEC05, 0x000004B1, 0x000023C8, 0xFFFFF2CC, 0x000003DE, 0x000023C8, 0xFFFFF2CC, 0x000003DE },
+ { 0x0213F0FE992C2864, 0x0000389B, 0xFFFFE6D5, 0x00000582, 0x00002C6C, 0xFFFFEC92, 0x000004DE, 0x00002C6C, 0xFFFFEC92, 0x000004DE },
+ { 0x0213F0FE992E1124, 0x00003058, 0xFFFFEB30, 0x000004E6, 0x000019B5, 0xFFFFF88B, 0x000002F1, 0x000019B5, 0xFFFFF88B, 0x000002F1 },
+ { 0x0213F0FE992E0904, 0x00002F69, 0xFFFFEB4A, 0x000004F1, 0x00001B82, 0xFFFFF6EC, 0x00000341, 0x00001B82, 0xFFFFF6EC, 0x00000341 },
+ { 0x0213F0FE991A18E4, 0x000031EB, 0xFFFFEA64, 0x00000508, 0x00002059, 0xFFFFF427, 0x000003B0, 0x00002059, 0xFFFFF427, 0x000003B0 },
+ { 0x0213F0FE99224124, 0x000033E2, 0xFFFFE94D, 0x0000052A, 0x000020BF, 0xFFFFF40B, 0x000003AB, 0x000020BF, 0xFFFFF40B, 0x000003AB },
+ { 0x0213F0FE99283184, 0x00002AF9, 0xFFFFEFE9, 0x00000427, 0x00001F72, 0xFFFFF57A, 0x00000383, 0x00001F72, 0xFFFFF57A, 0x00000383 },
+ { 0x0213F0FE992C2824, 0x00003282, 0xFFFFEA88, 0x000004FA, 0x00002561, 0xFFFFF126, 0x0000042B, 0x00002561, 0xFFFFF126, 0x0000042B },
+ { 0x0213F0FE993010E4, 0x0000308A, 0xFFFFEB5D, 0x000004E0, 0x00001E83, 0xFFFFF577, 0x00000378, 0x00001E83, 0xFFFFF577, 0x00000378 },
+ { 0x0213F0FE99324884, 0x0000336E, 0xFFFFE8C8, 0x00000553, 0x0000217C, 0xFFFFF2E1, 0x000003EB, 0x0000217C, 0xFFFFF2E1, 0x000003EB },
+ { 0x0213F0FE991A2164, 0x000034A9, 0xFFFFE838, 0x00000561, 0x000020CE, 0xFFFFF38A, 0x000003C7, 0x000020CE, 0xFFFFF38A, 0x000003C7 },
+ { 0x0213F0FE99222184, 0x00003152, 0xFFFFE9EB, 0x00000522, 0x00001755, 0xFFFFF9A9, 0x000002C6, 0x00001755, 0xFFFFF9A9, 0x000002C6 },
+ { 0x0213F0FE99281884, 0x0000286E, 0xFFFFF136, 0x000003FD, 0x00001BAB, 0xFFFFF7C3, 0x0000032C, 0x00001BAB, 0xFFFFF7C3, 0x0000032C },
+ { 0x0213F0FE99300944, 0x0000316B, 0xFFFFEA02, 0x00000528, 0x00002247, 0xFFFFF24E, 0x00000408, 0x00002247, 0xFFFFF24E, 0x00000408 },
+ { 0x0213F0FE992C08E4, 0x000034CF, 0xFFFFE83D, 0x00000562, 0x00002458, 0xFFFFF130, 0x00000430, 0x00002458, 0xFFFFF130, 0x00000430 },
+ { 0x0213F0FE992C2984, 0x00003352, 0xFFFFE9D1, 0x00000515, 0x0000212A, 0xFFFFF3DC, 0x000003B4, 0x0000212A, 0xFFFFF3DC, 0x000003B4 },
+ { 0x0213F0FE992840A4, 0x00002946, 0xFFFFF09B, 0x00000415, 0x00001DC9, 0xFFFFF650, 0x00000366, 0x00001DC9, 0xFFFFF650, 0x00000366 },
+ { 0x0213F0FE99301124, 0x00003080, 0xFFFFEB47, 0x000004E1, 0x00001BD5, 0xFFFFF73B, 0x00000329, 0x00001BD5, 0xFFFFF73B, 0x00000329 },
+ { 0x0213F0FE991A1884, 0x00002FBD, 0xFFFFEB7B, 0x000004DD, 0x000017FC, 0xFFFFF99E, 0x000002C7, 0x000017FC, 0xFFFFF99E, 0x000002C7 },
+ { 0x0213F0FE99281124, 0x00002A28, 0xFFFFF032, 0x0000041F, 0x00001B19, 0xFFFFF83A, 0x00000312, 0x00001B19, 0xFFFFF83A, 0x00000312 },
+ { 0x0213F0FE992240C4, 0x00003420, 0xFFFFE936, 0x00000530, 0x000023C2, 0xFFFFF203, 0x00000406, 0x000023C2, 0xFFFFF203, 0x00000406 },
+ { 0x0213F0FE99301144, 0x00002F7C, 0xFFFFEBBA, 0x000004D1, 0x0000185D, 0xFFFFF975, 0x000002CA, 0x0000185D, 0xFFFFF975, 0x000002CA },
+ { 0x0213F0FE992E2044, 0x00002C51, 0xFFFFEE3B, 0x0000046F, 0x000019AA, 0xFFFFF8DD, 0x000002ED, 0x000019AA, 0xFFFFF8DD, 0x000002ED },
+ { 0x0213F0FE991A4144, 0x000033D6, 0xFFFFE8F2, 0x0000053D, 0x00001D73, 0xFFFFF5FB, 0x0000035B, 0x00001D73, 0xFFFFF5FB, 0x0000035B },
+ { 0x0213F0FE99323084, 0x000031D9, 0xFFFFEAF7, 0x000004E4, 0x00001EBD, 0xFFFFF5A6, 0x00000368, 0x00001EBD, 0xFFFFF5A6, 0x00000368 },
+ { 0x0213F0FE991A20A4, 0x00003386, 0xFFFFE9CE, 0x00000515, 0x00002422, 0xFFFFF1F3, 0x00000405, 0x00002422, 0xFFFFF1F3, 0x00000405 },
+ { 0x0213F0FE992C50E4, 0x000032FB, 0xFFFFE9BC, 0x00000520, 0x00002301, 0xFFFFF267, 0x000003F7, 0x00002301, 0xFFFFF267, 0x000003F7 },
+ { 0x0213F0FE99322924, 0x000032C2, 0xFFFFEAC0, 0x000004EA, 0x0000250F, 0xFFFFF1A2, 0x00000413, 0x0000250F, 0xFFFFF1A2, 0x00000413 },
+ { 0x0213F0FE991C2944, 0x00003722, 0xFFFFE8A6, 0x00000527, 0x000026E4, 0xFFFFF0F5, 0x0000041C, 0x000026E4, 0xFFFFF0F5, 0x0000041C },
+ { 0x0213F0FE992C48C4, 0x000035A4, 0xFFFFE822, 0x00000558, 0x000022F2, 0xFFFFF288, 0x000003E8, 0x000022F2, 0xFFFFF288, 0x000003E8 },
+ { 0x0213F0FE99280924, 0x00002CD1, 0xFFFFEDC6, 0x0000048C, 0x00001EAF, 0xFFFFF53D, 0x00000396, 0x00001EAF, 0xFFFFF53D, 0x00000396 },
+ { 0x0213F0FE99301164, 0x00003156, 0xFFFFEA60, 0x0000050B, 0x00001BBC, 0xFFFFF704, 0x00000335, 0x00001BBC, 0xFFFFF704, 0x00000335 },
+ { 0x0213F0FE992C5104, 0x000034A1, 0xFFFFE8C0, 0x00000544, 0x00002528, 0xFFFFF105, 0x0000042C, 0x00002528, 0xFFFFF105, 0x0000042C },
+ { 0x0213F0FE99323064, 0x000032CE, 0xFFFFE9D3, 0x00000520, 0x000021FF, 0xFFFFF2FD, 0x000003E4, 0x000021FF, 0xFFFFF2FD, 0x000003E4 },
+ { 0x0213F0FE991A50A4, 0x000034A0, 0xFFFFE823, 0x0000056D, 0x0000256F, 0xFFFFF047, 0x0000045A, 0x0000256F, 0xFFFFF047, 0x0000045A },
+ { 0x0213F0FE99303944, 0x00003109, 0xFFFFEBD6, 0x000004BF, 0x000022D4, 0xFFFFF32D, 0x000003D0, 0x000022D4, 0xFFFFF32D, 0x000003D0 },
+ { 0x0213F0FE992C1164, 0x000030B7, 0xFFFFEAF0, 0x000004F3, 0x00001AEC, 0xFFFFF7A9, 0x0000031B, 0x00001AEC, 0xFFFFF7A9, 0x0000031B },
+ { 0x0213F0FE992C39A4, 0x00003078, 0xFFFFEBA4, 0x000004CF, 0x00001E7A, 0xFFFFF5AF, 0x0000036B, 0x00001E7A, 0xFFFFF5AF, 0x0000036B },
+ { 0x0213F0FE99304124, 0x00003442, 0xFFFFE998, 0x00000518, 0x000025EA, 0xFFFFF0F3, 0x0000042B, 0x000025EA, 0xFFFFF0F3, 0x0000042B },
+ { 0x0213F0FE993021A4, 0x000031CB, 0xFFFFEA80, 0x00000501, 0x000020A3, 0xFFFFF403, 0x000003B2, 0x000020A3, 0xFFFFF403, 0x000003B2 },
+ { 0x0213F0FE992A2984, 0x00002947, 0xFFFFF018, 0x00000433, 0x00001BA5, 0xFFFFF75C, 0x00000340, 0x00001BA5, 0xFFFFF75C, 0x00000340 },
+ { 0x0213F0FE992C3984, 0x000033F9, 0xFFFFE99D, 0x00000518, 0x00002231, 0xFFFFF358, 0x000003C5, 0x00002231, 0xFFFFF358, 0x000003C5 },
+ { 0x0213F0FE99321124, 0x00003131, 0xFFFFEA45, 0x00000513, 0x00001973, 0xFFFFF85E, 0x00000301, 0x00001973, 0xFFFFF85E, 0x00000301 },
+ { 0x0213F0FE991C29A4, 0x00003571, 0xFFFFE8AC, 0x00000539, 0x00002049, 0xFFFFF49C, 0x0000038D, 0x00002049, 0xFFFFF49C, 0x0000038D },
+ { 0x0213F0FE992E3864, 0x0000309E, 0xFFFFEB1D, 0x000004E8, 0x000019ED, 0xFFFFF86E, 0x000002F8, 0x000019ED, 0xFFFFF86E, 0x000002F8 },
+ { 0x0213F0FE99302984, 0x00003091, 0xFFFFEB9B, 0x000004CC, 0x00001D2C, 0xFFFFF6A2, 0x0000033D, 0x00001D2C, 0xFFFFF6A2, 0x0000033D },
+ { 0x0213F0FE993008E4, 0x00003069, 0xFFFFEAFD, 0x000004F8, 0x00001E82, 0xFFFFF51C, 0x0000038D, 0x00001E82, 0xFFFFF51C, 0x0000038D },
+ { 0x0213F0FE992210A4, 0x00003459, 0xFFFFE7F2, 0x00000572, 0x00001DA7, 0xFFFFF552, 0x0000037F, 0x00001DA7, 0xFFFFF552, 0x0000037F },
+ { 0x0213F0FE99321104, 0x0000304B, 0xFFFFEAFB, 0x000004F4, 0x0000191E, 0xFFFFF8BD, 0x000002EE, 0x0000191E, 0xFFFFF8BD, 0x000002EE },
+ { 0x0213F0FE993020C4, 0x0000346E, 0xFFFFEA07, 0x000004FD, 0x00002767, 0xFFFFF058, 0x00000440, 0x00002767, 0xFFFFF058, 0x00000440 },
+ { 0x0213F0FE992E3084, 0x000030B5, 0xFFFFEBC1, 0x000004C1, 0x00001B3C, 0xFFFFF818, 0x000002FD, 0x00001B3C, 0xFFFFF818, 0x000002FD },
+ { 0x0213F0FE99300904, 0x0000321F, 0xFFFFE9EA, 0x00000524, 0x00002380, 0xFFFFF1C2, 0x0000041A, 0x00002380, 0xFFFFF1C2, 0x0000041A },
+ { 0x0213F0FE992E3044, 0x000030DF, 0xFFFFEB37, 0x000004E2, 0x00001E3C, 0xFFFFF5BB, 0x00000369, 0x00001E3C, 0xFFFFF5BB, 0x00000369 },
+ { 0x0213F0FE992848A4, 0x000027E0, 0xFFFFF0E2, 0x00000416, 0x00001A6A, 0xFFFFF820, 0x00000321, 0x00001A6A, 0xFFFFF820, 0x00000321 },
+ { 0x0213F0FE991A1084, 0x00002FA1, 0xFFFFEB63, 0x000004E7, 0x0000196B, 0xFFFFF880, 0x000002FB, 0x0000196B, 0xFFFFF880, 0x000002FB },
+ { 0x0213F0FE991C1084, 0x0000310C, 0xFFFFEAAF, 0x000004FC, 0x000019EF, 0xFFFFF850, 0x000002FD, 0x000019EF, 0xFFFFF850, 0x000002FD },
+ { 0x0213F0FE99323904, 0x0000334A, 0xFFFFEA07, 0x0000050B, 0x00002380, 0xFFFFF26F, 0x000003F0, 0x00002380, 0xFFFFF26F, 0x000003F0 },
+ { 0x0213F0FE99302944, 0x00002FF9, 0xFFFFECDC, 0x00000492, 0x00002297, 0xFFFFF394, 0x000003BF, 0x00002297, 0xFFFFF394, 0x000003BF },
+ { 0x0213F0FE992C2164, 0x0000354B, 0xFFFFE894, 0x00000546, 0x000024C4, 0xFFFFF16C, 0x0000041B, 0x000024C4, 0xFFFFF16C, 0x0000041B },
+ { 0x0213F0FE99220924, 0x00003245, 0xFFFFE92F, 0x00000544, 0x00001829, 0xFFFFF8F1, 0x000002EA, 0x00001829, 0xFFFFF8F1, 0x000002EA },
+ { 0x0213F0FE992E4884, 0x0000302F, 0xFFFFEB51, 0x000004E3, 0x0000199F, 0xFFFFF894, 0x000002F4, 0x0000199F, 0xFFFFF894, 0x000002F4 },
+ { 0x0213F0FE992E18C4, 0x00002F54, 0xFFFFEC86, 0x000004A6, 0x00001A6F, 0xFFFFF891, 0x000002EC, 0x00001A6F, 0xFFFFF891, 0x000002EC },
+ { 0x0213F0FE99284164, 0x00002908, 0xFFFFF0D8, 0x0000040A, 0x00001C9B, 0xFFFFF729, 0x00000342, 0x00001C9B, 0xFFFFF729, 0x00000342 },
+ { 0x0213F0FE99302964, 0x000031D9, 0xFFFFEB40, 0x000004D7, 0x000023F5, 0xFFFFF259, 0x000003F4, 0x000023F5, 0xFFFFF259, 0x000003F4 },
+ { 0x0213F0FE993048E4, 0x000034C8, 0xFFFFE8C6, 0x0000053F, 0x00002313, 0xFFFFF280, 0x000003EC, 0x00002313, 0xFFFFF280, 0x000003EC },
+ { 0x0213F0FE993050C4, 0x000037D1, 0xFFFFE6A1, 0x0000059C, 0x00002C6A, 0xFFFFEBFF, 0x00000504, 0x00002C6A, 0xFFFFEBFF, 0x00000504 },
+ { 0x0213F0FE99321964, 0x000030E9, 0xFFFFEA6B, 0x0000050F, 0x00001A2D, 0xFFFFF7DF, 0x00000316, 0x00001A2D, 0xFFFFF7DF, 0x00000316 },
+ { 0x0213F0FE99302084, 0x0000323D, 0xFFFFEA95, 0x000004F4, 0x00001ED2, 0xFFFFF584, 0x0000036C, 0x00001ED2, 0xFFFFF584, 0x0000036C },
+ { 0x0213F0FE992C3024, 0x000033D6, 0xFFFFE9DB, 0x00000510, 0x000027A7, 0xFFFFEFC7, 0x0000045E, 0x000027A7, 0xFFFFEFC7, 0x0000045E },
+ { 0x0213F0FE991C3164, 0x00003444, 0xFFFFE98A, 0x00000517, 0x000020FD, 0xFFFFF43F, 0x0000039D, 0x000020FD, 0xFFFFF43F, 0x0000039D },
+ { 0x0213F0FE992808E4, 0x00002987, 0xFFFFEFA1, 0x0000044B, 0x00001B06, 0xFFFFF788, 0x0000033C, 0x00001B06, 0xFFFFF788, 0x0000033C },
+ { 0x0213F0FE992C28E4, 0x0000311D, 0xFFFFED20, 0x00000474, 0x000025DA, 0xFFFFF223, 0x000003F0, 0x000025DA, 0xFFFFF223, 0x000003F0 },
+ { 0x0213F0FE992C1124, 0x000032A2, 0xFFFFEA0A, 0x0000050D, 0x00001D48, 0xFFFFF659, 0x0000034A, 0x00001D48, 0xFFFFF659, 0x0000034A },
+ { 0x0213F0FE992208E4, 0x00003110, 0xFFFFE9EA, 0x00000529, 0x00001786, 0xFFFFF958, 0x000002DB, 0x00001786, 0xFFFFF958, 0x000002DB },
+ { 0x0213F0FE992821A4, 0x000027F2, 0xFFFFF174, 0x000003F7, 0x00001C7A, 0xFFFFF72A, 0x00000348, 0x00001C7A, 0xFFFFF72A, 0x00000348 },
+ { 0x0213F0FE991C10E4, 0x000031DB, 0xFFFFEA7D, 0x000004FB, 0x000019C4, 0xFFFFF8B1, 0x000002E6, 0x000019C4, 0xFFFFF8B1, 0x000002E6 },
+ { 0x0213F0FE992C1104, 0x00003158, 0xFFFFEAAC, 0x000004FA, 0x00001BC1, 0xFFFFF737, 0x0000032B, 0x00001BC1, 0xFFFFF737, 0x0000032B },
+ { 0x0213F0FE993010C4, 0x00002F36, 0xFFFFEBF9, 0x000004CA, 0x00001A2A, 0xFFFFF83F, 0x00000303, 0x00001A2A, 0xFFFFF83F, 0x00000303 },
+ { 0x0213F0FE993238A4, 0x000032B4, 0xFFFFEA72, 0x000004FA, 0x000021FF, 0xFFFFF378, 0x000003C5, 0x000021FF, 0xFFFFF378, 0x000003C5 },
+ { 0x0213F0FE99303164, 0x00003262, 0xFFFFEAFA, 0x000004DF, 0x00002441, 0xFFFFF237, 0x000003F6, 0x00002441, 0xFFFFF237, 0x000003F6 },
+ { 0x0213F0FE99303924, 0x0000336A, 0xFFFFEAFB, 0x000004D1, 0x00002746, 0xFFFFF0B8, 0x0000042B, 0x00002746, 0xFFFFF0B8, 0x0000042B },
+ { 0x0213F0FE991A4084, 0x000032E5, 0xFFFFE923, 0x00000541, 0x00001DF0, 0xFFFFF552, 0x00000380, 0x00001DF0, 0xFFFFF552, 0x00000380 },
+ { 0x0213F0FE99304064, 0x000035D1, 0xFFFFE80B, 0x0000055F, 0x00002780, 0xFFFFEF74, 0x0000046F, 0x00002780, 0xFFFFEF74, 0x0000046F },
+ { 0x0213F0FE993028A4, 0x000033EC, 0xFFFFEA48, 0x000004F4, 0x0000269F, 0xFFFFF0D8, 0x0000042A, 0x0000269F, 0xFFFFF0D8, 0x0000042A },
+ { 0x0213F0FE99323884, 0x000030C4, 0xFFFFEB39, 0x000004E2, 0x00001B44, 0xFFFFF7AA, 0x00000318, 0x00001B44, 0xFFFFF7AA, 0x00000318 },
+ { 0x0213F0FE99281144, 0x00002926, 0xFFFFF0AF, 0x0000040E, 0x0000194E, 0xFFFFF959, 0x000002E2, 0x0000194E, 0xFFFFF959, 0x000002E2 },
+ { 0x0213F0FE992C10C4, 0x00003141, 0xFFFFEAAF, 0x000004F6, 0x00001864, 0xFFFFF97C, 0x000002C6, 0x00001864, 0xFFFFF97C, 0x000002C6 },
+ { 0x0213F0FE99301064, 0x000030B2, 0xFFFFEB7C, 0x000004DB, 0x000022CE, 0xFFFFF2B5, 0x000003F0, 0x000022CE, 0xFFFFF2B5, 0x000003F0 },
+ { 0x0213F0FE99301944, 0x0000318C, 0xFFFFEAC7, 0x000004F6, 0x00002113, 0xFFFFF3CA, 0x000003BD, 0x00002113, 0xFFFFF3CA, 0x000003BD },
+ { 0x0213F0FE992E1104, 0x00002FD2, 0xFFFFEB8F, 0x000004D9, 0x00001996, 0xFFFFF89F, 0x000002F1, 0x00001996, 0xFFFFF89F, 0x000002F1 },
+ { 0x0213F0FE991A28A4, 0x0000310D, 0xFFFFEB25, 0x000004E7, 0x00001F67, 0xFFFFF4EF, 0x0000038E, 0x00001F67, 0xFFFFF4EF, 0x0000038E },
+ { 0x0213F0FE992A4964, 0x00002BBC, 0xFFFFEE68, 0x00000477, 0x00002050, 0xFFFFF41D, 0x000003C8, 0x00002050, 0xFFFFF41D, 0x000003C8 },
+ { 0x0213F0FE99302104, 0x00003096, 0xFFFFECED, 0x00000486, 0x000024C9, 0xFFFFF278, 0x000003E7, 0x000024C9, 0xFFFFF278, 0x000003E7 },
+ { 0x0213F0FE992C10A4, 0x00003401, 0xFFFFE8F1, 0x0000053C, 0x00001E75, 0xFFFFF55C, 0x00000376, 0x00001E75, 0xFFFFF55C, 0x00000376 },
+ { 0x0213F0FE99302844, 0x0000319E, 0xFFFFEAB1, 0x000004F8, 0x00001EA3, 0xFFFFF567, 0x00000378, 0x00001EA3, 0xFFFFF567, 0x00000378 },
+ { 0x0213F0FE99322964, 0x000030FD, 0xFFFFEB4C, 0x000004DB, 0x00001CA6, 0xFFFFF6E8, 0x00000335, 0x00001CA6, 0xFFFFF6E8, 0x00000335 },
+ { 0x0213F0FE992E40A4, 0x000030D6, 0xFFFFEB1A, 0x000004E4, 0x00001A0D, 0xFFFFF87D, 0x000002EF, 0x00001A0D, 0xFFFFF87D, 0x000002EF },
+ { 0x0213F0FE992C2124, 0x0000324B, 0xFFFFEB17, 0x000004D9, 0x00002225, 0xFFFFF3A8, 0x000003BA, 0x00002225, 0xFFFFF3A8, 0x000003BA },
+ { 0x0213F0FE99284084, 0x00002A00, 0xFFFFF02E, 0x00000424, 0x00001E21, 0xFFFFF61D, 0x0000036C, 0x00001E21, 0xFFFFF61D, 0x0000036C },
+ { 0x0213F0FE992A48A4, 0x000029CF, 0xFFFFEF53, 0x00000457, 0x00001B11, 0xFFFFF772, 0x0000033D, 0x00001B11, 0xFFFFF772, 0x0000033D },
+ { 0x0213F0FE991A30A4, 0x000032A1, 0xFFFFEA63, 0x000004FB, 0x00001F83, 0xFFFFF516, 0x0000037E, 0x00001F83, 0xFFFFF516, 0x0000037E },
+ { 0x0213F0FE992E20C4, 0x0000305C, 0xFFFFEC14, 0x000004B5, 0x00001D0B, 0xFFFFF6ED, 0x00000332, 0x00001D0B, 0xFFFFF6ED, 0x00000332 },
+ { 0x0213F0FE992C1064, 0x00003467, 0xFFFFE8D5, 0x00000543, 0x0000243F, 0xFFFFF190, 0x00000418, 0x0000243F, 0xFFFFF190, 0x00000418 },
+ { 0x0213F0FE992A2064, 0x00002796, 0xFFFFF133, 0x00000409, 0x00001903, 0xFFFFF91C, 0x000002FC, 0x00001903, 0xFFFFF91C, 0x000002FC },
+ { 0x0213F0FE99302164, 0x000031F6, 0xFFFFEAB7, 0x000004F5, 0x000022B9, 0xFFFFF2D0, 0x000003E6, 0x000022B9, 0xFFFFF2D0, 0x000003E6 },
+ { 0x0213F0FE992E5104, 0x00003196, 0xFFFFEA76, 0x00000503, 0x00001CC5, 0xFFFFF67D, 0x0000034A, 0x00001CC5, 0xFFFFF67D, 0x0000034A },
+ { 0x0213F0FE99321144, 0x00002F9E, 0xFFFFEAD9, 0x00000505, 0x000017C1, 0xFFFFF93D, 0x000002DF, 0x000017C1, 0xFFFFF93D, 0x000002DF },
+ { 0x0213F0FE992E2124, 0x00002FBC, 0xFFFFEC75, 0x000004A8, 0x00001D6D, 0xFFFFF6AC, 0x0000033D, 0x00001D6D, 0xFFFFF6AC, 0x0000033D },
+ { 0x0213F0FE992C38A4, 0x00003541, 0xFFFFE921, 0x00000524, 0x00002662, 0xFFFFF0CB, 0x0000042B, 0x00002662, 0xFFFFF0CB, 0x0000042B },
+ { 0x0213F0FE992A21A4, 0x00002953, 0xFFFFEF76, 0x00000459, 0x00001C05, 0xFFFFF6A0, 0x00000368, 0x00001C05, 0xFFFFF6A0, 0x00000368 },
+ { 0x0213F0FE992C4924, 0x000034BC, 0xFFFFE8DD, 0x00000536, 0x0000210E, 0xFFFFF3F4, 0x000003A8, 0x0000210E, 0xFFFFF3F4, 0x000003A8 },
+ { 0x0213F0FE992C29A4, 0x000034BE, 0xFFFFE916, 0x0000052F, 0x000024A1, 0xFFFFF1A6, 0x00000410, 0x000024A1, 0xFFFFF1A6, 0x00000410 },
+ { 0x0213F0FE99304964, 0x000037B5, 0xFFFFE7A9, 0x0000055B, 0x000028A1, 0xFFFFEF51, 0x00000467, 0x000028A1, 0xFFFFEF51, 0x00000467 },
+ { 0x0213F0FE99301104, 0x00002FC5, 0xFFFFEBBE, 0x000004D1, 0x00001BA5, 0xFFFFF757, 0x00000328, 0x00001BA5, 0xFFFFF757, 0x00000328 },
+ { 0x0213F0FE993040A4, 0x000033CB, 0xFFFFE944, 0x0000052B, 0x00001FBE, 0xFFFFF4B1, 0x0000038C, 0x00001FBE, 0xFFFFF4B1, 0x0000038C },
+ { 0x0213F0FE99301844, 0x000030AE, 0xFFFFEBA0, 0x000004D3, 0x00002268, 0xFFFFF316, 0x000003DD, 0x00002268, 0xFFFFF316, 0x000003DD },
+ { 0x0213F0FE992C20A4, 0x00002F90, 0xFFFFEC5A, 0x000004B0, 0x00001C3A, 0xFFFFF752, 0x00000323, 0x00001C3A, 0xFFFFF752, 0x00000323 },
+ { 0x0213F0FE992E38E4, 0x00003113, 0xFFFFEB91, 0x000004C8, 0x00001E3C, 0xFFFFF623, 0x0000034E, 0x00001E3C, 0xFFFFF623, 0x0000034E },
+ { 0x0213F0FE99323984, 0x0000330B, 0xFFFFE94B, 0x00000539, 0x000020E7, 0xFFFFF37E, 0x000003CD, 0x000020E7, 0xFFFFF37E, 0x000003CD },
+ { 0x0213F0FE992E2864, 0x000031D1, 0xFFFFEACB, 0x000004ED, 0x00001E82, 0xFFFFF5B2, 0x00000365, 0x00001E82, 0xFFFFF5B2, 0x00000365 },
+ { 0x0213F0FE992A3984, 0x00002CD5, 0xFFFFEDC1, 0x0000048D, 0x000020F8, 0xFFFFF3C1, 0x000003D1, 0x000020F8, 0xFFFFF3C1, 0x000003D1 },
+ { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
};
int pp_override_get_default_fuse_value(uint64_t key,
- struct phm_fuses_default list[],
struct phm_fuses_default *result)
{
+ const struct phm_fuses_default *list = vega10_fuses_default;
uint32_t i;
- uint64_t temp_serial_numer;
- uint32_t bit;
- const char *temp;
- for (i = 0; list[i].key != NULL; i++) {
- temp = list[i].key;
- temp_serial_numer = 0;
- do {
- bit = *temp=='1'? 1 : 0;
- temp_serial_numer = (temp_serial_numer <<1 ) | bit;
- temp++;
- } while (*temp);
-
- if (key == temp_serial_numer) {
+ for (i = 0; list[i].key != 0; i++) {
+ if (key == list[i].key) {
result->key = list[i].key;
result->VFT2_m1 = list[i].VFT2_m1;
result->VFT2_m2 = list[i].VFT2_m2;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
index 6e8f7a2..c6ba0d6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
@@ -28,7 +28,7 @@
#include <linux/kernel.h>
struct phm_fuses_default {
- const char *key;
+ uint64_t key;
uint32_t VFT2_m1;
uint32_t VFT2_m2;
uint32_t VFT2_b;
@@ -40,9 +40,7 @@ struct phm_fuses_default {
uint32_t VFT0_b;
};
-extern struct phm_fuses_default vega10_fuses_default[];
extern int pp_override_get_default_fuse_value(uint64_t key,
- struct phm_fuses_default list[],
struct phm_fuses_default *result);
#endif
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
new file mode 100644
index 0000000..ffa44bb
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -0,0 +1,250 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include "pp_psm.h"
+
+int psm_init_power_state_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ unsigned int i;
+ unsigned int table_entries;
+ struct pp_power_state *state;
+ int size;
+
+ if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
+ return -EINVAL;
+
+ if (hwmgr->hwmgr_func->get_power_state_size == NULL)
+ return -EINVAL;
+
+ hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
+
+ hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
+ sizeof(struct pp_power_state);
+
+ hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
+ if (hwmgr->ps == NULL)
+ return -ENOMEM;
+
+ hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
+ if (hwmgr->request_ps == NULL) {
+ kfree(hwmgr->ps);
+ hwmgr->ps = NULL;
+ return -ENOMEM;
+ }
+
+ hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
+ if (hwmgr->current_ps == NULL) {
+ kfree(hwmgr->request_ps);
+ kfree(hwmgr->ps);
+ hwmgr->request_ps = NULL;
+ hwmgr->ps = NULL;
+ return -ENOMEM;
+ }
+
+ state = hwmgr->ps;
+
+ for (i = 0; i < table_entries; i++) {
+ result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
+
+ if (state->classification.flags & PP_StateClassificationFlag_Boot) {
+ hwmgr->boot_ps = state;
+ memcpy(hwmgr->current_ps, state, size);
+ memcpy(hwmgr->request_ps, state, size);
+ }
+
+ state->id = i + 1; /* assigned unique num for every power state id */
+
+ if (state->classification.flags & PP_StateClassificationFlag_Uvd)
+ hwmgr->uvd_ps = state;
+ state = (struct pp_power_state *)((unsigned long)state + size);
+ }
+
+ return 0;
+}
+
+int psm_fini_power_state_table(struct pp_hwmgr *hwmgr)
+{
+ if (hwmgr == NULL)
+ return -EINVAL;
+
+ kfree(hwmgr->current_ps);
+ kfree(hwmgr->request_ps);
+ kfree(hwmgr->ps);
+ hwmgr->request_ps = NULL;
+ hwmgr->ps = NULL;
+ hwmgr->current_ps = NULL;
+ return 0;
+}
+
+static int psm_get_ui_state(struct pp_hwmgr *hwmgr,
+ enum PP_StateUILabel ui_label,
+ unsigned long *state_id)
+{
+ struct pp_power_state *state;
+ int table_entries;
+ int i;
+
+ table_entries = hwmgr->num_ps;
+ state = hwmgr->ps;
+
+ for (i = 0; i < table_entries; i++) {
+ if (state->classification.ui_label & ui_label) {
+ *state_id = state->id;
+ return 0;
+ }
+ state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
+ }
+ return -EINVAL;
+}
+
+static int psm_get_state_by_classification(struct pp_hwmgr *hwmgr,
+ enum PP_StateClassificationFlag flag,
+ unsigned long *state_id)
+{
+ struct pp_power_state *state;
+ int table_entries;
+ int i;
+
+ table_entries = hwmgr->num_ps;
+ state = hwmgr->ps;
+
+ for (i = 0; i < table_entries; i++) {
+ if (state->classification.flags & flag) {
+ *state_id = state->id;
+ return 0;
+ }
+ state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
+ }
+ return -EINVAL;
+}
+
+static int psm_set_states(struct pp_hwmgr *hwmgr, unsigned long state_id)
+{
+ struct pp_power_state *state;
+ int table_entries;
+ int i;
+
+ table_entries = hwmgr->num_ps;
+
+ state = hwmgr->ps;
+
+ for (i = 0; i < table_entries; i++) {
+ if (state->id == state_id) {
+ memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
+ return 0;
+ }
+ state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
+ }
+ return -EINVAL;
+}
+
+int psm_set_boot_states(struct pp_hwmgr *hwmgr)
+{
+ unsigned long state_id;
+ int ret = -EINVAL;
+
+ if (!psm_get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot,
+ &state_id))
+ ret = psm_set_states(hwmgr, state_id);
+
+ return ret;
+}
+
+int psm_set_performance_states(struct pp_hwmgr *hwmgr)
+{
+ unsigned long state_id;
+ int ret = -EINVAL;
+
+ if (!psm_get_ui_state(hwmgr, PP_StateUILabel_Performance,
+ &state_id))
+ ret = psm_set_states(hwmgr, state_id);
+
+ return ret;
+}
+
+int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
+ enum PP_StateUILabel label_id,
+ struct pp_power_state **state)
+{
+ int table_entries;
+ int i;
+
+ table_entries = hwmgr->num_ps;
+ *state = hwmgr->ps;
+
+restart_search:
+ for (i = 0; i < table_entries; i++) {
+ if ((*state)->classification.ui_label & label_id)
+ return 0;
+ *state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size);
+ }
+
+ switch (label_id) {
+ case PP_StateUILabel_Battery:
+ case PP_StateUILabel_Balanced:
+ label_id = PP_StateUILabel_Performance;
+ goto restart_search;
+ default:
+ break;
+ }
+ return -EINVAL;
+}
+
+int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
+ struct pp_power_state *new_ps)
+{
+ struct pp_power_state *pcurrent;
+ struct pp_power_state *requested;
+ bool equal;
+
+ if (skip)
+ return 0;
+
+ phm_display_configuration_changed(hwmgr);
+
+ if (new_ps != NULL)
+ requested = new_ps;
+ else
+ requested = hwmgr->request_ps;
+
+ pcurrent = hwmgr->current_ps;
+
+ phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
+ if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr,
+ &pcurrent->hardware, &requested->hardware, &equal)))
+ equal = false;
+
+ if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
+ phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
+ memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
+ }
+
+ phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
+
+ return 0;
+}
+
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h
similarity index 65%
copy from drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h
copy to drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h
index 9ef96aa..fa1b682 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -21,14 +21,20 @@
*
*/
-#ifndef _EVENTINIT_H_
-#define _EVENTINIT_H_
+#ifndef PP_PSM_H
+#define PP_PSM_H
-#define PEM_CURRENT_POWERPLAY_FEATURE_VERSION 4
+#include "hwmgr.h"
-void pem_init_feature_info(struct pp_eventmgr *eventmgr);
-void pem_uninit_featureInfo(struct pp_eventmgr *eventmgr);
-int pem_register_interrupts(struct pp_eventmgr *eventmgr);
-int pem_unregister_interrupts(struct pp_eventmgr *eventmgr);
+int psm_init_power_state_table(struct pp_hwmgr *hwmgr);
+int psm_fini_power_state_table(struct pp_hwmgr *hwmgr);
+int psm_set_boot_states(struct pp_hwmgr *hwmgr);
+int psm_set_performance_states(struct pp_hwmgr *hwmgr);
+int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
+ enum PP_StateUILabel label_id,
+ struct pp_power_state **state);
+int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr,
+ bool skip,
+ struct pp_power_state *new_ps);
-#endif /* _EVENTINIT_H_ */
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index 953e0c9..a129bc5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -470,7 +470,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
* SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
* voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
*/
-bool atomctrl_is_voltage_controled_by_gpio_v3(
+bool atomctrl_is_voltage_controlled_by_gpio_v3(
struct pp_hwmgr *hwmgr,
uint8_t voltage_type,
uint8_t voltage_mode)
@@ -1100,10 +1100,10 @@ int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr,
}
}
- PP_ASSERT_WITH_CODE(entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count,
- "Can't find requested voltage id in vddc_dependency_on_sclk table!",
+ if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) {
+ pr_debug("Can't find requested voltage id in vddc_dependency_on_sclk table!\n");
return -EINVAL;
- );
+ }
get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC;
get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
@@ -1418,3 +1418,83 @@ int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
return 0;
}
+
+int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
+{
+ int result;
+ SET_VOLTAGE_PS_ALLOCATION allocation;
+ SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
+ (SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
+
+ voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;
+
+ result = cgs_atom_exec_cmd_table(hwmgr->device,
+ GetIndexIntoMasterTable(COMMAND, SetVoltage),
+ voltage_parameters);
+
+ *virtual_voltage_id = voltage_parameters->usVoltageLevel;
+
+ return result;
+}
+
+int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
+ uint16_t *vddc, uint16_t *vddci,
+ uint16_t virtual_voltage_id,
+ uint16_t efuse_voltage_id)
+{
+ int i, j;
+ int ix;
+ u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
+ ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
+
+ *vddc = 0;
+ *vddci = 0;
+
+ ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
+
+ profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
+ cgs_atom_get_data_table(hwmgr->device,
+ ix,
+ NULL, NULL, NULL);
+ if (!profile)
+ return -EINVAL;
+
+ if ((profile->asHeader.ucTableFormatRevision >= 2) &&
+ (profile->asHeader.ucTableContentRevision >= 1) &&
+ (profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) {
+ leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset);
+ vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset);
+ vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset);
+ if (profile->ucElbVDDC_Num > 0) {
+ for (i = 0; i < profile->ucElbVDDC_Num; i++) {
+ if (vddc_id_buf[i] == virtual_voltage_id) {
+ for (j = 0; j < profile->ucLeakageBinNum; j++) {
+ if (efuse_voltage_id <= leakage_bin[j]) {
+ *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
+ break;
+ }
+ }
+ break;
+ }
+ }
+ }
+
+ vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset);
+ vddci_buf = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset);
+ if (profile->ucElbVDDCI_Num > 0) {
+ for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
+ if (vddci_id_buf[i] == virtual_voltage_id) {
+ for (j = 0; j < profile->ucLeakageBinNum; j++) {
+ if (efuse_voltage_id <= leakage_bin[j]) {
+ *vddci = vddci_buf[j * profile->ucElbVDDC_Num + i];
+ break;
+ }
+ }
+ break;
+ }
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index e9fe2e8..c44a920 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -291,7 +291,7 @@ extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
-extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
+extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
@@ -314,5 +314,11 @@ extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_
extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
uint16_t *load_line);
+
+extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
+ uint16_t *vddc, uint16_t *vddci,
+ uint16_t virtual_voltage_id,
+ uint16_t efuse_voltage_id);
+extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index 84f01fd3..d1af148 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -173,8 +173,6 @@ static int get_vddc_lookup_table(
if (NULL == table)
return -ENOMEM;
- memset(table, 0x00, table_size);
-
table->count = vddc_lookup_pp_tables->ucNumEntries;
for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) {
@@ -335,8 +333,6 @@ static int get_valid_clk(
if (NULL == table)
return -ENOMEM;
- memset(table, 0x00, table_size);
-
table->count = (uint32_t)clk_volt_pp_table->count;
for (i = 0; i < table->count; i++) {
@@ -390,8 +386,6 @@ static int get_mclk_voltage_dependency_table(
if (NULL == mclk_table)
return -ENOMEM;
- memset(mclk_table, 0x00, table_size);
-
mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
@@ -439,8 +433,6 @@ static int get_sclk_voltage_dependency_table(
if (NULL == sclk_table)
return -ENOMEM;
- memset(sclk_table, 0x00, table_size);
-
sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
for (i = 0; i < tonga_table->ucNumEntries; i++) {
@@ -473,8 +465,6 @@ static int get_sclk_voltage_dependency_table(
if (NULL == sclk_table)
return -ENOMEM;
- memset(sclk_table, 0x00, table_size);
-
sclk_table->count = (uint32_t)polaris_table->ucNumEntries;
for (i = 0; i < polaris_table->ucNumEntries; i++) {
@@ -525,8 +515,6 @@ static int get_pcie_table(
if (pcie_table == NULL)
return -ENOMEM;
- memset(pcie_table, 0x00, table_size);
-
/*
* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
@@ -567,8 +555,6 @@ static int get_pcie_table(
if (pcie_table == NULL)
return -ENOMEM;
- memset(pcie_table, 0x00, table_size);
-
/*
* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
@@ -615,8 +601,6 @@ static int get_cac_tdp_table(
if (NULL == tdp_table)
return -ENOMEM;
- memset(tdp_table, 0x00, table_size);
-
hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
if (NULL == hwmgr->dyn_state.cac_dtp_table) {
@@ -624,8 +608,6 @@ static int get_cac_tdp_table(
return -ENOMEM;
}
- memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size);
-
if (table->ucRevId < 3) {
const ATOM_Tonga_PowerTune_Table *tonga_table =
(ATOM_Tonga_PowerTune_Table *)table;
@@ -725,8 +707,6 @@ static int get_mm_clock_voltage_table(
if (NULL == mm_table)
return -ENOMEM;
- memset(mm_table, 0x00, table_size);
-
mm_table->count = mm_dependency_table->ucNumEntries;
for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index 2716721..afae32e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -24,7 +24,7 @@
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
-
+#include <drm/amdgpu_drm.h>
#include "processpptables.h"
#include <atom-types.h>
#include <atombios.h>
@@ -790,6 +790,39 @@ static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
return pstate;
}
+static const unsigned char soft_dummy_pp_table[] = {
+ 0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 0x00, 0x6c, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x18, 0x05, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1, 0x00, 0x43, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x8e, 0x01, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c,
+ 0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x70, 0x00, 0x91, 0xf4, 0x00,
+ 0x64, 0x00, 0x40, 0x19, 0x01, 0x5a, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a,
+ 0x00, 0x00, 0x09, 0x30, 0x75, 0x00, 0x30, 0x75, 0x00, 0x40, 0x9c, 0x00, 0x40, 0x9c, 0x00, 0x59,
+ 0xd8, 0x00, 0x59, 0xd8, 0x00, 0x91, 0xf4, 0x00, 0x91, 0xf4, 0x00, 0x0e, 0x28, 0x01, 0x0e, 0x28,
+ 0x01, 0x90, 0x5f, 0x01, 0x90, 0x5f, 0x01, 0x00, 0x77, 0x01, 0x00, 0x77, 0x01, 0xca, 0x91, 0x01,
+ 0xca, 0x91, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01,
+ 0x7c, 0x00, 0x02, 0x70, 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a,
+ 0x00, 0x07, 0x08, 0x08, 0x00, 0x08, 0x00, 0x01, 0x02, 0x02, 0x02, 0x01, 0x02, 0x02, 0x02, 0x03,
+ 0x02, 0x04, 0x02, 0x00, 0x08, 0x40, 0x9c, 0x00, 0x30, 0x75, 0x00, 0x74, 0xb5, 0x00, 0xa0, 0x8c,
+ 0x00, 0x60, 0xea, 0x00, 0x74, 0xb5, 0x00, 0x0e, 0x28, 0x01, 0x60, 0xea, 0x00, 0x90, 0x5f, 0x01,
+ 0x40, 0x19, 0x01, 0xb2, 0xb0, 0x01, 0x90, 0x5f, 0x01, 0xc0, 0xd4, 0x01, 0x00, 0x77, 0x01, 0x5e,
+ 0xff, 0x01, 0xca, 0x91, 0x01, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01, 0x7c, 0x00, 0x02, 0x70,
+ 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a, 0x00, 0x07, 0x00, 0x08,
+ 0x80, 0x00, 0x30, 0x75, 0x00, 0x7e, 0x00, 0x40, 0x9c, 0x00, 0x7c, 0x00, 0x59, 0xd8, 0x00, 0x70,
+ 0x00, 0xdc, 0x0b, 0x01, 0x64, 0x00, 0x80, 0x38, 0x01, 0x5a, 0x00, 0x80, 0x38, 0x01, 0x52, 0x00,
+ 0x80, 0x38, 0x01, 0x4a, 0x00, 0x80, 0x38, 0x01, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c,
+ 0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x74, 0x00, 0x91, 0xf4, 0x00,
+ 0x66, 0x00, 0x40, 0x19, 0x01, 0x58, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a,
+ 0x00
+};
static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
struct pp_hwmgr *hwmgr)
@@ -799,12 +832,17 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
uint16_t size;
if (!table_addr) {
- table_addr = cgs_atom_get_data_table(hwmgr->device,
- GetIndexIntoMasterTable(DATA, PowerPlayInfo),
- &size, &frev, &crev);
-
- hwmgr->soft_pp_table = table_addr;
- hwmgr->soft_pp_table_size = size;
+ if (hwmgr->chip_id == CHIP_RAVEN) {
+ table_addr = &soft_dummy_pp_table[0];
+ hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
+ hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
+ } else {
+ table_addr = cgs_atom_get_data_table(hwmgr->device,
+ GetIndexIntoMasterTable(DATA, PowerPlayInfo),
+ &size, &frev, &crev);
+ hwmgr->soft_pp_table = table_addr;
+ hwmgr->soft_pp_table_size = size;
+ }
}
return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr;
@@ -924,15 +962,14 @@ int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
}
}
- if ((0 == result) &&
- (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot)))
- result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
+ if ((0 == result) && (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot))) {
+ if (hwmgr->chip_family < AMDGPU_FAMILY_RV)
+ result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
+ }
return result;
}
-
-
static int init_powerplay_tables(
struct pp_hwmgr *hwmgr,
const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table
@@ -1615,85 +1652,53 @@ static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
if (hwmgr->chip_id == CHIP_RAVEN)
return 0;
- if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) {
- kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
- hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
- }
+ kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
+ hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
- if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
- kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
- hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
- }
+ kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
+ hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
- if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) {
- kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
- hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
- }
+ kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
+ hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
- if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
- kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
- hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
- }
+ kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
+ hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
- if (NULL != hwmgr->dyn_state.valid_mclk_values) {
- kfree(hwmgr->dyn_state.valid_mclk_values);
- hwmgr->dyn_state.valid_mclk_values = NULL;
- }
+ kfree(hwmgr->dyn_state.valid_mclk_values);
+ hwmgr->dyn_state.valid_mclk_values = NULL;
- if (NULL != hwmgr->dyn_state.valid_sclk_values) {
- kfree(hwmgr->dyn_state.valid_sclk_values);
- hwmgr->dyn_state.valid_sclk_values = NULL;
- }
+ kfree(hwmgr->dyn_state.valid_sclk_values);
+ hwmgr->dyn_state.valid_sclk_values = NULL;
- if (NULL != hwmgr->dyn_state.cac_leakage_table) {
- kfree(hwmgr->dyn_state.cac_leakage_table);
- hwmgr->dyn_state.cac_leakage_table = NULL;
- }
+ kfree(hwmgr->dyn_state.cac_leakage_table);
+ hwmgr->dyn_state.cac_leakage_table = NULL;
- if (NULL != hwmgr->dyn_state.vddc_phase_shed_limits_table) {
- kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
- hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
- }
+ kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
+ hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
- if (NULL != hwmgr->dyn_state.vce_clock_voltage_dependency_table) {
- kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
- hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
- }
+ kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
+ hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
- if (NULL != hwmgr->dyn_state.uvd_clock_voltage_dependency_table) {
- kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
- hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
- }
+ kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
+ hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
- if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) {
- kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
- hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
- }
+ kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
+ hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
- if (NULL != hwmgr->dyn_state.acp_clock_voltage_dependency_table) {
- kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
- hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
- }
+ kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
+ hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
- if (NULL != hwmgr->dyn_state.cac_dtp_table) {
- kfree(hwmgr->dyn_state.cac_dtp_table);
- hwmgr->dyn_state.cac_dtp_table = NULL;
- }
+ kfree(hwmgr->dyn_state.cac_dtp_table);
+ hwmgr->dyn_state.cac_dtp_table = NULL;
- if (NULL != hwmgr->dyn_state.ppm_parameter_table) {
- kfree(hwmgr->dyn_state.ppm_parameter_table);
- hwmgr->dyn_state.ppm_parameter_table = NULL;
- }
+ kfree(hwmgr->dyn_state.ppm_parameter_table);
+ hwmgr->dyn_state.ppm_parameter_table = NULL;
- if (NULL != hwmgr->dyn_state.vdd_gfx_dependency_on_sclk) {
- kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
- hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
- }
+ kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
+ hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
- if (NULL != hwmgr->dyn_state.vq_budgeting_table) {
- kfree(hwmgr->dyn_state.vq_budgeting_table);
- hwmgr->dyn_state.vq_budgeting_table = NULL;
- }
+ kfree(hwmgr->dyn_state.vq_budgeting_table);
+ hwmgr->dyn_state.vq_budgeting_table = NULL;
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 2c3e6ba..3e0b267 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -38,20 +38,17 @@
#include "pp_soc15.h"
#define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5
-#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip
+#define RAVEN_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
#define SCLK_MIN_DIV_INTV_SHIFT 12
-#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz
+#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
#define SMC_RAM_END 0x40000
static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic;
+
+
int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock_req);
-struct phm_vq_budgeting_record rv_vqtable[] = {
- /* _TBD
- * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */
- { 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 },
-};
static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
{
@@ -70,101 +67,27 @@ static const struct rv_power_state *cast_const_rv_ps(
return (struct rv_power_state *)hw_ps;
}
-static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
-{
- uint32_t table_size, i;
- struct phm_vq_budgeting_table *ptable;
- uint32_t num_entries = ARRAY_SIZE(rv_vqtable);
-
- if (hwmgr->dyn_state.vq_budgeting_table != NULL)
- return 0;
-
- table_size = sizeof(struct phm_vq_budgeting_table) +
- sizeof(struct phm_vq_budgeting_record) * (num_entries - 1);
-
- ptable = kzalloc(table_size, GFP_KERNEL);
- if (NULL == ptable)
- return -ENOMEM;
-
- ptable->numEntries = (uint8_t) num_entries;
-
- for (i = 0; i < ptable->numEntries; i++) {
- ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs;
- ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow;
- ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh;
- ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow;
- ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh;
- ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig;
- ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk;
- ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk;
- ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk;
- ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs;
- }
-
- hwmgr->dyn_state.vq_budgeting_table = ptable;
-
- return 0;
-}
-
static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
- struct cgs_system_info sys_info = {0};
- int result;
- rv_hwmgr->ddi_power_gating_disabled = 0;
- rv_hwmgr->bapm_enabled = 1;
rv_hwmgr->dce_slow_sclk_threshold = 30000;
- rv_hwmgr->disable_driver_thermal_policy = 1;
rv_hwmgr->thermal_auto_throttling_treshold = 0;
rv_hwmgr->is_nb_dpm_enabled = 1;
rv_hwmgr->dpm_flags = 1;
- rv_hwmgr->disable_smu_acp_s3_handshake = 1;
- rv_hwmgr->disable_notify_smu_vpu_recovery = 0;
rv_hwmgr->gfx_off_controled_by_driver = false;
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_DynamicM3Arbiter);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDPowerGating);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDDynamicPowerGating);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_VCEPowerGating);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SamuPowerGating);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ACP);
+ rv_hwmgr->need_min_deep_sleep_dcefclk = true;
+ rv_hwmgr->num_active_display = 0;
+ rv_hwmgr->deep_sleep_dcefclk = 0;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_GFXDynamicMGPowerGating);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_DisableVoltageIsland);
-
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_DynamicUVDState);
-
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
- result = cgs_query_system_info(hwmgr->device, &sys_info);
- if (!result) {
- if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG)
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_GFXDynamicMGPowerGating);
- }
-
+ PHM_PlatformCaps_PowerPlaySupport);
return 0;
}
@@ -234,102 +157,88 @@ static int rv_construct_boot_state(struct pp_hwmgr *hwmgr)
return 0;
}
-static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
{
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
struct PP_Clocks clocks = {0};
struct pp_display_clock_request clock_req;
clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
- clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
clock_req.clock_type = amd_pp_dcf_clock;
clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
- if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0)
- clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq;
-
PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
"Attempt to set DCF Clock Failed!", return -EINVAL);
- if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetMinDeepSleepDcefclk,
- clocks.dcefClockInSR / 100);
- /*
- if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) {
- if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) {
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100);
- rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq),
- }
- } */
-
if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) ||
((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinVcn,
(rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
}
if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinSocclkByFreq,
hwmgr->gfx_arbiter.sclk_hard_min / 100);
- rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq);
+ rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);
}
if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinVideoGfxclkFreq,
hwmgr->gfx_arbiter.gfxclk / 100);
- rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq);
+ rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);
}
if ((hwmgr->gfx_arbiter.fclk != 0) &&
(rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinVideoFclkFreq,
hwmgr->gfx_arbiter.fclk / 100);
- rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq);
+ rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);
}
return 0;
}
-static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
{
- uint32_t num_of_active_displays = 0;
- struct cgs_display_info info = {0};
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- cgs_get_active_displays_info(hwmgr->device, &info);
- num_of_active_displays = info.display_count;
-
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetDisplayCount,
- num_of_active_displays);
+ if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) {
+ rv_data->deep_sleep_dcefclk = clock/100;
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetMinDeepSleepDcefclk,
+ rv_data->deep_sleep_dcefclk);
+ }
return 0;
}
-static const struct phm_master_table_item rv_set_power_state_list[] = {
- { .tableFunction = rv_tf_set_clock_limit },
- { .tableFunction = rv_tf_set_num_active_display },
- { }
-};
+static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
-static const struct phm_master_table_header rv_set_power_state_master = {
- 0,
- PHM_MasterTableFlag_None,
- rv_set_power_state_list
-};
+ if (rv_data->num_active_display != count) {
+ rv_data->num_active_display = count;
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetDisplayCount,
+ rv_data->num_active_display);
+ }
-static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result)
+ return 0;
+}
+
+static int rv_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+{
+ return rv_set_clock_limit(hwmgr, input);
+}
+
+static int rv_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
@@ -340,20 +249,13 @@ static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
return 0;
}
-static const struct phm_master_table_item rv_setup_asic_list[] = {
- { .tableFunction = rv_tf_init_power_gate_state },
- { }
-};
-static const struct phm_master_table_header rv_setup_asic_master = {
- 0,
- PHM_MasterTableFlag_None,
- rv_setup_asic_list
-};
+static int rv_setup_asic_task(struct pp_hwmgr *hwmgr)
+{
+ return rv_init_power_gate_state(hwmgr);
+}
-static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static int rv_reset_cc6_data(struct pp_hwmgr *hwmgr)
{
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
@@ -365,66 +267,42 @@ static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
return 0;
}
-static const struct phm_master_table_item rv_power_down_asic_list[] = {
- { .tableFunction = rv_tf_reset_cc6_data },
- { }
-};
+static int rv_power_off_asic(struct pp_hwmgr *hwmgr)
+{
+ return rv_reset_cc6_data(hwmgr);
+}
-static const struct phm_master_table_header rv_power_down_asic_master = {
- 0,
- PHM_MasterTableFlag_None,
- rv_power_down_asic_list
-};
-
-
-static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
if (rv_data->gfx_off_controled_by_driver)
- smum_send_msg_to_smc(hwmgr->smumgr,
+ smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_DisableGfxOff);
return 0;
}
-static const struct phm_master_table_item rv_disable_dpm_list[] = {
- { .tableFunction = rv_tf_disable_gfx_off },
- { },
-};
+static int rv_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+ return rv_disable_gfx_off(hwmgr);
+}
-
-static const struct phm_master_table_header rv_disable_dpm_master = {
- 0,
- PHM_MasterTableFlag_None,
- rv_disable_dpm_list
-};
-
-static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr,
- void *input, void *output,
- void *storage, int result)
+static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
if (rv_data->gfx_off_controled_by_driver)
- smum_send_msg_to_smc(hwmgr->smumgr,
+ smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_EnableGfxOff);
return 0;
}
-static const struct phm_master_table_item rv_enable_dpm_list[] = {
- { .tableFunction = rv_tf_enable_gfx_off },
- { },
-};
-
-static const struct phm_master_table_header rv_enable_dpm_master = {
- 0,
- PHM_MasterTableFlag_None,
- rv_enable_dpm_list
-};
+static int rv_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+ return rv_enable_gfx_off(hwmgr);
+}
static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *prequest_ps,
@@ -434,37 +312,37 @@ static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
}
/* temporary hardcoded clock voltage breakdown tables */
-DpmClock_t VddDcfClk[]= {
+static const DpmClock_t VddDcfClk[]= {
{ 300, 2600},
{ 600, 3200},
{ 600, 3600},
};
-DpmClock_t VddSocClk[]= {
+static const DpmClock_t VddSocClk[]= {
{ 478, 2600},
{ 722, 3200},
{ 722, 3600},
};
-DpmClock_t VddFClk[]= {
+static const DpmClock_t VddFClk[]= {
{ 400, 2600},
{1200, 3200},
{1200, 3600},
};
-DpmClock_t VddDispClk[]= {
+static const DpmClock_t VddDispClk[]= {
{ 435, 2600},
{ 661, 3200},
{1086, 3600},
};
-DpmClock_t VddDppClk[]= {
+static const DpmClock_t VddDppClk[]= {
{ 435, 2600},
{ 661, 3200},
{ 661, 3600},
};
-DpmClock_t VddPhyClk[]= {
+static const DpmClock_t VddPhyClk[]= {
{ 540, 2600},
{ 810, 3200},
{ 810, 3600},
@@ -472,7 +350,7 @@ DpmClock_t VddPhyClk[]= {
static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
struct rv_voltage_dependency_table **pptable,
- uint32_t num_entry, DpmClock_t *pclk_dependency_table)
+ uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
{
uint32_t table_size, i;
struct rv_voltage_dependency_table *ptable;
@@ -505,7 +383,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
DpmClocks_t *table = &(rv_data->clock_table);
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
- result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE);
+ result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
PP_ASSERT_WITH_CODE((0 == result),
"Attempt to copy clock table from smc failed",
@@ -543,6 +421,26 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+ PPSMC_MSG_GetMinGfxclkFrequency),
+ "Attempt to get min GFXCLK Failed!",
+ return -1);
+ PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
+ &result),
+ "Attempt to get min GFXCLK Failed!",
+ return -1);
+ rv_data->gfx_min_freq_limit = result * 100;
+
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+ PPSMC_MSG_GetMaxGfxclkFrequency),
+ "Attempt to get max GFXCLK Failed!",
+ return -1);
+ PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
+ &result),
+ "Attempt to get max GFXCLK Failed!",
+ return -1);
+ rv_data->gfx_max_freq_limit = result * 100;
+
return 0;
}
@@ -563,9 +461,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
return result;
}
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerPlaySupport);
-
rv_populate_clock_table(hwmgr);
result = rv_get_system_info_data(hwmgr);
@@ -576,40 +471,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
rv_construct_boot_state(hwmgr);
- result = phm_construct_table(hwmgr, &rv_setup_asic_master,
- &(hwmgr->setup_asic));
- if (result != 0) {
- pr_err("Fail to construct setup ASIC\n");
- return result;
- }
-
- result = phm_construct_table(hwmgr, &rv_power_down_asic_master,
- &(hwmgr->power_down_asic));
- if (result != 0) {
- pr_err("Fail to construct power down ASIC\n");
- return result;
- }
-
- result = phm_construct_table(hwmgr, &rv_set_power_state_master,
- &(hwmgr->set_power_state));
- if (result != 0) {
- pr_err("Fail to construct set_power_state\n");
- return result;
- }
-
- result = phm_construct_table(hwmgr, &rv_disable_dpm_master,
- &(hwmgr->disable_dynamic_state_management));
- if (result != 0) {
- pr_err("Fail to disable_dynamic_state\n");
- return result;
- }
- result = phm_construct_table(hwmgr, &rv_enable_dpm_master,
- &(hwmgr->enable_dynamic_state_management));
- if (result != 0) {
- pr_err("Fail to enable_dynamic_state\n");
- return result;
- }
-
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
RAVEN_MAX_HARDWARE_POWERLEVELS;
@@ -624,8 +485,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
- rv_init_vq_budget_table(hwmgr);
-
return result;
}
@@ -634,46 +493,21 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
- phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
- phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
- phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
- phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
- phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
+ kfree(pinfo->vdd_dep_on_dcefclk);
+ pinfo->vdd_dep_on_dcefclk = NULL;
+ kfree(pinfo->vdd_dep_on_socclk);
+ pinfo->vdd_dep_on_socclk = NULL;
+ kfree(pinfo->vdd_dep_on_fclk);
+ pinfo->vdd_dep_on_fclk = NULL;
+ kfree(pinfo->vdd_dep_on_dispclk);
+ pinfo->vdd_dep_on_dispclk = NULL;
+ kfree(pinfo->vdd_dep_on_dppclk);
+ pinfo->vdd_dep_on_dppclk = NULL;
+ kfree(pinfo->vdd_dep_on_phyclk);
+ pinfo->vdd_dep_on_phyclk = NULL;
- if (pinfo->vdd_dep_on_dcefclk) {
- kfree(pinfo->vdd_dep_on_dcefclk);
- pinfo->vdd_dep_on_dcefclk = NULL;
- }
- if (pinfo->vdd_dep_on_socclk) {
- kfree(pinfo->vdd_dep_on_socclk);
- pinfo->vdd_dep_on_socclk = NULL;
- }
- if (pinfo->vdd_dep_on_fclk) {
- kfree(pinfo->vdd_dep_on_fclk);
- pinfo->vdd_dep_on_fclk = NULL;
- }
- if (pinfo->vdd_dep_on_dispclk) {
- kfree(pinfo->vdd_dep_on_dispclk);
- pinfo->vdd_dep_on_dispclk = NULL;
- }
- if (pinfo->vdd_dep_on_dppclk) {
- kfree(pinfo->vdd_dep_on_dppclk);
- pinfo->vdd_dep_on_dppclk = NULL;
- }
- if (pinfo->vdd_dep_on_phyclk) {
- kfree(pinfo->vdd_dep_on_phyclk);
- pinfo->vdd_dep_on_phyclk = NULL;
- }
-
- if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
- kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
- hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
- }
-
- if (NULL != hwmgr->dyn_state.vq_budgeting_table) {
- kfree(hwmgr->dyn_state.vq_budgeting_table);
- hwmgr->dyn_state.vq_budgeting_table = NULL;
- }
+ kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
+ hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
kfree(hwmgr->backend);
hwmgr->backend = NULL;
@@ -687,12 +521,12 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
return 0;
}
-static int rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
return 0;
}
-static int rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
return 0;
}
@@ -711,18 +545,9 @@ static int rv_dpm_get_pp_table_entry_callback(
{
struct rv_power_state *rv_ps = cast_rv_ps(hw_ps);
- const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info;
+ rv_ps->levels[index].engine_clock = 0;
- struct phm_clock_voltage_dependency_table *table =
- hwmgr->dyn_state.vddc_dependency_on_sclk;
- uint8_t clock_info_index = rv_clock_info->index;
-
- if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
- clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
-
- rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk;
- rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v;
-
+ rv_ps->levels[index].vddc_index = 0;
rv_ps->level = index + 1;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
@@ -794,43 +619,74 @@ static int rv_force_clock_level(struct pp_hwmgr *hwmgr,
static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
- return 0;
+ struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct rv_voltage_dependency_table *mclk_table =
+ data->clock_vol_info.vdd_dep_on_fclk;
+ int i, now, size = 0;
+
+ switch (type) {
+ case PP_SCLK:
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+ PPSMC_MSG_GetGfxclkFrequency),
+ "Attempt to get current GFXCLK Failed!",
+ return -1);
+ PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
+ &now),
+ "Attempt to get current GFXCLK Failed!",
+ return -1);
+
+ size += sprintf(buf + size, "0: %uMhz %s\n",
+ data->gfx_min_freq_limit / 100,
+ ((data->gfx_min_freq_limit / 100)
+ == now) ? "*" : "");
+ size += sprintf(buf + size, "1: %uMhz %s\n",
+ data->gfx_max_freq_limit / 100,
+ ((data->gfx_max_freq_limit / 100)
+ == now) ? "*" : "");
+ break;
+ case PP_MCLK:
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+ PPSMC_MSG_GetFclkFrequency),
+ "Attempt to get current MEMCLK Failed!",
+ return -1);
+ PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
+ &now),
+ "Attempt to get current MEMCLK Failed!",
+ return -1);
+
+ for (i = 0; i < mclk_table->count; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i,
+ mclk_table->entries[i].clk / 100,
+ ((mclk_table->entries[i].clk / 100)
+ == now) ? "*" : "");
+ break;
+ default:
+ break;
+ }
+
+ return size;
}
static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
PHM_PerformanceLevelDesignation designation, uint32_t index,
PHM_PerformanceLevel *level)
{
- const struct rv_power_state *ps;
struct rv_hwmgr *data;
- uint32_t level_index;
- uint32_t i;
- uint32_t vol_dep_record_index = 0;
if (level == NULL || hwmgr == NULL || state == NULL)
return -EINVAL;
data = (struct rv_hwmgr *)(hwmgr->backend);
- ps = cast_const_rv_ps(state);
- level_index = index > ps->level - 1 ? ps->level - 1 : index;
- level->coreClock = ps->levels[level_index].engine_clock;
-
- if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
- for (i = 1; i < ps->level; i++) {
- if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) {
- level->coreClock = ps->levels[i].engine_clock;
- break;
- }
- }
- }
-
- if (level_index == 0) {
- vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
- level->memory_clock =
- data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk;
- } else
+ if (index == 0) {
level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
+ level->coreClock = data->gfx_min_freq_limit;
+ } else {
+ level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
+ data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
+ level->coreClock = data->gfx_max_freq_limit;
+ }
level->nonLocalMemoryFreq = 0;
level->nonLocalMemoryWidth = 0;
@@ -993,7 +849,7 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
return -EINVAL;
}
- result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg,
+ result = smum_send_msg_to_smc_with_parameter(hwmgr, msg,
clk_freq);
return result;
@@ -1001,7 +857,8 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
{
- return -EINVAL;
+ clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
+ return 0;
}
static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
@@ -1023,13 +880,37 @@ static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
+ uint32_t sclk, mclk;
+ int ret = 0;
+
switch (idx) {
+ case AMDGPU_PP_SENSOR_GFX_SCLK:
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
+ if (!ret) {
+ rv_read_arg_from_smc(hwmgr, &sclk);
+ /* in units of 10KHZ */
+ *((uint32_t *)value) = sclk * 100;
+ *size = 4;
+ }
+ break;
+ case AMDGPU_PP_SENSOR_GFX_MCLK:
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
+ if (!ret) {
+ rv_read_arg_from_smc(hwmgr, &mclk);
+ /* in units of 10KHZ */
+ *((uint32_t *)value) = mclk * 100;
+ *size = 4;
+ }
+ break;
case AMDGPU_PP_SENSOR_GPU_TEMP:
*((uint32_t *)value) = rv_thermal_get_temperature(hwmgr);
- return 0;
+ break;
default:
- return -EINVAL;
+ ret = -EINVAL;
+ break;
}
+
+ return ret;
}
static const struct pp_hwmgr_func rv_hwmgr_funcs = {
@@ -1058,6 +939,13 @@ static const struct pp_hwmgr_func rv_hwmgr_funcs = {
.get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage,
.get_max_high_clocks = rv_get_max_high_clocks,
.read_sensor = rv_read_sensor,
+ .set_active_display_count = rv_set_active_display_count,
+ .set_deep_sleep_dcefclk = rv_set_deep_sleep_dcefclk,
+ .dynamic_state_management_enable = rv_enable_dpm_tasks,
+ .power_off_asic = rv_power_off_asic,
+ .asic_setup = rv_setup_asic_task,
+ .power_state_set = rv_set_power_state_tasks,
+ .dynamic_state_management_disable = rv_disable_dpm_tasks,
};
int rv_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index 2472b50..9dc5030 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -283,6 +283,8 @@ struct rv_hwmgr {
uint32_t vclk_soft_min;
uint32_t dclk_soft_min;
uint32_t gfx_actual_soft_min_freq;
+ uint32_t gfx_min_freq_limit;
+ uint32_t gfx_max_freq_limit;
bool vcn_power_gated;
bool vcn_dpg_mode;
@@ -293,7 +295,9 @@ struct rv_hwmgr {
DpmClocks_t clock_table;
uint32_t active_process_mask;
- bool need_min_deep_sleep_dcefclk; /* disabled by default */
+ bool need_min_deep_sleep_dcefclk;
+ uint32_t deep_sleep_dcefclk;
+ uint32_t num_active_display;
};
struct pp_hwmgr;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 261b828..69a0678 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -27,21 +27,21 @@
static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
- return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
+ return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_UVDDPM_Enable :
PPSMC_MSG_UVDDPM_Disable);
}
static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
- return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
+ return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_VCEDPM_Enable :
PPSMC_MSG_VCEDPM_Disable);
}
static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
- return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
+ return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_SAMUDPM_Enable :
PPSMC_MSG_SAMUDPM_Disable);
}
@@ -70,7 +70,7 @@ static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_uvd_power_gating(hwmgr))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_UVDPowerOFF);
return 0;
}
@@ -80,10 +80,10 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
if (phm_cf_want_uvd_power_gating(hwmgr)) {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDDynamicPowerGating)) {
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDPowerON, 1);
} else {
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDPowerON, 0);
}
}
@@ -94,7 +94,7 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerOFF);
return 0;
}
@@ -102,7 +102,7 @@ static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerON);
return 0;
}
@@ -111,7 +111,7 @@ static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SAMPowerOFF);
return 0;
}
@@ -120,7 +120,7 @@ static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SAMPowerON);
return 0;
}
@@ -140,7 +140,7 @@ int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
return 0;
}
-int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
+void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -166,10 +166,9 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
smu7_update_uvd_dpm(hwmgr, false);
}
- return 0;
}
-int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
+void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -194,7 +193,6 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
AMD_PG_STATE_UNGATE);
smu7_update_vce_dpm(hwmgr, false);
}
- return 0;
}
int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
@@ -237,7 +235,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -247,7 +245,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -260,7 +258,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_3DCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
@@ -271,7 +269,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_3DLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -284,7 +282,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_RLC_LS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -297,7 +295,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CP_LS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -311,7 +309,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
CG_GFX_OTHERS_MGCG_MASK);
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -331,7 +329,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_BIF_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -341,7 +339,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_BIF_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -354,7 +352,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_MC_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
@@ -365,7 +363,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_MC_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -378,7 +376,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_DRM_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -388,7 +386,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_DRM_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -401,7 +399,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_HDP_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
@@ -412,7 +410,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_HDP_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -425,7 +423,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_SDMA_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
@@ -436,7 +434,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_SDMA_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -449,7 +447,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_ROM_MASK;
if (smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, msg, value))
+ hwmgr, msg, value))
return -EINVAL;
}
break;
@@ -489,9 +487,9 @@ int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
active_cus = sys_info.value;
if (enable)
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
else
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GFX_CU_PG_DISABLE);
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index c96ed9e..7b54d48b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -27,8 +27,8 @@
#include "smu7_hwmgr.h"
#include "pp_asicblocks.h"
-int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
+void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
+void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b526f49..4466469 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -26,6 +26,7 @@
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/div64.h>
+#include <drm/amdgpu_drm.h>
#include "pp_acpi.h"
#include "ppatomctrl.h"
#include "atombios.h"
@@ -163,7 +164,7 @@ static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
{
if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
return 0;
}
@@ -300,28 +301,28 @@ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
"Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
}
- tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC);
+ tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
PP_ASSERT_WITH_CODE(
(data->vddc_voltage_table.count <= tmp),
"Too many voltage values for VDDC. Trimming to fit state table.",
phm_trim_voltage_table_to_fit_state_table(tmp,
&(data->vddc_voltage_table)));
- tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);
+ tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
PP_ASSERT_WITH_CODE(
(data->vddgfx_voltage_table.count <= tmp),
"Too many voltage values for VDDC. Trimming to fit state table.",
phm_trim_voltage_table_to_fit_state_table(tmp,
&(data->vddgfx_voltage_table)));
- tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI);
+ tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
PP_ASSERT_WITH_CODE(
(data->vddci_voltage_table.count <= tmp),
"Too many voltage values for VDDCI. Trimming to fit state table.",
phm_trim_voltage_table_to_fit_state_table(tmp,
&(data->vddci_voltage_table)));
- tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD);
+ tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
PP_ASSERT_WITH_CODE(
(data->mvdd_voltage_table.count <= tmp),
"Too many voltage values for MVDD. Trimming to fit state table.",
@@ -387,6 +388,7 @@ static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ int i;
/* Clear reset for voting clients before enabling DPM */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
@@ -394,50 +396,26 @@ static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
-
+ for (i = 0; i < 8; i++)
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_FREQ_TRAN_VOTING_0 + i * 4,
+ data->voting_rights_clients[i]);
return 0;
}
static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
{
+ int i;
+
/* Reset voting clients before disabling DPM */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_0, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_1, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_2, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_3, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_4, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_5, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_6, 0);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_FREQ_TRAN_VOTING_7, 0);
+ for (i = 0; i < 8; i++)
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
return 0;
}
@@ -493,7 +471,7 @@ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
{
- return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
}
/**
@@ -551,7 +529,7 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
data->pcie_gen_performance = data->pcie_gen_power_saving;
data->pcie_lane_performance = data->pcie_lane_power_saving;
}
- tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK);
+ tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
tmp,
MAX_REGULAR_DPM_NUMBER);
@@ -607,13 +585,20 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
data->dpm_table.pcie_speed_table.count = 6;
}
/* Populate last level for boot PCIE level, but do not increment count. */
- phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
+ if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
+ for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
+ phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
+ get_pcie_gen_support(data->pcie_gen_cap,
+ PP_Max_PCIEGen),
+ data->vbios_boot_state.pcie_lane_bootup_value);
+ } else {
+ phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
data->dpm_table.pcie_speed_table.count,
get_pcie_gen_support(data->pcie_gen_cap,
PP_Min_PCIEGen),
get_pcie_lane_support(data->pcie_lane_cap,
PP_Max_PCIELane));
-
+ }
return 0;
}
@@ -625,27 +610,27 @@ static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
phm_reset_single_dpm_table(
&data->dpm_table.sclk_table,
- smum_get_mac_definition(hwmgr->smumgr,
+ smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_GRAPHICS),
MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table(
&data->dpm_table.mclk_table,
- smum_get_mac_definition(hwmgr->smumgr,
+ smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table(
&data->dpm_table.vddc_table,
- smum_get_mac_definition(hwmgr->smumgr,
+ smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_VDDC),
MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table(
&data->dpm_table.vddci_table,
- smum_get_mac_definition(hwmgr->smumgr,
+ smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
phm_reset_single_dpm_table(
&data->dpm_table.mvdd_table,
- smum_get_mac_definition(hwmgr->smumgr,
+ smum_get_mac_definition(hwmgr,
SMU_MAX_LEVELS_MVDD),
MAX_REGULAR_DPM_NUMBER);
return 0;
@@ -689,7 +674,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
allowed_vdd_sclk_table->entries[i].clk) {
data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
allowed_vdd_sclk_table->entries[i].clk;
- data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
+ data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
data->dpm_table.sclk_table.count++;
}
}
@@ -703,7 +688,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
allowed_vdd_mclk_table->entries[i].clk) {
data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
allowed_vdd_mclk_table->entries[i].clk;
- data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
+ data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
data->dpm_table.mclk_table.count++;
}
}
@@ -855,7 +840,7 @@ static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_RegulatorHot))
- return smum_send_msg_to_smc(hwmgr->smumgr,
+ return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_EnableVRHotGPIOInterrupt);
return 0;
@@ -873,7 +858,7 @@ static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (data->ulv_supported)
- return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
return 0;
}
@@ -883,7 +868,7 @@ static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (data->ulv_supported)
- return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
return 0;
}
@@ -892,12 +877,12 @@ static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) {
- if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
+ if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
PP_ASSERT_WITH_CODE(false,
"Attempt to enable Master Deep Sleep switch failed!",
return -EINVAL);
} else {
- if (smum_send_msg_to_smc(hwmgr->smumgr,
+ if (smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MASTER_DeepSleep_OFF)) {
PP_ASSERT_WITH_CODE(false,
"Attempt to disable Master Deep Sleep switch failed!",
@@ -912,7 +897,7 @@ static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) {
- if (smum_send_msg_to_smc(hwmgr->smumgr,
+ if (smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MASTER_DeepSleep_OFF)) {
PP_ASSERT_WITH_CODE(false,
"Attempt to disable Master Deep Sleep switch failed!",
@@ -928,12 +913,12 @@ static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t soft_register_value = 0;
uint32_t handshake_disables_offset = data->soft_regs_start
- + smum_get_offsetof(hwmgr->smumgr,
+ + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, HandshakeDisables);
soft_register_value = cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, handshake_disables_offset);
- soft_register_value |= smum_get_mac_definition(hwmgr->smumgr,
+ soft_register_value |= smum_get_mac_definition(hwmgr,
SMU_UVD_MCLK_HANDSHAKE_DISABLE);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
handshake_disables_offset, soft_register_value);
@@ -947,7 +932,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
/* enable SCLK dpm */
if (!data->sclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE(
- (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
+ (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
"Failed to enable SCLK DPM during DPM Start Function!",
return -EINVAL);
@@ -956,20 +941,31 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
smu7_disable_handshake_uvd(hwmgr);
PP_ASSERT_WITH_CODE(
- (0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ (0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MCLKDPM_Enable)),
"Failed to enable MCLK DPM during DPM Start Function!",
return -EINVAL);
PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
- udelay(10);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
+
+ if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
+ udelay(10);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
+ } else {
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
+ udelay(10);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
+ }
}
return 0;
@@ -993,11 +989,15 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
data->soft_regs_start +
- smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters,
+ smum_get_offsetof(hwmgr, SMU_SoftRegisters,
VoltageChangeTimeout), 0x1000);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
SWRST_COMMAND_1, RESETLC, 0x0);
+ if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
+ cgs_write_register(hwmgr->device, 0x1488,
+ (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
+
if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
pr_err("Failed to enable Sclk DPM and Mclk DPM!");
return -EINVAL;
@@ -1006,7 +1006,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
/* enable PCIE dpm */
if (0 == data->pcie_dpm_key_disabled) {
PP_ASSERT_WITH_CODE(
- (0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ (0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PCIeDPM_Enable)),
"Failed to enable pcie DPM during DPM Start Function!",
return -EINVAL);
@@ -1014,7 +1014,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_Falcon_QuickTransition)) {
- PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_EnableACDCGPIOInterrupt)),
"Failed to enable AC DC GPIO Interrupt!",
);
@@ -1032,7 +1032,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to disable SCLK DPM when DPM is disabled",
return 0);
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
}
/* disable MCLK dpm */
@@ -1040,7 +1040,7 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to disable MCLK DPM when DPM is disabled",
return 0);
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
}
return 0;
@@ -1060,7 +1060,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
/* disable PCIE dpm */
if (!data->pcie_dpm_key_disabled) {
PP_ASSERT_WITH_CODE(
- (smum_send_msg_to_smc(hwmgr->smumgr,
+ (smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PCIeDPM_Disable) == 0),
"Failed to disable pcie DPM during DPM Stop Function!",
return -EINVAL);
@@ -1072,7 +1072,7 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
"Trying to disable voltage DPM when DPM is disabled",
return 0);
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
return 0;
}
@@ -1226,7 +1226,7 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
- smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay);
+ smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
tmp_result = smu7_enable_sclk_control(hwmgr);
PP_ASSERT_WITH_CODE((0 == tmp_result),
@@ -1361,14 +1361,14 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->vddc_vddgfx_delta = 300;
data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
- data->voting_rights_clients0 = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
- data->voting_rights_clients1 = SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
- data->voting_rights_clients2 = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
- data->voting_rights_clients3 = SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
- data->voting_rights_clients4 = SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
- data->voting_rights_clients5 = SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
- data->voting_rights_clients6 = SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
- data->voting_rights_clients7 = SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
+ data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
+ data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
+ data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
+ data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
+ data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
+ data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
+ data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
+ data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
@@ -1382,23 +1382,40 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->force_pcie_gen = PP_PCIEGenInvalid;
data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
- if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) {
+ if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
uint8_t tmp1, tmp2;
uint16_t tmp3 = 0;
atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
&tmp3);
tmp3 = (tmp3 >> 5) & 0x3;
data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
+ } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
+ data->vddc_phase_shed_control = 1;
+ } else {
+ data->vddc_phase_shed_control = 0;
+ }
+
+ if (hwmgr->chip_id == CHIP_HAWAII) {
+ data->thermal_temp_setting.temperature_low = 94500;
+ data->thermal_temp_setting.temperature_high = 95000;
+ data->thermal_temp_setting.temperature_shutdown = 104000;
+ } else {
+ data->thermal_temp_setting.temperature_low = 99500;
+ data->thermal_temp_setting.temperature_high = 100000;
+ data->thermal_temp_setting.temperature_shutdown = 104000;
}
data->fast_watermark_threshold = 100;
- if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+ if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
+ else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
+ VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
+ data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ControlVDDGFX)) {
- if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+ if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
}
@@ -1406,25 +1423,24 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableMVDDControl)) {
- if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+ if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
- else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+ else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
}
- if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ControlVDDGFX);
- }
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ControlVDDCI)) {
- if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+ if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
- else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+ else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
}
@@ -1543,7 +1559,7 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
if (vddc >= 2000 || vddc == 0)
return -EINVAL;
} else {
- pr_warn("failed to retrieving EVV voltage!\n");
+ pr_debug("failed to retrieving EVV voltage!\n");
continue;
}
@@ -1676,7 +1692,7 @@ static int phm_add_voltage(struct pp_hwmgr *hwmgr,
PP_ASSERT_WITH_CODE((0 != look_up_table->count),
"Lookup Table empty.", return -EINVAL);
- i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);
+ i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
PP_ASSERT_WITH_CODE((i >= look_up_table->count),
"Lookup Table is full.", return -EINVAL);
@@ -2274,7 +2290,7 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
}
- if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count > 1)
+ if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
return 0;
@@ -2282,40 +2298,65 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
- kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
- hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
- }
- pp_smu7_thermal_fini(hwmgr);
- if (NULL != hwmgr->backend) {
- kfree(hwmgr->backend);
- hwmgr->backend = NULL;
- }
+ kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
+ hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
+ kfree(hwmgr->backend);
+ hwmgr->backend = NULL;
return 0;
}
+static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
+{
+ uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ int i;
+
+ if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
+ for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
+ virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
+ if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
+ virtual_voltage_id,
+ efuse_voltage_id) == 0) {
+ if (vddc != 0 && vddc != virtual_voltage_id) {
+ data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
+ data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
+ data->vddc_leakage.count++;
+ }
+ if (vddci != 0 && vddci != virtual_voltage_id) {
+ data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
+ data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
+ data->vddci_leakage.count++;
+ }
+ }
+ }
+ }
+ return 0;
+}
+
static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data;
- int result;
+ int result = 0;
data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
hwmgr->backend = data;
- pp_smu7_thermal_initialize(hwmgr);
-
smu7_patch_voltage_workaround(hwmgr);
smu7_init_dpm_defaults(hwmgr);
/* Get leakage voltage based on leakage ID. */
- result = smu7_get_evv_voltages(hwmgr);
-
- if (result) {
- pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
- return -EINVAL;
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EVV)) {
+ result = smu7_get_evv_voltages(hwmgr);
+ if (result) {
+ pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
+ return -EINVAL;
+ }
+ } else {
+ smu7_get_elb_voltages(hwmgr);
}
if (hwmgr->pp_table_version == PP_TABLE_V1) {
@@ -2382,7 +2423,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
level++;
if (level)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel, level);
}
}
@@ -2395,7 +2436,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
level++;
if (level)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
(1 << level));
}
@@ -2409,7 +2450,7 @@ static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
level++;
if (level)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
(1 << level));
}
@@ -2428,14 +2469,14 @@ static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
if (!data->sclk_dpm_key_disabled) {
if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.sclk_dpm_enable_mask);
}
if (!data->mclk_dpm_key_disabled) {
if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.mclk_dpm_enable_mask);
}
@@ -2451,7 +2492,7 @@ static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
return -EINVAL;
if (!data->pcie_dpm_key_disabled) {
- smum_send_msg_to_smc(hwmgr->smumgr,
+ smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PCIeDPM_UnForceLevel);
}
@@ -2468,7 +2509,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr,
data->dpm_level_enable_mask.sclk_dpm_enable_mask);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
(1 << level));
@@ -2478,7 +2519,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr,
data->dpm_level_enable_mask.mclk_dpm_enable_mask);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
(1 << level));
}
@@ -2488,7 +2529,7 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
level = phm_get_lowest_enabled_level(hwmgr,
data->dpm_level_enable_mask.pcie_dpm_enable_mask);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel,
(level));
}
@@ -2572,51 +2613,16 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
uint32_t sclk_mask = 0;
uint32_t mclk_mask = 0;
uint32_t pcie_mask = 0;
- uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
- AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
-
- if (level == hwmgr->dpm_level)
- return ret;
-
- if (!(hwmgr->dpm_level & profile_mode_mask)) {
- /* enter profile mode, save current level, disable gfx cg*/
- if (level & profile_mode_mask) {
- hwmgr->saved_dpm_level = hwmgr->dpm_level;
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_UNGATE);
- }
- } else {
- /* exit profile mode, restore level, enable gfx cg*/
- if (!(level & profile_mode_mask)) {
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
- level = hwmgr->saved_dpm_level;
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_GATE);
- }
- }
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
ret = smu7_force_dpm_highest(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
ret = smu7_force_dpm_lowest(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
ret = smu7_unforce_dpm_levels(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
@@ -2625,26 +2631,23 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
if (ret)
return ret;
- hwmgr->dpm_level = level;
smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
-
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
- hwmgr->dpm_level = level;
- break;
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
default:
break;
}
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
- smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
- else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
- smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
-
- return 0;
+ if (!ret) {
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
+ }
+ return ret;
}
static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
@@ -2843,7 +2846,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
}
-static int smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
struct smu7_power_state *smu7_ps;
@@ -2865,7 +2868,7 @@ static int smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
[smu7_ps->performance_level_count-1].memory_clock;
}
-static int smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
struct smu7_power_state *smu7_ps;
@@ -3002,7 +3005,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
[smu7_power_state->performance_level_count++]);
PP_ASSERT_WITH_CODE(
- (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
+ (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
"Performance levels exceeds SMC limit!",
return -EINVAL);
@@ -3071,11 +3074,11 @@ static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
if (dep_mclk_table->entries[0].clk !=
data->vbios_boot_state.mclk_bootup_value)
- pr_err("Single MCLK entry VDDCI/MCLK dependency table "
+ pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
"does not match VBIOS boot MCLK level");
if (dep_mclk_table->entries[0].vddci !=
data->vbios_boot_state.vddci_bootup_value)
- pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
+ pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
"does not match VBIOS boot VDDCI level");
}
@@ -3166,7 +3169,7 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
data->highest_mclk = memory_clock;
PP_ASSERT_WITH_CODE(
- (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
+ (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
"Performance levels exceeds SMC limit!",
return -EINVAL);
@@ -3219,11 +3222,11 @@ static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
if (dep_mclk_table->entries[0].clk !=
data->vbios_boot_state.mclk_bootup_value)
- pr_err("Single MCLK entry VDDCI/MCLK dependency table "
+ pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
"does not match VBIOS boot MCLK level");
if (dep_mclk_table->entries[0].v !=
data->vbios_boot_state.vddci_bootup_value)
- pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
+ pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
"does not match VBIOS boot VDDCI level");
}
@@ -3312,14 +3315,14 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
struct pp_gpu_power *query)
{
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PmStatusLogStart),
"Failed to start pm status log!",
return -1);
msleep_interruptible(20);
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_PmStatusLogSample),
"Failed to sample pm status log!",
return -1);
@@ -3353,19 +3356,19 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
*((uint32_t *)value) = sclk;
*size = 4;
return 0;
case AMDGPU_PP_SENSOR_GFX_MCLK:
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
*((uint32_t *)value) = mclk;
*size = 4;
return 0;
case AMDGPU_PP_SENSOR_GPU_LOAD:
- offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
+ offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters,
AverageGraphicsActivity);
@@ -3532,7 +3535,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to freeze SCLK DPM when DPM is disabled",
);
- PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SCLKDPM_FreezeLevel),
"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
return -EINVAL);
@@ -3544,7 +3547,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to freeze MCLK DPM when DPM is disabled",
);
- PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_MCLKDPM_FreezeLevel),
"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
return -EINVAL);
@@ -3762,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to Unfreeze SCLK DPM when DPM is disabled",
);
- PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SCLKDPM_UnfreezeLevel),
"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
return -EINVAL);
@@ -3774,7 +3777,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
"Trying to Unfreeze MCLK DPM when DPM is disabled",
);
- PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SCLKDPM_UnfreezeLevel),
"Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
return -EINVAL);
@@ -3824,9 +3827,9 @@ static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
(PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
- return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
+ return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
}
static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
@@ -3899,10 +3902,7 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
- if (phm_is_hw_access_blocked(hwmgr))
- return 0;
-
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
}
@@ -3911,7 +3911,7 @@ smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
{
PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
- return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
+ return (smum_send_msg_to_smc(hwmgr, msg) == 0) ? 0 : -1;
}
static int
@@ -3974,12 +3974,12 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
+ data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters,
PreVBlankGap), 0x64);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
+ data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters,
VBlankTimeout),
(frame_time_in_us - pre_vbi_time_in_us));
@@ -4004,10 +4004,7 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
- if (phm_is_hw_access_blocked(hwmgr))
- return 0;
-
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
}
@@ -4249,21 +4246,21 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- if (hwmgr->dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
- AMD_DPM_FORCED_LEVEL_LOW |
- AMD_DPM_FORCED_LEVEL_HIGH))
+ if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
+ AMD_DPM_FORCED_LEVEL_LOW |
+ AMD_DPM_FORCED_LEVEL_HIGH))
return -EINVAL;
switch (type) {
case PP_SCLK:
if (!data->sclk_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
break;
case PP_MCLK:
if (!data->mclk_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
break;
@@ -4276,7 +4273,7 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
level++;
if (!data->pcie_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PCIeDPM_ForceLevel,
level);
break;
@@ -4300,7 +4297,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
switch (type) {
case PP_SCLK:
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
for (i = 0; i < sclk_table->count; i++) {
@@ -4316,7 +4313,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
(i == now) ? "*" : "");
break;
case PP_MCLK:
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
for (i = 0; i < mclk_table->count; i++) {
@@ -4353,31 +4350,27 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
return size;
}
-static int smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
+static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
{
- int result = 0;
-
switch (mode) {
case AMD_FAN_CTRL_NONE:
- result = smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
break;
case AMD_FAN_CTRL_MANUAL:
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl))
- result = smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
+ smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
break;
case AMD_FAN_CTRL_AUTO:
- result = smu7_fan_ctrl_set_static_mode(hwmgr, mode);
- if (!result)
- result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
+ if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
+ smu7_fan_ctrl_start_smc_fan_control(hwmgr);
break;
default:
break;
}
- return result;
}
-static int smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
+static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
{
return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
}
@@ -4606,7 +4599,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (sclk_mask) {
if (!data->sclk_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.
sclk_dpm_enable_mask &
@@ -4615,7 +4608,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (mclk_mask) {
if (!data->mclk_dpm_key_disabled)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
data->dpm_level_enable_mask.
mclk_dpm_enable_mask &
@@ -4627,8 +4620,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
{
- struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
if (smu_data == NULL)
return -EINVAL;
@@ -4640,19 +4632,60 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr->smumgr, PPSMC_MSG_EnableAvfs),
+ hwmgr, PPSMC_MSG_EnableAvfs),
"Failed to enable AVFS!",
return -EINVAL);
} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr->smumgr, PPSMC_MSG_DisableAvfs),
+ hwmgr, PPSMC_MSG_DisableAvfs),
"Failed to disable AVFS!",
return -EINVAL);
return 0;
}
+static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+ uint32_t virtual_addr_low,
+ uint32_t virtual_addr_hi,
+ uint32_t mc_addr_low,
+ uint32_t mc_addr_hi,
+ uint32_t size)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ data->soft_regs_start +
+ smum_get_offsetof(hwmgr,
+ SMU_SoftRegisters, DRAM_LOG_ADDR_H),
+ mc_addr_hi);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ data->soft_regs_start +
+ smum_get_offsetof(hwmgr,
+ SMU_SoftRegisters, DRAM_LOG_ADDR_L),
+ mc_addr_low);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ data->soft_regs_start +
+ smum_get_offsetof(hwmgr,
+ SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
+ virtual_addr_hi);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ data->soft_regs_start +
+ smum_get_offsetof(hwmgr,
+ SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
+ virtual_addr_low);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ data->soft_regs_start +
+ smum_get_offsetof(hwmgr,
+ SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
+ size);
+ return 0;
+}
+
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init,
.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4703,6 +4736,8 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.set_power_profile_state = smu7_set_power_profile_state,
.avfs_control = smu7_avfs_control,
.disable_smc_firmware_ctf = smu7_thermal_disable_alert,
+ .start_thermal_controller = smu7_start_thermal_controller,
+ .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index f221e17..e021154 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -182,14 +182,7 @@ struct smu7_hwmgr {
struct smu7_dpm_table dpm_table;
struct smu7_dpm_table golden_dpm_table;
- uint32_t voting_rights_clients0;
- uint32_t voting_rights_clients1;
- uint32_t voting_rights_clients2;
- uint32_t voting_rights_clients3;
- uint32_t voting_rights_clients4;
- uint32_t voting_rights_clients5;
- uint32_t voting_rights_clients6;
- uint32_t voting_rights_clients7;
+ uint32_t voting_rights_clients[8];
uint32_t static_screen_threshold_unit;
uint32_t static_screen_threshold;
uint32_t voltage_control;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 1dc31aa..85ca16a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -629,51 +629,38 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
uint32_t block_en = 0;
int32_t result = 0;
uint32_t didt_block;
- uint32_t data;
if (hwmgr->chip_id == CHIP_POLARIS11)
didt_block = Polaris11_DIDTBlock_Info;
else
didt_block = DIDTBlock_Info;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ? en : 0;
-
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
- data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((block_en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
+ block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0;
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_SQ_CTRL0, DIDT_CTRL_EN, block_en);
didt_block &= ~SQ_Enable_MASK;
didt_block |= block_en << SQ_Enable_SHIFT;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ? en : 0;
-
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
- data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((block_en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
+ block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0;
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_DB_CTRL0, DIDT_CTRL_EN, block_en);
didt_block &= ~DB_Enable_MASK;
didt_block |= block_en << DB_Enable_SHIFT;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ? en : 0;
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
- data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((block_en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
+ block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0;
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_TD_CTRL0, DIDT_CTRL_EN, block_en);
didt_block &= ~TD_Enable_MASK;
didt_block |= block_en << TD_Enable_SHIFT;
- block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping) ? en : 0;
-
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
- data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((block_en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
+ block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0;
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_TCP_CTRL0, DIDT_CTRL_EN, block_en);
didt_block &= ~TCP_Enable_MASK;
didt_block |= block_en << TCP_Enable_SHIFT;
-
if (enable)
- result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block);
+ result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block);
return result;
}
@@ -753,12 +740,13 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
if (result == 0)
num_se = sys_info.value;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
+ PP_CAP(PHM_PlatformCaps_DBRamping) ||
+ PP_CAP(PHM_PlatformCaps_TDRamping) ||
+ PP_CAP(PHM_PlatformCaps_TCPRamping)) {
cgs_enter_safe_mode(hwmgr->device, true);
+ cgs_lock_grbm_idx(hwmgr->device, true);
value = 0;
value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
for (count = 0; count < num_se; count++) {
@@ -775,7 +763,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
} else if (hwmgr->chip_id == CHIP_POLARIS11) {
result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
- if (hwmgr->smumgr->is_kicker)
+ if (hwmgr->is_kicker)
result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
else
result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
@@ -793,11 +781,12 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
if (hwmgr->chip_id == CHIP_POLARIS11) {
- result = smum_send_msg_to_smc(hwmgr->smumgr,
+ result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_EnableDpmDidt));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to enable DPM DIDT.", return result);
}
+ cgs_lock_grbm_idx(hwmgr->device, false);
cgs_enter_safe_mode(hwmgr->device, false);
}
@@ -808,10 +797,10 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
{
int result;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
+ PP_CAP(PHM_PlatformCaps_DBRamping) ||
+ PP_CAP(PHM_PlatformCaps_TDRamping) ||
+ PP_CAP(PHM_PlatformCaps_TCPRamping)) {
cgs_enter_safe_mode(hwmgr->device, true);
@@ -820,7 +809,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
"Post DIDT enable clock gating failed.",
return result);
if (hwmgr->chip_id == CHIP_POLARIS11) {
- result = smum_send_msg_to_smc(hwmgr->smumgr,
+ result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableDpmDidt));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to disable DPM DIDT.", return result);
@@ -836,10 +825,9 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
int result = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_CAC)) {
+ if (PP_CAP(PHM_PlatformCaps_CAC)) {
int smc_result;
- smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
+ smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_EnableCac));
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable CAC in SMC.", result = -1);
@@ -854,9 +842,8 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
int result = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_CAC) && data->cac_enabled) {
- int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
+ if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) {
+ int smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableCac));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable CAC in SMC.", result = -1);
@@ -872,7 +859,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PkgPwrSetLimit, n);
return 0;
}
@@ -880,7 +867,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
uint32_t target_tdp)
{
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
}
@@ -899,11 +886,9 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
else
cac_table = hwmgr->dyn_state.cac_dtp_table;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
-
+ if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->enable_tdc_limit_feature) {
- smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
+ smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_TDCLimitEnable));
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable TDCLimit in SMC.", result = -1;);
@@ -913,14 +898,13 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
}
if (data->enable_pkg_pwr_tracking_feature) {
- smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
+ smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable PkgPwrTracking in SMC.", result = -1;);
if (0 == smc_result) {
uint32_t default_limit =
(uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
-
data->power_containment_features |=
POWERCONTAINMENT_FEATURE_PkgPwrLimit;
@@ -937,14 +921,13 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
int result = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment) &&
- data->power_containment_features) {
+ if (PP_CAP(PHM_PlatformCaps_PowerContainment) &&
+ data->power_containment_features) {
int smc_result;
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_TDCLimit) {
- smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
+ smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_TDCLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable TDCLimit in SMC.",
@@ -953,7 +936,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_DTE) {
- smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
+ smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableDTE));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable DTE in SMC.",
@@ -962,7 +945,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
- smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
+ smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable PkgPwrTracking in SMC.",
@@ -987,16 +970,17 @@ int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
cac_table = table_info->cac_dtp_table;
else
cac_table = hwmgr->dyn_state.cac_dtp_table;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
+ if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
/* adjustment percentage has already been validated */
adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
hwmgr->platform_descriptor.TDPAdjustment :
(-1 * hwmgr->platform_descriptor.TDPAdjustment);
- /* SMC requested that target_tdp to be 7 bit fraction in DPM table
- * but message to be 8 bit fraction for messages
- */
- target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
+
+ if (hwmgr->chip_id > CHIP_TONGA)
+ target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
+ else
+ target_tdp = ((100 + adjust_percent) * (int)(cac_table->usConfigurableTDP * 256)) / 100;
+
result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index baddb56..d7aa643 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -37,9 +37,8 @@ int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
fan_speed_info->min_percent = 0;
fan_speed_info->max_percent = 100;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
- hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
+ if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
+ hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
fan_speed_info->supports_rpm_read = true;
fan_speed_info->supports_rpm_write = true;
fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
@@ -87,8 +86,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
uint32_t crystal_clock_freq;
if (hwmgr->thermal_controller.fanInfo.bNoFan ||
- (hwmgr->thermal_controller.fanInfo.
- ucTachometerPulsesPerRevolution == 0))
+ !hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
return -ENODEV;
tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
@@ -152,13 +150,11 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
int result;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
+ if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
- result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
+ result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_FanSpeedInTableIsRPM))
+ if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM);
@@ -169,12 +165,12 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
} else {
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
- result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
+ result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
}
if (!result && hwmgr->thermal_controller.
advanceFanControlParameters.ucTargetTemperature)
- result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanTemperatureTarget,
hwmgr->thermal_controller.
advanceFanControlParameters.ucTargetTemperature);
@@ -187,7 +183,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
{
hwmgr->fan_ctrl_enabled = false;
- return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
+ return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl);
}
/**
@@ -209,8 +205,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (speed > 100)
speed = 100;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
@@ -241,8 +236,7 @@ int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl)) {
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
if (!result)
result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
@@ -270,8 +264,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
return 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
crystal_clock_freq = smu7_get_xclk(hwmgr);
@@ -367,7 +360,7 @@ static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
*
* @param hwmgr The address of the hardware manager.
*/
-int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
+static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
{
uint32_t alert;
@@ -378,7 +371,7 @@ int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
CG_THERMAL_INT, THERM_INT_MASK, alert);
/* send message to SMU to enable internal thermal interrupts */
- return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable);
}
/**
@@ -396,7 +389,7 @@ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr)
CG_THERMAL_INT, THERM_INT_MASK, alert);
/* send message to SMU to disable internal thermal interrupts */
- return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
+ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable);
}
/**
@@ -423,16 +416,14 @@ int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
-static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
+static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
/* If the fantable setup has failed we could have disabled
* PHM_PlatformCaps_MicrocodeFanControl even after
* this function was included in the table.
* Make sure that we still think controlling the fan is OK.
*/
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl)) {
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
smu7_fan_ctrl_start_smc_fan_control(hwmgr);
smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
@@ -440,108 +431,34 @@ static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
return 0;
}
-/**
-* Set temperature range for high and low alerts
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from set temperature range routine
-*/
-static int tf_smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
+int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *range)
{
- struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
+ int ret = 0;
if (range == NULL)
return -EINVAL;
- return smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
-}
+ smu7_thermal_initialize(hwmgr);
+ ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
+ if (ret)
+ return -EINVAL;
+ smu7_thermal_enable_alert(hwmgr);
+ ret = smum_thermal_avfs_enable(hwmgr);
+ if (ret)
+ return -EINVAL;
-/**
-* Programs one-time setting registers
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from initialize thermal controller routine
-*/
-static int tf_smu7_thermal_initialize(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
-{
- return smu7_thermal_initialize(hwmgr);
-}
-
-/**
-* Enable high and low alerts
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from enable alert routine
-*/
-static int tf_smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
-{
- return smu7_thermal_enable_alert(hwmgr);
-}
-
-/**
-* Disable high and low alerts
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from disable alert routine
-*/
-static int tf_smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
-{
- return smu7_thermal_disable_alert(hwmgr);
-}
-
-static const struct phm_master_table_item
-phm_thermal_start_thermal_controller_master_list[] = {
- { .tableFunction = tf_smu7_thermal_initialize },
- { .tableFunction = tf_smu7_thermal_set_temperature_range },
- { .tableFunction = tf_smu7_thermal_enable_alert },
- { .tableFunction = smum_thermal_avfs_enable },
/* We should restrict performance levels to low before we halt the SMC.
* On the other hand we are still in boot state when we do this
* so it would be pointless.
* If this assumption changes we have to revisit this table.
*/
- { .tableFunction = smum_thermal_setup_fan_table },
- { .tableFunction = tf_smu7_thermal_start_smc_fan_control },
- { }
-};
+ smum_thermal_setup_fan_table(hwmgr);
+ smu7_thermal_start_smc_fan_control(hwmgr);
+ return 0;
+}
-static const struct phm_master_table_header
-phm_thermal_start_thermal_controller_master = {
- 0,
- PHM_MasterTableFlag_None,
- phm_thermal_start_thermal_controller_master_list
-};
-static const struct phm_master_table_item
-phm_thermal_set_temperature_range_master_list[] = {
- { .tableFunction = tf_smu7_thermal_disable_alert },
- { .tableFunction = tf_smu7_thermal_set_temperature_range },
- { .tableFunction = tf_smu7_thermal_enable_alert },
- { }
-};
-
-static const struct phm_master_table_header
-phm_thermal_set_temperature_range_master = {
- 0,
- PHM_MasterTableFlag_None,
- phm_thermal_set_temperature_range_master_list
-};
int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
{
@@ -550,35 +467,3 @@ int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
return 0;
}
-/**
-* Initializes the thermal controller related functions in the Hardware Manager structure.
-* @param hwmgr The address of the hardware manager.
-* @exception Any error code from the low-level communication.
-*/
-int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
-{
- int result;
-
- result = phm_construct_table(hwmgr,
- &phm_thermal_set_temperature_range_master,
- &(hwmgr->set_temperature_range));
-
- if (!result) {
- result = phm_construct_table(hwmgr,
- &phm_thermal_start_thermal_controller_master,
- &(hwmgr->start_thermal_controller));
- if (result)
- phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
- }
-
- if (!result)
- hwmgr->fan_ctrl_is_in_default_mode = true;
- return result;
-}
-
-void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr)
-{
- phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
- phm_destroy_table(hwmgr, &(hwmgr->start_thermal_controller));
- return;
-}
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
index ba71b60..42c1ba0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h
@@ -46,14 +46,13 @@ extern int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-extern int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr);
-extern void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr);
extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
extern int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
-extern int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr);
extern int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr);
extern int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *temperature_range);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f8f02e7..4f79c21 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -56,7 +56,7 @@
#define HBM_MEMORY_CHANNEL_WIDTH 128
-uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
+static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
#define MEM_FREQ_LOW_LATENCY 25000
#define MEM_FREQ_HIGH_LATENCY 80000
@@ -81,7 +81,7 @@ uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
-const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
+static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
struct vega10_power_state *cast_phw_vega10_power_state(
struct pp_hw_power_state *hw_ps)
@@ -201,9 +201,6 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_ControlVDDCI);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_TablelessHardwareInterface);
-
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableSMU7ThermalManagement);
sys_info.size = sizeof(struct cgs_system_info);
@@ -381,12 +378,10 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
if (!data->registry_data.socclk_dpm_key_disabled)
data->smu_features[GNLD_DPM_SOCCLK].supported = true;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDDPM))
+ if (PP_CAP(PHM_PlatformCaps_UVDDPM))
data->smu_features[GNLD_DPM_UVD].supported = true;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_VCEDPM))
+ if (PP_CAP(PHM_PlatformCaps_VCEDPM))
data->smu_features[GNLD_DPM_VCE].supported = true;
if (!data->registry_data.pcie_dpm_key_disabled)
@@ -395,9 +390,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
if (!data->registry_data.dcefclk_dpm_key_disabled)
data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkDeepSleep) &&
- data->registry_data.sclk_deep_sleep_support) {
+ if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
+ data->registry_data.sclk_deep_sleep_support) {
data->smu_features[GNLD_DS_GFXCLK].supported = true;
data->smu_features[GNLD_DS_SOCCLK].supported = true;
data->smu_features[GNLD_DS_LCLK].supported = true;
@@ -431,8 +425,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
if (data->registry_data.vr0hot_enabled)
data->smu_features[GNLD_VR0HOT].supported = true;
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetSmuVersion);
- vega10_read_arg_from_smc(hwmgr->smumgr, &(data->smu_version));
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
+ vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
/* ACG firmware has major version 5 */
if ((data->smu_version & 0xff000000) == 0x5000000)
data->smu_features[GNLD_ACG].supported = true;
@@ -497,8 +491,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
if (!vega10_get_socclk_for_voltage_evv(hwmgr,
table_info->vddc_lookup_table, vv_id, &sclk)) {
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ClockStretcher)) {
+ if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
for (j = 1; j < socclk_table->count; j++) {
if (socclk_table->entries[j].clk == sclk &&
socclk_table->entries[j].cks_enable == 0) {
@@ -591,61 +584,37 @@ static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
static int vega10_patch_voltage_dependency_tables_with_lookup_table(
struct pp_hwmgr *hwmgr)
{
- uint8_t entry_id;
- uint8_t voltage_id;
+ uint8_t entry_id, voltage_id;
+ unsigned i;
struct phm_ppt_v2_information *table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
- struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
- table_info->vdd_dep_on_socclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *gfxclk_table =
- table_info->vdd_dep_on_sclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *dcefclk_table =
- table_info->vdd_dep_on_dcefclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *pixclk_table =
- table_info->vdd_dep_on_pixclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *dspclk_table =
- table_info->vdd_dep_on_dispclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *phyclk_table =
- table_info->vdd_dep_on_phyclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
- table_info->vdd_dep_on_mclk;
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
table_info->mm_dep_table;
+ struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
+ table_info->vdd_dep_on_mclk;
- for (entry_id = 0; entry_id < socclk_table->count; entry_id++) {
- voltage_id = socclk_table->entries[entry_id].vddInd;
- socclk_table->entries[entry_id].vddc =
- table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
+ for (i = 0; i < 6; i++) {
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
+ switch (i) {
+ case 0: vdt = table_info->vdd_dep_on_socclk; break;
+ case 1: vdt = table_info->vdd_dep_on_sclk; break;
+ case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
+ case 3: vdt = table_info->vdd_dep_on_pixclk; break;
+ case 4: vdt = table_info->vdd_dep_on_dispclk; break;
+ case 5: vdt = table_info->vdd_dep_on_phyclk; break;
+ }
+
+ for (entry_id = 0; entry_id < vdt->count; entry_id++) {
+ voltage_id = vdt->entries[entry_id].vddInd;
+ vdt->entries[entry_id].vddc =
+ table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
+ }
}
- for (entry_id = 0; entry_id < gfxclk_table->count; entry_id++) {
- voltage_id = gfxclk_table->entries[entry_id].vddInd;
- gfxclk_table->entries[entry_id].vddc =
- table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
- }
-
- for (entry_id = 0; entry_id < dcefclk_table->count; entry_id++) {
- voltage_id = dcefclk_table->entries[entry_id].vddInd;
- dcefclk_table->entries[entry_id].vddc =
- table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
- }
-
- for (entry_id = 0; entry_id < pixclk_table->count; entry_id++) {
- voltage_id = pixclk_table->entries[entry_id].vddInd;
- pixclk_table->entries[entry_id].vddc =
- table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
- }
-
- for (entry_id = 0; entry_id < dspclk_table->count; entry_id++) {
- voltage_id = dspclk_table->entries[entry_id].vddInd;
- dspclk_table->entries[entry_id].vddc =
- table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
- }
-
- for (entry_id = 0; entry_id < phyclk_table->count; entry_id++) {
- voltage_id = phyclk_table->entries[entry_id].vddInd;
- phyclk_table->entries[entry_id].vddc =
- table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
+ for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
+ voltage_id = mm_table->entries[entry_id].vddcInd;
+ mm_table->entries[entry_id].vddc =
+ table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
}
for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
@@ -660,11 +629,6 @@ static int vega10_patch_voltage_dependency_tables_with_lookup_table(
table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
}
- for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
- voltage_id = mm_table->entries[entry_id].vddcInd;
- mm_table->entries[entry_id].vddc =
- table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
- }
return 0;
@@ -838,8 +802,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
}
/* VDDCI_MEM */
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ControlVDDCI)) {
+ if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
@@ -959,7 +922,7 @@ static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
{
uint32_t features_enabled;
- if (!vega10_get_smc_features(hwmgr->smumgr, &features_enabled)) {
+ if (!vega10_get_smc_features(hwmgr, &features_enabled)) {
if (features_enabled & SMC_DPM_FEATURES)
return true;
}
@@ -1198,6 +1161,8 @@ static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
{
int i;
+ dpm_table->count = 0;
+
for (i = 0; i < dep_table->count; i++) {
if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
dep_table->entries[i].clk) {
@@ -1306,10 +1271,6 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
return -EINVAL);
/* Initialize Sclk DPM table based on allow Sclk values */
- data->dpm_table.soc_table.count = 0;
- data->dpm_table.gfx_table.count = 0;
- data->dpm_table.dcef_table.count = 0;
-
dpm_table = &(data->dpm_table.soc_table);
vega10_setup_default_single_dpm_table(hwmgr,
dpm_table,
@@ -1411,10 +1372,8 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
memcpy(&(data->golden_dpm_table), &(data->dpm_table),
sizeof(struct vega10_dpm_table));
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODNinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODNinDCSupport)) {
+ if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
+ PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
data->odn_dpm_table.odn_core_clock_dpm_levels.
number_of_performance_levels = data->dpm_table.gfx_table.count;
for (i = 0; i < data->dpm_table.gfx_table.count; i++) {
@@ -1848,6 +1807,10 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
mem_channels = (cgs_read_register(hwmgr->device, reg) &
DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
+ PP_ASSERT_WITH_CODE(mem_channels < ARRAY_SIZE(channel_number),
+ "Mem Channel Index Exceeded maximum!",
+ return -1);
+
pp_table->NumMemoryChannels = cpu_to_le16(mem_channels);
pp_table->MemoryChannelWidth =
cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH *
@@ -2311,21 +2274,21 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
uint32_t agc_btc_response;
if (data->smu_features[GNLD_ACG].supported) {
- if (0 == vega10_enable_smc_features(hwmgr->smumgr, true,
+ if (0 == vega10_enable_smc_features(hwmgr, true,
data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_InitializeAcg);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgBtc);
- vega10_read_arg_from_smc(hwmgr->smumgr, &agc_btc_response);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
+ vega10_read_arg_from_smc(hwmgr, &agc_btc_response);
if (1 == agc_btc_response) {
if (1 == data->acg_loop_state)
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInClosedLoop);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
else if (2 == data->acg_loop_state)
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInOpenLoop);
- if (0 == vega10_enable_smc_features(hwmgr->smumgr, true,
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
+ if (0 == vega10_enable_smc_features(hwmgr, true,
data->smu_features[GNLD_ACG].smu_feature_bitmap))
data->smu_features[GNLD_ACG].enabled = true;
} else {
@@ -2342,13 +2305,11 @@ static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
struct vega10_hwmgr *data =
(struct vega10_hwmgr *)(hwmgr->backend);
- if (data->smu_features[GNLD_ACG].supported) {
- if (data->smu_features[GNLD_ACG].enabled) {
- if (0 == vega10_enable_smc_features(hwmgr->smumgr, false,
- data->smu_features[GNLD_ACG].smu_feature_bitmap))
+ if (data->smu_features[GNLD_ACG].supported &&
+ data->smu_features[GNLD_ACG].enabled)
+ if (!vega10_enable_smc_features(hwmgr, false,
+ data->smu_features[GNLD_ACG].smu_feature_bitmap))
data->smu_features[GNLD_ACG].enabled = false;
- }
- }
return 0;
}
@@ -2363,9 +2324,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
if (!result) {
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot) &&
- (data->registry_data.regulator_hot_gpio_support)) {
+ if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
+ data->registry_data.regulator_hot_gpio_support) {
pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
@@ -2377,9 +2337,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
pp_table->VR1HotPolarity = 0;
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition) &&
- (data->registry_data.ac_dc_switch_gpio_support)) {
+ if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
+ data->registry_data.ac_dc_switch_gpio_support) {
pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
} else {
@@ -2398,16 +2357,16 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
if (data->smu_features[GNLD_AVFS].supported) {
if (enable) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_AVFS].smu_feature_bitmap),
"[avfs_control] Attempt to Enable AVFS feature Failed!",
return -1);
data->smu_features[GNLD_AVFS].enabled = true;
} else {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false,
- data->smu_features[GNLD_AVFS].smu_feature_id),
+ data->smu_features[GNLD_AVFS].smu_feature_bitmap),
"[avfs_control] Attempt to Disable AVFS feature Failed!",
return -1);
data->smu_features[GNLD_AVFS].enabled = false;
@@ -2428,15 +2387,15 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumTop32);
- vega10_read_arg_from_smc(hwmgr->smumgr, &top32);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
+ vega10_read_arg_from_smc(hwmgr, &top32);
- smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumBottom32);
- vega10_read_arg_from_smc(hwmgr->smumgr, &bottom32);
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
+ vega10_read_arg_from_smc(hwmgr, &bottom32);
serial_number = ((uint64_t)bottom32 << 32) | top32;
- if (pp_override_get_default_fuse_value(serial_number, vega10_fuses_default, &fuse) == 0) {
+ if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
avfs_fuse_table->VFT0_b = fuse.VFT0_b;
avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
@@ -2446,7 +2405,7 @@ static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
avfs_fuse_table->VFT2_b = fuse.VFT2_b;
avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
- result = vega10_copy_table_to_smc(hwmgr->smumgr,
+ result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)avfs_fuse_table, AVFSFUSETABLE);
PP_ASSERT_WITH_CODE(!result,
"Failed to upload FuseOVerride!",
@@ -2585,14 +2544,14 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
if (0 != boot_up_values.usVddc) {
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFloorSocVoltage,
(boot_up_values.usVddc * 4));
data->vbios_boot_state.bsoc_vddc_lock = true;
} else {
data->vbios_boot_state.bsoc_vddc_lock = false;
}
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk,
(uint32_t)(data->vbios_boot_state.dcef_clock / 100));
}
@@ -2618,7 +2577,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
vega10_populate_and_upload_avfs_fuse_override(hwmgr);
- result = vega10_copy_table_to_smc(hwmgr->smumgr,
+ result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)pp_table, PPTABLE);
PP_ASSERT_WITH_CODE(!result,
"Failed to upload PPtable!", return result);
@@ -2641,7 +2600,7 @@ static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
pr_info("THERMAL Feature Already enabled!");
PP_ASSERT_WITH_CODE(
- !vega10_enable_smc_features(hwmgr->smumgr,
+ !vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
"Enable THERMAL Feature Failed!",
@@ -2661,7 +2620,7 @@ static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
pr_info("THERMAL Feature Already disabled!");
PP_ASSERT_WITH_CODE(
- !vega10_enable_smc_features(hwmgr->smumgr,
+ !vega10_enable_smc_features(hwmgr,
false,
data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
"disable THERMAL Feature Failed!",
@@ -2677,11 +2636,10 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
struct vega10_hwmgr *data =
(struct vega10_hwmgr *)(hwmgr->backend);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot)) {
+ if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
if (data->smu_features[GNLD_VR0HOT].supported) {
PP_ASSERT_WITH_CODE(
- !vega10_enable_smc_features(hwmgr->smumgr,
+ !vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
"Attempt to Enable VR0 Hot feature Failed!",
@@ -2690,7 +2648,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
} else {
if (data->smu_features[GNLD_VR1HOT].supported) {
PP_ASSERT_WITH_CODE(
- !vega10_enable_smc_features(hwmgr->smumgr,
+ !vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
"Attempt to Enable VR0 Hot feature Failed!",
@@ -2708,7 +2666,7 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.ulv_support) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
"Enable ULV Feature Failed!",
return -1);
@@ -2724,7 +2682,7 @@ static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.ulv_support) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
"disable ULV Feature Failed!",
return -EINVAL);
@@ -2740,7 +2698,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DS_GFXCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
"Attempt to Enable DS_GFXCLK Feature Failed!",
return -EINVAL);
@@ -2748,7 +2706,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
}
if (data->smu_features[GNLD_DS_SOCCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
"Attempt to Enable DS_SOCCLK Feature Failed!",
return -EINVAL);
@@ -2756,7 +2714,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
}
if (data->smu_features[GNLD_DS_LCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
"Attempt to Enable DS_LCLK Feature Failed!",
return -EINVAL);
@@ -2764,7 +2722,7 @@ static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
}
if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
"Attempt to Enable DS_DCEFCLK Feature Failed!",
return -EINVAL);
@@ -2780,7 +2738,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DS_GFXCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
"Attempt to disable DS_GFXCLK Feature Failed!",
return -EINVAL);
@@ -2788,7 +2746,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
}
if (data->smu_features[GNLD_DS_SOCCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
"Attempt to disable DS_ Feature Failed!",
return -EINVAL);
@@ -2796,7 +2754,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
}
if (data->smu_features[GNLD_DS_LCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
"Attempt to disable DS_LCLK Feature Failed!",
return -EINVAL);
@@ -2804,7 +2762,7 @@ static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
}
if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
"Attempt to disable DS_DCEFCLK Feature Failed!",
return -EINVAL);
@@ -2822,7 +2780,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
"Attempt to disable LED DPM feature failed!", return -EINVAL);
data->smu_features[GNLD_LED_DISPLAY].enabled = false;
@@ -2840,7 +2798,7 @@ static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
}
}
- vega10_enable_smc_features(hwmgr->smumgr, false, feature_mask);
+ vega10_enable_smc_features(hwmgr, false, feature_mask);
return 0;
}
@@ -2870,7 +2828,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
}
}
- if (vega10_enable_smc_features(hwmgr->smumgr,
+ if (vega10_enable_smc_features(hwmgr,
true, feature_mask)) {
for (i = 0; i < GNLD_DPM_MAX; i++) {
if (data->smu_features[i].smu_feature_bitmap &
@@ -2880,22 +2838,21 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
}
if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
"Attempt to Enable LED DPM feature Failed!", return -EINVAL);
data->smu_features[GNLD_LED_DISPLAY].enabled = true;
}
if (data->vbios_boot_state.bsoc_vddc_lock) {
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFloorSocVoltage, 0);
data->vbios_boot_state.bsoc_vddc_lock = false;
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_Falcon_QuickTransition)) {
+ if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
if (data->smu_features[GNLD_ACDC].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
"Attempt to Enable DS_GFXCLK Feature Failed!",
return -1);
@@ -2912,13 +2869,13 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
(struct vega10_hwmgr *)(hwmgr->backend);
int tmp_result, result = 0;
- tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
PP_ASSERT_WITH_CODE(!tmp_result,
"Failed to configure telemetry!",
return tmp_result);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_NumOfDisplays, 0);
tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1;
@@ -2926,6 +2883,15 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
"DPM is already running right , skipping re-enablement!",
return 0);
+ if ((data->smu_version == 0x001c2c00) ||
+ (data->smu_version == 0x001c2d00)) {
+ tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
+ PP_ASSERT_WITH_CODE(!tmp_result,
+ "Failed to set package power PID!",
+ return tmp_result);
+ }
+
tmp_result = vega10_construct_voltage_tables(hwmgr);
PP_ASSERT_WITH_CODE(!tmp_result,
"Failed to contruct voltage tables!",
@@ -2936,8 +2902,7 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
"Failed to initialize SMC table!",
result = tmp_result);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ThermalController)) {
+ if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
tmp_result = vega10_enable_thermal_protection(hwmgr);
PP_ASSERT_WITH_CODE(!tmp_result,
"Failed to enable thermal protection!",
@@ -3172,8 +3137,9 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState)) {
+ if (PP_CAP(PHM_PlatformCaps_StablePState)) {
+ stable_pstate_sclk_dpm_percentage =
+ data->registry_data.stable_pstate_sclk_dpm_percentage;
PP_ASSERT_WITH_CODE(
data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
@@ -3238,10 +3204,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
disable_mclk_switching_for_frame_lock = phm_cap_enabled(
hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
- disable_mclk_switching_for_vr = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_DisableMclkSwitchForVR);
- force_mclk_high = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ForceMclkHigh);
+ disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
+ force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
disable_mclk_switching = (info.display_count > 1) ||
disable_mclk_switching_for_frame_lock ||
@@ -3292,8 +3256,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
vega10_ps->performance_levels[1].mem_clock;
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState)) {
+ if (PP_CAP(PHM_PlatformCaps_StablePState)) {
for (i = 0; i < vega10_ps->performance_level_count; i++) {
vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
@@ -3325,10 +3288,8 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
data->need_update_dpm_table = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODNinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODNinDCSupport)) {
+ if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
+ PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
for (i = 0; i < sclk_table->count; i++) {
if (sclk == sclk_table->dpm_levels[i].value)
break;
@@ -3412,10 +3373,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
uint32_t dpm_count, clock_percent;
uint32_t i;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODNinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ODNinDCSupport)) {
+ if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
+ PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
if (!data->need_update_dpm_table &&
!data->apply_optimized_settings &&
@@ -3480,10 +3439,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->
gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
value = sclk;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_OD6PlusinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_OD6PlusinDCSupport)) {
+ if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
+ PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
/* Need to do calculation based on the golden DPM table
* as the Heatmap GPU Clock axis is also based on
* the default values
@@ -3537,10 +3494,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
mem_table.dpm_levels[dpm_table->mem_table.count - 1].
value = mclk;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_OD6PlusinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_OD6PlusinDCSupport)) {
+ if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
+ PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
PP_ASSERT_WITH_CODE(
golden_dpm_table->mem_table.dpm_levels
@@ -3732,7 +3687,7 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.gfx_boot_level !=
data->dpm_table.gfx_table.dpm_state.soft_min_level) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
+ hwmgr,
PPSMC_MSG_SetSoftMinGfxclkByIndex,
data->smc_state_table.gfx_boot_level),
"Failed to set soft min sclk index!",
@@ -3748,14 +3703,14 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
+ hwmgr,
PPSMC_MSG_SetSoftMinSocclkByIndex,
socclk_idx),
"Failed to set soft min uclk index!",
return -EINVAL);
} else {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
+ hwmgr,
PPSMC_MSG_SetSoftMinUclkByIndex,
data->smc_state_table.mem_boot_level),
"Failed to set soft min uclk index!",
@@ -3780,7 +3735,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.gfx_max_level !=
data->dpm_table.gfx_table.dpm_state.soft_max_level) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
+ hwmgr,
PPSMC_MSG_SetSoftMaxGfxclkByIndex,
data->smc_state_table.gfx_max_level),
"Failed to set soft max sclk index!",
@@ -3794,7 +3749,7 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
if (data->smc_state_table.mem_max_level !=
data->dpm_table.mem_table.dpm_state.soft_max_level) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
+ hwmgr,
PPSMC_MSG_SetSoftMaxUclkByIndex,
data->smc_state_table.mem_max_level),
"Failed to set soft max mclk index!",
@@ -3853,7 +3808,7 @@ int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DPM_VCE].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
enable,
data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
"Attempt to Enable/Disable DPM VCE Failed!",
@@ -3871,9 +3826,8 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
int result = 0;
uint32_t low_sclk_interrupt_threshold = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
+ if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
+ (hwmgr->gfx_arbiter.sclk_threshold !=
data->low_sclk_interrupt_threshold)) {
data->low_sclk_interrupt_threshold =
hwmgr->gfx_arbiter.sclk_threshold;
@@ -3884,7 +3838,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
cpu_to_le32(low_sclk_interrupt_threshold);
/* This message will also enable SmcToHost Interrupt */
- result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetLowGfxclkInterruptThreshold,
(uint32_t)low_sclk_interrupt_threshold);
}
@@ -3920,7 +3874,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
"Failed to update SCLK threshold!",
result = tmp_result);
- result = vega10_copy_table_to_smc(hwmgr->smumgr,
+ result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)pp_table, PPTABLE);
PP_ASSERT_WITH_CODE(!result,
"Failed to upload PPtable!", return result);
@@ -3931,7 +3885,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
return 0;
}
-static int vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
struct vega10_power_state *vega10_ps;
@@ -3953,7 +3907,7 @@ static int vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
[vega10_ps->performance_level_count - 1].gfx_clock;
}
-static int vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
struct pp_power_state *ps;
struct vega10_power_state *vega10_ps;
@@ -3980,12 +3934,12 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
{
uint32_t value;
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrPkgPwr),
"Failed to get current package power!",
return -EINVAL);
- vega10_read_arg_from_smc(hwmgr->smumgr, &value);
+ vega10_read_arg_from_smc(hwmgr, &value);
/* power value is an integer */
query->average_gpu_power = value << 8;
@@ -4002,25 +3956,25 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
- ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentGfxclkIndex);
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
if (!ret) {
- vega10_read_arg_from_smc(hwmgr->smumgr, &sclk_idx);
+ vega10_read_arg_from_smc(hwmgr, &sclk_idx);
*((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
*size = 4;
}
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
- ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentUclkIndex);
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
if (!ret) {
- vega10_read_arg_from_smc(hwmgr->smumgr, &mclk_idx);
+ vega10_read_arg_from_smc(hwmgr, &mclk_idx);
*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
*size = 4;
}
break;
case AMDGPU_PP_SENSOR_GPU_LOAD:
- ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetAverageGfxActivity, 0);
+ ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
if (!ret) {
- vega10_read_arg_from_smc(hwmgr->smumgr, &activity_percent);
+ vega10_read_arg_from_smc(hwmgr, &activity_percent);
*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
*size = 4;
}
@@ -4055,7 +4009,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
bool has_disp)
{
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetUclkFastSwitch,
has_disp ? 0 : 1);
}
@@ -4090,7 +4044,7 @@ int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
if (!result) {
clk_request = (clk_freq << 16) | clk_select;
- result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_RequestDisplayClockByFreq,
clk_request);
}
@@ -4160,7 +4114,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
+ hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
min_clocks.dcefClockInSR /100),
"Attempt to set divider for DCEFCLK Failed!",);
} else {
@@ -4172,7 +4126,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
if (min_clocks.memoryClock != 0) {
idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
+ smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
}
@@ -4275,28 +4229,23 @@ static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_fo
return 0;
}
-static int vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
+static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
{
- int result = 0;
-
switch (mode) {
case AMD_FAN_CTRL_NONE:
- result = vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
break;
case AMD_FAN_CTRL_MANUAL:
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
- result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
+ vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
break;
case AMD_FAN_CTRL_AUTO:
- result = vega10_fan_ctrl_set_static_mode(hwmgr, mode);
- if (!result)
- result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
+ vega10_fan_ctrl_start_smc_fan_control(hwmgr);
break;
default:
break;
}
- return result;
}
static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
@@ -4306,51 +4255,16 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
uint32_t sclk_mask = 0;
uint32_t mclk_mask = 0;
uint32_t soc_mask = 0;
- uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
- AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
-
- if (level == hwmgr->dpm_level)
- return ret;
-
- if (!(hwmgr->dpm_level & profile_mode_mask)) {
- /* enter profile mode, save current level, disable gfx cg*/
- if (level & profile_mode_mask) {
- hwmgr->saved_dpm_level = hwmgr->dpm_level;
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_UNGATE);
- }
- } else {
- /* exit profile mode, restore level, enable gfx cg*/
- if (!(level & profile_mode_mask)) {
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
- level = hwmgr->saved_dpm_level;
- cgs_set_clockgating_state(hwmgr->device,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_GATE);
- }
- }
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
ret = vega10_force_dpm_highest(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
ret = vega10_force_dpm_lowest(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
ret = vega10_unforce_dpm_levels(hwmgr);
- if (ret)
- return ret;
- hwmgr->dpm_level = level;
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
@@ -4359,27 +4273,25 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
if (ret)
return ret;
- hwmgr->dpm_level = level;
vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
- hwmgr->dpm_level = level;
- break;
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
default:
break;
}
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
- vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
- else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
- vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
-
- return 0;
+ if (!ret) {
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
+ else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
+ }
+ return ret;
}
-static int vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
+static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
{
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
@@ -4624,7 +4536,7 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
int i;
- if (hwmgr->dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
+ if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
AMD_DPM_FORCED_LEVEL_LOW |
AMD_DPM_FORCED_LEVEL_HIGH))
return -EINVAL;
@@ -4697,11 +4609,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
if (data->registry_data.sclk_dpm_key_disabled)
break;
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentGfxclkIndex),
"Attempt to get current sclk index Failed!",
return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
&now),
"Attempt to read sclk index Failed!",
return -1);
@@ -4715,11 +4627,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
if (data->registry_data.mclk_dpm_key_disabled)
break;
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentUclkIndex),
"Attempt to get current mclk index Failed!",
return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
&now),
"Attempt to read mclk index Failed!",
return -1);
@@ -4730,11 +4642,11 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
(i == now) ? "*" : "");
break;
case PP_PCIE:
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentLinkIndex),
"Attempt to get current mclk index Failed!",
return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
&now),
"Attempt to read mclk index Failed!",
return -1);
@@ -4762,7 +4674,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) {
- result = vega10_copy_table_to_smc(hwmgr->smumgr,
+ result = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)wm_table, WMTABLE);
PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded;
@@ -4771,7 +4683,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if (data->water_marks_bitmap & WaterMarksLoaded) {
cgs_get_active_displays_info(hwmgr->device, &info);
num_turned_on_displays = info.display_count;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
}
@@ -4784,7 +4696,7 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->smu_features[GNLD_DPM_UVD].supported) {
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
enable,
data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
"Attempt to Enable/Disable DPM UVD Failed!",
@@ -4794,20 +4706,20 @@ int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
return 0;
}
-static int vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
+static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
{
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
data->vce_power_gated = bgate;
- return vega10_enable_disable_vce_dpm(hwmgr, !bgate);
+ vega10_enable_disable_vce_dpm(hwmgr, !bgate);
}
-static int vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
+static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
data->uvd_power_gated = bgate;
- return vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
+ vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
}
static inline bool vega10_are_power_levels_equal(
@@ -4866,7 +4778,7 @@ vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmg
if (data->display_timing.num_existing_displays != info.display_count)
is_update_required = true;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
+ if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr)
is_update_required = true;
}
@@ -4883,8 +4795,7 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
"DPM is not running right now, no need to disable DPM!",
return 0);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ThermalController))
+ if (PP_CAP(PHM_PlatformCaps_ThermalController))
vega10_disable_thermal_protection(hwmgr);
tmp_result = vega10_disable_power_containment(hwmgr);
@@ -4972,7 +4883,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (!data->registry_data.sclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE(
!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
+ hwmgr,
PPSMC_MSG_SetSoftMinGfxclkByIndex,
sclk_idx),
"Failed to set soft min sclk index!",
@@ -4983,7 +4894,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
if (!data->registry_data.mclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE(
!smum_send_msg_to_smc_with_parameter(
- hwmgr->smumgr,
+ hwmgr,
PPSMC_MSG_SetSoftMinUclkByIndex,
mclk_idx),
"Failed to set soft min mclk index!",
@@ -5096,6 +5007,65 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
return 0;
}
+static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+ uint32_t virtual_addr_low,
+ uint32_t virtual_addr_hi,
+ uint32_t mc_addr_low,
+ uint32_t mc_addr_hi,
+ uint32_t size)
+{
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSystemVirtualDramAddrHigh,
+ virtual_addr_hi);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSystemVirtualDramAddrLow,
+ virtual_addr_low);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramLogSetDramAddrHigh,
+ mc_addr_hi);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramLogSetDramAddrLow,
+ mc_addr_low);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DramLogSetDramSize,
+ size);
+ return 0;
+}
+
+static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
+ const void *info)
+{
+ struct cgs_irq_src_funcs *irq_src =
+ (struct cgs_irq_src_funcs *)info;
+
+ if (hwmgr->thermal_controller.ucType ==
+ ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 ||
+ hwmgr->thermal_controller.ucType ==
+ ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
+ PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
+ 0xf, /* AMDGPU_IH_CLIENTID_THM */
+ 0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
+ "Failed to register high thermal interrupt!",
+ return -EINVAL);
+ PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
+ 0xf, /* AMDGPU_IH_CLIENTID_THM */
+ 1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
+ "Failed to register low thermal interrupt!",
+ return -EINVAL);
+ }
+
+ /* Register CTF(GPIO_19) interrupt */
+ PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
+ 0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */
+ 83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
+ "Failed to register CTF thermal interrupt!",
+ return -EINVAL);
+
+ return 0;
+}
+
static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.backend_init = vega10_hwmgr_backend_init,
.backend_fini = vega10_hwmgr_backend_fini,
@@ -5149,12 +5119,15 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.get_mclk_od = vega10_get_mclk_od,
.set_mclk_od = vega10_set_mclk_od,
.avfs_control = vega10_avfs_enable,
+ .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
+ .register_internal_thermal_interrupt = vega10_register_thermal_interrupt,
+ .start_thermal_controller = vega10_start_thermal_controller,
};
int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
{
hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
hwmgr->pptable_func = &vega10_pptable_funcs;
- pp_vega10_thermal_initialize(hwmgr);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 676cd77..b4b461c3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -31,7 +31,6 @@
#include "vega10_ppsmc.h"
#include "vega10_powertune.h"
-extern const uint32_t PhwVega10_Magic;
#define VEGA10_MAX_HARDWARE_POWERLEVELS 2
#define WaterMarksExist 1
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index e7fa670..598a194 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -854,99 +854,79 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
uint32_t en = (enable ? 1 : 0);
uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
- data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
+ if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
didt_block_info &= ~SQ_Enable_MASK;
didt_block_info |= en << SQ_Enable_SHIFT;
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
- data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
+ if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
didt_block_info &= ~DB_Enable_MASK;
didt_block_info |= en << DB_Enable_SHIFT;
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
- data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
+ if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
didt_block_info &= ~TD_Enable_MASK;
didt_block_info |= en << TD_Enable_SHIFT;
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
- data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
+ if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
didt_block_info &= ~TCP_Enable_MASK;
didt_block_info |= en << TCP_Enable_SHIFT;
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) {
- data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0);
- data &= ~DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK;
- data |= ((en << DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0, data);
+ if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
+ CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+ DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable)) {
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
+ if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
- data &= ~DIDT_SQ_EDC_CTRL__EDC_EN_MASK;
- data |= ((en << DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT) & DIDT_SQ_EDC_CTRL__EDC_EN_MASK);
- data &= ~DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK;
- data |= ((~en << DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK);
+ data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
+ data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
- data &= ~DIDT_DB_EDC_CTRL__EDC_EN_MASK;
- data |= ((en << DIDT_DB_EDC_CTRL__EDC_EN__SHIFT) & DIDT_DB_EDC_CTRL__EDC_EN_MASK);
- data &= ~DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK;
- data |= ((~en << DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK);
+ data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
+ data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
- data &= ~DIDT_TD_EDC_CTRL__EDC_EN_MASK;
- data |= ((en << DIDT_TD_EDC_CTRL__EDC_EN__SHIFT) & DIDT_TD_EDC_CTRL__EDC_EN_MASK);
- data &= ~DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK;
- data |= ((~en << DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK);
+ data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
+ data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
- data &= ~DIDT_TCP_EDC_CTRL__EDC_EN_MASK;
- data |= ((en << DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT) & DIDT_TCP_EDC_CTRL__EDC_EN_MASK);
- data &= ~DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK;
- data |= ((~en << DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK);
+ data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
+ data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) {
+ if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
- data &= ~DIDT_DBR_EDC_CTRL__EDC_EN_MASK;
- data |= ((en << DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT) & DIDT_DBR_EDC_CTRL__EDC_EN_MASK);
- data &= ~DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK;
- data |= ((~en << DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK);
+ data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
+ data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
}
}
if (enable) {
/* For Vega10, SMC does not support any mask yet. */
- result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
+ result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
}
}
@@ -1040,10 +1020,10 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
cgs_enter_safe_mode(hwmgr->device, false);
vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC))
+ if (PP_CAP(PHM_PlatformCaps_GCEDC))
vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
+ if (PP_CAP(PHM_PlatformCaps_PSM))
vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
return 0;
@@ -1059,12 +1039,12 @@ static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
cgs_enter_safe_mode(hwmgr->device, false);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
+ if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
data = 0x00000000;
cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
+ if (PP_CAP(PHM_PlatformCaps_PSM))
vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
return 0;
@@ -1159,12 +1139,12 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
+ if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
+ if (PP_CAP(PHM_PlatformCaps_PSM))
vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
return 0;
@@ -1180,12 +1160,12 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
cgs_enter_safe_mode(hwmgr->device, false);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
+ if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
data = 0x00000000;
cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
}
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
+ if (PP_CAP(PHM_PlatformCaps_PSM))
vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
return 0;
@@ -1263,8 +1243,8 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
}
if (0 == result) {
- PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
- "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
+ result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
+ PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
data->smu_features[GNLD_DIDT].enabled = true;
}
}
@@ -1310,8 +1290,8 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
}
if (0 == result) {
- PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
- "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
+ result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
+ PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
data->smu_features[GNLD_DIDT].enabled = false;
}
}
@@ -1364,7 +1344,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.enable_pkg_pwr_tracking_feature)
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetPptLimit, n);
return 0;
@@ -1381,16 +1361,15 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
(uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
int result = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
+ if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported)
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
"Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_PPT].supported = false);
if (data->smu_features[GNLD_TDC].supported)
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
"Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false);
@@ -1409,16 +1388,15 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
struct vega10_hwmgr *data =
(struct vega10_hwmgr *)(hwmgr->backend);
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
+ if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported)
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
"Attempt to disable PPT feature Failed!",
data->smu_features[GNLD_PPT].supported = false);
if (data->smu_features[GNLD_TDC].supported)
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
"Attempt to disable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false);
@@ -1430,7 +1408,7 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
uint32_t adjust_percent)
{
- return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
}
@@ -1438,8 +1416,7 @@ int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
{
int adjust_percent, result = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
+ if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
adjust_percent =
hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
hwmgr->platform_descriptor.TDPAdjustment :
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index e343df1..f14c761 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -291,8 +291,7 @@ static int get_mm_clock_voltage_table(
table_size = sizeof(uint32_t) +
sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) *
mm_dependency_table->ucNumEntries;
- mm_table = (phm_ppt_v1_mm_clock_voltage_dependency_table *)
- kzalloc(table_size, GFP_KERNEL);
+ mm_table = kzalloc(table_size, GFP_KERNEL);
if (!mm_table)
return -ENOMEM;
@@ -519,8 +518,7 @@ static int get_socclk_voltage_dependency_table(
sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
clk_dep_table->ucNumEntries;
- clk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
- kzalloc(table_size, GFP_KERNEL);
+ clk_table = kzalloc(table_size, GFP_KERNEL);
if (!clk_table)
return -ENOMEM;
@@ -554,8 +552,7 @@ static int get_mclk_voltage_dependency_table(
sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
mclk_dep_table->ucNumEntries;
- mclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
- kzalloc(table_size, GFP_KERNEL);
+ mclk_table = kzalloc(table_size, GFP_KERNEL);
if (!mclk_table)
return -ENOMEM;
@@ -596,8 +593,7 @@ static int get_gfxclk_voltage_dependency_table(
sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
clk_dep_table->ucNumEntries;
- clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
- kzalloc(table_size, GFP_KERNEL);
+ clk_table = kzalloc(table_size, GFP_KERNEL);
if (!clk_table)
return -ENOMEM;
@@ -663,8 +659,7 @@ static int get_pix_clk_voltage_dependency_table(
sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
clk_dep_table->ucNumEntries;
- clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
- kzalloc(table_size, GFP_KERNEL);
+ clk_table = kzalloc(table_size, GFP_KERNEL);
if (!clk_table)
return -ENOMEM;
@@ -728,8 +723,7 @@ static int get_dcefclk_voltage_dependency_table(
sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
num_entries;
- clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
- kzalloc(table_size, GFP_KERNEL);
+ clk_table = kzalloc(table_size, GFP_KERNEL);
if (!clk_table)
return -ENOMEM;
@@ -772,8 +766,7 @@ static int get_pcie_table(struct pp_hwmgr *hwmgr,
sizeof(struct phm_ppt_v1_pcie_record) *
atom_pcie_table->ucNumEntries;
- pcie_table = (struct phm_ppt_v1_pcie_table *)
- kzalloc(table_size, GFP_KERNEL);
+ pcie_table = kzalloc(table_size, GFP_KERNEL);
if (!pcie_table)
return -ENOMEM;
@@ -1026,10 +1019,9 @@ static int get_vddc_lookup_table(
table_size = sizeof(uint32_t) +
sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
- table = (phm_ppt_v1_voltage_lookup_table *)
- kzalloc(table_size, GFP_KERNEL);
+ table = kzalloc(table_size, GFP_KERNEL);
- if (NULL == table)
+ if (table == NULL)
return -ENOMEM;
table->count = vddc_lookup_pp_tables->ucNumEntries;
@@ -1138,12 +1130,12 @@ int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
- PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
+ PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
"Failed to allocate hwmgr->pptable!", return -ENOMEM);
powerplay_table = get_powerplay_table(hwmgr);
- PP_ASSERT_WITH_CODE((NULL != powerplay_table),
+ PP_ASSERT_WITH_CODE((powerplay_table != NULL),
"Missing PowerPlay Table!", return -1);
result = check_powerplay_tables(hwmgr, powerplay_table);
@@ -1182,7 +1174,6 @@ int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
{
- int result = 0;
struct phm_ppt_v2_information *pp_table_info =
(struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -1225,7 +1216,7 @@ static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
kfree(hwmgr->pptable);
hwmgr->pptable = NULL;
- return result;
+ return 0;
}
const struct pp_table_func vega10_pptable_funcs = {
@@ -1238,7 +1229,7 @@ int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
const ATOM_Vega10_State_Array *state_arrays;
const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
- PP_ASSERT_WITH_CODE((NULL != pp_table),
+ PP_ASSERT_WITH_CODE((pp_table != NULL),
"Missing PowerPlay Table!", return -1);
PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
ATOM_Vega10_TABLE_REVISION_VEGA10),
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index d442434..dc3761b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -31,11 +31,11 @@
static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
{
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentRpm),
"Attempt to get current RPM from SMC Failed!",
return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
current_rpm),
"Attempt to read current RPM from SMC Failed!",
return -1);
@@ -54,8 +54,7 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
fan_speed_info->min_percent = 0;
fan_speed_info->max_percent = 100;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
+ if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
hwmgr->thermal_controller.fanInfo.
ucTachometerPulsesPerRevolution) {
fan_speed_info->supports_rpm_read = true;
@@ -105,14 +104,15 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return -1;
- if (data->smu_features[GNLD_FAN_CONTROL].supported)
+ if (data->smu_features[GNLD_FAN_CONTROL].supported) {
result = vega10_get_current_rpm(hwmgr, speed);
- else {
+ } else {
uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
- tach_period = (cgs_read_register(hwmgr->device,
- reg) & CG_TACH_STATUS__TACH_PERIOD_MASK) >>
- CG_TACH_STATUS__TACH_PERIOD__SHIFT;
+ tach_period =
+ CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_TACH_STATUS,
+ TACH_PERIOD);
if (tach_period == 0)
return -EINVAL;
@@ -141,23 +141,20 @@ int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
if (hwmgr->fan_ctrl_is_in_default_mode) {
hwmgr->fan_ctrl_default_mode =
- (cgs_read_register(hwmgr->device, reg) &
- CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
- CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
- hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
- CG_FDO_CTRL2__TMIN_MASK) >>
- CG_FDO_CTRL2__TMIN__SHIFT;
+ CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL2, FDO_PWM_MODE);
+ hwmgr->tmin =
+ CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL2, TMIN);
hwmgr->fan_ctrl_is_in_default_mode = false;
}
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_FDO_CTRL2__TMIN_MASK) |
- (0 << CG_FDO_CTRL2__TMIN__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL2, TMIN, 0));
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
- (mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL2, FDO_PWM_MODE, mode));
return 0;
}
@@ -176,14 +173,13 @@ int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
if (!hwmgr->fan_ctrl_is_in_default_mode) {
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
- (hwmgr->fan_ctrl_default_mode <<
- CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL2, FDO_PWM_MODE,
+ hwmgr->fan_ctrl_default_mode));
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_FDO_CTRL2__TMIN_MASK) |
- (hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL2, TMIN,
+ hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
hwmgr->fan_ctrl_is_in_default_mode = true;
}
@@ -203,7 +199,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
- hwmgr->smumgr, true,
+ hwmgr, true,
data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!",
@@ -220,7 +216,7 @@ static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
- hwmgr->smumgr, false,
+ hwmgr, false,
data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!",
@@ -279,16 +275,14 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (speed > 100)
speed = 100;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
- duty100 = (cgs_read_register(hwmgr->device, reg) &
- CG_FDO_CTRL1__FMAX_DUTY100_MASK) >>
- CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
+ duty100 = CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL1, FMAX_DUTY100);
if (duty100 == 0)
return -EINVAL;
@@ -300,9 +294,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) |
- (duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
@@ -314,18 +307,13 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
*/
int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
{
- int result;
-
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl)) {
- result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
- } else
- result = vega10_fan_ctrl_set_default_mode(hwmgr);
-
- return result;
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
+ return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
+ else
+ return vega10_fan_ctrl_set_default_mode(hwmgr);
}
/**
@@ -342,12 +330,11 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
uint32_t reg;
if (hwmgr->thermal_controller.fanInfo.bNoFan ||
- (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
- (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
+ (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
+ (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
return -1;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
if (!result) {
@@ -356,9 +343,9 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_TACH_STATUS__TACH_PERIOD_MASK) |
- (tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_TACH_STATUS, TACH_PERIOD,
+ tach_period));
}
return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
}
@@ -374,12 +361,12 @@ int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
uint32_t reg;
reg = soc15_get_register_offset(THM_HWID, 0,
- mmCG_TACH_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS);
+ mmCG_MULT_THERMAL_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS);
temp = cgs_read_register(hwmgr->device, reg);
- temp = (temp & CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK) >>
- CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT;
+ temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
+ CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
temp = temp & 0x1ff;
@@ -418,20 +405,10 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
val = cgs_read_register(hwmgr->device, reg);
- val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
- val |= (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
-
- val &= (~THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK);
- val |= (1 << THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT);
-
- val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
- val |= ((high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
- << THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT);
-
- val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
- val |= ((low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
- << THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
-
+ val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
+ val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
+ val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+ val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
cgs_write_register(hwmgr->device, reg, val);
@@ -452,19 +429,16 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
- ((hwmgr->thermal_controller.fanInfo.
- ucTachometerPulsesPerRevolution - 1) <<
- CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_TACH_CTRL, EDGE_PER_REV,
+ hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
}
reg = soc15_get_register_offset(THM_HWID, 0,
mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
cgs_write_register(hwmgr->device, reg,
- (cgs_read_register(hwmgr->device, reg) &
- ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) |
- (0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
+ CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+ CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
return 0;
}
@@ -484,7 +458,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FW_CTF].enabled)
printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to Enable FW CTF feature Failed!",
@@ -516,7 +490,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
- PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to disable FW CTF feature Failed!",
@@ -554,8 +528,7 @@ int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
-int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
+int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
{
int ret;
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
@@ -573,7 +546,7 @@ int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
table->FanTargetTemperature = hwmgr->thermal_controller.
advanceFanControlParameters.usTMax;
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanTemperatureTarget,
(uint32_t)table->FanTargetTemperature);
@@ -602,7 +575,7 @@ int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
table->FanStartTemp = hwmgr->thermal_controller.
advanceFanControlParameters.usZeroRPMStartTemperature;
- ret = vega10_copy_table_to_smc(hwmgr->smumgr,
+ ret = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
if (ret)
pr_info("Failed to update Fan Control Table in PPTable!");
@@ -619,123 +592,50 @@ int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
* @param Result the last failure code
* @return result from set temperature range routine
*/
-int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
+int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
/* If the fantable setup has failed we could have disabled
* PHM_PlatformCaps_MicrocodeFanControl even after
* this function was included in the table.
* Make sure that we still think controlling the fan is OK.
*/
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl)) {
+ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega10_fan_ctrl_start_smc_fan_control(hwmgr);
- }
return 0;
}
-/**
-* Set temperature range for high and low alerts
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from set temperature range routine
-*/
-int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
+
+int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *range)
{
- struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
+ int ret = 0;
if (range == NULL)
return -EINVAL;
- return vega10_thermal_set_temperature_range(hwmgr, range);
-}
+ vega10_thermal_initialize(hwmgr);
+ ret = vega10_thermal_set_temperature_range(hwmgr, range);
+ if (ret)
+ return -EINVAL;
-/**
-* Programs one-time setting registers
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from initialize thermal controller routine
-*/
-int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
-{
- return vega10_thermal_initialize(hwmgr);
-}
-
-/**
-* Enable high and low alerts
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from enable alert routine
-*/
-int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
-{
- return vega10_thermal_enable_alert(hwmgr);
-}
-
-/**
-* Disable high and low alerts
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from disable alert routine
-*/
-static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
-{
- return vega10_thermal_disable_alert(hwmgr);
-}
-
-static struct phm_master_table_item
-vega10_thermal_start_thermal_controller_master_list[] = {
- { .tableFunction = tf_vega10_thermal_initialize },
- { .tableFunction = tf_vega10_thermal_set_temperature_range },
- { .tableFunction = tf_vega10_thermal_enable_alert },
+ vega10_thermal_enable_alert(hwmgr);
/* We should restrict performance levels to low before we halt the SMC.
* On the other hand we are still in boot state when we do this
* so it would be pointless.
* If this assumption changes we have to revisit this table.
*/
- { .tableFunction = tf_vega10_thermal_setup_fan_table },
- { .tableFunction = tf_vega10_thermal_start_smc_fan_control },
- { }
+ ret = vega10_thermal_setup_fan_table(hwmgr);
+ if (ret)
+ return -EINVAL;
+
+ vega10_thermal_start_smc_fan_control(hwmgr);
+
+ return 0;
};
-static struct phm_master_table_header
-vega10_thermal_start_thermal_controller_master = {
- 0,
- PHM_MasterTableFlag_None,
- vega10_thermal_start_thermal_controller_master_list
-};
-static struct phm_master_table_item
-vega10_thermal_set_temperature_range_master_list[] = {
- { .tableFunction = tf_vega10_thermal_disable_alert },
- { .tableFunction = tf_vega10_thermal_set_temperature_range },
- { .tableFunction = tf_vega10_thermal_enable_alert },
- { }
-};
-struct phm_master_table_header
-vega10_thermal_set_temperature_range_master = {
- 0,
- PHM_MasterTableFlag_None,
- vega10_thermal_set_temperature_range_master_list
-};
int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
{
@@ -745,32 +645,3 @@ int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
}
return 0;
}
-
-/**
-* Initializes the thermal controller related functions
-* in the Hardware Manager structure.
-* @param hwmgr The address of the hardware manager.
-* @exception Any error code from the low-level communication.
-*/
-int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
-{
- int result;
-
- result = phm_construct_table(hwmgr,
- &vega10_thermal_set_temperature_range_master,
- &(hwmgr->set_temperature_range));
-
- if (!result) {
- result = phm_construct_table(hwmgr,
- &vega10_thermal_start_thermal_controller_master,
- &(hwmgr->start_thermal_controller));
- if (result)
- phm_destroy_table(hwmgr,
- &(hwmgr->set_temperature_range));
- }
-
- if (!result)
- hwmgr->fan_ctrl_is_in_default_mode = true;
- return result;
-}
-
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
index 776f3a2..82f10bd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
@@ -50,13 +50,6 @@ struct vega10_temperature {
#define FDO_PWM_MODE_STATIC_RPM 5
-extern int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result);
-extern int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result);
-extern int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result);
-
extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
@@ -69,7 +62,6 @@ extern int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr,
extern int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t speed);
extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-extern int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr);
extern int vega10_thermal_ctrl_uninitialize_thermal_controller(
struct pp_hwmgr *hwmgr);
extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
@@ -77,9 +69,11 @@ extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
extern int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
uint32_t *speed);
extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
-extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr);
-int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
+ struct PP_TemperatureRange *range);
+extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 07e9c0b..95932cc 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -31,9 +31,7 @@
#include "dm_pp_interface.h"
extern const struct amd_ip_funcs pp_ip_funcs;
-extern const struct amd_powerplay_funcs pp_dpm_funcs;
-
-#define PP_DPM_DISABLED 0xCCCC
+extern const struct amd_pm_funcs pp_dpm_funcs;
enum amd_pp_sensors {
AMDGPU_PP_SENSOR_GFX_SCLK = 0,
@@ -50,94 +48,12 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_GPU_POWER,
};
-enum amd_pp_event {
- AMD_PP_EVENT_INITIALIZE = 0,
- AMD_PP_EVENT_UNINITIALIZE,
- AMD_PP_EVENT_POWER_SOURCE_CHANGE,
- AMD_PP_EVENT_SUSPEND,
- AMD_PP_EVENT_RESUME,
- AMD_PP_EVENT_ENTER_REST_STATE,
- AMD_PP_EVENT_EXIT_REST_STATE,
- AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
- AMD_PP_EVENT_THERMAL_NOTIFICATION,
- AMD_PP_EVENT_VBIOS_NOTIFICATION,
- AMD_PP_EVENT_ENTER_THERMAL_STATE,
- AMD_PP_EVENT_EXIT_THERMAL_STATE,
- AMD_PP_EVENT_ENTER_FORCED_STATE,
- AMD_PP_EVENT_EXIT_FORCED_STATE,
- AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
- AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
- AMD_PP_EVENT_ENTER_SCREEN_SAVER,
- AMD_PP_EVENT_EXIT_SCREEN_SAVER,
- AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
- AMD_PP_EVENT_VPU_RECOVERY_END,
- AMD_PP_EVENT_ENABLE_POWER_PLAY,
- AMD_PP_EVENT_DISABLE_POWER_PLAY,
- AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
- AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
- AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
- AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
- AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
- AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
- AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
- AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
- AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
- AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
- AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
- AMD_PP_EVENT_ENABLE_CGPG,
- AMD_PP_EVENT_DISABLE_CGPG,
- AMD_PP_EVENT_ENTER_TEXT_MODE,
- AMD_PP_EVENT_EXIT_TEXT_MODE,
- AMD_PP_EVENT_VIDEO_START,
- AMD_PP_EVENT_VIDEO_STOP,
- AMD_PP_EVENT_ENABLE_USER_STATE,
- AMD_PP_EVENT_DISABLE_USER_STATE,
- AMD_PP_EVENT_READJUST_POWER_STATE,
- AMD_PP_EVENT_START_INACTIVITY,
- AMD_PP_EVENT_STOP_INACTIVITY,
- AMD_PP_EVENT_LINKED_ADAPTERS_READY,
- AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
- AMD_PP_EVENT_COMPLETE_INIT,
- AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
- AMD_PP_EVENT_BACKLIGHT_CHANGED,
- AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
- AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
- AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
- AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
- AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
- AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
- AMD_PP_EVENT_SCREEN_ON,
- AMD_PP_EVENT_SCREEN_OFF,
- AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
- AMD_PP_EVENT_ENTER_ULP_STATE,
- AMD_PP_EVENT_EXIT_ULP_STATE,
- AMD_PP_EVENT_REGISTER_IP_STATE,
- AMD_PP_EVENT_UNREGISTER_IP_STATE,
- AMD_PP_EVENT_ENTER_MGPU_MODE,
- AMD_PP_EVENT_EXIT_MGPU_MODE,
- AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
- AMD_PP_EVENT_PRE_SUSPEND,
- AMD_PP_EVENT_PRE_RESUME,
- AMD_PP_EVENT_ENTER_BACOS,
- AMD_PP_EVENT_EXIT_BACOS,
- AMD_PP_EVENT_RESUME_BACO,
- AMD_PP_EVENT_RESET_BACO,
- AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
- AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
- AMD_PP_EVENT_START_COMPUTE_APPLICATION,
- AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
- AMD_PP_EVENT_REDUCE_POWER_LIMIT,
- AMD_PP_EVENT_ENTER_FRAME_LOCK,
- AMD_PP_EVENT_EXIT_FRAME_LOOCK,
- AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
- AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
- AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
- AMD_PP_EVENT_HIBERNATE,
- AMD_PP_EVENT_CONNECTED_STANDBY,
- AMD_PP_EVENT_ENTER_SELF_REFRESH,
- AMD_PP_EVENT_EXIT_SELF_REFRESH,
- AMD_PP_EVENT_START_AVFS_BTC,
- AMD_PP_EVENT_MAX
+enum amd_pp_task {
+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
+ AMD_PP_TASK_ENABLE_USER_STATE,
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ AMD_PP_TASK_COMPLETE_INIT,
+ AMD_PP_TASK_MAX
};
struct amd_pp_init {
@@ -295,12 +211,6 @@ enum {
PP_GROUP_MAX
};
-enum pp_clock_type {
- PP_SCLK,
- PP_MCLK,
- PP_PCIE,
-};
-
struct pp_states_info {
uint32_t nums;
uint32_t states[16];
@@ -355,56 +265,13 @@ struct pp_display_clock_request {
support << PP_STATE_SUPPORT_SHIFT |\
state << PP_STATE_SHIFT)
-struct amd_powerplay_funcs {
- int (*get_temperature)(void *handle);
- int (*load_firmware)(void *handle);
- int (*wait_for_fw_loading_complete)(void *handle);
- int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
- enum amd_dpm_forced_level (*get_performance_level)(void *handle);
- enum amd_pm_state_type (*get_current_power_state)(void *handle);
- int (*get_sclk)(void *handle, bool low);
- int (*get_mclk)(void *handle, bool low);
- int (*powergate_vce)(void *handle, bool gate);
- int (*powergate_uvd)(void *handle, bool gate);
- int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
- void *input, void *output);
- int (*set_fan_control_mode)(void *handle, uint32_t mode);
- int (*get_fan_control_mode)(void *handle);
- int (*set_fan_speed_percent)(void *handle, uint32_t percent);
- int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
- int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
- int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
- int (*get_pp_table)(void *handle, char **table);
- int (*set_pp_table)(void *handle, const char *buf, size_t size);
- int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
- int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
- int (*get_sclk_od)(void *handle);
- int (*set_sclk_od)(void *handle, uint32_t value);
- int (*get_mclk_od)(void *handle);
- int (*set_mclk_od)(void *handle, uint32_t value);
- int (*read_sensor)(void *handle, int idx, void *value, int *size);
- struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx);
- int (*reset_power_profile_state)(void *handle,
- struct amd_pp_profile *request);
- int (*get_power_profile_state)(void *handle,
- struct amd_pp_profile *query);
- int (*set_power_profile_state)(void *handle,
- struct amd_pp_profile *request);
- int (*switch_power_profile)(void *handle,
- enum amd_pp_profile_type type);
-};
-
struct amd_powerplay {
+ struct cgs_device *cgs_device;
void *pp_handle;
const struct amd_ip_funcs *ip_funcs;
- const struct amd_powerplay_funcs *pp_funcs;
+ const struct amd_pm_funcs *pp_funcs;
};
-int amd_powerplay_create(struct amd_pp_init *pp_init,
- void **handle);
-
-int amd_powerplay_destroy(void *handle);
-
int amd_powerplay_reset(void *handle);
int amd_powerplay_display_configuration_change(void *handle,
@@ -437,6 +304,5 @@ int amd_powerplay_display_clock_voltage_request(void *handle,
int amd_powerplay_get_display_mode_validation_clocks(void *handle,
struct amd_pp_simple_clock_info *output);
-int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
#endif /* _AMD_POWERPLAY_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h b/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h
deleted file mode 100644
index b9d84de..0000000
--- a/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _EVENT_MANAGER_H_
-#define _EVENT_MANAGER_H_
-
-#include "power_state.h"
-#include "pp_power_source.h"
-#include "hardwaremanager.h"
-#include "pp_asicblocks.h"
-
-struct pp_eventmgr;
-enum amd_pp_event;
-
-enum PEM_EventDataValid {
- PEM_EventDataValid_RequestedStateID = 0,
- PEM_EventDataValid_RequestedUILabel,
- PEM_EventDataValid_NewPowerState,
- PEM_EventDataValid_RequestedPowerSource,
- PEM_EventDataValid_RequestedClocks,
- PEM_EventDataValid_CurrentTemperature,
- PEM_EventDataValid_AsicBlocks,
- PEM_EventDataValid_ODParameters,
- PEM_EventDataValid_PXAdapterPrefs,
- PEM_EventDataValid_PXUserPrefs,
- PEM_EventDataValid_PXSwitchReason,
- PEM_EventDataValid_PXSwitchPhase,
- PEM_EventDataValid_HdVideo,
- PEM_EventDataValid_BacklightLevel,
- PEM_EventDatavalid_VariBrightParams,
- PEM_EventDataValid_VariBrightLevel,
- PEM_EventDataValid_VariBrightImmediateChange,
- PEM_EventDataValid_PercentWhite,
- PEM_EventDataValid_SdVideo,
- PEM_EventDataValid_HTLinkChangeReason,
- PEM_EventDataValid_HWBlocks,
- PEM_EventDataValid_RequestedThermalState,
- PEM_EventDataValid_MvcVideo,
- PEM_EventDataValid_Max
-};
-
-typedef enum PEM_EventDataValid PEM_EventDataValid;
-
-/* Number of bits in ULONG variable */
-#define PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD (sizeof(unsigned long)*8)
-
-/* Number of ULONG entries used by event data valid bits */
-#define PEM_MAX_NUM_EVENTDATAVALID_ULONG_ENTRIES \
- ((PEM_EventDataValid_Max + PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD - 1) / \
- PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)
-
-static inline void pem_set_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field)
-{
- fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] |=
- (1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD));
-}
-
-static inline void pem_unset_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field)
-{
- fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] &=
- ~(1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD));
-}
-
-static inline unsigned long pem_is_event_data_valid(const unsigned long *fields, PEM_EventDataValid valid_field)
-{
- return fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] &
- (1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD));
-}
-
-struct pem_event_data {
- unsigned long valid_fields[100];
- unsigned long requested_state_id;
- enum PP_StateUILabel requested_ui_label;
- struct pp_power_state *pnew_power_state;
- enum pp_power_source requested_power_source;
- struct PP_Clocks requested_clocks;
- bool skip_state_adjust_rules;
- struct phm_asic_blocks asic_blocks;
- /* to doPP_ThermalState requestedThermalState;
- enum ThermalStateRequestSrc requestThermalStateSrc;
- PP_Temperature currentTemperature;*/
-
-};
-
-int pem_handle_event(struct pp_eventmgr *eventmgr, enum amd_pp_event event,
- struct pem_event_data *event_data);
-
-bool pem_is_hw_access_blocked(struct pp_eventmgr *eventmgr);
-
-#endif /* _EVENT_MANAGER_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
deleted file mode 100644
index 7bd8a7e..0000000
--- a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _EVENTMGR_H_
-#define _EVENTMGR_H_
-
-#include <linux/mutex.h>
-#include "pp_instance.h"
-#include "hardwaremanager.h"
-#include "eventmanager.h"
-#include "pp_feature.h"
-#include "pp_power_source.h"
-#include "power_state.h"
-
-typedef int (*pem_event_action)(struct pp_eventmgr *eventmgr,
- struct pem_event_data *event_data);
-
-struct action_chain {
- const char *description; /* action chain description for debugging purpose */
- const pem_event_action * const *action_chain; /* pointer to chain of event actions */
-};
-
-struct pem_power_source_ui_state_info {
- enum PP_StateUILabel current_ui_label;
- enum PP_StateUILabel default_ui_lable;
- unsigned long configurable_ui_mapping;
-};
-
-struct pp_clock_range {
- uint32_t min_sclk_khz;
- uint32_t max_sclk_khz;
-
- uint32_t min_mclk_khz;
- uint32_t max_mclk_khz;
-
- uint32_t min_vclk_khz;
- uint32_t max_vclk_khz;
-
- uint32_t min_dclk_khz;
- uint32_t max_dclk_khz;
-
- uint32_t min_aclk_khz;
- uint32_t max_aclk_khz;
-
- uint32_t min_eclk_khz;
- uint32_t max_eclk_khz;
-};
-
-enum pp_state {
- UNINITIALIZED,
- INACTIVE,
- ACTIVE
-};
-
-enum pp_ring_index {
- PP_RING_TYPE_GFX_INDEX = 0,
- PP_RING_TYPE_DMA_INDEX,
- PP_RING_TYPE_DMA1_INDEX,
- PP_RING_TYPE_UVD_INDEX,
- PP_RING_TYPE_VCE0_INDEX,
- PP_RING_TYPE_VCE1_INDEX,
- PP_RING_TYPE_CP1_INDEX,
- PP_RING_TYPE_CP2_INDEX,
- PP_NUM_RINGS,
-};
-
-struct pp_request {
- uint32_t flags;
- uint32_t sclk;
- uint32_t sclk_throttle;
- uint32_t mclk;
- uint32_t vclk;
- uint32_t dclk;
- uint32_t eclk;
- uint32_t aclk;
- uint32_t iclk;
- uint32_t vp8clk;
- uint32_t rsv[32];
-};
-
-struct pp_eventmgr {
- struct pp_hwmgr *hwmgr;
- struct pp_smumgr *smumgr;
-
- struct pp_feature_info features[PP_Feature_Max];
- const struct action_chain *event_chain[AMD_PP_EVENT_MAX];
- struct phm_platform_descriptor *platform_descriptor;
- struct pp_clock_range clock_range;
- enum pp_power_source current_power_source;
- struct pem_power_source_ui_state_info ui_state_info[PP_PowerSource_Max];
- enum pp_state states[PP_NUM_RINGS];
- struct pp_request hi_req;
- struct list_head context_list;
- struct mutex lock;
- bool block_adjust_power_state;
- bool enable_cg;
- bool enable_gfx_cgpg;
- int (*pp_eventmgr_init)(struct pp_eventmgr *eventmgr);
- void (*pp_eventmgr_fini)(struct pp_eventmgr *eventmgr);
-};
-
-int eventmgr_early_init(struct pp_instance *handle);
-
-#endif /* _EVENTMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
deleted file mode 100644
index 8a31665..0000000
--- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
+++ /dev/null
@@ -1,10299 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _FIJI_PWRVIRUS_H_
-#define _FIJI_PWRVIRUS_H_
-
-#define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a
-#define mmCP_HYP_MEC1_UCODE_DATA 0xf81b
-#define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c
-#define mmCP_HYP_MEC2_UCODE_DATA 0xf81d
-
-enum PWR_Command
-{
- PwrCmdNull = 0,
- PwrCmdWrite,
- PwrCmdEnd,
- PwrCmdMax
-};
-typedef enum PWR_Command PWR_Command;
-
-struct PWR_Command_Table
-{
- PWR_Command command;
- ULONG data;
- ULONG reg;
-};
-typedef struct PWR_Command_Table PWR_Command_Table;
-
-#define PWR_VIRUS_TABLE_SIZE 10243
-static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
-{
- { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX },
- { PwrCmdWrite, 0x00000000, mmPCIE_DATA },
- { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX },
- { PwrCmdWrite, 0x0300078c, mmPCIE_DATA },
- { PwrCmdWrite, 0x00000000, mmBIF_CLK_CTRL },
- { PwrCmdWrite, 0x00000001, mmBIF_CLK_CTRL },
- { PwrCmdWrite, 0x00000000, mmBIF_CLK_CTRL },
- { PwrCmdWrite, 0x00000003, mmBIF_FB_EN },
- { PwrCmdWrite, 0x00000000, mmBIF_FB_EN },
- { PwrCmdWrite, 0x00000001, mmBIF_DOORBELL_APER_EN },
- { PwrCmdWrite, 0x00000000, mmBIF_DOORBELL_APER_EN },
- { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX },
- { PwrCmdWrite, 0x00000000, mmPCIE_DATA },
- { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX },
- { PwrCmdWrite, 0x22000000, mmPCIE_DATA },
- { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX },
- { PwrCmdWrite, 0x00000000, mmPCIE_DATA },
- /*
- { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION },
- { PwrCmdWrite, 0x00000000, mmMC_CITF_CNTL },
- { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION },
- { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION },
- { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION },
- { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION },
- { PwrCmdWrite, 0x00000000, mmMC_VM_FB_OFFSET },*/
- { PwrCmdWrite, 0x00000000, mmRLC_CSIB_ADDR_LO },
- { PwrCmdWrite, 0x00000000, mmRLC_CSIB_ADDR_HI },
- { PwrCmdWrite, 0x00000000, mmRLC_CSIB_LENGTH },
- /*
- { PwrCmdWrite, 0x00000000, mmMC_VM_MX_L1_TLB_CNTL },
- { PwrCmdWrite, 0x00000001, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR },
- { PwrCmdWrite, 0x00000000, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR },
- { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION },
- { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION },*/
- { PwrCmdWrite, 0x00000000, mmVM_CONTEXT0_CNTL },
- { PwrCmdWrite, 0x00000000, mmVM_CONTEXT1_CNTL },
- /*
- { PwrCmdWrite, 0x00000000, mmMC_VM_AGP_BASE },
- { PwrCmdWrite, 0x00000002, mmMC_VM_AGP_BOT },
- { PwrCmdWrite, 0x00000000, mmMC_VM_AGP_TOP },*/
- { PwrCmdWrite, 0x04000000, mmATC_VM_APERTURE0_LOW_ADDR },
- { PwrCmdWrite, 0x0400ff20, mmATC_VM_APERTURE0_HIGH_ADDR },
- { PwrCmdWrite, 0x00000002, mmATC_VM_APERTURE0_CNTL },
- { PwrCmdWrite, 0x0000ffff, mmATC_VM_APERTURE0_CNTL2 },
- { PwrCmdWrite, 0x00000001, mmATC_VM_APERTURE1_LOW_ADDR },
- { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_HIGH_ADDR },
- { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_CNTL },
- { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_CNTL2 },
- //{ PwrCmdWrite, 0x00000000, mmMC_ARB_RAMCFG },
- { PwrCmdWrite, 0x12011003, mmGB_ADDR_CONFIG },
- { PwrCmdWrite, 0x00800010, mmGB_TILE_MODE0 },
- { PwrCmdWrite, 0x00800810, mmGB_TILE_MODE1 },
- { PwrCmdWrite, 0x00801010, mmGB_TILE_MODE2 },
- { PwrCmdWrite, 0x00801810, mmGB_TILE_MODE3 },
- { PwrCmdWrite, 0x00802810, mmGB_TILE_MODE4 },
- { PwrCmdWrite, 0x00802808, mmGB_TILE_MODE5 },
- { PwrCmdWrite, 0x00802814, mmGB_TILE_MODE6 },
- { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE7 },
- { PwrCmdWrite, 0x00000004, mmGB_TILE_MODE8 },
- { PwrCmdWrite, 0x02000008, mmGB_TILE_MODE9 },
- { PwrCmdWrite, 0x02000010, mmGB_TILE_MODE10 },
- { PwrCmdWrite, 0x06000014, mmGB_TILE_MODE11 },
- { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE12 },
- { PwrCmdWrite, 0x02400008, mmGB_TILE_MODE13 },
- { PwrCmdWrite, 0x02400010, mmGB_TILE_MODE14 },
- { PwrCmdWrite, 0x02400030, mmGB_TILE_MODE15 },
- { PwrCmdWrite, 0x06400014, mmGB_TILE_MODE16 },
- { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE17 },
- { PwrCmdWrite, 0x0040000c, mmGB_TILE_MODE18 },
- { PwrCmdWrite, 0x0100000c, mmGB_TILE_MODE19 },
- { PwrCmdWrite, 0x0100001c, mmGB_TILE_MODE20 },
- { PwrCmdWrite, 0x01000034, mmGB_TILE_MODE21 },
- { PwrCmdWrite, 0x01000024, mmGB_TILE_MODE22 },
- { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE23 },
- { PwrCmdWrite, 0x0040001c, mmGB_TILE_MODE24 },
- { PwrCmdWrite, 0x01000020, mmGB_TILE_MODE25 },
- { PwrCmdWrite, 0x01000038, mmGB_TILE_MODE26 },
- { PwrCmdWrite, 0x02c00008, mmGB_TILE_MODE27 },
- { PwrCmdWrite, 0x02c00010, mmGB_TILE_MODE28 },
- { PwrCmdWrite, 0x06c00014, mmGB_TILE_MODE29 },
- { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE30 },
- { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE31 },
- { PwrCmdWrite, 0x000000a8, mmGB_MACROTILE_MODE0 },
- { PwrCmdWrite, 0x000000a4, mmGB_MACROTILE_MODE1 },
- { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE2 },
- { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE3 },
- { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE4 },
- { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE5 },
- { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE6 },
- { PwrCmdWrite, 0x00000000, mmGB_MACROTILE_MODE7 },
- { PwrCmdWrite, 0x000000ee, mmGB_MACROTILE_MODE8 },
- { PwrCmdWrite, 0x000000ea, mmGB_MACROTILE_MODE9 },
- { PwrCmdWrite, 0x000000e9, mmGB_MACROTILE_MODE10 },
- { PwrCmdWrite, 0x000000e5, mmGB_MACROTILE_MODE11 },
- { PwrCmdWrite, 0x000000e4, mmGB_MACROTILE_MODE12 },
- { PwrCmdWrite, 0x000000e0, mmGB_MACROTILE_MODE13 },
- { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE14 },
- { PwrCmdWrite, 0x00000000, mmGB_MACROTILE_MODE15 },
- { PwrCmdWrite, 0x00900000, mmHDP_NONSURFACE_BASE },
- { PwrCmdWrite, 0x00008000, mmHDP_NONSURFACE_INFO },
- { PwrCmdWrite, 0x3fffffff, mmHDP_NONSURFACE_SIZE },
- { PwrCmdWrite, 0x00000003, mmBIF_FB_EN },
- //{ PwrCmdWrite, 0x00000000, mmMC_VM_FB_OFFSET },
- { PwrCmdWrite, 0x00000000, mmSRBM_CNTL },
- { PwrCmdWrite, 0x00020000, mmSRBM_CNTL },
- { PwrCmdWrite, 0x80000000, mmATC_VMID0_PASID_MAPPING },
- { PwrCmdWrite, 0x00000000, mmATC_VMID_PASID_MAPPING_UPDATE_STATUS },
- { PwrCmdWrite, 0x00000000, mmRLC_CNTL },
- { PwrCmdWrite, 0x00000000, mmRLC_CNTL },
- { PwrCmdWrite, 0x00000000, mmRLC_CNTL },
- { PwrCmdWrite, 0xe0000000, mmGRBM_GFX_INDEX },
- { PwrCmdWrite, 0x00000000, mmCGTS_TCC_DISABLE },
- { PwrCmdWrite, 0x00000000, mmTCP_ADDR_CONFIG },
- { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG },
- { PwrCmdWrite, 0x76543210, mmTCP_CHAN_STEER_LO },
- { PwrCmdWrite, 0xfedcba98, mmTCP_CHAN_STEER_HI },
- { PwrCmdWrite, 0x00000000, mmDB_DEBUG2 },
- { PwrCmdWrite, 0x00000000, mmDB_DEBUG },
- { PwrCmdWrite, 0x00002b16, mmCP_QUEUE_THRESHOLDS },
- { PwrCmdWrite, 0x00006030, mmCP_MEQ_THRESHOLDS },
- { PwrCmdWrite, 0x01000104, mmSPI_CONFIG_CNTL_1 },
- { PwrCmdWrite, 0x98184020, mmPA_SC_FIFO_SIZE },
- { PwrCmdWrite, 0x00000001, mmVGT_NUM_INSTANCES },
- { PwrCmdWrite, 0x00000000, mmCP_PERFMON_CNTL },
- { PwrCmdWrite, 0x01180000, mmSQ_CONFIG },
- { PwrCmdWrite, 0x00000000, mmVGT_CACHE_INVALIDATION },
- { PwrCmdWrite, 0x00000000, mmSQ_THREAD_TRACE_BASE },
- { PwrCmdWrite, 0x0000df80, mmSQ_THREAD_TRACE_MASK },
- { PwrCmdWrite, 0x02249249, mmSQ_THREAD_TRACE_MODE },
- { PwrCmdWrite, 0x00000000, mmPA_SC_LINE_STIPPLE_STATE },
- { PwrCmdWrite, 0x00000000, mmCB_PERFCOUNTER0_SELECT1 },
- { PwrCmdWrite, 0x06000100, mmCGTT_VGT_CLK_CTRL },
- { PwrCmdWrite, 0x00000007, mmPA_CL_ENHANCE },
- { PwrCmdWrite, 0x00000001, mmPA_SC_ENHANCE },
- { PwrCmdWrite, 0x00ffffff, mmPA_SC_FORCE_EOV_MAX_CNTS },
- { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000010, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000020, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000030, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000040, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000050, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000060, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000070, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000080, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000090, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x000000a0, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x000000b0, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x000000c0, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x000000d0, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x000000e0, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x000000f0, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmRLC_PG_CNTL },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS2 },
- { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL },
- { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x0000000e, mmSH_MEM_APE1_BASE },
- { PwrCmdWrite, 0x0000020d, mmSH_MEM_APE1_LIMIT },
- { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG },
- { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_RB_VMID },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmRLC_CNTL },
- { PwrCmdWrite, 0x00000000, mmRLC_CNTL },
- { PwrCmdWrite, 0x00000000, mmRLC_SRM_CNTL },
- { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_ME_CNTL },
- { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL },
- { PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL },
- { PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE },
- { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG },
- { PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO },
- { PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI },
- { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR },
- { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR },
- { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdEnd, 0x00000000, 0x00000000 },
-};
-
-#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index a4c8b09..57a0467 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -283,6 +283,8 @@ static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps
(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
}
+#define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
+
#define PP_PCIEGenInvalid 0xffff
enum PP_PCIEGen {
PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
@@ -295,7 +297,7 @@ typedef enum PP_PCIEGen PP_PCIEGen;
#define PP_Min_PCIEGen PP_PCIEGen1
#define PP_Max_PCIEGen PP_PCIEGen3
#define PP_Min_PCIELane 1
-#define PP_Max_PCIELane 32
+#define PP_Max_PCIELane 16
enum phm_clock_Type {
PHM_DispClock = 1,
@@ -373,8 +375,6 @@ struct phm_odn_clock_levels {
extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
-extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
-extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 91b0105..004a40e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -32,6 +32,7 @@
#include "ppatomctrl.h"
#include "hwmgr_ppt.h"
#include "power_state.h"
+#include "cgs_linux.h"
struct pp_instance;
struct pp_hwmgr;
@@ -61,10 +62,6 @@ struct vi_dpm_table {
struct vi_dpm_level dpm_level[1];
};
-enum PP_Result {
- PP_Result_TableImmediateExit = 0x13,
-};
-
#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
#define PCIE_PERF_REQ_GEN1 2
@@ -103,17 +100,6 @@ enum PHM_BackEnd_Magic {
PHM_Rv_Magic = 0x20161121
};
-
-#define PHM_PCIE_POWERGATING_TARGET_GFX 0
-#define PHM_PCIE_POWERGATING_TARGET_DDI 1
-#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
-#define PHM_PCIE_POWERGATING_TARGET_PHY 3
-
-typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
- void *output, void *storage, int result);
-
-typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
-
struct phm_set_power_state_input {
const struct pp_hw_power_state *pcurrent_state;
const struct pp_hw_power_state *pnew_state;
@@ -149,30 +135,6 @@ struct phm_gfx_arbiter {
uint32_t fclk;
};
-/* Entries in the master tables */
-struct phm_master_table_item {
- phm_check_function isFunctionNeededInRuntimeTable;
- phm_table_function tableFunction;
-};
-
-enum phm_master_table_flag {
- PHM_MasterTableFlag_None = 0,
- PHM_MasterTableFlag_ExitOnError = 1,
-};
-
-/* The header of the master tables */
-struct phm_master_table_header {
- uint32_t storage_size;
- uint32_t flags;
- const struct phm_master_table_item *master_list;
-};
-
-struct phm_runtime_table_header {
- uint32_t storage_size;
- bool exit_error;
- phm_table_function *function_list;
-};
-
struct phm_clock_array {
uint32_t count;
uint32_t values[1];
@@ -216,19 +178,6 @@ struct phm_phase_shedding_limits_record {
uint32_t Mclk;
};
-
-extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
- struct phm_runtime_table_header *rt_table,
- void *input, void *output);
-
-extern int phm_construct_table(struct pp_hwmgr *hwmgr,
- const struct phm_master_table_header *master_table,
- struct phm_runtime_table_header *rt_table);
-
-extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
- struct phm_runtime_table_header *rt_table);
-
-
struct phm_uvd_clock_voltage_dependency_record {
uint32_t vclk;
uint32_t dclk;
@@ -286,6 +235,39 @@ struct phm_vce_clock_voltage_dependency_table {
struct phm_vce_clock_voltage_dependency_record entries[1];
};
+struct pp_smumgr_func {
+ int (*smu_init)(struct pp_hwmgr *hwmgr);
+ int (*smu_fini)(struct pp_hwmgr *hwmgr);
+ int (*start_smu)(struct pp_hwmgr *hwmgr);
+ int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
+ uint32_t firmware);
+ int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
+ int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
+ uint32_t firmware);
+ int (*get_argument)(struct pp_hwmgr *hwmgr);
+ int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
+ int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
+ uint16_t msg, uint32_t parameter);
+ int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
+ void **table);
+ int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
+ int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
+ int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
+ int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
+ int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
+ int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
+ int (*init_smc_table)(struct pp_hwmgr *hwmgr);
+ int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
+ int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
+ int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
+ uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
+ uint32_t (*get_mac_definition)(uint32_t value);
+ bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
+ int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
+ struct amd_pp_profile *request);
+ bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
+};
+
struct pp_hwmgr_func {
int (*backend_init)(struct pp_hwmgr *hw_mgr);
int (*backend_fini)(struct pp_hwmgr *hw_mgr);
@@ -311,10 +293,10 @@ struct pp_hwmgr_func {
unsigned long, struct pp_power_state *);
int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
- int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
- int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
- int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
- int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
+ void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
+ void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
+ uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
+ uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
int (*power_state_set)(struct pp_hwmgr *hwmgr,
const void *state);
int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
@@ -328,8 +310,8 @@ struct pp_hwmgr_func {
int (*get_temperature)(struct pp_hwmgr *hwmgr);
int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
- int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
- int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
+ void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
+ uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
@@ -378,6 +360,15 @@ struct pp_hwmgr_func {
struct amd_pp_profile *request);
int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
+ int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
+ int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
+ int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
+ int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
+ uint32_t virtual_addr_low,
+ uint32_t virtual_addr_hi,
+ uint32_t mc_addr_low,
+ uint32_t mc_addr_hi,
+ uint32_t size);
};
struct pp_table_func {
@@ -745,7 +736,7 @@ struct pp_hwmgr {
enum amd_dpm_forced_level dpm_level;
enum amd_dpm_forced_level saved_dpm_level;
- bool block_hw_access;
+ enum amd_dpm_forced_level request_dpm_level;
struct phm_gfx_arbiter gfx_arbiter;
struct phm_acp_arbiter acp_arbiter;
struct phm_uvd_arbiter uvd_arbiter;
@@ -754,19 +745,17 @@ struct pp_hwmgr {
void *pptable;
struct phm_platform_descriptor platform_descriptor;
void *backend;
+
+ void *smu_backend;
+ const struct pp_smumgr_func *smumgr_funcs;
+ bool is_kicker;
+ bool reload_fw;
+
enum PP_DAL_POWERLEVEL dal_power_level;
struct phm_dynamic_state_info dyn_state;
- struct phm_runtime_table_header setup_asic;
- struct phm_runtime_table_header power_down_asic;
- struct phm_runtime_table_header disable_dynamic_state_management;
- struct phm_runtime_table_header enable_dynamic_state_management;
- struct phm_runtime_table_header set_power_state;
- struct phm_runtime_table_header enable_clock_power_gatings;
- struct phm_runtime_table_header display_configuration_changed;
- struct phm_runtime_table_header start_thermal_controller;
- struct phm_runtime_table_header set_temperature_range;
const struct pp_hwmgr_func *hwmgr_func;
const struct pp_table_func *pptable_func;
+
struct pp_power_state *ps;
enum pp_power_source power_source;
uint32_t num_ps;
@@ -784,26 +773,44 @@ struct pp_hwmgr {
struct amd_pp_display_configuration display_config;
uint32_t feature_mask;
- /* power profile */
+ /* UMD Pstate */
struct amd_pp_profile gfx_power_profile;
struct amd_pp_profile compute_power_profile;
struct amd_pp_profile default_gfx_power_profile;
struct amd_pp_profile default_compute_power_profile;
enum amd_pp_profile_type current_power_profile;
+ bool en_umd_pstate;
+};
+
+struct cgs_irq_src_funcs {
+ cgs_irq_source_set_func_t set;
+ cgs_irq_handler_func_t handler;
};
extern int hwmgr_early_init(struct pp_instance *handle);
extern int hwmgr_hw_init(struct pp_instance *handle);
extern int hwmgr_hw_fini(struct pp_instance *handle);
+extern int hwmgr_hw_suspend(struct pp_instance *handle);
+extern int hwmgr_hw_resume(struct pp_instance *handle);
+extern int hwmgr_handle_task(struct pp_instance *handle,
+ enum amd_pp_task task_id,
+ void *input, void *output);
extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
uint32_t value, uint32_t mask);
-extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
+extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
uint32_t mask);
+extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t index,
+ uint32_t value, uint32_t mask);
+extern int phm_wait_for_indirect_register_unequal(
+ struct pp_hwmgr *hwmgr,
+ uint32_t indirect_port, uint32_t index,
+ uint32_t value, uint32_t mask);
extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
@@ -888,5 +895,58 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t
PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
+ phm_wait_for_indirect_register_unequal(hwmgr, \
+ mm##port##_INDEX, index, value, mask)
+
+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field) )
+
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ port, index, value, mask) \
+ phm_wait_for_indirect_register_unequal(hwmgr, \
+ mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
+ port, index, value, mask) \
+ phm_wait_on_indirect_register(hwmgr, \
+ mm##port##_INDEX_11, index, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
+
+#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
+ PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
+
+#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ index, value, mask) \
+ phm_wait_for_register_unequal(hwmgr, \
+ index, value, mask)
+
+#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
+ PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
+ mm##reg, value, mask)
+
+#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
+ PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
+ (fieldval) << PHM_FIELD_SHIFT(reg, field), \
+ PHM_FIELD_MASK(reg, field))
#endif /* _HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
index 0de4436..6a53b7e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
@@ -29,10058 +29,1764 @@
#define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c
#define mmCP_HYP_MEC2_UCODE_DATA 0xf81d
-enum PWR_Command {
- PwrCmdNull = 0,
- PwrCmdWrite,
- PwrCmdEnd,
- PwrCmdMax
-};
-
-typedef enum PWR_Command PWR_Command;
-
struct PWR_Command_Table {
- PWR_Command command;
uint32_t data;
uint32_t reg;
};
typedef struct PWR_Command_Table PWR_Command_Table;
+struct PWR_DFY_Section {
+ uint32_t dfy_cntl;
+ uint32_t dfy_addr_hi, dfy_addr_lo;
+ uint32_t dfy_size;
+ uint32_t dfy_data[];
+};
-#define PWR_VIRUS_TABLE_SIZE 10031
+typedef struct PWR_DFY_Section PWR_DFY_Section;
-static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
- { PwrCmdWrite, 0x00000000, mmRLC_CNTL },
- { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL },
- { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL },
- { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL },
- { PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL },
- { PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE },
- { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG },
- { PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO },
- { PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI },
- { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR },
- { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
- { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR },
- { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI },
- { PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0 },
- { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL },
- { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
- { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI },
- { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
- { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
- { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE },
- { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID },
- { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL },
- { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR },
- { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR },
- { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE },
- { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL },
- { PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdWrite, 0x00000000, mmGRBM_STATUS },
- { PwrCmdEnd, 0x00000000, 0x00000000 },
+static const PWR_Command_Table pwr_virus_table_pre[] = {
+ { 0x00000000, mmRLC_CNTL },
+ { 0x00000002, mmRLC_SRM_CNTL },
+ { 0x15000000, mmCP_ME_CNTL },
+ { 0x50000000, mmCP_MEC_CNTL },
+ { 0x80000004, mmCP_DFY_CNTL },
+ { 0x0840800a, mmCP_RB0_CNTL },
+ { 0xf30fff0f, mmTCC_CTRL },
+ { 0x00000002, mmTCC_EXE_DISABLE },
+ { 0x000000ff, mmTCP_ADDR_CONFIG },
+ { 0x540ff000, mmCP_CPC_IC_BASE_LO },
+ { 0x000000b4, mmCP_CPC_IC_BASE_HI },
+ { 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR },
+ { 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00221408, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00591260, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00621387, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA },
+ { 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR },
+ { 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00221408, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00591260, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00621387, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA },
+ { 0x00000000, 0xFFFFFFFF },
+};
+
+static const PWR_DFY_Section pwr_virus_section1 = {
+ .dfy_cntl = 0x80000004,
+ .dfy_addr_hi = 0x000000b4,
+ .dfy_addr_lo = 0x540fe800,
+ .dfy_data = {
+ 0x7e000200, 0x7e020201, 0x7e040204, 0x7e060205, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
+ 0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0xbf810000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x54106f00, 0x000400b4, 0x00004000, 0x00804fac, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ },
+ .dfy_size = 416
+};
+
+static const PWR_DFY_Section pwr_virus_section2 = {
+ .dfy_cntl = 0x80000004,
+ .dfy_addr_hi = 0x000000b4,
+ .dfy_addr_lo = 0x540fef00,
+ .dfy_data = {
+ 0xc0031502, 0x00001e00, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ },
+ .dfy_size = 16
+};
+
+static const PWR_DFY_Section pwr_virus_section3 = {
+ .dfy_cntl = 0x80000004,
+ .dfy_addr_hi = 0x000000b4,
+ .dfy_addr_lo = 0x540ff000,
+ .dfy_data = {
+ 0xc424000b, 0x80000145, 0x94800001, 0x94c00001, 0x95000001, 0x95400001, 0x95800001, 0xdc810000,
+ 0xdcc10000, 0xdd010000, 0xdd410000, 0xdd810000, 0xc4080061, 0xd8400013, 0xd8000003, 0xc40c0001,
+ 0x24ccffff, 0x3cd08000, 0x9500fffd, 0x1cd0ffcf, 0x7d018001, 0xc4140004, 0x050c0019, 0xd8400008,
+ 0x84c00000, 0x80000023, 0x80000067, 0x8000006a, 0x8000006d, 0x80000079, 0x80000084, 0x8000008f,
+ 0x80000099, 0x800000a0, 0x800000af, 0xd8400053, 0xc4080007, 0x388c0001, 0x08880002, 0x04100003,
+ 0x94c00005, 0x98800003, 0x04100004, 0x8000002d, 0x04100005, 0x8c00003f, 0x8c000043, 0x28cc0000,
+ 0xccc00050, 0x8c000055, 0x28080001, 0xcc000004, 0x7d808001, 0xd8400013, 0xd88130b8, 0xcd400008,
+ 0xdc180000, 0xdc140000, 0xdc100000, 0xdc0c0000, 0xcc800005, 0xdc080000, 0x80000168, 0xc40c000e,
+ 0x28cc0008, 0xccc00013, 0x90000000, 0xcd013278, 0xc4113278, 0x95000001, 0x24cc0700, 0xd8400029,
+ 0xc4113255, 0xcd01324f, 0xc4113254, 0x1d10ffdf, 0xcd013254, 0x10cc0014, 0x1d10c017, 0x7d0d000a,
+ 0xd8400013, 0xd8400008, 0xcd0130b7, 0x14cc0010, 0x90000000, 0xd9c00036, 0x8000005d, 0xd8400013,
+ 0xc00c4000, 0xccc130b5, 0xc40c000e, 0x28cc0008, 0xccc00013, 0xc40c0021, 0x14d00011, 0x9500fffe,
+ 0xdc030000, 0xd800000c, 0xd800000d, 0xc40c005e, 0x94c01b10, 0xd8400013, 0x90000000, 0xc00e0080,
+ 0xccc130b5, 0x8000013b, 0xc00e0800, 0xccc130b5, 0x8000013b, 0xd8400053, 0x04100006, 0x8c00003f,
+ 0x8c000043, 0x28cc0000, 0xccc00050, 0x8c000055, 0x280c0008, 0xccc00052, 0xd8000021, 0x28180039,
+ 0x80000034, 0xd8400053, 0x04100007, 0x8c00003f, 0x8c000043, 0x28cc0001, 0xccc00050, 0x8c000055,
+ 0x280c0010, 0xccc00052, 0x28180039, 0x80000034, 0xd8400053, 0x04100008, 0x8c00003f, 0x8c000043,
+ 0x28cc0003, 0xccc00050, 0x8c000055, 0x280c0020, 0xccc00052, 0x28180039, 0x80000034, 0xdc030000,
+ 0xd8000069, 0x28080001, 0xc428000d, 0x7ca88004, 0xcc800079, 0x04280001, 0xcc00006f, 0x8000013b,
+ 0x80000034, 0x04100010, 0x8c00003f, 0x8c000043, 0xccc00078, 0x8c000055, 0x28180080, 0x80000034,
+ 0x04100001, 0xc40c000e, 0x28cc0008, 0xccc00013, 0xcd013278, 0xc4113278, 0x95000001, 0xc00c4000,
+ 0xc4113254, 0x1d10c017, 0xd8400013, 0xd8400008, 0xccc130b5, 0xcd0130b7, 0x8000013b, 0x95c00001,
+ 0x96000001, 0x96400001, 0x96800001, 0x96c00001, 0x97000001, 0x97400001, 0x97800001, 0x97c00001,
+ 0xdc810000, 0xc40c000c, 0xcd4c0380, 0xcdcc0388, 0x55dc0020, 0xcdcc038c, 0xce0c0390, 0x56200020,
+ 0xce0c0394, 0xce4c0398, 0x56640020, 0xce4c039c, 0xce8c03a0, 0x56a80020, 0xce8c03a4, 0xcecc03a8,
+ 0x56ec0020, 0xcecc03ac, 0xcf0c03b0, 0x57300020, 0xcf0c03b4, 0xcf4c03b8, 0x57740020, 0xcf4c03bc,
+ 0xcf8c03c0, 0x57b80020, 0xcf8c03c4, 0xcfcc03c8, 0x57fc0020, 0xcfcc03cc, 0xd9000033, 0xc41c0009,
+ 0x25dc0010, 0x95c0fffe, 0xd8400013, 0xc41c000c, 0x05dc002f, 0xcdc12009, 0xc41d200a, 0xd8400013,
+ 0xcc012009, 0xd9000034, 0x25e01c00, 0x12200013, 0x25e40300, 0x12640008, 0x25e800c0, 0x12a80002,
+ 0x25ec003f, 0x7e25c00a, 0x7eae400a, 0x7de5c00a, 0xddc10000, 0xc02ee000, 0xcec1c200, 0xc40c005f,
+ 0xccc00037, 0x24d000ff, 0x31100006, 0x9500007b, 0x8c000190, 0xdc1c0000, 0xd8400013, 0xcdc1c200,
+ 0xc40c000c, 0xc4df0388, 0xc4d7038c, 0x51540020, 0x7d5dc01a, 0xc4e30390, 0xc4d70394, 0x51540020,
+ 0x7d62001a, 0xc4e70398, 0xc4d7039c, 0x51540020, 0x7d66401a, 0xc4eb03a0, 0xc4d703a4, 0x51540020,
+ 0x7d6a801a, 0xc4ef03a8, 0xc4d703ac, 0x51540020, 0x7d6ec01a, 0xc4f303b0, 0xc4d703b4, 0x51540020,
+ 0x7d73001a, 0xc4f703b8, 0xc4d703bc, 0x51540020, 0x7d77401a, 0xc4fb03c0, 0xc4d703c4, 0x51540020,
+ 0x7d7b801a, 0xc4ff03c8, 0xc4d703cc, 0x51540020, 0x7d7fc01a, 0xdc080000, 0xcc800013, 0xc4d70380,
+ 0xc4080001, 0x1c88001c, 0xcd400008, 0xc40c0083, 0x94c00010, 0xdc0e0000, 0x94c0000e, 0xc40c0082,
+ 0x24d00001, 0x9900000b, 0x18cc01e3, 0x3cd00004, 0x95000008, 0xc40c0085, 0x18cc006a, 0x98c00005,
+ 0xc40c0082, 0x18cc01e3, 0x3cd00004, 0x9900fffa, 0xdc180000, 0xdc140000, 0xdc100000, 0xdc0c0000,
+ 0xcc800004, 0xdc080000, 0x90000000, 0xc4080001, 0x1c88001c, 0xcd400008, 0xdc180000, 0xdc140000,
+ 0xdc100000, 0xdc0c0000, 0xcc800004, 0xdc080000, 0x90000000, 0xd8400051, 0xc428000c, 0x04180018,
+ 0x32640002, 0x9a80001f, 0x9a40001e, 0xcd800013, 0xc4293265, 0x040c0000, 0x1aac0027, 0x2aa80080,
+ 0xce813265, 0x9ac00017, 0xd80002f1, 0x04080002, 0x08880001, 0xd8080250, 0xd8080258, 0xd8080230,
+ 0xd8080238, 0xd8080240, 0xd8080248, 0xd8080268, 0xd8080270, 0xd8080278, 0xd8080280, 0xd8080228,
+ 0xd8000367, 0x9880fff3, 0x04080010, 0x08880001, 0xd80c0309, 0xd80c0319, 0x04cc0001, 0x9880fffc,
+ 0x7c408001, 0x88000000, 0xc00e0100, 0xd8400013, 0xd8400008, 0xccc130b5, 0x8000016e, 0xc4180032,
+ 0x29980008, 0xcd800013, 0x95800001, 0x7c40c001, 0x18d0003f, 0x24d4001f, 0x24d80001, 0x155c0001,
+ 0x05e80180, 0x9900000b, 0x202c003d, 0xcd800010, 0xcec1325b, 0xc42d325b, 0x96c00001, 0x86800000,
+ 0x80000168, 0x80000aa7, 0x80000bfc, 0x800012e9, 0xc4200007, 0x0a200001, 0xce000010, 0x80001b70,
+ 0x7c40c001, 0x8c000190, 0xc410001b, 0xd8000032, 0xd8000031, 0x9900091a, 0x7c408001, 0x88000000,
+ 0x24d000ff, 0x05280196, 0x18d4fe04, 0x29540008, 0xcd400013, 0x86800000, 0x800001b4, 0x8000032b,
+ 0x80000350, 0x80000352, 0x8000035f, 0x80000701, 0x8000047c, 0x8000019f, 0x80000800, 0xc419325b,
+ 0x1d98001f, 0xcd81325b, 0x8c00003f, 0xc4140004, 0xd8400008, 0x04100002, 0x8c000043, 0x28cc0002,
+ 0xccc00050, 0xc43c0044, 0x27fc0003, 0x9bc00002, 0x97c00006, 0xc00c4000, 0xccc130b5, 0x8c000055,
+ 0xd8400013, 0xd88130b8, 0xcd400008, 0x90000000, 0xd8400008, 0xcd400013, 0x7d40c001, 0xd8400028,
+ 0xd8400029, 0xd9400036, 0xc4193256, 0xc41d3254, 0x15540008, 0xcd400009, 0xcd40005b, 0xcd40005e,
+ 0xcd40005d, 0xd840006d, 0xc421325a, 0xc42d3249, 0x11540015, 0x19a4003c, 0x1998003f, 0x1af0007d,
+ 0x11dc000b, 0x1264001f, 0x15dc000d, 0x7d65400a, 0x13300018, 0x1a38003f, 0x7dd5c00a, 0x7df1c00a,
+ 0xcd800045, 0xcdc00100, 0xc411326a, 0xc415326b, 0xc419326c, 0xc41d326d, 0xc425326e, 0xc4293279,
+ 0xce800077, 0xcd000056, 0xcd400057, 0xcd800058, 0xcdc00059, 0xc4193265, 0x259c8000, 0x99c00004,
+ 0xce40005a, 0x29988000, 0xcd813265, 0xc4113248, 0x2510000f, 0xcd000073, 0xc418000d, 0xc411326f,
+ 0x17300019, 0x97000009, 0x25140fff, 0x95400007, 0xd800003a, 0x8c001b6d, 0xc4153279, 0xcd400077,
+ 0xcd00005f, 0xd8000075, 0x26f00001, 0x15100010, 0x7d190004, 0xcd000035, 0x97000035, 0x1af07fe8,
+ 0xd8800013, 0xd8400010, 0xd8400008, 0xcf00000d, 0xcf00000a, 0x8c001427, 0x04340022, 0x07740001,
+ 0x04300010, 0xdf430000, 0x7c434001, 0x7c408001, 0xd4412e01, 0x0434001e, 0xdf430000, 0xd4400078,
+ 0xdf030000, 0xd4412e40, 0xd8400013, 0xcc41c030, 0xcc41c031, 0xc43dc031, 0xccc00013, 0x04343000,
+ 0xc4113246, 0xc41d3245, 0xcf413267, 0x51100020, 0x7dd1c01a, 0xc4353267, 0x45dc0160, 0xc810001f,
+ 0x1b4c0057, 0x1b700213, 0x1b740199, 0x7f4f400a, 0x7f73400a, 0x55180020, 0x2198003f, 0xd1c00025,
+ 0xcf400024, 0xcd000026, 0xcd800026, 0xd8400027, 0x9bc00001, 0x248dfffe, 0xd8800013, 0xccc12e00,
+ 0x7c434001, 0x7c434001, 0x8c00142b, 0xc43c000e, 0x1af4007d, 0x2bfc0008, 0x33740003, 0x26d80001,
+ 0xcfc00013, 0x1ae8003e, 0x9680000c, 0xc4253277, 0x26680001, 0x96800009, 0x2a640002, 0xce413277,
+ 0xd8400013, 0xc4253348, 0xce413348, 0xc4253348, 0x96400001, 0xcfc00013, 0x9b400003, 0x958000d8,
+ 0x80000315, 0xc4253277, 0x04303000, 0x26680001, 0xcf013267, 0xc4193246, 0xc41d3245, 0xc4313267,
+ 0x96800041, 0x51980020, 0x1b342010, 0x7d9d801a, 0x1714000c, 0x25540800, 0x1b30c012, 0x459801b0,
+ 0x7d77400a, 0x7f37000a, 0x2b300000, 0xcf00001c, 0xd180001e, 0xd8400021, 0x04240010, 0x199c01e2,
+ 0x7e5e4002, 0x3e5c0004, 0x3e540002, 0xc428000f, 0x9a80ffff, 0x95c00006, 0xc80c0011, 0xc8140011,
+ 0x54d00020, 0x55580020, 0x80000282, 0x95400015, 0xc80c0011, 0x0a640002, 0x041c0001, 0x45980008,
+ 0x54d00020, 0x96400004, 0xc8140011, 0x45980004, 0x041c0000, 0xcf00001c, 0xd180001e, 0xd8400021,
+ 0xc428000f, 0x9a80ffff, 0x99c00003, 0xc8180011, 0x80000282, 0xc8140011, 0x55580020, 0x80000282,
+ 0x45980004, 0xc80c0011, 0xcf00001c, 0xd180001e, 0xd8400021, 0xc428000f, 0x9a80ffff, 0xc8100011,
+ 0xc8140011, 0x55580020, 0xd8400013, 0xccc1334e, 0xcd01334f, 0xcd413350, 0xcd813351, 0xd881334d,
+ 0xcfc00013, 0xc4193273, 0xc41d3275, 0xc40d3271, 0xc4113270, 0xc4153274, 0x50cc0020, 0x7cd0c01a,
+ 0x7cdcc011, 0x05900008, 0xcd00006a, 0xcdc0006b, 0xc41d3272, 0x7d594002, 0x54d00020, 0xd8800013,
+ 0xccc12e23, 0xcd012e24, 0xcdc12e25, 0xcfc00013, 0xc4193246, 0xc41d3245, 0xc4313267, 0x15540002,
+ 0x51980020, 0x7d9d801a, 0xc81c001f, 0x1b340057, 0x1b280213, 0x1b300199, 0x45980198, 0x7f37000a,
+ 0x7f2b000a, 0x55e40020, 0xcf000024, 0xd1800025, 0xcdc00026, 0xce400026, 0xd8400027, 0xcd40000d,
+ 0xcd40000a, 0xc40d3249, 0x20cc003c, 0xccc13249, 0xc4113274, 0xdd430000, 0xc01e0001, 0x29dc0002,
+ 0x04280000, 0xd8000036, 0xcc400078, 0xcc400078, 0x2d540002, 0x95400022, 0x078c0000, 0x07d40000,
+ 0x8c00120d, 0x8c001239, 0x8c001232, 0x04f80000, 0x057c0000, 0xcdc00013, 0xc414000d, 0xc41c0019,
+ 0x7dd5c005, 0x25dc0001, 0xd840007c, 0xd8400074, 0xd8400069, 0xc40c005e, 0x94c018a6, 0xd4412e22,
+ 0xd800007c, 0xc40c005e, 0x94c018a2, 0x95c00007, 0xc40c0019, 0x7cd4c005, 0x24cc0001, 0x94c00008,
+ 0x9680fffc, 0x800002e3, 0xc40c0057, 0x7cd0c002, 0x94c00003, 0x9680fffd, 0x800002e3, 0xd8000069,
+ 0xcfc00013, 0xcd013273, 0xcd013275, 0xd8000074, 0xc414005e, 0x9540188f, 0xcfc00013, 0xc40d3249,
+ 0xc013cfff, 0x7cd0c009, 0xccc13249, 0x9680000b, 0xc40c0077, 0x38d00001, 0x99000006, 0x04cc0002,
+ 0xdcc30000, 0xc40c005e, 0x94c01882, 0xd4400078, 0xd800000d, 0x80000304, 0x7c41c001, 0x7c41c001,
+ 0xd840002f, 0xc41c0015, 0x95c0ffff, 0xd8400030, 0xc41c0016, 0x95c0ffff, 0xd8000030, 0xc41c0016,
+ 0x99c0ffff, 0xd800002f, 0xc41c0015, 0x99c0ffff, 0xc81c001f, 0x49980198, 0x55e40020, 0x459801a0,
+ 0xcf000024, 0xd1800025, 0xcdc00026, 0xce400026, 0xd8400027, 0x04302000, 0xcfc00013, 0xcf013267,
+ 0xc4313267, 0x96800004, 0x97000001, 0xd8000036, 0x80000329, 0xd8800013, 0xcc812e00, 0x04302000,
+ 0xcfc00013, 0xcf013267, 0xc4313267, 0x97000001, 0xc4193256, 0xc42d3249, 0x16ec001f, 0xd8000028,
+ 0xd800002b, 0x1998003e, 0xcec00031, 0xd8000036, 0xd8000010, 0x97800004, 0xd8400010, 0xce00000a,
+ 0x1a18003e, 0xcd800008, 0x90000000, 0xc4380004, 0xd8400008, 0xd8400013, 0xd88130b8, 0x04100000,
+ 0x7d43c001, 0xcd400013, 0xc4093249, 0x1888003e, 0x94800015, 0xd8400074, 0x8c000671, 0xcd400013,
+ 0x9a400006, 0xc419324c, 0x259c0001, 0x1598001f, 0x95c0000d, 0x9580000c, 0x99000003, 0xd8400036,
+ 0x04100001, 0xc40c0021, 0x14d80011, 0x24dc00ff, 0x31e00002, 0x31dc0003, 0x9580fff0, 0x9a000003,
+ 0x99c00002, 0xd9c00036, 0x94800004, 0xd8000074, 0xc418005e, 0x95801827, 0xcf800008, 0x90000000,
+ 0xd8800036, 0x90000000, 0xd8c00036, 0xc424000b, 0x32640002, 0x9a400004, 0xc4180014, 0x9580ffff,
+ 0xd840002f, 0xc40c0021, 0x14dc0011, 0x95c0fffe, 0xccc00037, 0x8c000190, 0x90000000, 0xd8400008,
+ 0xd800006d, 0xc41d3246, 0xc4193245, 0x51dc0020, 0x7d9d801a, 0xd8400028, 0xd8400029, 0xc420000b,
+ 0x32200002, 0x9a0000ad, 0x04200032, 0xd9000010, 0xde030000, 0xd8400033, 0x04080000, 0xc43c0009,
+ 0x27fc0002, 0x97c0fffe, 0xc42c0015, 0x96c0ffff, 0xd800002e, 0xc42d3249, 0x1af4003e, 0x9740004d,
+ 0xc428000d, 0xc4080060, 0x7ca88005, 0x24880001, 0x7f4b4009, 0x97400046, 0xc4313274, 0xc4100057,
+ 0x7d33400c, 0x97400009, 0x28240100, 0x7e6a4004, 0xce400079, 0x1eecffdd, 0xcec13249, 0xcf013273,
+ 0xcf013275, 0x800003c3, 0xc429326f, 0x1aa80030, 0x96800006, 0x28240001, 0xc428000d, 0x06a80008,
+ 0x7e6a8004, 0xce800035, 0xc41d3272, 0x25cc0001, 0x10cc0004, 0x19e80042, 0x25dc0006, 0x11dc0001,
+ 0x7e8e800a, 0x7de9c00a, 0xc40d3271, 0xc4293270, 0x50cc0020, 0x7ce8c01a, 0x7cd30011, 0x11e80007,
+ 0x2aa80000, 0xce80001c, 0xd300001e, 0xd8400021, 0xc428000f, 0x9a80ffff, 0xc4300011, 0x1b30003f,
+ 0x33300000, 0xc4240059, 0x1660001f, 0x7e320009, 0xc0328000, 0x7e72400a, 0x0430000c, 0x9a000002,
+ 0x04300008, 0xc02ac000, 0x7d310002, 0x17300002, 0x2aa87600, 0x7cd0c011, 0xcdc00024, 0xd0c00025,
+ 0xce800026, 0x04280222, 0xce800026, 0x96000002, 0xce400026, 0xd8400027, 0xc4280058, 0x22ec003d,
+ 0xcec13249, 0xcd013273, 0xce813275, 0xd800007b, 0xc8380018, 0x57b00020, 0x04343108, 0xc429325d,
+ 0x040c3000, 0x13740008, 0x2374007e, 0x32a80003, 0xccc13267, 0xc40d3267, 0x18ec0057, 0x18e40213,
+ 0x18cc0199, 0x7cecc00a, 0x7ce4c00a, 0x94800003, 0xd4400078, 0x800003e7, 0x04200022, 0xde030000,
+ 0xccc00024, 0xd1800025, 0xcf400026, 0xd4400026, 0xd8400027, 0x04200010, 0xde030000, 0xccc00024,
+ 0x45980104, 0xd1800025, 0xd4400026, 0xcf800026, 0xcf000026, 0xd8400027, 0x49980104, 0x9a80000a,
+ 0xc81c001f, 0x45980168, 0x55e00020, 0xccc00024, 0xd1800025, 0xcdc00026, 0xce000026, 0xd8400027,
+ 0x800003f2, 0x8c000448, 0xcd400013, 0x040c2000, 0xccc13267, 0xc40d3267, 0x94c00001, 0xc40d3249,
+ 0x18cc003e, 0xd8400030, 0xc42c0016, 0x96c0ffff, 0xd8000030, 0xc42c0016, 0x9ac0ffff, 0xd800002f,
+ 0xc42c0015, 0x9ac0ffff, 0xd8400034, 0xc4300025, 0xc4340024, 0xc4380081, 0xcf813279, 0xcf41326e,
+ 0xcf01326d, 0x94c0000d, 0x254c0700, 0xc424001e, 0x10cc0010, 0x1a641fe8, 0x28cc0726, 0x2a640200,
+ 0xd8400013, 0xccc1237b, 0x2264003f, 0xcd400013, 0xd8813260, 0xce41325b, 0xc4240033, 0xc4280034,
+ 0xd9000036, 0xd8000010, 0x8c001427, 0x96400006, 0xde430000, 0xce40000c, 0xc40c005e, 0x94c01755,
+ 0xd4400078, 0x9680000a, 0xce80000a, 0x06a80002, 0xd8400010, 0xde830000, 0xce80000d, 0xc40c005e,
+ 0x94c0174c, 0xd4400078, 0xd8000010, 0x8c00142b, 0xc4393265, 0x2bb80040, 0xd8400032, 0xcf813265,
+ 0xc4200012, 0x9a00ffff, 0xc4100044, 0x19180024, 0xc8100072, 0x551c003f, 0x99c00003, 0x95800010,
+ 0x8000043d, 0xc00c8000, 0xd840006c, 0x28200000, 0x8000043f, 0xc00c4000, 0x282000f0, 0xcd400013,
+ 0xd8400008, 0xc4113255, 0xcd01324f, 0xd8400013, 0xd88130b8, 0xccc130b5, 0xce000053, 0x90000000,
+ 0x195c00e8, 0xc4100004, 0x2555fff0, 0xc0360001, 0x042c0000, 0x29540001, 0xd8400008, 0x04240000,
+ 0x04280004, 0xc420000b, 0x32200002, 0x9a000009, 0xcd400013, 0xcec1c200, 0xc5e124dc, 0x0aa80001,
+ 0x7ef6c001, 0x7e624001, 0x96000001, 0x9a80fff9, 0xc02ee000, 0xcd400013, 0x2555fff0, 0xcec1c200,
+ 0x29540008, 0xc81c001f, 0xcd400013, 0x55e00020, 0xc42d3255, 0xc4353259, 0xd8013260, 0x45980158,
+ 0xccc00024, 0xd1800025, 0xcdc00026, 0xce000026, 0xd8400027, 0x49980158, 0x45980170, 0xc4200012,
+ 0x16200010, 0x9a00fffe, 0xccc00024, 0xd1800025, 0xc429324f, 0xce400026, 0xce800026, 0xcec00026,
+ 0xcf400026, 0xd8400027, 0xcd000008, 0x90000000, 0xc40d325b, 0x7d43c001, 0x195400e8, 0x1154000a,
+ 0x18dc00e8, 0x05e80488, 0x18d0006c, 0x18f807f0, 0x18e40077, 0x18ec0199, 0x7e6e400a, 0x86800000,
+ 0x8000048e, 0x80000494, 0x800004de, 0x80000685, 0x80000686, 0x800006ac, 0x1ccc001f, 0xccc1325b,
+ 0xc411325d, 0x251001ef, 0xcd01325d, 0x90000000, 0xc4293254, 0x1264000a, 0xc4300004, 0x7d79400a,
+ 0x7e7a400a, 0x52a8001e, 0x15180001, 0x7d69401a, 0x202c007d, 0xcec1325b, 0x95000008, 0x95800028,
+ 0xc42d3267, 0xc4193246, 0xc41d3245, 0x1aec0028, 0xc40d325c, 0x800004cc, 0xc42d3256, 0xc419324e,
+ 0x26e8003f, 0x1aec003e, 0x12f4000e, 0xc41d324d, 0xc40d324f, 0x7d75401a, 0x04100002, 0x7d290004,
+ 0x7f8f4001, 0x7f52800f, 0x51980020, 0x7d9d801a, 0x50e00002, 0x51980008, 0x9a800002, 0x800004d1,
+ 0x7d0dc002, 0x6665fc00, 0x7e5e401a, 0xcec00008, 0x7da1c011, 0xd140000b, 0xd1c00002, 0x2a644000,
+ 0xce400002, 0x7f534002, 0x6665fc00, 0x7e76401a, 0xd1800002, 0xce400002, 0x800004d7, 0xc42d325a,
+ 0xc4193258, 0x1aec003e, 0xc41d3257, 0xc4213259, 0x12f4000e, 0x7d75401a, 0x51980020, 0x52200002,
+ 0x7d9d801a, 0xcec00008, 0x7da1c011, 0xd140000b, 0xd1c00002, 0x2a644000, 0xce400002, 0x202c003d,
+ 0xcf000008, 0xcfc00013, 0xcec1325b, 0xc42d325b, 0x96c00001, 0x90000000, 0xc4193260, 0x259c0007,
+ 0x15980004, 0x05e804e3, 0x86800000, 0x800004e7, 0x800004f0, 0x80000505, 0x8000016a, 0xc4380004,
+ 0xcfc00013, 0xd8400008, 0xc435325d, 0xd801325b, 0x277401ef, 0xcf41325d, 0xcf800008, 0x90000000,
+ 0xc4380004, 0xd8400008, 0x8c000671, 0x9640fff4, 0x17e00008, 0xc418000d, 0xce000009, 0xd84131db,
+ 0xcf800008, 0xcd800009, 0xc430001e, 0xcfc00013, 0xc42d325b, 0x1b301ff8, 0x2b300400, 0x2330003f,
+ 0x26edf000, 0x7ef2c00a, 0xd8413260, 0xcec1325b, 0x90000000, 0x05a80507, 0x86800000, 0x8000050c,
+ 0x80000528, 0x8000057d, 0x800005c2, 0x800005f3, 0xc4380004, 0xd8400008, 0x8c000671, 0xcfc00013,
+ 0x9a400012, 0x1bd400e8, 0xc42c004a, 0xcd40005e, 0xc41c004d, 0xcec0005e, 0x99c0000c, 0xc4100019,
+ 0x7d150005, 0x25100001, 0x99000008, 0x8c00063b, 0xcfc00013, 0xc4113277, 0x2511fffd, 0xcd013277,
+ 0xd801326f, 0x80000624, 0x04240012, 0x1be00fe4, 0xce413260, 0xce000066, 0xcf800008, 0x90000000,
+ 0xd8400068, 0xc4380004, 0xd8400008, 0x8c000671, 0xcfc00013, 0x9a400013, 0x1bd400e8, 0xc42c004a,
+ 0xcd40005e, 0xc41c004d, 0xcec0005e, 0x99c0000d, 0xc4100019, 0x7d150005, 0x25100001, 0x99000009,
+ 0xd8400067, 0x8c00063b, 0xcfc00013, 0xc4113277, 0x2511fffd, 0xcd013277, 0xd801326f, 0x80000624,
+ 0x1bd400e8, 0xc42c0060, 0x7ed6c005, 0x26ec0001, 0xc4113271, 0xc4153270, 0xc4193272, 0xc41d3273,
+ 0x04280022, 0x51100020, 0x7d51401a, 0xc4113274, 0xc4213275, 0xc4253276, 0xc4313248, 0xd1400061,
+ 0x2730000f, 0x13300010, 0x7db1800a, 0xcd800060, 0x96c00002, 0x05dc0008, 0xcdc00062, 0x042c3000,
+ 0xcd000063, 0xce000064, 0xce400065, 0xcec13267, 0xc42d3246, 0xc4313245, 0xc4353267, 0xce813260,
+ 0x52ec0020, 0x7ef2c01a, 0xc820001f, 0x1b700057, 0x1b680213, 0x1b740199, 0x46ec0188, 0x7f73400a,
+ 0x7f6b400a, 0x56240020, 0xcf400024, 0xd2c00025, 0xce000026, 0xce400026, 0x042c2000, 0xd8400027,
+ 0xc418000d, 0x17e00008, 0xce000009, 0xcec13267, 0xc42d3267, 0x26e01000, 0x9a00fffe, 0xd8400013,
+ 0xd9c131fc, 0xcd800009, 0xcf800008, 0x96c00001, 0x90000000, 0xc4380004, 0xd8400008, 0xc4113277,
+ 0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001, 0x11dc0008, 0x29dc0001, 0x25140001, 0x191807e4,
+ 0x192007ec, 0x95400004, 0xd8400013, 0xcdc1334a, 0xcfc00013, 0x9580000e, 0x09980001, 0x041c0001,
+ 0x95800005, 0x09980001, 0x51dc0001, 0x69dc0001, 0x9980fffd, 0x7de20014, 0x561c0020, 0xd8400013,
+ 0xce013344, 0xcdc13345, 0xcfc00013, 0x95400022, 0x042c3000, 0xcec13267, 0xc42d3246, 0xc4313245,
+ 0xc4353267, 0xd8400013, 0xc425334d, 0x26640001, 0x9640fffe, 0xc419334e, 0xc41d334f, 0xc4213350,
+ 0xc4253351, 0x52ec0020, 0x1b680057, 0x7ef2c01a, 0x1b700213, 0x1b740199, 0x46ec01b0, 0x7f6b400a,
+ 0x7f73400a, 0xcfc00013, 0xcf400024, 0xd2c00025, 0xcd800026, 0xcdc00026, 0xce000026, 0xce400026,
+ 0x042c2000, 0xd8400027, 0xcec13267, 0xc42d3267, 0x96c00001, 0x04280032, 0xce813260, 0xd8800068,
+ 0xcf800008, 0x90000000, 0xc4380004, 0xd8400008, 0x2010007d, 0xcd01325b, 0xc411325b, 0x1910003e,
+ 0x9500fffe, 0x04100040, 0xcd00001b, 0xd8400021, 0xc410000f, 0x9900ffff, 0x04100060, 0xcd00001b,
+ 0xd8400021, 0xc410000f, 0x9900ffff, 0xcfc00013, 0x2010003d, 0xcd01325b, 0xc4113277, 0x25140001,
+ 0x191807e4, 0x9540000b, 0x2511fffd, 0xcd013277, 0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001,
+ 0x11dc0008, 0xd8400013, 0xcdc1334a, 0xcfc00013, 0x95800005, 0xd8400013, 0xd8013344, 0xd8013345,
+ 0xcfc00013, 0xc4180050, 0xc41c0052, 0x04280042, 0xcd813273, 0xcdc13275, 0xce813260, 0xd9000068,
+ 0xd8400067, 0xcf800008, 0x90000000, 0x07d40000, 0x8c00120d, 0x8c00124f, 0x8c001232, 0x057c0000,
+ 0x042c3000, 0xc4380004, 0xcfc00013, 0xd8400008, 0xcec13267, 0xc42d3246, 0xc4313245, 0xc4353267,
+ 0x52ec0020, 0x7ef2c01a, 0x1b680057, 0x1b700213, 0x1b740199, 0xc820001f, 0x46ec0190, 0x7f6b400a,
+ 0x7f73400a, 0x56240020, 0xcf400024, 0xd2c00025, 0xce000026, 0xce400026, 0x042c2000, 0xd8400027,
+ 0xcfc00013, 0xcec13267, 0xc4153249, 0x2154003d, 0xc41c0019, 0x1bd800e8, 0x7dd9c005, 0x25dc0001,
+ 0xc42c004a, 0xcd80005e, 0xc420004d, 0xcec0005e, 0x11dc0010, 0x7e1e000a, 0xcd413249, 0xce01326f,
+ 0x28340001, 0x05980008, 0x7f598004, 0xcd800035, 0x1be800e8, 0xc42c004a, 0xce80005e, 0xd801327a,
+ 0xd800005f, 0xd8000075, 0xd800007f, 0xc424004c, 0xce41326e, 0xcec0005e, 0x28240100, 0x7e6a4004,
+ 0xce400079, 0xc435325d, 0x277401ef, 0x04240020, 0xce41325e, 0xd801325b, 0xd8013260, 0xcf41325d,
+ 0xda000068, 0xcf800008, 0x90000000, 0xc4113277, 0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001,
+ 0x11dc0008, 0x29dc0001, 0x25140001, 0x9540002d, 0xd8400013, 0xcdc1334a, 0xcfc00013, 0x042c3000,
+ 0xcec13267, 0xc42d3246, 0xc4313245, 0xc4353267, 0xd8400013, 0xc425334d, 0x26640001, 0x9640fffe,
+ 0xc419334e, 0xc41d334f, 0xc4213350, 0xc4253351, 0x52ec0020, 0x1b680057, 0x7ef2c01a, 0x1b700213,
+ 0x1b740199, 0x46ec01b0, 0x7f6b400a, 0x7f73400a, 0xcfc00013, 0xcf400024, 0xd2c00025, 0xcd800026,
+ 0xcdc00026, 0xce000026, 0xce400026, 0x042c2000, 0xd8400027, 0xcec13267, 0xc42d3267, 0x96c00001,
+ 0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001, 0x11dc0008, 0xd8400013, 0xcdc1334a, 0xcfc00013,
+ 0x90000000, 0xc430000b, 0x33300002, 0x04240000, 0x9b000010, 0x1be000e8, 0x042c0000, 0xc0360001,
+ 0x04280004, 0xd8400013, 0xcec1c200, 0xc63124dc, 0x0aa80001, 0x7ef6c001, 0x7e724001, 0x97000001,
+ 0x9a80fff9, 0xc02ee000, 0xd8400013, 0xcec1c200, 0x90000000, 0x90000000, 0xc4253260, 0x7fc14001,
+ 0xc40d3249, 0x18cc003e, 0x98c00005, 0x194c1c03, 0xccc0003b, 0xc40c002d, 0x80000697, 0xc420004a,
+ 0x194c00e8, 0xccc0005e, 0xc40c004c, 0xc431326d, 0x27301fff, 0xce00005e, 0x7cf0c00d, 0x98c00003,
+ 0x8c0007e0, 0x95c00008, 0xc430001e, 0x1b301ff8, 0x2b300400, 0x2330003f, 0xcd400013, 0xcf01325b,
+ 0x90000000, 0xcd400013, 0xd801325b, 0xc411325d, 0x251001ef, 0xcd01325d, 0x25100007, 0x31100005,
+ 0x9900008e, 0xc40c0007, 0xd9000010, 0x8000075e, 0x202c007d, 0xcec1325b, 0xc4293265, 0xc4353254,
+ 0x26a9feff, 0xc4380004, 0xd8400008, 0x1374000b, 0xc40c000d, 0xd8000009, 0x1774000d, 0xd8400013,
+ 0xc41d30b8, 0xcfc00013, 0x95c00008, 0xc411325d, 0xd801325b, 0xccc00009, 0xcf800008, 0x251001ef,
+ 0xcd01325d, 0x90000000, 0xce813265, 0xcf400100, 0xc00ac006, 0xc00e0000, 0x28880700, 0x28cc0014,
+ 0x8c0006de, 0x14cc0010, 0x30d4000f, 0x04cc0001, 0x10cc0010, 0x28cc0014, 0x99400009, 0xd8400013,
+ 0xc41530b8, 0xcfc00013, 0xc4193265, 0x19980028, 0x99400003, 0x99800002, 0x800006c8, 0xcfc00013,
+ 0xc411325d, 0xd801325b, 0xcf800008, 0x251001ef, 0xcd01325d, 0x90000000, 0x15600008, 0xce000009,
+ 0xc8380023, 0xc4180081, 0x11a00002, 0x7fa38011, 0xc4100026, 0x05980008, 0x7d1a0002, 0x282c2002,
+ 0x3e280008, 0xcec00013, 0xc4300027, 0x042c0008, 0xd3800025, 0xcf000024, 0x202400d0, 0x7ca48001,
+ 0xcc800026, 0xccc00026, 0x28240006, 0xcc000026, 0x0a640001, 0x9a40fffe, 0x9a800004, 0x32280000,
+ 0x9a800002, 0x9a000000, 0xd8400027, 0x24d8003f, 0xd840003c, 0xcec0003a, 0xd8800013, 0xcd81a2a4,
+ 0x90000000, 0xc41d325d, 0x25dc0007, 0xc40d3249, 0x18cc003e, 0x94c0000a, 0xc420004a, 0x194c00e8,
+ 0xccc0005e, 0xc40c004c, 0xc431326d, 0x27301fff, 0xce00005e, 0x7cf0c00d, 0x80000712, 0x194c1c03,
+ 0xccc0003b, 0xc40c002d, 0x05e80714, 0x86800000, 0x8000071c, 0x80000720, 0x80000747, 0x8000071d,
+ 0x800007c4, 0x80000732, 0x80000745, 0x80000744, 0x90000000, 0x98c00006, 0x8000072e, 0x90000000,
+ 0x98c00003, 0x8c0007e0, 0x95c0000c, 0xcd400013, 0xc4253265, 0x2a64008c, 0xce413265, 0xc430001e,
+ 0x1b301fe8, 0x2b300400, 0x2330003f, 0xd8013260, 0xcf01325b, 0x90000000, 0xc40c0007, 0xd9000010,
+ 0x04240000, 0x8000075e, 0x98c0fff1, 0x8c0007e0, 0x95c00002, 0x80000723, 0xcd400013, 0xc41f02f1,
+ 0x95c00004, 0xd8013247, 0xd801325d, 0x80000743, 0xd8813247, 0xd801325d, 0xc4100004, 0xd8400008,
+ 0xd8400013, 0xd88130b8, 0xcd000008, 0x90000000, 0x04100001, 0x98c0ffde, 0x8000072e, 0x98c00003,
+ 0x8c0007e0, 0x95c00012, 0xc4340004, 0xd8400008, 0x15600008, 0xc418000d, 0xce000009, 0xd8400013,
+ 0xd84131db, 0xcf400008, 0xcd800009, 0xc430001e, 0x1b301ff8, 0x2b300400, 0x2330003f, 0xcd400013,
+ 0xd8413260, 0xcf01325b, 0x90000000, 0xc40c0007, 0xd9000010, 0x04240000, 0xcd400013, 0x041c3000,
+ 0xcdc13267, 0xc41d3267, 0xc41d3265, 0x25dc8000, 0x95c00007, 0xc41c004a, 0x195800e8, 0xcd80005e,
+ 0xc418004c, 0xcd81326e, 0xcdc0005e, 0xc41d3265, 0x25dd7fff, 0xcdc13265, 0xc41d3246, 0xc4193245,
+ 0xc42d3267, 0x51e00020, 0x7e1a001a, 0x46200200, 0x04283247, 0x04300033, 0x1af80057, 0x1af40213,
+ 0x042c000c, 0x7f7b400a, 0x7f6f400a, 0xcf400024, 0xd2000025, 0xcd800026, 0xcdc00026, 0xc6990000,
+ 0x329c325d, 0x99c00008, 0x329c3269, 0x99c00006, 0x329c3267, 0x95c00005, 0xc01defff, 0x7d9d8009,
+ 0x8000078a, 0x25980000, 0x0b300001, 0x06a80001, 0xcd800026, 0x9b00fff2, 0xd8400027, 0xc43c0012,
+ 0x9bc0ffff, 0xcd400013, 0xd801325b, 0xc431325a, 0xc03e7ff0, 0x7f3f0009, 0xcf01325a, 0xc4313249,
+ 0x1f30001f, 0xcf013249, 0xc03e4000, 0xcfc13254, 0xcd400013, 0xd8013254, 0xc431325d, 0xd801324f,
+ 0xd8013255, 0xd8013247, 0xd801325d, 0x1b300028, 0x8c00120d, 0x8c001219, 0x8c001232, 0xc4380004,
+ 0xd8400008, 0xd8400013, 0x9900000d, 0xd88130b8, 0x9700000b, 0xc43d30b5, 0x1bf0003a, 0x9b000b80,
+ 0x203c003a, 0xc430000e, 0x27300700, 0x13300014, 0x2b300001, 0xcf0130b7, 0xcfc130b5, 0x46200008,
+ 0xcf400024, 0xd2000025, 0xd8000026, 0xd8400027, 0x043c2000, 0xcd400013, 0xcfc13267, 0xc43d3267,
+ 0x9bc00001, 0xccc00010, 0xcf800008, 0x90000000, 0xc4080007, 0xd9000010, 0xc4193260, 0x259c0003,
+ 0x31dc0003, 0x95c00014, 0x040c3000, 0xd8400008, 0xccc13267, 0xc40d3267, 0x18ec0057, 0x18e40213,
+ 0x18cc0199, 0x7cecc00a, 0x7ce4c00a, 0xc4193246, 0xc41d3245, 0x51980020, 0x7d9d801a, 0x8c000448,
+ 0xcd400013, 0x040c2000, 0xccc13267, 0xc40d3267, 0x94c00001, 0xcc800010, 0xd801325d, 0x90000000,
+ 0xc418000b, 0x31980002, 0x041c0000, 0x9980001c, 0x19580066, 0x15600008, 0x040c0000, 0xc0120001,
+ 0x11980003, 0x04240004, 0x7da18001, 0xc4200007, 0xc4340004, 0xd9000010, 0xd8400008, 0xd8400013,
+ 0xccc1c200, 0xc41d24db, 0x7cd0c001, 0x0a640001, 0x7dd9c005, 0x25dc0001, 0x99c00002, 0x9a40fff8,
+ 0xc418005e, 0x9580137b, 0xc00ee000, 0xd8400013, 0xccc1c200, 0xce000010, 0xcf400008, 0x90000000,
+ 0xd840004f, 0xc4113269, 0x19080070, 0x190c00e8, 0x2510003f, 0x2518000f, 0xcd813268, 0x05a80809,
+ 0x86800000, 0x8000080e, 0x8000080f, 0x80000898, 0x80000946, 0x800009e1, 0x80000a5a, 0x04a80811,
+ 0x86800000, 0x80000815, 0x80000834, 0x8000085e, 0x8000085e, 0x04341001, 0xcf400013, 0xc4380004,
+ 0xd8400008, 0xc42d3045, 0xcec1c091, 0x31300021, 0x9700000b, 0xd84002f1, 0xd8400013, 0xc43130b8,
+ 0x27300001, 0xc4293059, 0x56a8001f, 0x7f2b000a, 0xcf800008, 0x9b000241, 0x8000084a, 0xcf400013,
+ 0xd8400008, 0xc43130b6, 0x9b000003, 0xc02f0001, 0xcec130b6, 0xc4252087, 0x5668001a, 0x26a80005,
+ 0x9a80fffd, 0xcf400013, 0xd80130b6, 0x8000084a, 0xc4380004, 0xd8400008, 0x04341001, 0xcf400013,
+ 0xc431ecaa, 0x27300080, 0x9b000010, 0xc02e0001, 0xcec130b6, 0xcf400013, 0xd80130b6, 0x31300021,
+ 0x9700000a, 0xd84002f1, 0xd8400013, 0xc43130b8, 0x27300001, 0xc4293059, 0x56a8001f, 0x7f2b000a,
+ 0xcf800008, 0x9b00021d, 0xdd410000, 0x040c0005, 0xd84802e9, 0x8c001a41, 0xc43b02f1, 0x9b800006,
+ 0xc4380004, 0xd8400008, 0xd8400013, 0xd88130b8, 0xcf800008, 0xcec80278, 0x56f00020, 0xcf080280,
+ 0x8c001608, 0xdc140000, 0xcd400013, 0xd8813247, 0xd80802e9, 0x8000085e, 0xcd400013, 0x31100011,
+ 0x950001fa, 0xc02e0001, 0x2aec0008, 0xc01c0020, 0xc0180001, 0xc00c0007, 0x11a40006, 0x7de6000a,
+ 0x10e40008, 0x7e26000a, 0x7e2e000a, 0xce000013, 0xc4113254, 0x1d10ffdf, 0x2110003e, 0xcd013254,
+ 0xd801324f, 0xd8013255, 0x1d10ff9e, 0xcd013254, 0xd8013247, 0xd801325d, 0xd801325e, 0xc0245301,
+ 0xce413249, 0xd801325f, 0xc425326c, 0xc0121fff, 0x29108eff, 0x7e524009, 0xce41326c, 0xc425325a,
+ 0xc0127ff0, 0x7e524009, 0xce41325a, 0xc425325b, 0xc0131fff, 0x7e524009, 0xce41325b, 0xd801326d,
+ 0xd801326e, 0xd8013279, 0x94c00003, 0x08cc0001, 0x80000866, 0xc00c0007, 0x95800003, 0x09980001,
+ 0x80000866, 0xc0100010, 0x7dd2400c, 0x9a400004, 0xc0180003, 0x7dd1c002, 0x80000866, 0x80000a5a,
+ 0x04a8089a, 0x86800000, 0x8000089e, 0x800008fa, 0x80000945, 0x80000945, 0x31300022, 0x97000007,
+ 0xc4380004, 0xd8400008, 0xd8400013, 0xc43130b8, 0x27300001, 0xcf800008, 0xcd400013, 0x04183000,
+ 0xcd813267, 0xc4113246, 0xc4193245, 0x51100020, 0x7d91801a, 0x459801e0, 0xc4313267, 0x2738000f,
+ 0x1b342010, 0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c,
+ 0xd180001e, 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8300011, 0x97000036, 0x45980008, 0xd180001e,
+ 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8340011, 0x9740002f, 0xc43c0004, 0xd8400008, 0xd8400013,
+ 0x13b80001, 0xc79d3300, 0xc7a13301, 0x96000001, 0xd8393300, 0xc0260001, 0xce793301, 0xc424005e,
+ 0x964012a4, 0x7c028009, 0x9740001c, 0x27580001, 0x99800004, 0x57740001, 0x06a80400, 0x800008d2,
+ 0xc4180006, 0x9980ffff, 0x29640001, 0xce40001a, 0x242c0000, 0x06ec0400, 0x57740001, 0x27580001,
+ 0x9980fffd, 0xc02620c0, 0xce41c078, 0xce81c080, 0xcc01c081, 0xcf01c082, 0x57240020, 0xce41c083,
+ 0xc0260400, 0x7e6e400a, 0xce41c084, 0x7eae8001, 0x7f2f0011, 0x800008d2, 0xc4180006, 0x9980ffff,
+ 0xcdf93300, 0xce393301, 0xcfc00008, 0xcd400013, 0xc43c0004, 0xd8400008, 0x04182000, 0xcd813267,
+ 0xcfc00008, 0x80000903, 0x31240022, 0x96400008, 0x04100001, 0xc4380004, 0xd8400008, 0xd8400013,
+ 0xc43130b8, 0x27300001, 0xcf800008, 0xc4af0280, 0xc4b30278, 0x52ec0020, 0x7ef2c01a, 0x7ec30011,
+ 0x32f80000, 0x9b800011, 0x043c0020, 0x04280000, 0x67180001, 0x0bfc0001, 0x57300001, 0x95800006,
+ 0x8c001628, 0x9a400003, 0xd981325d, 0x80000915, 0xd9c1325d, 0x06a80001, 0x9bc0fff6, 0x7f818001,
+ 0x8c001606, 0x7d838001, 0x94800010, 0xcd400013, 0xc41d3259, 0xc421325a, 0x16240014, 0x12640014,
+ 0x1a2801f0, 0x12a80010, 0x2620ffff, 0x7e2a000a, 0x7de1c001, 0x7e5e400a, 0x9b800002, 0x2264003f,
+ 0xce41325a, 0xd8013259, 0xc40c0007, 0xd9000010, 0x8c00075e, 0xc4af0228, 0x043c0000, 0x66d80001,
+ 0x95800010, 0x04300002, 0x1330000d, 0x13f40014, 0x7f73400a, 0xcf400013, 0x04380040, 0xcf80001b,
+ 0xd8400021, 0xc438000f, 0x9b80ffff, 0x04380060, 0xcf80001b, 0xd8400021, 0xc438000f, 0x9b80ffff,
+ 0x07fc0001, 0x56ec0001, 0x33e80010, 0x9680ffec, 0x80000a5a, 0x80000a5a, 0x04a80948, 0x86800000,
+ 0x8000094c, 0x8000099b, 0x800009e0, 0x800009e0, 0xc43c0004, 0xd8400008, 0xcd400013, 0x04183000,
+ 0xcd813267, 0xc4113246, 0xc4193245, 0x51100020, 0x7d91801a, 0x459801e0, 0xc4313267, 0x2738000f,
+ 0x1b342010, 0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c,
+ 0xd180001e, 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8300011, 0x97000033, 0x45980008, 0xd180001e,
+ 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8340011, 0x9740002c, 0xd8400013, 0x13b80001, 0xc79d3300,
+ 0xc7a13301, 0x96000001, 0xd8393300, 0xc0260001, 0xce793301, 0xc424005e, 0x964011fe, 0x7c028009,
+ 0x9740001c, 0x27580001, 0x99800004, 0x57740001, 0x06a80400, 0x80000978, 0xc4180006, 0x9980ffff,
+ 0x29640001, 0xce40001a, 0x242c0000, 0x06ec0400, 0x57740001, 0x27580001, 0x9980fffd, 0xc0260010,
+ 0xce41c078, 0xcf01c080, 0x57240020, 0xce41c081, 0xce81c082, 0xcc01c083, 0xc0260800, 0x7e6e400a,
+ 0xce41c084, 0x7eae8001, 0x7f2f0011, 0x80000978, 0xc4180006, 0x9980ffff, 0xcdf93300, 0xce393301,
+ 0x04182000, 0xcd813267, 0xcfc00008, 0xcd400013, 0xc4193246, 0xc41d3245, 0x51980020, 0x7dda801a,
+ 0x7d41c001, 0x7e838011, 0xd84802e9, 0x8c001802, 0x469c0390, 0xc4313267, 0x04183000, 0xcd813267,
+ 0x1b342010, 0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c,
+ 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4200011, 0x45dc0004, 0xd1c0001e,
+ 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4240011, 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f,
+ 0x9980ffff, 0xc4280011, 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc42c0011,
+ 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4300011, 0x45dc0004, 0xd1c0001e,
+ 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4340011, 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f,
+ 0x9980ffff, 0xc4380011, 0xcd400013, 0x04182000, 0xcd813267, 0x043c0001, 0x8c0014df, 0x80000a5a,
+ 0x80000a5a, 0x31280014, 0xce8802ef, 0x9a800062, 0x31280034, 0x9a800060, 0x04a809e8, 0x86800000,
+ 0x800009ec, 0x80000a45, 0x80000a59, 0x80000a59, 0xcd400013, 0xc4113246, 0xc4193245, 0x51100020,
+ 0x7d91801a, 0x45980400, 0xc4b30258, 0xc4a70250, 0x53300020, 0x7e72401a, 0xc4313267, 0x1b342010,
+ 0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c, 0x042c0020,
+ 0x66740001, 0x97400041, 0xcd400013, 0x04383000, 0xcf813267, 0xc4393267, 0x9b800001, 0xd180001e,
+ 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4300011, 0x1b38007e, 0x33b40003, 0x9b400003, 0x4598001c,
+ 0x9740002f, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc40c0011, 0x45980004,
+ 0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4100011, 0x45980004, 0xd180001e, 0xd8400021,
+ 0xc438000f, 0x9b80ffff, 0xc4340011, 0xcf4002eb, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f,
+ 0x9b80ffff, 0xc4340011, 0xcf4002ec, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff,
+ 0xc4340011, 0xcf4002ed, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4340011,
+ 0xcf4002ee, 0x45980004, 0xcd400013, 0x04382000, 0xcf813267, 0xd84802e9, 0x8c001715, 0xcd400013,
+ 0x04382000, 0xcf813267, 0x56640001, 0x0aec0001, 0x9ac0ffbc, 0xc4380004, 0xd8400008, 0x04341001,
+ 0xcf400013, 0x94800005, 0xc431ecaa, 0x27300080, 0x97000002, 0x80000a55, 0xc43130b6, 0x233c0032,
+ 0xcfc130b6, 0xcf400013, 0xcf0130b6, 0xc49302ef, 0x99000003, 0xcd400013, 0xd8413247, 0xcf800008,
+ 0x80000a5a, 0x80000a5a, 0xcd400013, 0x04180001, 0x5198001f, 0xcd813268, 0xc4193269, 0x2598000f,
+ 0x9980fffe, 0xd80002f1, 0xcd400013, 0xd8013268, 0xd800004f, 0x90000000, 0xcd400013, 0x04380001,
+ 0x53b8001f, 0x7db9801a, 0xcd813268, 0x80000a5e, 0xd8400029, 0xc40c005e, 0x94c01106, 0xd8800013,
+ 0xcc412e01, 0xcc412e02, 0xcc412e03, 0xcc412e00, 0x80000aa7, 0xd8400029, 0xc40c005e, 0x94c010fd,
+ 0x7c40c001, 0x50640020, 0x7ce4c01a, 0xd0c00072, 0xc80c0072, 0x58e801fc, 0x12a80009, 0x2aa80000,
+ 0xd0c0001e, 0xce80001c, 0xd8400021, 0xc424000f, 0x9a40ffff, 0x04240010, 0x18dc01e2, 0x7e5e4002,
+ 0x3e5c0003, 0x3e540002, 0x95c00006, 0xc8180011, 0xc8100011, 0xc8100011, 0x55140020, 0x80000aa2,
+ 0x9540000a, 0xc8180011, 0x44cc0008, 0x55900020, 0xd0c0001e, 0xd8400021, 0xc424000f, 0x9a40ffff,
+ 0xc4140011, 0x80000aa2, 0x44cc0004, 0xc4180011, 0xd0c0001e, 0xd8400021, 0xc424000f, 0x9a40ffff,
+ 0xc8100011, 0x55140020, 0xd8800013, 0xcd812e01, 0xcd012e02, 0xcd412e03, 0xcc412e00, 0xc428000e,
+ 0x2aa80008, 0xce800013, 0xc4253249, 0x2264003f, 0xce413249, 0xce800013, 0xc4253249, 0x96400001,
+ 0xd800002a, 0xc410001a, 0xc40c0021, 0xc4140028, 0x95000005, 0x1e64001f, 0xce800013, 0xce413249,
+ 0x80001b70, 0x14d00010, 0xc4180030, 0xc41c0007, 0x99000004, 0x99400009, 0x9980000c, 0x80000ab1,
+ 0xccc00037, 0x8c000190, 0xc420001c, 0xd8000032, 0x9a0010ac, 0x80000aa7, 0xd880003f, 0x95c00002,
+ 0xd8c0003f, 0x80001082, 0xd8800040, 0x95c00002, 0xd8c00040, 0x800010de, 0xc010ffff, 0x18d403f7,
+ 0x7d0cc009, 0xc41b0367, 0x7d958004, 0x7d85800a, 0xdc1e0000, 0x90000000, 0xc424000b, 0x32640002,
+ 0x7c40c001, 0x18d001fc, 0x05280adc, 0x86800000, 0x80000af1, 0x80000adf, 0x80000ae7, 0x8c000ace,
+ 0xd8c00013, 0x96400002, 0xd8400013, 0xcd8d2000, 0x99c00010, 0x7c408001, 0x88000000, 0x18d803f7,
+ 0xc010ffff, 0x7d0cc009, 0x04140000, 0x11940014, 0x29544001, 0x9a400002, 0x29544003, 0xcd400013,
+ 0x80000af4, 0xd8c00013, 0x96400002, 0xd8400013, 0xd44d2000, 0x7c408001, 0x88000000, 0xc424000b,
+ 0x32640002, 0x7c40c001, 0xd8c00013, 0x96400002, 0xd8400013, 0xd44dc000, 0x7c408001, 0x88000000,
+ 0x7c40c001, 0x18d0003c, 0x95000006, 0x8c000ace, 0xd8800013, 0xcd8d2c00, 0x99c00003, 0x80000b0a,
+ 0xd8800013, 0xd44d2c00, 0x7c408001, 0x88000000, 0x7c40c001, 0x28148004, 0x24d800ff, 0xccc00019,
+ 0xcd400013, 0xd4593240, 0x7c408001, 0x88000000, 0xd8400029, 0xc40c005e, 0x94c0105e, 0x7c410001,
+ 0x50540020, 0x7c418001, 0x2198003f, 0x199c0034, 0xc40c0007, 0x95c00028, 0xc428000e, 0x2aa80008,
+ 0xce800013, 0xc42d324f, 0xc4313255, 0x7ef3400c, 0x9b400021, 0xd800002a, 0x80001b70, 0xc40c0007,
+ 0x14e80001, 0x9a8000af, 0xd9000010, 0x041c0002, 0x042c01c8, 0x8c000d61, 0xccc00010, 0xd8400029,
+ 0xc40c005e, 0x94c01043, 0x7c410001, 0x50540020, 0x7c418001, 0x18a01fe8, 0x3620005c, 0x9a00000e,
+ 0x2464003f, 0xd8400013, 0xc6290ce7, 0x16ac001f, 0x96c00004, 0x26ac003f, 0x7ee6c00d, 0x96c00005,
+ 0x06200001, 0x2620000f, 0x9a00fff8, 0x8000016a, 0xce000367, 0xc424005e, 0x9640102e, 0xc428000e,
+ 0x199c0037, 0x19a00035, 0x2aa80008, 0xce800013, 0x95c0005d, 0xd800002a, 0xc42d3256, 0xc431325a,
+ 0x2330003f, 0x16f8001f, 0x9780000d, 0xc4253248, 0xc035f0ff, 0x7e764009, 0x19b401f8, 0x13740008,
+ 0x7e76400a, 0xce800013, 0xce413248, 0xcf01325a, 0xce800013, 0xc431325a, 0x97000001, 0x7d15001a,
+ 0xd1000072, 0xc8100072, 0x55140020, 0x199c0034, 0xd8400010, 0xd8400029, 0x9b800004, 0x1ae4003e,
+ 0xce400008, 0x80000b7c, 0xc4353254, 0x16a80008, 0x1aec003c, 0x19a4003f, 0x12a80015, 0x12ec001f,
+ 0x1374000b, 0x7eae800a, 0xc02e4000, 0x1774000d, 0x7eae800a, 0xce400008, 0x7f6b400a, 0x95c00005,
+ 0xc43d3248, 0x1bfc01e8, 0x13fc0018, 0x7dbd800a, 0x1d98ff15, 0x592c00fc, 0xcd80000a, 0x12e00016,
+ 0x7da1800a, 0x592c007e, 0x12e00015, 0x7da1800a, 0xd1000001, 0xcd800001, 0x11a0000c, 0x1264001e,
+ 0x1620000c, 0x7e26000a, 0x7e32000a, 0x12e4001b, 0x7e26000a, 0x5924007e, 0x12640017, 0x7e26000a,
+ 0x19a4003c, 0x12640018, 0x7e26000a, 0xd800002a, 0xce01325a, 0xcd013257, 0xcd413258, 0xc429325a,
+ 0xc40c005e, 0x94c00fdb, 0x96800001, 0x95c00003, 0x7c40c001, 0x7c410001, 0x9780f5ca, 0xcf400100,
+ 0xc40c0007, 0xd9000010, 0x8c00120d, 0x8c001219, 0x8c001232, 0xccc00010, 0x8c001b6d, 0x7c408001,
+ 0x88000000, 0xc42d324e, 0xc431324d, 0x52ec0020, 0x7ef2c01a, 0xc435324f, 0xc4293256, 0x52ec0008,
+ 0x07740003, 0x04240002, 0x269c003f, 0x7e5e4004, 0x7f67000f, 0x97000003, 0x7f674002, 0x0b740001,
+ 0x53740002, 0x7ef6c011, 0x1ab42010, 0x1ab8c006, 0x16a8000c, 0x26a80800, 0x2b740000, 0x7f7b400a,
+ 0x7f6b400a, 0xcf40001c, 0xd2c0001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4180011, 0x9a000003,
+ 0x8c000bec, 0x80000b47, 0xc42c001d, 0xc4313256, 0x1b34060b, 0x1b300077, 0x7f370009, 0x13300017,
+ 0x04340100, 0x26ec00ff, 0xc03a8004, 0x7ef6c00a, 0x7f3b000a, 0x7ef2c00a, 0xcec1325b, 0x80000c16,
+ 0xc40c0032, 0xc410001d, 0x28cc0008, 0xccc00013, 0xc415325b, 0x7c418001, 0x7c418001, 0x18580037,
+ 0x251000ff, 0xc421325d, 0x262001ef, 0xce01325d, 0x99800004, 0x7d15400a, 0xcd41325b, 0x80000168,
+ 0x1d54001f, 0xcd41325b, 0x7c408001, 0x88000000, 0xc428000b, 0xc42c000c, 0x12a80001, 0x26a80004,
+ 0x7eae800a, 0xc40c0021, 0xc4340028, 0x14f00010, 0xc4380030, 0xc43c0007, 0xcd280200, 0xcd680208,
+ 0xcda80210, 0x9b00000c, 0x9b400014, 0x9b800017, 0xc428000b, 0xc42c000c, 0x12a80001, 0x26a80004,
+ 0x7eae800a, 0xc6930200, 0xc6970208, 0xc69b0210, 0x90000000, 0x17300001, 0x9b000005, 0xccc00037,
+ 0x8c000190, 0xd8000032, 0x90000000, 0xd8000028, 0xd800002b, 0x80000168, 0xd900003f, 0x97c00002,
+ 0xd940003f, 0x80001082, 0xd9000040, 0x97c00002, 0xd9400040, 0x800010de, 0xc40c0021, 0x14fc0011,
+ 0x24f800ff, 0x33b80001, 0x97c0fffc, 0x9b800007, 0xccc00037, 0x8c000190, 0xd8000032, 0xd8000028,
+ 0xd800002b, 0x80001b70, 0xc4380004, 0xd8400008, 0xd8400013, 0xd88130b8, 0x04100000, 0x04140000,
+ 0xc418000e, 0x29980008, 0x7d83c001, 0xcd800013, 0xc4093249, 0x1888003e, 0x94800020, 0xd8400074,
+ 0x8c000671, 0x9a400009, 0xc418000e, 0x29980008, 0xcd800013, 0xc419324c, 0x259c0001, 0x1598001f,
+ 0x95c00016, 0x95800015, 0x99000003, 0xd8400036, 0x04100001, 0xc40c0021, 0x14d80011, 0x24e000ff,
+ 0x321c0002, 0x32200001, 0x9580ffee, 0x99c00014, 0x96000004, 0xccc00037, 0x04140001, 0x80000c30,
+ 0x9480000a, 0xd8000074, 0xc418005e, 0x95800f29, 0xcf800008, 0x80000c16, 0x94800004, 0xd8000074,
+ 0xc418005e, 0x95800f23, 0xd9c00036, 0x99400002, 0xccc00037, 0xcf800008, 0x80000c16, 0x94800004,
+ 0xd8000074, 0xc418005e, 0x95800f1a, 0xccc00037, 0xd8800036, 0x80001b70, 0x041c0003, 0x042c01c8,
+ 0x8c000d61, 0xc4200007, 0xc40c0077, 0x94c00001, 0x7c418001, 0xc428000e, 0x9600f502, 0x0a200001,
+ 0x98c0f500, 0x2aa80008, 0xce000010, 0x9a000f05, 0xce800013, 0xc431325a, 0xc42d3256, 0x1f30001f,
+ 0x16e4001f, 0xcf01325a, 0xc431325a, 0x97000001, 0x9640f4f4, 0xc434000b, 0x33740002, 0x9b40f4f1,
+ 0xc4353254, 0x16a80008, 0x1aec003c, 0x12a80015, 0x12ec001f, 0x1374000b, 0x7eae800a, 0xc02e4000,
+ 0x1774000d, 0x7eae800a, 0x7f6b400a, 0xcf400100, 0x12780001, 0x2bb80001, 0xc00ac005, 0xc00e0002,
+ 0x28cc8000, 0x28884900, 0x28cc0014, 0x80000ff3, 0xc43c0007, 0x7c40c001, 0x17fc0001, 0xd8400013,
+ 0x9bc00004, 0xd8400029, 0xc424005e, 0x96400ee1, 0xcc41c40a, 0xcc41c40c, 0xcc41c40d, 0x7c414001,
+ 0x24d0007f, 0x15580010, 0x255400ff, 0xcd01c411, 0xcd81c40f, 0xcd41c40e, 0xcc41c410, 0x7c414001,
+ 0x7c418001, 0x04200000, 0x18e80033, 0x18ec0034, 0xcc41c414, 0xcc41c415, 0xcd81c413, 0xcd41c412,
+ 0x18dc0032, 0x7c030011, 0x7c038011, 0x95c00027, 0x96c00002, 0xc431c417, 0xc435c416, 0x96800004,
+ 0x96c00002, 0xc439c419, 0xc43dc418, 0xc41c000e, 0x29dc0008, 0xcdc00013, 0xcf413261, 0x96c00002,
+ 0xcf013262, 0x96800004, 0xcfc13263, 0x96c00002, 0xcf813264, 0x18dc0030, 0xc43c0007, 0x95c00017,
+ 0x17fc0001, 0x9ac00005, 0x7d77000c, 0x9bc00015, 0x9700000a, 0x80000cd6, 0x51b80020, 0x53300020,
+ 0x7f97801a, 0x7f37001a, 0x7f3b000c, 0x9bc0000d, 0x97800002, 0x80000cd6, 0x9a000018, 0xd8400013,
+ 0x28200001, 0x80000ca7, 0x18dc0031, 0x95c00003, 0xc435c40b, 0x9740fffd, 0xd800002a, 0x80001b70,
+ 0xc4280032, 0x2aa80008, 0xce800013, 0xc40d325b, 0x97000002, 0x800012c2, 0xc438001d, 0x1bb81ff0,
+ 0x7f8cc00a, 0xccc1325b, 0xc411325d, 0x251001ef, 0xcd01325d, 0x80001b70, 0xc428000e, 0xc43c0007,
+ 0x2aa80008, 0xc438001d, 0xce800013, 0x13f4000c, 0x9bc00006, 0xc43d3256, 0x1bf0060b, 0x1bfc0077,
+ 0x7ff3c00a, 0x80000cf4, 0xc43d325a, 0x1bfc0677, 0x13fc0017, 0x04300100, 0x1bb81fe8, 0x7f73400a,
+ 0xc032800b, 0x7fb7800a, 0x7ff3c00a, 0x7ffbc00a, 0xcfc1325b, 0x80000c16, 0xc43c0007, 0x7c40c001,
+ 0x18d42011, 0x17fc0001, 0x18d001e8, 0x24cc007f, 0x7cd4c00a, 0x9bc00004, 0xd8400029, 0xc428005e,
+ 0x96800e6c, 0x7c414001, 0x50580020, 0x7d59401a, 0xd1400072, 0xc8140072, 0x596001fc, 0x12200009,
+ 0x7ce0c00a, 0x7c418001, 0x505c0020, 0x7d9d801a, 0x7c41c001, 0x50600020, 0x7de1c01a, 0x7c420001,
+ 0xccc0001b, 0xd140001d, 0xd180001f, 0xd1c00020, 0xd8400021, 0x95000010, 0x04300000, 0xc428000f,
+ 0x9a80ffff, 0xc8240010, 0x7e5e800c, 0x9bc00015, 0x9a80000c, 0x9b000024, 0x28300001, 0x122c0004,
+ 0x06ec0001, 0x0aec0001, 0x9ac0ffff, 0xd8400021, 0x80000d1f, 0xc428000f, 0x9a80ffff, 0xc8240010,
+ 0x566c0020, 0xc428000e, 0x2aa80008, 0xce800013, 0xce413261, 0xcec13262, 0xd800002a, 0x80001b70,
+ 0xc4340032, 0x2b740008, 0xcf400013, 0xc40d325b, 0x96800005, 0x566c0020, 0xce413261, 0xcec13262,
+ 0x800012c2, 0xc438001d, 0x1bb81fe8, 0x7f8cc00a, 0xccc1325b, 0xc411325d, 0x251001ef, 0xcd01325d,
+ 0x80001b70, 0xc43c0007, 0xc438001d, 0xc428000e, 0x2aa80008, 0xce800013, 0x13f4000c, 0x9bc00006,
+ 0xc43d3256, 0x1bf0060b, 0x1bfc0077, 0x7ff3c00a, 0x80000d57, 0xc43d325a, 0x1bfc0677, 0x13fc0017,
+ 0x04300100, 0x1bb81fe8, 0x7f73400a, 0xc0328009, 0x7fb7800a, 0x7ff3c00a, 0x7ffbc00a, 0xcfc1325b,
+ 0x80000c16, 0xc43c000e, 0x2bfc0008, 0xcfc00013, 0xc4253246, 0xc4113245, 0x04143000, 0xcd413267,
+ 0x52640020, 0x7e51001a, 0xc4153267, 0x7d2d0011, 0x19640057, 0x19580213, 0x19600199, 0x7da6400a,
+ 0x7e26400a, 0xd1000025, 0xce400024, 0xcdc00026, 0xd8400027, 0x04142000, 0xcfc00013, 0xcd413267,
+ 0xc4153267, 0x99400001, 0x90000000, 0x7c40c001, 0x18d001e8, 0x18d40030, 0x18d80034, 0x05280d83,
+ 0x7c420001, 0x7c424001, 0x86800000, 0x80000d8a, 0x8000016a, 0x80000d95, 0x80000db1, 0x8000016a,
+ 0x80000d95, 0x80000dbc, 0x11540010, 0x7e010001, 0x8c00187c, 0x7d75400a, 0xcd400013, 0xd4610000,
+ 0x9580f3d8, 0xc439c040, 0x97800001, 0x7c408001, 0x88000000, 0xd8000016, 0x526c0020, 0x18e80058,
+ 0x7e2ec01a, 0xd2c00072, 0xc82c0072, 0x5ae0073a, 0x7ea2800a, 0x9940000a, 0xce800024, 0xd2c00025,
+ 0xd4400026, 0xd8400027, 0x9580f3c6, 0xc4380012, 0x9b80ffff, 0x7c408001, 0x88000000, 0xdc3a0000,
+ 0x0bb80001, 0xce800024, 0xd2c00025, 0xcc400026, 0xd8400027, 0x9b80fffb, 0x9980fff5, 0x7c408001,
+ 0x88000000, 0xc02a0001, 0x2aa80001, 0x16200002, 0xce800013, 0xce01c405, 0xd441c406, 0x9580f3b1,
+ 0xc439c409, 0x97800001, 0x7c408001, 0x88000000, 0xc424000b, 0x32640002, 0x9a40000b, 0x11540010,
+ 0x29540002, 0xcd400013, 0xd4610000, 0x9580f3a5, 0xd8400013, 0xc439c040, 0x97800001, 0x7c408001,
+ 0x88000000, 0xd4400078, 0x80000168, 0xd8400029, 0xc40c005e, 0x94c00da7, 0x7c40c001, 0x50500020,
+ 0x7cd0c01a, 0xd0c00072, 0xc8280072, 0x5aac007e, 0x12d80017, 0x7c41c001, 0x7d9d800a, 0x56a00020,
+ 0x2620ffff, 0x7da1800a, 0x51980020, 0x7e82400a, 0x7e58c01a, 0x19d4003d, 0x28182002, 0x99400030,
+ 0x8c00104f, 0xc430000d, 0xc4340035, 0xd800002a, 0xcd800013, 0xc8140023, 0xc4180081, 0x13300005,
+ 0xc011000f, 0xc4240004, 0x11a00002, 0x7c908009, 0x12640004, 0x7d614011, 0xc4100026, 0x05980008,
+ 0x7ca4800a, 0x7d1a0002, 0x7cb0800a, 0x3e280008, 0x20880188, 0x54ec0020, 0x7cb4800a, 0xc4300027,
+ 0x04380008, 0xd1400025, 0xcf000024, 0x20240090, 0x7ca48001, 0xcc800026, 0xccc00026, 0xcec00026,
+ 0xcec00026, 0x28240004, 0xcc000026, 0x0a640001, 0x9a40fffe, 0x9a800005, 0x32280000, 0x9a800002,
+ 0x9a000000, 0x7c018001, 0xd8400027, 0xd8000016, 0xcf80003a, 0xd901a2a4, 0x80001037, 0xc418000e,
+ 0x29980008, 0xcd800013, 0xc421326c, 0x1624001f, 0x9a40fffe, 0xd841325f, 0xd8800033, 0xc43c0009,
+ 0x27fc0004, 0x97c0fffe, 0xd8000039, 0xd0c00038, 0xc43c0022, 0x9bc0ffff, 0xd8800034, 0xc429325f,
+ 0x26ac0001, 0x9ac0fffe, 0x26ac0002, 0x96c00003, 0xd800002a, 0x80001b70, 0xc43c0007, 0xc430001e,
+ 0xd8800033, 0x13f4000c, 0x1b301ff0, 0x2b300300, 0x2330003f, 0x7f37000a, 0x9680000b, 0xc43c0009,
+ 0x27fc0004, 0x97c0fffe, 0xd8400039, 0xd0c00038, 0xc43c0022, 0x9bc0ffff, 0xcf01325b, 0xd8800034,
+ 0x80000c16, 0xd8800034, 0x8c0001a2, 0x80001b70, 0xcc80003b, 0x24b00008, 0xc418000e, 0x1330000a,
+ 0x18ac0024, 0x2b304000, 0x7c40c001, 0xcec00008, 0x18a800e5, 0x1d980008, 0x12a80008, 0x7da9800a,
+ 0x29980008, 0xcd800013, 0xc4113249, 0x1910003e, 0x99000002, 0xd840003d, 0x7c410001, 0xd4400078,
+ 0x51100020, 0xcf01326c, 0x7cd0c01a, 0xc421326c, 0x12a80014, 0x2220003f, 0x7e2a000a, 0xcd800013,
+ 0xce01326c, 0xd8800033, 0xc43c0009, 0x27fc0004, 0x97c0fffe, 0xd8000039, 0xd0c00038, 0xc43c0022,
+ 0x9bc0ffff, 0xd8800034, 0x80001190, 0x7c40c001, 0x18dc003d, 0x95c00004, 0x041c0001, 0x042c01c8,
+ 0x8c000d61, 0x18d40030, 0x18d001e8, 0x18fc0034, 0x24e8000f, 0x06a80e71, 0x7c418001, 0x7c41c001,
+ 0x86800000, 0x80000edd, 0x80000e91, 0x80000e91, 0x80000ea1, 0x80000eaa, 0x80000e7c, 0x80000e7f,
+ 0x80000e7f, 0x80000e87, 0x80000e8f, 0x8000016a, 0x51dc0020, 0x7d9e001a, 0x80000ee6, 0xc420000e,
+ 0x2a200008, 0xce000013, 0xc4213262, 0xc4253261, 0x52200020, 0x7e26001a, 0x80000ee6, 0xc420000e,
+ 0x2a200008, 0xce000013, 0xc4213264, 0xc4253263, 0x52200020, 0x7e26001a, 0x80000ee6, 0xc820001f,
+ 0x80000ee6, 0x18e82005, 0x51e00020, 0x2aa80000, 0x7da1801a, 0xd1800072, 0xc8180072, 0x59a001fc,
+ 0x12200009, 0x7ea2800a, 0xce80001c, 0xd180001e, 0xd8400021, 0xc428000f, 0x9a80ffff, 0xc8200011,
+ 0x80000ee6, 0x15980002, 0xd8400013, 0xcd81c400, 0xc421c401, 0x95400041, 0xc425c401, 0x52640020,
+ 0x7e26001a, 0x80000ee6, 0x31ac2580, 0x9ac00011, 0x31ac260c, 0x9ac0000f, 0x31ac0800, 0x9ac0000d,
+ 0x31ac0828, 0x9ac0000b, 0x31ac2440, 0x9ac00009, 0x31ac2390, 0x9ac00007, 0x31ac0093, 0x9ac00005,
+ 0x31ac31dc, 0x9ac00003, 0x31ac31e6, 0x96c00004, 0xc4340004, 0xd8400008, 0x80000ede, 0x39ac7c06,
+ 0x3db07c00, 0x9ac00003, 0x97000002, 0x80000ebc, 0x39acc337, 0x3db0c330, 0x9ac00003, 0x97000002,
+ 0x80000ebc, 0x39acc335, 0x3db0c336, 0x9ac00003, 0x97000002, 0x80000ebc, 0x39ac9002, 0x3db09001,
+ 0x9ac00003, 0x97000002, 0x80000ebc, 0x39ac9012, 0x3db09011, 0x9ac00003, 0x97000002, 0x80000ebc,
+ 0x39acec70, 0x3db0ec6f, 0x9ac00003, 0x97000002, 0x80000ebc, 0xc4340004, 0xd8400013, 0xc5a10000,
+ 0x95400005, 0x05980001, 0xc5a50000, 0x52640020, 0x7e26001a, 0xcf400008, 0x05280eea, 0x7c418001,
+ 0x7c41c001, 0x86800000, 0x80000ef1, 0x8000016a, 0x80000efe, 0x80000f11, 0x80000f2e, 0x80000efe,
+ 0x80000f1f, 0xc4340004, 0xd8400013, 0xce190000, 0x95400005, 0x05980001, 0x56200020, 0xce190000,
+ 0xcf400008, 0x97c0f26f, 0xc439c040, 0x97800001, 0x7c408001, 0x88000000, 0x51ec0020, 0x18e80058,
+ 0x7daec01a, 0xd2c00072, 0xc82c0072, 0x5af8073a, 0x7eba800a, 0xd2c00025, 0xce800024, 0xce000026,
+ 0x95400003, 0x56240020, 0xce400026, 0xd8400027, 0x97c0f25c, 0xc4380012, 0x9b80ffff, 0x7c408001,
+ 0x88000000, 0xc02a0001, 0x2aa80001, 0x15980002, 0xce800013, 0xcd81c405, 0xce01c406, 0x95400003,
+ 0x56240020, 0xce41c406, 0x97c0f24e, 0xc439c409, 0x97800001, 0x7c408001, 0x88000000, 0xc424000b,
+ 0x32640002, 0x9a40f247, 0xd8800013, 0xce190000, 0x95400004, 0x05980001, 0x56200020, 0xce190000,
+ 0x97c0f240, 0xd8400013, 0xc439c040, 0x97800001, 0x7c408001, 0x88000000, 0x31ac2580, 0x9ac00011,
+ 0x31ac260c, 0x9ac0000f, 0x31ac0800, 0x9ac0000d, 0x31ac0828, 0x9ac0000b, 0x31ac2440, 0x9ac00009,
+ 0x31ac2390, 0x9ac00007, 0x31ac0093, 0x9ac00005, 0x31ac31dc, 0x9ac00003, 0x31ac31e6, 0x96c00004,
+ 0xc4340004, 0xd8400008, 0x80000ef2, 0x39ac7c06, 0x3db07c00, 0x9ac00003, 0x97000002, 0x80000f40,
+ 0x39acc337, 0x3db0c330, 0x9ac00003, 0x97000002, 0x80000f40, 0x39acc335, 0x3db0c336, 0x9ac00003,
+ 0x97000002, 0x80000f40, 0x39acec70, 0x3db0ec6f, 0x9ac00003, 0x97000002, 0x80000f40, 0x39ac9002,
+ 0x3db09002, 0x9ac00003, 0x97000002, 0x80000f40, 0x39ac9012, 0x3db09012, 0x9ac00003, 0x97000002,
+ 0x80000f40, 0x80000ef1, 0xc40c0006, 0x98c0ffff, 0x7c40c001, 0x7c410001, 0x7c414001, 0x7c418001,
+ 0x7c41c001, 0x7c43c001, 0x95c00001, 0xc434000e, 0x2b740008, 0x2b780001, 0xcf400013, 0xd8c1325e,
+ 0xcf80001a, 0xd8400013, 0x7c034001, 0x7c038001, 0x18e0007d, 0x32240003, 0x9a400006, 0x32240000,
+ 0x9a400004, 0xcd01c080, 0xcd41c081, 0x80000f88, 0x51640020, 0x7e52401a, 0xd2400072, 0xc8280072,
+ 0xce81c080, 0x56ac0020, 0x26f0ffff, 0xcf01c081, 0x1af000fc, 0x1334000a, 0x24e02000, 0x7f63400a,
+ 0x18e00074, 0x32240003, 0x9a400006, 0x32240000, 0x9a400004, 0xcd81c082, 0xcdc1c083, 0x80000f9d,
+ 0x51e40020, 0x7e5a401a, 0xd2400072, 0xc8280072, 0xce81c082, 0x56ac0020, 0x26f0ffff, 0xcf01c083,
+ 0x1af000fc, 0x13380016, 0x18e00039, 0x12200019, 0x7fa3800a, 0x7fb7800a, 0x18e0007d, 0x1220001d,
+ 0x7fa3800a, 0x18e00074, 0x12200014, 0x7fa3800a, 0xcf81c078, 0xcfc1c084, 0x80000c16, 0x7c40c001,
+ 0x18dc003d, 0x95c00004, 0x041c0000, 0x042c01c8, 0x8c000d61, 0x18d001e8, 0x31140005, 0x99400003,
+ 0x31140006, 0x95400002, 0x8c00104f, 0x05280fb7, 0x28140002, 0xcd400013, 0x86800000, 0x80000fbe,
+ 0x80000fbe, 0x80000fc2, 0x80000fbe, 0x80000fd1, 0x80000ff2, 0x80000ff2, 0x24cc003f, 0xccc1a2a4,
+ 0x7c408001, 0x88000000, 0x7c414001, 0x18e80039, 0x52a8003b, 0x50580020, 0x24cc003f, 0x7d59401a,
+ 0xd1400072, 0xc8140072, 0x7d69401a, 0xc41c0017, 0x99c0ffff, 0xd140004b, 0xccc1a2a4, 0x7c408001,
+ 0x88000000, 0xc414000d, 0x04180001, 0x24cc003f, 0x7d958004, 0xcd800035, 0xccc1a2a4, 0xc43c000e,
+ 0x2bfc0008, 0xcfc00013, 0xc43d3249, 0x1bfc003e, 0x97c00002, 0xd8400074, 0xc4100019, 0x7d150005,
+ 0x25100001, 0x9500000b, 0x97c0fffc, 0xc4180021, 0x159c0011, 0x259800ff, 0x31a00003, 0x31a40001,
+ 0x7e25800a, 0x95c0fff5, 0x9580fff4, 0x80000fef, 0xc411326f, 0x1d100010, 0xcd01326f, 0x97c00002,
+ 0xd8000074, 0x80001b70, 0x04380000, 0xc430000d, 0xc8140023, 0xc4180081, 0x13300005, 0xc011000f,
+ 0xc4240004, 0x33b40003, 0x97400003, 0xc0340008, 0x80000ffe, 0xc4340035, 0x11a00002, 0x7c908009,
+ 0x12640004, 0x7d614011, 0xc4100026, 0x05980008, 0x7ca4800a, 0x7d1a0002, 0x7cb0800a, 0x282c2002,
+ 0x208801a8, 0x3e280008, 0x7cb4800a, 0xcec00013, 0xc4300027, 0x042c0008, 0xd1400025, 0xcf000024,
+ 0x20240030, 0x7ca48001, 0xcc800026, 0xccc00026, 0x9b800013, 0xcc400026, 0x7c414001, 0x28340000,
+ 0xcf400013, 0x507c0020, 0x7d7d401a, 0xd1400072, 0xc8140072, 0x557c0020, 0x28342002, 0xcf400013,
+ 0xcd400026, 0xcfc00026, 0xd4400026, 0x9a80000e, 0x32280000, 0x9a80000b, 0x8000102f, 0xcc000026,
+ 0xcc000026, 0xcc000026, 0xcc000026, 0xcc000026, 0x9a800005, 0x32280000, 0x9a800002, 0x9a000000,
+ 0x7c018001, 0xcc000026, 0xd8400027, 0x1cccfe08, 0xd8800013, 0xcec0003a, 0xccc1a2a4, 0xc43c000e,
+ 0x2bfc0008, 0xcfc00013, 0xc43d3249, 0x1bfc003e, 0x9bc00007, 0xc428000e, 0x16a80008, 0xce800009,
+ 0xc42c005e, 0x96c00b33, 0xd840003c, 0xc4200025, 0x7da2400f, 0x7da28002, 0x7e1ac002, 0x0aec0001,
+ 0x96400002, 0x7d2ac002, 0x3ef40010, 0x9b40f11d, 0x04380030, 0xcf81325e, 0x80000c16, 0xde410000,
+ 0xdcc10000, 0xdd010000, 0xdd410000, 0xdd810000, 0xddc10000, 0xde010000, 0xc40c000e, 0x7c024001,
+ 0x28cc0008, 0xccc00013, 0xc8100086, 0x5510003f, 0xc40d3249, 0x18cc003e, 0x98c00003, 0x99000011,
+ 0x80001075, 0x9900000c, 0xc40c0026, 0xc4100081, 0xc4140025, 0x7d15800f, 0x7d15c002, 0x7d520002,
+ 0x0a200001, 0x95800002, 0x7cde0002, 0x3e20001a, 0x9a000009, 0x040c0030, 0xccc1325e, 0x80001071,
+ 0xd9c00036, 0xd8400029, 0xc40c005e, 0x94c00b01, 0x04240001, 0xdc200000, 0xdc1c0000, 0xdc180000,
+ 0xdc140000, 0xdc100000, 0xdc0c0000, 0x96400004, 0xdc240000, 0xdc0c0000, 0x80000c16, 0xdc240000,
+ 0x90000000, 0xcc40003f, 0xd8c00010, 0xc4080029, 0xcc80003b, 0xc418000e, 0x18a800e5, 0x1d980008,
+ 0x12a80008, 0x7da9800a, 0x29980008, 0xcd800013, 0x18a400e5, 0x12500009, 0x248c0008, 0x94c00006,
+ 0x200c006d, 0x7cd0c00a, 0xccc1326c, 0xc421326c, 0x96000001, 0xcd800013, 0x200c0228, 0x7cd0c00a,
+ 0xccc1326c, 0xc421326c, 0x96000001, 0xc40c002a, 0xc410002b, 0x18881fe8, 0x18d4072c, 0x18cc00d1,
+ 0x7cd4c00a, 0x3094000d, 0x38d80000, 0x311c0003, 0x99400006, 0x30940007, 0x1620001f, 0x9940001d,
+ 0x9a000023, 0x800010c4, 0x9580001a, 0x99c00019, 0xccc00041, 0x25140001, 0xc418002c, 0x9940000d,
+ 0x259c007f, 0x95c00013, 0x19a00030, 0xcdc0001b, 0xd8400021, 0xd8400022, 0xc430000f, 0x17300001,
+ 0x9b00fffe, 0x9a000012, 0xd8400023, 0x800010cb, 0x199c0fe8, 0xcdc0001b, 0xd8400021, 0xd8400023,
+ 0xc430000f, 0x17300001, 0x9b00fffe, 0x800010cb, 0xd8c00010, 0xd8000022, 0xd8000023, 0xc430005e,
+ 0x97000aac, 0x7c408001, 0x88000000, 0xc43c000e, 0xc434002e, 0x2bfc0008, 0x2020002c, 0xcfc00013,
+ 0xce01326c, 0x17780001, 0x27740001, 0x07a810d8, 0xcf400010, 0xc421326c, 0x96000001, 0x86800000,
+ 0x80000168, 0x80000aa7, 0x80000bfc, 0x800012e9, 0x8000104c, 0xcc400040, 0xd8800010, 0xc4180032,
+ 0x29980008, 0xcd800013, 0x200c007d, 0xccc1325b, 0xc411325b, 0x95000001, 0x7c408001, 0x88000000,
+ 0x28240007, 0xde430000, 0xd4400078, 0x80001190, 0xcc80003b, 0x24b00008, 0xc418000e, 0x1330000a,
+ 0x18a800e5, 0x1d980008, 0x12a80008, 0x7da9800a, 0x29980008, 0xcd800013, 0xc40d3249, 0x18cc003e,
+ 0x98c00002, 0xd840003d, 0x2b304000, 0xcf01326c, 0xc431326c, 0x7c40c001, 0x7c410001, 0x7c414001,
+ 0x192400fd, 0x50580020, 0x7d59401a, 0x7c41c001, 0x06681110, 0x7c420001, 0xcc400078, 0x18ac0024,
+ 0x19180070, 0x19100078, 0xcec00008, 0x18f40058, 0x5978073a, 0x7f7b400a, 0x97000001, 0x86800000,
+ 0x80001117, 0x80001118, 0x80001122, 0x8000112d, 0x80001130, 0x80001133, 0x8000016a, 0x8000117b,
+ 0x24ec0f00, 0x32ec0600, 0x96c00003, 0xc4300006, 0x9b00ffff, 0xd1400025, 0xcf400024, 0xcdc00026,
+ 0xd8400027, 0x8000117b, 0x24ec0f00, 0x32ec0600, 0x96c00003, 0xc4300006, 0x9b00ffff, 0xd1400025,
+ 0xcf400024, 0xcdc00026, 0xce000026, 0xd8400027, 0x8000117b, 0xc81c001f, 0x55e00020, 0x80001122,
+ 0xc81c0020, 0x55e00020, 0x80001122, 0x8c00116b, 0xd8400013, 0xc02a0200, 0x7e8e8009, 0x22a8003d,
+ 0x22a80074, 0x2774001c, 0x13740014, 0x7eb6800a, 0x25ecffff, 0x55700020, 0x15f40010, 0x13740002,
+ 0x275c001f, 0x95c00027, 0x7c018001, 0x7f41c001, 0x15dc0002, 0x39e00008, 0x25dc0007, 0x7dc1c01e,
+ 0x05dc0001, 0x96000004, 0x05e40008, 0x8c00116e, 0x80001168, 0x7dc2001e, 0x06200001, 0x05e40008,
+ 0x7e62000e, 0x9a000004, 0x7da58001, 0x8c00116e, 0x80001165, 0x7dc2001e, 0x06200001, 0x7e1a0001,
+ 0x05cc0008, 0x7e0d000e, 0x95000007, 0x7e02401e, 0x06640001, 0x06640008, 0x05d80008, 0x8c00116e,
+ 0x80001168, 0x7dc2401e, 0x06640001, 0x7da58001, 0x8c00116e, 0x05e00008, 0x7da2000c, 0x9600ffe6,
+ 0x17640002, 0x8c00116e, 0x80001190, 0xc4200006, 0x9a00ffff, 0x90000000, 0x8c00116b, 0xc420000e,
+ 0x2a200001, 0xce00001a, 0xce81c078, 0xcec1c080, 0xcc01c081, 0xcd41c082, 0xcf01c083, 0x12640002,
+ 0x22640435, 0xce41c084, 0x90000000, 0x0528117e, 0x312c0003, 0x86800000, 0x80001190, 0x80001185,
+ 0x80001182, 0x80001182, 0xc4300012, 0x9b00ffff, 0x9ac0000c, 0xc03a0400, 0xc4340004, 0xd8400013,
+ 0xd8400008, 0xc418000e, 0x15980008, 0x1198001c, 0x7d81c00a, 0xcdc130b7, 0xcf8130b5, 0xcf400008,
+ 0x04240008, 0xc418000e, 0xc41c0049, 0x19a000e8, 0x29a80008, 0x7de2c00c, 0xce800013, 0xc421325e,
+ 0x26200010, 0xc415326d, 0x9a000006, 0xc420007d, 0x96000004, 0x96c00003, 0xce40003e, 0x800011a3,
+ 0x7d654001, 0xcd41326d, 0x7c020001, 0x96000005, 0xc4100026, 0xc4240081, 0xc4140025, 0x800011b6,
+ 0xc4253279, 0xc415326d, 0xc431326c, 0x2730003f, 0x3b380006, 0x97800004, 0x3f38000b, 0x9b800004,
+ 0x800011b4, 0x04300006, 0x800011b4, 0x0430000b, 0x04380002, 0x7fb10004, 0x7e57000f, 0x7e578002,
+ 0x7d67c002, 0x0be40001, 0x97000002, 0x7d3a4002, 0x202c002c, 0xc421325e, 0x04280020, 0xcec1326c,
+ 0x26200010, 0x3e640010, 0x96000003, 0x96400002, 0xce81325e, 0xc4300028, 0xc434002e, 0x17780001,
+ 0x27740001, 0x07a811cf, 0x9b00feb8, 0xcf400010, 0xc414005e, 0x954009a7, 0x86800000, 0x80000168,
+ 0x80000aa7, 0x80000bfc, 0x800012e9, 0x80000168, 0x8c00120d, 0x7c40c001, 0xccc1c07c, 0xcc41c07d,
+ 0xcc41c08c, 0x7c410001, 0xcc41c079, 0xcd01c07e, 0x7c414001, 0x18f0012f, 0x18f40612, 0x18cc00c1,
+ 0x7f73400a, 0x7cf7400a, 0x39600004, 0x9a000002, 0xc0140004, 0x11600001, 0x18fc003e, 0x9740001c,
+ 0xcf400041, 0xc425c07f, 0x97c00003, 0x166c001f, 0x800011ee, 0x1a6c003e, 0x96c00006, 0x04200002,
+ 0x0a200001, 0x9a00ffff, 0xd8400013, 0x800011e8, 0xc428002c, 0x96800010, 0x26ac007f, 0xcec0001b,
+ 0xd8400021, 0x1ab00030, 0x1aac0fe8, 0xc434000f, 0x9b40ffff, 0x97000008, 0xcec0001b, 0xd8400021,
+ 0xc434000f, 0x9b40ffff, 0x80001205, 0x0a200001, 0x9a00ffff, 0xd8400013, 0xc425c07f, 0x166c001f,
+ 0x11600001, 0x9ac0fffa, 0x8c001232, 0x7c408001, 0x88000000, 0xd8000033, 0xc438000b, 0xc43c0009,
+ 0x27fc0001, 0x97c0fffe, 0xd8400013, 0xd841c07f, 0xc43dc07f, 0x1bfc0078, 0x7ffbc00c, 0x97c0fffd,
+ 0x90000000, 0xc03a2800, 0xcf81c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079, 0xcc01c07e, 0x04380040,
+ 0xcf80001b, 0xd8400021, 0xc438000f, 0x9b80ffff, 0x04380060, 0xcf80001b, 0xd8400021, 0xc438000f,
+ 0x9b80ffff, 0x04380002, 0x0bb80001, 0x9b80ffff, 0xd8400013, 0xc43dc07f, 0x17fc001f, 0x04380010,
+ 0x9bc0fffa, 0x90000000, 0xd8400013, 0xd801c07f, 0xd8400013, 0xc43dc07f, 0xcfc00078, 0xd8000034,
+ 0x90000000, 0xc03ae000, 0xcf81c200, 0xc03a0800, 0xcf81c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079,
+ 0xcc01c07e, 0x04380040, 0xcf80001b, 0xd8400021, 0xc438000f, 0x9b80ffff, 0x04380002, 0x0bb80001,
+ 0x9b80ffff, 0xd8400013, 0xc43dc07f, 0x17fc001f, 0x04380010, 0x9bc0fffa, 0x90000000, 0xc03ae000,
+ 0xcf81c200, 0xc03a4000, 0xcf81c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079, 0xcc01c07e, 0x04380002,
+ 0x0bb80001, 0x9b80ffff, 0xd8400013, 0xc43dc07f, 0x17fc001f, 0x04380010, 0x9bc0fffa, 0x90000000,
+ 0xc40c0007, 0x30d00002, 0x99000052, 0xd8400029, 0xc424005e, 0x9640090f, 0x7c410001, 0xc428000e,
+ 0x1514001f, 0x19180038, 0x2aa80008, 0x99400030, 0x30dc0001, 0xce800013, 0x99c0000a, 0xc42d324e,
+ 0xc431324d, 0x52ec0020, 0x7ef2c01a, 0xc435324f, 0xc4293256, 0x1ab0c006, 0x52ec0008, 0x8000127f,
+ 0xc42d3258, 0xc4313257, 0x52ec0020, 0x7ef2c01a, 0xc4353259, 0xc429325a, 0x1ab0c012, 0x07740001,
+ 0x04240002, 0x26a0003f, 0x7e624004, 0x7f67800f, 0x97800002, 0x04340000, 0x53740002, 0x7ef6c011,
+ 0x1ab42010, 0x16a8000c, 0x26a80800, 0x2b740000, 0x7f73400a, 0x7f6b400a, 0xcf40001c, 0xd2c0001e,
+ 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4100011, 0x1514001f, 0x99400006, 0x9980000a, 0x8c0012e1,
+ 0xc40c0007, 0x04100000, 0x80001267, 0xd800002a, 0xc424005e, 0x964008d7, 0xd9800036, 0x80000c16,
+ 0xc42c001d, 0x95c00005, 0xc431325a, 0x1b300677, 0x11dc000c, 0x800012aa, 0xc4313256, 0x1b34060b,
+ 0x1b300077, 0x7f37000a, 0x13300017, 0x04340100, 0x26ec00ff, 0xc03a8002, 0x7ef6c00a, 0x7edec00a,
+ 0x7f3b000a, 0x7ef2c00a, 0xcec1325b, 0x80000c16, 0xc4140032, 0xc410001d, 0x29540008, 0xcd400013,
+ 0xc40d325b, 0x1858003f, 0x251000ff, 0x99800007, 0x7d0cc00a, 0xccc1325b, 0xc411325d, 0x251001ef,
+ 0xcd01325d, 0x80000168, 0x18d0006c, 0x18d407f0, 0x9900000e, 0x04100002, 0xc4193256, 0xc41d324f,
+ 0x2598003f, 0x7d190004, 0x7d5d4001, 0x7d52000f, 0x9a000003, 0xcd41324f, 0x800012d8, 0x7d514002,
+ 0xcd41324f, 0x800012d8, 0xc4193259, 0xc41d325a, 0x7d958001, 0x7dd5c002, 0xcd813259, 0xcdc1325a,
+ 0xc411325d, 0x251001ef, 0xcd01325d, 0x1ccc001e, 0xccc1325b, 0xc40d325b, 0x94c00001, 0x7c408001,
+ 0x88000000, 0xc40c0021, 0xc4340028, 0x14f00010, 0xc4380030, 0xc43c0007, 0x9b000004, 0x9b40000c,
+ 0x9b80000f, 0x90000000, 0x17300001, 0x9b000005, 0xccc00037, 0x8c000190, 0xd8000032, 0x90000000,
+ 0xd8000028, 0xd800002b, 0x80000168, 0xd980003f, 0x97c00002, 0xd9c0003f, 0x80001082, 0xd9800040,
+ 0x97c00002, 0xd9c00040, 0x800010de, 0xc43c0007, 0x33f80003, 0x97800051, 0xcc80003b, 0x24b00008,
+ 0xc418000e, 0x1330000a, 0x18a800e5, 0x1d980008, 0x12a80008, 0x7da9800a, 0x29980008, 0xcd800013,
+ 0xc4353249, 0x1b74003e, 0x9b400002, 0xd840003d, 0x2b304000, 0xcf01326c, 0xc431326c, 0x97000001,
+ 0x7c434001, 0x1b4c00f8, 0x7c410001, 0x7c414001, 0x50700020, 0x04e81324, 0x18ac0024, 0x7c41c001,
+ 0x50600020, 0xcc400078, 0x30e40004, 0x9a400007, 0x7d71401a, 0x596401fc, 0x12640009, 0x1b74008d,
+ 0x7e76400a, 0x2a640000, 0xcec00008, 0x86800000, 0x8000016a, 0x8000016a, 0x8000016a, 0x8000016a,
+ 0x8000132c, 0x8000133b, 0x80001344, 0x8000016a, 0xc4340004, 0xd8400013, 0xd8400008, 0xc42530b5,
+ 0x1a68003a, 0x9a80fffe, 0x2024003a, 0xc418000e, 0x25980700, 0x11980014, 0x7d19000a, 0xcd0130b7,
+ 0xce4130b5, 0xcf400008, 0x80001190, 0xce40001c, 0xd140001e, 0xd8400021, 0xc428000f, 0x9a80ffff,
+ 0xc4240011, 0x7de6800f, 0x9a80ffea, 0x80001190, 0xce40001c, 0xd140001e, 0xd8400021, 0xc428000f,
+ 0x9a80ffff, 0xc8240011, 0x7de1c01a, 0x7de6800f, 0x9a80ffe0, 0x80001190, 0x8c00104f, 0x28182002,
+ 0xc430000d, 0xc4340035, 0xcd800013, 0xc8140023, 0xc4180081, 0x13300005, 0xc4240004, 0x11a00002,
+ 0x12640004, 0x7d614011, 0xc4100026, 0x05980008, 0x7ca4800a, 0x7d1a0002, 0x7cb0800a, 0x3e280008,
+ 0x7cb4800a, 0xc4300027, 0x042c0008, 0xd1400025, 0xcf000024, 0x20240030, 0x7ca48001, 0xcc800026,
+ 0x7c434001, 0x1b4c00f8, 0xcf400026, 0xcc400026, 0x28340000, 0xcf400013, 0x7c414001, 0x507c0020,
+ 0x30e40004, 0x9a400005, 0x7d7d401a, 0xd1400072, 0xc8140072, 0x557c0020, 0x28342002, 0xcf400013,
+ 0xcd400026, 0xcfc00026, 0xd4400026, 0xcc000026, 0x9a800005, 0x32280000, 0x9a800002, 0x9a000000,
+ 0x7c018001, 0xd8400027, 0xd8800013, 0x04380028, 0xcec0003a, 0xcf81a2a4, 0x80001037, 0xd8400029,
+ 0xc40c005e, 0x94c007eb, 0x7c40c001, 0x50500020, 0x7d0d001a, 0xd1000072, 0xc8100072, 0x591c01fc,
+ 0x11dc0009, 0x45140210, 0x595801fc, 0x11980009, 0x29dc0000, 0xcdc0001c, 0xd140001e, 0xd8400021,
+ 0xc418000f, 0x9980ffff, 0xc4200011, 0x1624001f, 0x96400069, 0xc40c000e, 0x28cc0008, 0xccc00013,
+ 0xce013249, 0x1a307fe8, 0xcf00000a, 0x23304076, 0xd1000001, 0xcf000001, 0xc41d3254, 0xc4253256,
+ 0x18cc00e8, 0x10cc0015, 0x4514020c, 0xd140001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4200011,
+ 0xce013248, 0x1a2001e8, 0x12200014, 0x2a204001, 0xce000013, 0x1a64003c, 0x1264001f, 0x11dc0009,
+ 0x15dc000b, 0x7dcdc00a, 0x7e5dc00a, 0xcdc00100, 0xd8800013, 0xd8400010, 0xd800002a, 0xd8400008,
+ 0xcf00000d, 0xcf00000a, 0x8c001427, 0x04340022, 0x07740001, 0x04300010, 0xdf430000, 0x7c434001,
+ 0x7c408001, 0xd4412e01, 0x0434001e, 0xdf430000, 0xd4400078, 0xdf030000, 0xd4412e40, 0xd8400013,
+ 0xcc41c030, 0xcc41c031, 0x248dfffe, 0xccc12e00, 0xd8800013, 0xcc812e00, 0x7c434001, 0x7c434001,
+ 0x8c00142b, 0xd8000010, 0xc40c000e, 0x28cc0008, 0xccc00013, 0x45140248, 0xd140001e, 0xd8400021,
+ 0xc418000f, 0x9980ffff, 0xc8200011, 0xce013257, 0x56200020, 0xce013258, 0x0434000c, 0xdb000024,
+ 0xd1400025, 0xd8000026, 0xd8000026, 0xd8400027, 0x45540008, 0xd140001e, 0xd8400021, 0xc418000f,
+ 0x9980ffff, 0xc8200011, 0xce013259, 0x56200020, 0xc0337fff, 0x7f220009, 0xce01325a, 0x55300020,
+ 0x7d01c001, 0x042c01d0, 0x8c000d61, 0x06ec0004, 0x7f01c001, 0x8c000d61, 0x041c0002, 0x042c01c8,
+ 0x8c000d61, 0xc4380012, 0x9b80ffff, 0xd800002a, 0x80000aa7, 0xd800002a, 0x7c408001, 0x88000000,
+ 0xd8400029, 0x7c40c001, 0x50500020, 0x8c001427, 0x7cd0c01a, 0xc4200007, 0xd0c00072, 0xc8240072,
+ 0xd240001e, 0x7c414001, 0x19682011, 0x5a6c01fc, 0x12ec0009, 0x7eeac00a, 0x2aec0000, 0xcec0001c,
+ 0xd8400021, 0xc430000f, 0x9b00ffff, 0xc4180011, 0x7c438001, 0x99800007, 0xdf830000, 0xcfa0000c,
+ 0x8c00142b, 0xd4400078, 0xd800002a, 0x80001b70, 0x8c00142b, 0xd800002a, 0x80001b70, 0xd8000012,
+ 0xc43c0008, 0x9bc0ffff, 0x90000000, 0xd8400012, 0xc43c0008, 0x97c0ffff, 0x90000000, 0xc4380007,
+ 0x7c40c001, 0x17b80001, 0x18d40038, 0x7c410001, 0x9b800004, 0xd8400029, 0xc414005e, 0x9540073d,
+ 0x18c80066, 0x7c414001, 0x30880001, 0x7c418001, 0x94800008, 0x8c00187c, 0xcf400013, 0xc42c0004,
+ 0xd8400008, 0xcd910000, 0xcec00008, 0x7d410001, 0x043c0000, 0x7c41c001, 0x7c420001, 0x04240001,
+ 0x06200001, 0x4220000c, 0x0a640001, 0xcc000078, 0x9a40fffe, 0x24e80007, 0x24ec0010, 0xd8400013,
+ 0x9ac00006, 0xc42c0004, 0xd8400008, 0xc5310000, 0xcec00008, 0x80001465, 0x51540020, 0x7d15001a,
+ 0xd1000072, 0xc82c0072, 0xd2c0001e, 0x18f02011, 0x5aec01fc, 0x12ec0009, 0x7ef2c00a, 0x2aec0000,
+ 0xcec0001c, 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc4300011, 0x96800012, 0x12a80001, 0x0aa80001,
+ 0x06a8146a, 0x7f1f0009, 0x86800000, 0x7f1b400f, 0x80001478, 0x7f1b400e, 0x80001478, 0x7f1b400c,
+ 0x8000147a, 0x7f1b400d, 0x8000147a, 0x7f1b400f, 0x8000147a, 0x7f1b400e, 0x8000147a, 0x7f334002,
+ 0x97400014, 0x8000147b, 0x9b400012, 0x9b800005, 0x9bc0001f, 0x7e024001, 0x043c0001, 0x8000144a,
+ 0xc40c0032, 0xc438001d, 0x28cc0008, 0xccc00013, 0xc43d325b, 0x1bb81ff0, 0x7fbfc00a, 0xcfc1325b,
+ 0xc411325d, 0x251001ef, 0xcd01325d, 0x80001b70, 0x94800007, 0x8c00187c, 0xcf400013, 0xc42c0004,
+ 0xd8400008, 0xcd910000, 0xcec00008, 0x9b800003, 0xd800002a, 0x80001b70, 0xc40c0032, 0x28cc0008,
+ 0xccc00013, 0xc40d325b, 0x800012c2, 0xc40c000e, 0xc43c0007, 0xc438001d, 0x28cc0008, 0xccc00013,
+ 0x13f4000c, 0x9bc00006, 0xc43d3256, 0x1bf0060b, 0x1bfc0077, 0x7ff3c00a, 0x800014a9, 0xc43d325a,
+ 0x1bfc0677, 0x04300100, 0x1bb81ff0, 0x7f73400a, 0xc0328007, 0x7fb7800a, 0x13fc0017, 0x7ff3c00a,
+ 0x7ffbc00a, 0xcfc1325b, 0xc03a0002, 0xc4340004, 0xd8400013, 0xd8400008, 0xcf8130b5, 0xcf400008,
+ 0x80000c16, 0x043c0000, 0xc414000e, 0x29540008, 0xcd400013, 0xc4193246, 0xc41d3245, 0x51980020,
+ 0x7dd9c01a, 0x45dc0390, 0xc4313267, 0x04183000, 0xcd813267, 0x1b380057, 0x1b340213, 0x1b300199,
+ 0x7f7b400a, 0x7f73400a, 0xcf400024, 0xd1c00025, 0xcc800026, 0x7c420001, 0xce000026, 0x7c424001,
+ 0xce400026, 0x7c428001, 0xce800026, 0x7c42c001, 0xcec00026, 0x7c430001, 0xcf000026, 0x7c434001,
+ 0xcf400026, 0x7c438001, 0xcf800026, 0xd8400027, 0xcd400013, 0x04182000, 0xcd813267, 0xd840004f,
+ 0x1a0800fd, 0x109c000a, 0xc4193265, 0x7dd9c00a, 0xcdc13265, 0x2620ffff, 0xce080228, 0x9880000e,
+ 0xce480250, 0xce880258, 0xd8080230, 0xd8080238, 0xd8080240, 0xd8080248, 0xd8080268, 0xd8080270,
+ 0xd8080278, 0xd8080280, 0xd800004f, 0x97c0ec75, 0x90000000, 0x040c0000, 0x041c0010, 0x26180001,
+ 0x09dc0001, 0x16200001, 0x95800002, 0x04cc0001, 0x99c0fffb, 0xccc80230, 0xd8080238, 0xd8080240,
+ 0xd8080248, 0x040c0000, 0xce480250, 0xce880258, 0x52a80020, 0x7e6a401a, 0x041c0020, 0x66580001,
+ 0x09dc0001, 0x56640001, 0x95800002, 0x04cc0001, 0x99c0fffb, 0xccc80260, 0xd8080268, 0xd8080270,
+ 0xd8080278, 0xd8080280, 0x040c0000, 0xcec80288, 0xcf080290, 0xcec80298, 0xcf0802a0, 0x040c0000,
+ 0x041c0010, 0xcf4802a8, 0x27580001, 0x09dc0001, 0x17740001, 0x95800002, 0x04cc0001, 0x99c0fffb,
+ 0xccc802b0, 0xd80802b8, 0x178c000b, 0x27b8003f, 0x7cf8c001, 0xcf8802c0, 0xccc802c8, 0xcf8802d0,
+ 0xcf8802d8, 0xd800004f, 0x97c00002, 0x90000000, 0x7c408001, 0x88000000, 0xc40c000e, 0x28cc0008,
+ 0xccc00013, 0xc43d3265, 0x1bc800ea, 0x7c418001, 0x25b8ffff, 0xc4930240, 0xc48f0238, 0x04cc0001,
+ 0x24cc000f, 0x7cd2800c, 0x9a80000b, 0xc5230309, 0x2620ffff, 0x7e3a400c, 0x9a400004, 0x05100001,
+ 0x2510000f, 0x80001539, 0xcd08034b, 0xd4400078, 0x80000168, 0xc48f0230, 0xc4930240, 0x98c00004,
+ 0xcd880353, 0x8c00163f, 0xc49b0353, 0xc4930238, 0xc48f0228, 0x05100001, 0x2510000f, 0x7cd14005,
+ 0x25540001, 0x99400004, 0x05100001, 0x2510000f, 0x8000154f, 0xc48f0230, 0x7c41c001, 0xcd080238,
+ 0xcd08034b, 0x08cc0001, 0x2598ffff, 0x3d200008, 0xccc80230, 0xcd900309, 0xd8100319, 0x04340801,
+ 0x2198003f, 0xcf400013, 0xcd910ce7, 0xc4190ce6, 0x7d918005, 0x25980001, 0x9580fffd, 0x7d918004,
+ 0xcd810ce6, 0x9a000003, 0xcdd1054f, 0x8000156e, 0x090c0008, 0xcdcd050e, 0x040c0000, 0x110c0014,
+ 0x28cc4001, 0xccc00013, 0xcc41230a, 0xcc41230b, 0xcc41230c, 0xcc41230d, 0xcc480329, 0xcc48032a,
+ 0xcc4802e0, 0xd8000055, 0xc48f02e0, 0x24d8003f, 0x09940001, 0x44100001, 0x9580002c, 0x95400005,
+ 0x09540001, 0x51100001, 0x69100001, 0x8000157f, 0x24cc003f, 0xc4970290, 0xc49b0288, 0x51540020,
+ 0x7d59401a, 0xc49b02a0, 0xc49f0298, 0x51980020, 0x7d9d801a, 0x041c0040, 0x04200000, 0x7dcdc002,
+ 0x7d924019, 0x7d26400c, 0x09dc0001, 0x9a400008, 0x51100001, 0x06200001, 0x99c0fffa, 0xc48f0230,
+ 0xc4930240, 0x8c00163f, 0x80001579, 0x7d010021, 0x7d914019, 0xc4930238, 0x55580020, 0xcd480298,
+ 0xcd8802a0, 0x10d40010, 0x12180016, 0xc51f0309, 0x7d95800a, 0x7d62000a, 0x7dd9c00a, 0xd8400013,
+ 0xcdd00309, 0xce113320, 0xc48f02e0, 0xc49b02b0, 0x18dc01e8, 0x7dd9400e, 0xc48f0230, 0xc4930240,
+ 0x95c0001d, 0x95400003, 0x8c00163f, 0x800015aa, 0xc48f0238, 0xc4a302b8, 0x12240004, 0x7e5e400a,
+ 0xc4ab02a8, 0x04100000, 0xce4c0319, 0x7d9d8002, 0x7ea14005, 0x25540001, 0x99400004, 0x06200001,
+ 0x2620000f, 0x800015bc, 0x09dc0001, 0x04240001, 0x7e624004, 0x06200001, 0x7d25000a, 0x2620000f,
+ 0x99c0fff4, 0xd8400013, 0xcd0d3330, 0xce0802b8, 0xcd8802b0, 0xc4ab02e0, 0x1aa807f0, 0xc48f02d0,
+ 0xc49702d8, 0xc49b02c8, 0xc49f02c0, 0x96800028, 0x7d4e000f, 0x9600000b, 0x7d964002, 0x7e6a000f,
+ 0x96000003, 0x7d694001, 0x800015e9, 0x7cde4002, 0x7e6a000f, 0x96000008, 0x7de94001, 0x800015e9,
+ 0x7cd64002, 0x7e6a000e, 0x96000003, 0x7d694001, 0x800015e9, 0xc48f0230, 0xc4930240, 0x8c00163f,
+ 0x800015cd, 0xc4930238, 0x7d698002, 0xcd4802d8, 0x129c0008, 0xc50f0319, 0x11a0000e, 0x11140001,
+ 0xc4340004, 0xd8400008, 0xd8400013, 0x7e1e000a, 0x1198000a, 0xcd953300, 0x7e0e000a, 0x12a8000a,
+ 0xce953301, 0xce100319, 0xcf400008, 0xc4b70280, 0xc4b30278, 0x7f73800a, 0x536c0020, 0x7ef2c01a,
+ 0x9780eb68, 0x8c001608, 0xd8080278, 0xd8080280, 0x7c408001, 0x88000000, 0x043c0003, 0x80001609,
+ 0x043c0001, 0x30b40000, 0x9b400011, 0xc4b70258, 0xc4b30250, 0x53780020, 0x7fb3801a, 0x7faf8019,
+ 0x04300020, 0x04280000, 0x67b40001, 0x0b300001, 0x57b80001, 0x97400002, 0x06a80001, 0x9b00fffb,
+ 0xc4bb0260, 0x7fab8001, 0xcf880260, 0x04300020, 0x04280000, 0x66f40001, 0x0b300001, 0x56ec0001,
+ 0x97400005, 0x8c001628, 0xc4353247, 0x7f7f4009, 0x9b40fffe, 0x06a80001, 0x9b00fff7, 0x90000000,
+ 0x269c0007, 0x11dc0008, 0x29dc0008, 0x26a00018, 0x12200003, 0x7de1c00a, 0x26a00060, 0x06200020,
+ 0x16200001, 0x7de1c00a, 0xcdc00013, 0x90000000, 0x269c0018, 0x26a00007, 0x26a40060, 0x11dc0006,
+ 0x12200006, 0x16640001, 0x29dc0008, 0x7de1c00a, 0x7de5c00a, 0xcdc00013, 0x90000000, 0xc4b70228,
+ 0x05100001, 0x04cc0001, 0x2510000f, 0xccc80230, 0x7f514005, 0x25540001, 0x99400004, 0x05100001,
+ 0x2510000f, 0x80001644, 0xc4b30248, 0xcd080240, 0x7f130005, 0x27300001, 0x9b000002, 0x8c001688,
+ 0x8c00120d, 0x8c001219, 0x8c001232, 0x04300001, 0x04340801, 0x7f130004, 0xcf400013, 0xcf01051e,
+ 0xc42d051f, 0x7ed2c005, 0x26ec0001, 0x96c0fffd, 0xcf01051f, 0xd8000055, 0xc5170309, 0x195c07f0,
+ 0x196007f6, 0x04340000, 0x95c00008, 0x09dc0001, 0x04340001, 0x95c00005, 0x09dc0001, 0x53740001,
+ 0x6b740001, 0x80001665, 0xc4a702a0, 0xc4ab0298, 0x52640020, 0x7e6a401a, 0x7f634014, 0x7e76401a,
+ 0xc4300004, 0xd8400008, 0xd8400013, 0x56680020, 0xd8113320, 0xce480298, 0xce8802a0, 0xc5170319,
+ 0xc4b702b0, 0x255c000f, 0x7f5f4001, 0xd8113330, 0xcf4802b0, 0x11340001, 0x195c07e8, 0x196007ee,
+ 0xd8353300, 0x7e1e4001, 0xd8353301, 0xce4802d0, 0xd8100309, 0xd8100319, 0xcf000008, 0x90000000,
+ 0xc4970258, 0xc48f0250, 0x51540020, 0x7cd4c01a, 0xc4af0280, 0xc4b30278, 0x52ec0020, 0x7ef2c01a,
+ 0x04140020, 0x04280000, 0x64d80001, 0x09540001, 0x54cc0001, 0x95800060, 0x8c001628, 0xc4193247,
+ 0x25980001, 0x9580005c, 0x7dc24001, 0xc41d3248, 0x25dc000f, 0x7dd2000c, 0x96000057, 0xc41d3255,
+ 0xc435324f, 0x7df5c00c, 0x99c00004, 0xc4193265, 0x25980040, 0x9580fffe, 0xc439325b, 0x1bb0003f,
+ 0x97000049, 0x1bb000e8, 0x33380003, 0x9b800046, 0x33300002, 0x9700000a, 0xc4393260, 0x1bb000e4,
+ 0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe, 0x800016f1, 0xce400013, 0xc033ffff,
+ 0x2f3000ff, 0xc439325b, 0x7f3b0009, 0xcf01325b, 0xc439325b, 0x27b800ff, 0x9b80fffe, 0xd8c00033,
+ 0xc4300009, 0x27300008, 0x9700fffe, 0x1a7003e6, 0x27380003, 0x13b80004, 0x27300003, 0x13300003,
+ 0x7fb38001, 0x1a7000e8, 0x7fb38001, 0x13300001, 0x7fb38001, 0x07b80002, 0xd8400013, 0x1a700064,
+ 0x33300002, 0x97000009, 0x17b00005, 0x07300003, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f,
+ 0x0b300003, 0x800016df, 0x17b00005, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f, 0x13300005,
+ 0x7fb30002, 0xc4392083, 0x7fb38005, 0x27b80001, 0x9b80ffdf, 0xd8c00034, 0xce400013, 0xc431325d,
+ 0x27300010, 0x9b00fffe, 0xc439325b, 0x27b000ff, 0x9b00ffca, 0xd841325d, 0x2030007b, 0xcf01325b,
+ 0x800016f2, 0xd841325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a, 0x06a80001, 0x9940ff9c, 0x8c001608,
+ 0xd8080278, 0xd8080280, 0x90000000, 0xd840004f, 0xc414000e, 0x29540008, 0xcd400013, 0xc43d3265,
+ 0x1bc800ea, 0xd80802e9, 0x7c40c001, 0x18fc0064, 0x9bc00042, 0xc4193246, 0xc41d3245, 0x51980020,
+ 0x7dd9801a, 0x45980400, 0xc4313267, 0x043c3000, 0xcfc13267, 0xc43d3267, 0x9bc00001, 0x1b380057,
+ 0x1b340213, 0x1b300199, 0x7f7b400a, 0x7f73400a, 0xcf400024, 0x14f4001d, 0xc4bf02e9, 0x9bc0001c,
+ 0x7c410001, 0x192807fa, 0xc4bf0258, 0xc4a70250, 0x53fc0020, 0x7e7e401a, 0x042c0000, 0x04300000,
+ 0x667c0001, 0x56640001, 0x06ec0001, 0x97c0fffd, 0x07300001, 0x0aec0001, 0x7eebc00c, 0x06ec0001,
+ 0x97c0fff8, 0x0b300001, 0x43300007, 0x53300002, 0x7db30011, 0xd3000025, 0xc03ec005, 0x2bfca200,
+ 0xcfc00026, 0xccc00026, 0xcd000026, 0x192807fa, 0xc01f007f, 0x7d1d0009, 0x2110007d, 0x8c001628,
+ 0x203c003f, 0xcfc13256, 0x8c0017f5, 0xcd013254, 0x18fc01e8, 0xcfc13248, 0x8c00185b, 0xd8413247,
+ 0x0b740001, 0x9b40ffd5, 0xd800004f, 0xc4bf02e9, 0x97c0ea24, 0x90000000, 0x14d4001d, 0xc4930260,
+ 0x7d52400e, 0xc49f0258, 0xc4a30250, 0x51dc0020, 0x7de1801a, 0x96400017, 0x7d534002, 0xc4af0270,
+ 0x7dae4005, 0x26640001, 0x32e0001f, 0x9a400006, 0x06ec0001, 0x96000002, 0x042c0000, 0xcec80270,
+ 0x8000174f, 0x0b740001, 0x8c00178a, 0x05100001, 0x9b40fff3, 0xc4af0280, 0xc4b30278, 0x52ec0020,
+ 0x7ef2c01a, 0x8c001608, 0xd8080278, 0xd8080280, 0xc4ab0268, 0x7daa4005, 0x26640001, 0x32a0001f,
+ 0x9a400005, 0x06a80001, 0x96000002, 0x24280000, 0x80001765, 0x7c410001, 0xc01f007f, 0x09540001,
+ 0x7d1d0009, 0x2110007d, 0x8c001628, 0xd8013256, 0x8c0017f2, 0xcd013254, 0xc4113248, 0x15100004,
+ 0x11100004, 0xc4b3034b, 0x7f13000a, 0xcf013248, 0xc4930260, 0x8c001855, 0x32a4001f, 0xd8413247,
+ 0xd800004f, 0x09100001, 0x06a80001, 0x96400002, 0x24280000, 0xcd080260, 0xce880268, 0x9940ffc0,
+ 0x7c408001, 0x88000000, 0x7ec28001, 0x8c001628, 0x32e0001f, 0xc4253247, 0x26640001, 0x9640005e,
+ 0xc4293265, 0xc4253255, 0xc431324f, 0x7e72400c, 0x26a80040, 0x9a400002, 0x9680fff7, 0xc429325b,
+ 0x1aa4003f, 0x96400049, 0x1aa400e8, 0x32680003, 0x9a800046, 0x32640002, 0x9640000a, 0xc4293260,
+ 0x1aa400e4, 0x32640004, 0x96400040, 0xc425325d, 0x26640010, 0x9a40fffe, 0x800017e2, 0xcdc00013,
+ 0xc027ffff, 0x2e6400ff, 0xc429325b, 0x7e6a4009, 0xce41325b, 0xc429325b, 0x26a800ff, 0x9a80fffe,
+ 0xd8c00033, 0xc4240009, 0x26640008, 0x9640fffe, 0x19e403e6, 0x26680003, 0x12a80004, 0x26640003,
+ 0x12640003, 0x7ea68001, 0x19e400e8, 0x7ea68001, 0x12640001, 0x7ea68001, 0x06a80002, 0xd8400013,
+ 0x19e40064, 0x32640002, 0x96400009, 0x16a40005, 0x06640003, 0xce412082, 0xcc01203f, 0xd8400013,
+ 0xcc01203f, 0x0a640003, 0x800017d0, 0x16a40005, 0xce412082, 0xcc01203f, 0xd8400013, 0xcc01203f,
+ 0x12640005, 0x7ea64002, 0xc4292083, 0x7ea68005, 0x26a80001, 0x9a80ffdf, 0xd8c00034, 0xcdc00013,
+ 0xc425325d, 0x26640010, 0x9a40fffe, 0xc429325b, 0x26a400ff, 0x9a40ffca, 0xd841325d, 0x2024007b,
+ 0xce41325b, 0x800017e3, 0xd841325d, 0xc4a70280, 0xc4ab0278, 0x52640020, 0x7e6a401a, 0x04280001,
+ 0x7eae8014, 0x7e6a401a, 0x56680020, 0xce480278, 0xce880280, 0x06ec0001, 0x96000002, 0x042c0000,
+ 0xcec80270, 0x90000000, 0x7c438001, 0x7c420001, 0x800017fe, 0xc4bf02e9, 0x9bc00006, 0x7c438001,
+ 0x7c420001, 0xcf800026, 0xce000026, 0x800017fe, 0xc43b02eb, 0xc42302ec, 0xcf813245, 0xce013246,
+ 0x52200020, 0x7fa3801a, 0x47b8020c, 0x15e00008, 0x1220000a, 0x2a206032, 0x513c001e, 0x7e3e001a,
+ 0xc4bf02e9, 0x9bc00005, 0xc43c000e, 0x2bfc0008, 0xcfc00013, 0x8000180f, 0xcd400013, 0xc4313267,
+ 0x1b3c0077, 0x1b300199, 0x7ff3000a, 0x1330000a, 0x2b300032, 0x043c3000, 0xcfc13267, 0xc43d3267,
+ 0xd200000b, 0xc4200007, 0xd3800002, 0xcf000002, 0xd8000040, 0x96000002, 0xd8400040, 0xd8400018,
+ 0x043c2000, 0xcfc13267, 0xd8000018, 0xd8800010, 0xcdc00013, 0x7dc30001, 0xdc1e0000, 0x04380032,
+ 0xcf80000e, 0x8c001427, 0xcc413248, 0xc43d3269, 0x27fc000f, 0x33fc0003, 0x97c00011, 0x043c001f,
+ 0xdfc30000, 0xd4413249, 0x7c43c001, 0x7c43c001, 0x043c0024, 0x0bfc0021, 0xdfc30000, 0xd441326a,
+ 0x173c0008, 0x1b300303, 0x7f3f0001, 0x043c0001, 0x7ff3c004, 0xcfc13084, 0x80001842, 0x043c0024,
+ 0xdfc30000, 0xd4413249, 0x7c43c001, 0x23fc003f, 0xcfc1326d, 0x0bb80026, 0xdf830000, 0xd441326e,
+ 0x7c438001, 0x7c438001, 0xc4393265, 0x1fb8ffc6, 0xddc30000, 0xcf813265, 0x9a000003, 0xcdc0000c,
+ 0x80001852, 0xcdc0000d, 0xce000010, 0x8c00142b, 0x90000000, 0x7c41c001, 0x7c420001, 0xcdc13252,
+ 0xce013253, 0x8c001628, 0x80001878, 0xc49f02e9, 0x99c00018, 0x7c41c001, 0x7c420001, 0xcdc13252,
+ 0xce013253, 0xc43c000e, 0x2bfc0008, 0xcfc00013, 0x043c3000, 0xcfc13267, 0xc43d3267, 0x97c0ffff,
+ 0xcdc00026, 0xce000026, 0xd8400027, 0xc41c0012, 0x99c0ffff, 0xc43c000e, 0x2bfc0008, 0xcfc00013,
+ 0x043c2000, 0xcfc13267, 0x8c001628, 0x80001878, 0xc41f02ed, 0xc42302ee, 0xcdc13252, 0xce013253,
+ 0x04200001, 0x7e2a0004, 0xce013084, 0x90000000, 0x28340001, 0x313c0bcc, 0x9bc00010, 0x393c051f,
+ 0x9bc00004, 0x3d3c050e, 0x9bc0000c, 0x97c0000c, 0x393c0560, 0x9bc00004, 0x3d3c054f, 0x9bc00007,
+ 0x97c00007, 0x393c1538, 0x9bc00005, 0x3d3c1537, 0x9bc00002, 0x97c00002, 0x2b740800, 0x90000000,
+ 0xc40c000e, 0x28cc0008, 0xccc00013, 0xc43d3265, 0x1bc800ea, 0x7c40c001, 0x18e8007c, 0x7c42c001,
+ 0x06a8189a, 0x86800000, 0x8000189e, 0x800018c5, 0x800018f2, 0x8000016a, 0x7c414001, 0x18d0007e,
+ 0x50580020, 0x09200001, 0x7d59401a, 0xd1400072, 0xc8140072, 0x09240002, 0x7c418001, 0x7c41c001,
+ 0x99000011, 0xc4340004, 0xd8400013, 0xd8400008, 0xc42130b5, 0x1a24002c, 0x9a40fffe, 0x2020002c,
+ 0xc418000d, 0x1198001c, 0x10cc0004, 0x14cc0004, 0x7cd8c00a, 0xccc130b7, 0xce0130b5, 0xcf400008,
+ 0x80000168, 0xd1400025, 0x5978073a, 0x2bb80002, 0xcf800024, 0xcd800026, 0xcdc00026, 0xd8400027,
+ 0x9600e8a8, 0xc4300012, 0x9b00ffff, 0x9640e8a5, 0x800018a9, 0x04140000, 0xc55b0309, 0x3d5c0010,
+ 0x05540001, 0x2598ffff, 0x09780001, 0x7dad800c, 0x99c0ffd2, 0x9580fff9, 0xc4970258, 0xc4930250,
+ 0x51540020, 0x7d15001a, 0x04140020, 0x04280000, 0x442c0000, 0x65180001, 0x09540001, 0x55100001,
+ 0x9580000b, 0x8c001628, 0xc41d3248, 0x04300001, 0x7f2b0014, 0x25dc000f, 0x7df9c00c, 0x95c00004,
+ 0x7ef2c01a, 0xd8c13260, 0xd901325d, 0x06a80001, 0x9940fff1, 0x04140020, 0x04280000, 0x66d80001,
+ 0x09540001, 0x56ec0001, 0x95800005, 0x8c001628, 0xc421325d, 0x26240007, 0x9a40fffe, 0x06a80001,
+ 0x9940fff7, 0x8000189e, 0x04140020, 0x04280000, 0x09540001, 0x8c001628, 0xc41d3254, 0xc023007f,
+ 0x19e4003e, 0x7de1c009, 0x7dee000c, 0x96400008, 0x96000007, 0xd8c13260, 0xd901325d, 0xc421325d,
+ 0x261c0007, 0x99c0fffe, 0x8000189e, 0x06a80001, 0x9940fff0, 0x8000189e, 0xc40c000e, 0x28cc0008,
+ 0xccc00013, 0xc43d3265, 0x1bc800ea, 0x7c40c001, 0x18e00064, 0x06281911, 0x14f4001d, 0x24cc0003,
+ 0x86800000, 0x80001915, 0x800019af, 0x80001a2b, 0x8000016a, 0xcc48032b, 0xcc480333, 0xcc48033b,
+ 0xcc480343, 0x98800011, 0xc4213246, 0xc4253245, 0x52200020, 0x7e26401a, 0x46640400, 0xc4313267,
+ 0x04203000, 0xce013267, 0xc4213267, 0x9a000001, 0x1b3c0057, 0x1b200213, 0x1b300199, 0x7e3e000a,
+ 0x7e32000a, 0xce000024, 0xc4970258, 0xc4930250, 0x51540020, 0x7d15001a, 0xc4af0280, 0xc4b30278,
+ 0x52ec0020, 0x7ef2c01a, 0x04180000, 0x04140020, 0x04280000, 0x7f438001, 0x8c001628, 0xc41d3247,
+ 0x25dc0001, 0x95c00068, 0xc4213254, 0x1a1c003e, 0x95c00065, 0xc01f007f, 0x7e1e0009, 0x97800062,
+ 0x0bb80001, 0x43bc0008, 0x7fcbc001, 0xc7df032b, 0x7e1fc00c, 0x97c0fffa, 0x043c0101, 0x94c00002,
+ 0x043c0102, 0xc439325b, 0x1bb0003f, 0x97000049, 0x1bb000e8, 0x33380003, 0x9b800046, 0x33300002,
+ 0x97000009, 0xc4393260, 0x1bb000e4, 0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe,
+ 0x80001994, 0x8c001628, 0xc033ffff, 0x2f3000ff, 0xc439325b, 0x7f3b0009, 0xcf01325b, 0xc439325b,
+ 0x27b800ff, 0x9b80fffe, 0xd8c00033, 0xc4300009, 0x27300008, 0x9700fffe, 0x19f003e6, 0x27380003,
+ 0x13b80004, 0x27300003, 0x13300003, 0x7fb38001, 0x19f000e8, 0x7fb38001, 0x13300001, 0x7fb38001,
+ 0x07b80002, 0xd8400013, 0x19f00064, 0x33300002, 0x97000009, 0x17b00005, 0x07300003, 0xcf012082,
+ 0xcc01203f, 0xd8400013, 0xcc01203f, 0x0b300003, 0x80001982, 0x17b00005, 0xcf012082, 0xcc01203f,
+ 0xd8400013, 0xcc01203f, 0x13300005, 0x7fb30002, 0xc4392083, 0x7fb38005, 0x27b80001, 0x9b80ffdf,
+ 0xd8c00034, 0xcdc00013, 0xc431325d, 0x27300010, 0x9b00fffe, 0xc439325b, 0x27b000ff, 0x9b00ffcb,
+ 0xcfc1325d, 0x2030007b, 0xcf01325b, 0x80001995, 0xcfc1325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a,
+ 0x98800009, 0x41bc0007, 0x53fc0002, 0x7e7fc011, 0xd3c00025, 0xd8000026, 0xd8400027, 0xc43c0012,
+ 0x9bc0ffff, 0x653c0001, 0x7dbd8001, 0x06a80001, 0x09540001, 0x55100001, 0x9940ff8f, 0xc43c000e,
+ 0x2bfc0008, 0xcfc00013, 0x043c2000, 0xcfc13267, 0xd8080278, 0xd8080280, 0x80000168, 0x7c410001,
+ 0x04140000, 0xc55b0309, 0x3d5c0010, 0x2598ffff, 0x05540001, 0x7d91800c, 0x95c00003, 0xd4400078,
+ 0x80000168, 0x9580fff8, 0x09780001, 0xc4970258, 0xc4930250, 0x51540020, 0x7d15001a, 0xc4af0280,
+ 0xc4b30278, 0x52ec0020, 0x7ef2c01a, 0x04140020, 0x04280000, 0x65180001, 0x09540001, 0x55100001,
+ 0x9580005d, 0x8c001628, 0xc4253247, 0x26640001, 0x04200101, 0x96400058, 0x7dc24001, 0xc41d3248,
+ 0x25dc000f, 0x7df9c00c, 0x95c00053, 0x94c00002, 0x04200102, 0x7e41c001, 0xc425325b, 0x1a70003f,
+ 0x97000049, 0x1a7000e8, 0x33240003, 0x9a400046, 0x33300002, 0x9700000a, 0xc4253260, 0x1a7000e4,
+ 0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe, 0x80001a21, 0xcdc00013, 0xc033ffff,
+ 0x2f3000ff, 0xc425325b, 0x7f270009, 0xcf01325b, 0xc425325b, 0x266400ff, 0x9a40fffe, 0xd8c00033,
+ 0xc4300009, 0x27300008, 0x9700fffe, 0x19f003e6, 0x27240003, 0x12640004, 0x27300003, 0x13300003,
+ 0x7e724001, 0x19f000e8, 0x7e724001, 0x13300001, 0x7e724001, 0x06640002, 0xd8400013, 0x19f00064,
+ 0x33300002, 0x97000009, 0x16700005, 0x07300003, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f,
+ 0x0b300003, 0x80001a0f, 0x16700005, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f, 0x13300005,
+ 0x7e730002, 0xc4252083, 0x7e724005, 0x26640001, 0x9a40ffdf, 0xd8c00034, 0xcdc00013, 0xc431325d,
+ 0x27300010, 0x9b00fffe, 0xc425325b, 0x267000ff, 0x9b00ffca, 0xce01325d, 0x2030007b, 0xcf01325b,
+ 0x80001a22, 0xce01325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a, 0x06a80001, 0x9940ff9f, 0xd4400078,
+ 0xd8080278, 0xd8080280, 0x80000168, 0x8c001a31, 0xd4400078, 0xd8080278, 0xd8080280, 0x7c408001,
+ 0x88000000, 0xc4213246, 0xc4253245, 0x52200020, 0x7e26401a, 0x46640400, 0xc4313267, 0x04203000,
+ 0xce013267, 0xc4213267, 0x9a000001, 0x1b180057, 0x1b200213, 0x1b300199, 0x7e1a000a, 0x7e32000a,
+ 0xce000024, 0xc4970258, 0xc4930250, 0x51540020, 0x7d15001a, 0xc4af0280, 0xc4b30278, 0x52ec0020,
+ 0x7ef2c01a, 0x04140020, 0x04280000, 0x65180001, 0x95800060, 0x8c001628, 0xc4193247, 0x25980001,
+ 0x04200101, 0x94c00005, 0x30f00005, 0x04200005, 0x9b000002, 0x04200102, 0x95800056, 0xc439325b,
+ 0x1bb0003f, 0x97000049, 0x1bb000e8, 0x33380003, 0x9b800046, 0x33300002, 0x9700000a, 0xc4393260,
+ 0x1bb000e4, 0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe, 0x80001aa2, 0xcdc00013,
+ 0xc033ffff, 0x2f3000ff, 0xc439325b, 0x7f3b0009, 0xcf01325b, 0xc439325b, 0x27b800ff, 0x9b80fffe,
+ 0xd8c00033, 0xc4300009, 0x27300008, 0x9700fffe, 0x19f003e6, 0x27380003, 0x13b80004, 0x27300003,
+ 0x13300003, 0x7fb38001, 0x19f000e8, 0x7fb38001, 0x13300001, 0x7fb38001, 0x07b80002, 0xd8400013,
+ 0x19f00064, 0x33300002, 0x97000009, 0x17b00005, 0x07300003, 0xcf012082, 0xcc01203f, 0xd8400013,
+ 0xcc01203f, 0x0b300003, 0x80001a90, 0x17b00005, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f,
+ 0x13300005, 0x7fb30002, 0xc4392083, 0x7fb38005, 0x27b80001, 0x9b80ffdf, 0xd8c00034, 0xcdc00013,
+ 0xc431325d, 0x27300010, 0x9b00fffe, 0xc439325b, 0x27b000ff, 0x9b00ffca, 0xce01325d, 0x2030007b,
+ 0xcf00325b, 0x80001aa3, 0xce01325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a, 0xc49b02e9, 0x99800005,
+ 0xd2400025, 0x4664001c, 0xd8000026, 0xd8400027, 0x06a80001, 0x09540001, 0x55100001, 0x9940ff9c,
+ 0xc49b02e9, 0x99800008, 0xc430000e, 0x2b300008, 0xcf000013, 0x04302000, 0xcf013267, 0xc4313267,
+ 0x97000001, 0x90000000, 0x244c00ff, 0xcc4c0200, 0x7c408001, 0x88000000, 0xc44f0200, 0xc410000b,
+ 0xc414000c, 0x7d158010, 0x059cc000, 0xd8400013, 0xccdd0000, 0x7c408001, 0x88000000, 0xc40c0037,
+ 0x94c0ffff, 0xcc000049, 0xc40c003a, 0x94c0ffff, 0x7c40c001, 0x24d00001, 0x9500e69a, 0x18d0003b,
+ 0x18d40021, 0x99400006, 0xd840004a, 0xc40c003c, 0x94c0ffff, 0x14cc0001, 0x94c00028, 0xd8000033,
+ 0xc438000b, 0xc43c0009, 0x27fc0001, 0x97c0fffe, 0xd8400013, 0xd841c07f, 0xc43dc07f, 0x1bfc0078,
+ 0x7ffbc00c, 0x97c0fffd, 0x99000004, 0xc0120840, 0x282c0040, 0x80001ae8, 0xc0121841, 0x282c001a,
+ 0xcd01c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079, 0xcc01c07e, 0x04200004, 0xcec0001b, 0xd8400021,
+ 0x0a200001, 0x9a00ffff, 0xc425c07f, 0x166c001f, 0x04200004, 0x9ac0fffb, 0xc434000f, 0x9b40ffff,
+ 0xd801c07f, 0xd8400013, 0xc425c07f, 0xce400078, 0xd8000034, 0x9940e66b, 0xd800004a, 0x7c408001,
+ 0x88000000, 0xc40c0036, 0x24d00001, 0x9900fffe, 0x18cc0021, 0xccc00047, 0xcc000046, 0xc40c0039,
+ 0x94c0ffff, 0xc40c003d, 0x98c0ffff, 0x7c40c001, 0x24d003ff, 0x18d47fea, 0x18d87ff4, 0xcd00004c,
+ 0xcd40004e, 0xcd80004d, 0xd8400013, 0xcd41c405, 0xc02a0001, 0x2aa80001, 0xce800013, 0xcd01c406,
+ 0xcc01c406, 0xcc01c406, 0xc40c0006, 0x98c0ffff, 0xc414000e, 0x29540008, 0x295c0001, 0xcd400013,
+ 0xd8c1325e, 0xcdc0001a, 0x11980002, 0x4110000c, 0xc0160800, 0x7d15000a, 0xc0164010, 0xd8400013,
+ 0xcd41c078, 0xcc01c080, 0xcc01c081, 0xcd81c082, 0xcc01c083, 0xcd01c084, 0xc40c0006, 0x98c0ffff,
+ 0xd8400048, 0xc40c003b, 0x94c0ffff, 0x80000c16, 0xd8400013, 0xd801c40a, 0xd901c40d, 0xd801c410,
+ 0xd801c40e, 0xd801c40f, 0xc40c0040, 0x04140001, 0x09540001, 0x9940ffff, 0x04140096, 0xd8400013,
+ 0xccc1c400, 0xc411c401, 0x9500fffa, 0xc424003e, 0x04d00001, 0x11100002, 0xcd01c40c, 0xc0180034,
+ 0xcd81c411, 0xd841c414, 0x0a540001, 0xcd41c412, 0x2468000f, 0xc419c416, 0x41980003, 0xc41c003f,
+ 0x7dda0001, 0x12200002, 0x10cc0002, 0xccc1c40c, 0xd901c411, 0xce41c412, 0xd8800013, 0xce292e40,
+ 0xcc412e01, 0xcc412e02, 0xcc412e03, 0xcc412e00, 0x80000aa7, 0xc43c0007, 0xdc120000, 0x31144000,
+ 0x95400005, 0xdc030000, 0xd800002a, 0xcc3c000c, 0x80001b70, 0x33f80003, 0xd4400078, 0x9780e601,
+ 0x188cfff0, 0x04e40002, 0x80001190, 0x7c408001, 0x88000000, 0xc424005e, 0x96400006, 0x90000000,
+ 0xc424005e, 0x96400003, 0x7c408001, 0x88000000, 0x80001b74, 0x80000168, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
+ 0xbf810000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ },
+ .dfy_size = 7440
+};
+
+static const PWR_DFY_Section pwr_virus_section4 = {
+ .dfy_cntl = 0x80000004,
+ .dfy_addr_hi = 0x000000b4,
+ .dfy_addr_lo = 0x54106500,
+ .dfy_data = {
+ 0x7e000200, 0x7e020204, 0xc00a0505, 0x00000000, 0xbf8c007f, 0xb8900904, 0xb8911a04, 0xb8920304,
+ 0xb8930b44, 0x921c0d0c, 0x921c1c13, 0x921d0c12, 0x811c1d1c, 0x811c111c, 0x921cff1c, 0x00000400,
+ 0x921dff10, 0x00000100, 0x81181d1c, 0x7e040218, 0xe0701000, 0x80050002, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0701000, 0x80050102,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0701000, 0x80050002, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0701000, 0x80050102, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0701000, 0x80050002, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0701000, 0x80050102,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
+ 0xbf810000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ },
+ .dfy_size = 240
+};
+
+static const PWR_DFY_Section pwr_virus_section5 = {
+ .dfy_cntl = 0x80000004,
+ .dfy_addr_hi = 0x000000b4,
+ .dfy_addr_lo = 0x54106900,
+ .dfy_data = {
+ 0x7e080200, 0x7e100204, 0xbefc00ff, 0x00010000, 0x24200087, 0x262200ff, 0x000001f0, 0x20222282,
+ 0x28182111, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
+ 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
+ 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
+ 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
+ 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
+ 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
+ 0x1100000c, 0xbf810000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ },
+ .dfy_size = 384
+};
+
+static const PWR_DFY_Section pwr_virus_section6 = {
+ .dfy_cntl = 0x80000004,
+ .dfy_addr_hi = 0x000000b4,
+ .dfy_addr_lo = 0x54116f00,
+ .dfy_data = {
+ 0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb4540fe8, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000041, 0x0000000c, 0x00000000, 0x07808000, 0xffffffff,
+ 0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
+ 0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x54116f00, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
+ 0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
+ 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb454105e, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x000000c0, 0x00000010, 0x00000000, 0x07808000, 0xffffffff,
+ 0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
+ 0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x54117300, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
+ 0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
+ 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb4541065, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000500, 0x0000001c, 0x00000000, 0x07808000, 0xffffffff,
+ 0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
+ 0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x54117700, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
+ 0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
+ 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb4541069, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000444, 0x0000008a, 0x00000000, 0x07808000, 0xffffffff,
+ 0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
+ 0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x54117b00, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
+ 0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
+ 0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ },
+ .dfy_size = 1024
+};
+
+static const PWR_Command_Table pwr_virus_table_post[] = {
+ { 0x00000000, mmCP_MEC_CNTL },
+ { 0x00000000, mmCP_MEC_CNTL },
+ { 0x00000004, mmSRBM_GFX_CNTL },
+ { 0x54116f00, mmCP_MQD_BASE_ADDR },
+ { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
+ { 0xb4540fef, mmCP_HQD_PQ_BASE },
+ { 0x00000000, mmCP_HQD_PQ_BASE_HI },
+ { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
+ { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
+ { 0x00005301, mmCP_HQD_PERSISTENT_STATE },
+ { 0x00010000, mmCP_HQD_VMID },
+ { 0xc8318509, mmCP_HQD_PQ_CONTROL },
+ { 0x00000005, mmSRBM_GFX_CNTL },
+ { 0x54117300, mmCP_MQD_BASE_ADDR },
+ { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
+ { 0xb4540fef, mmCP_HQD_PQ_BASE },
+ { 0x00000000, mmCP_HQD_PQ_BASE_HI },
+ { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
+ { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
+ { 0x00005301, mmCP_HQD_PERSISTENT_STATE },
+ { 0x00010000, mmCP_HQD_VMID },
+ { 0xc8318509, mmCP_HQD_PQ_CONTROL },
+ { 0x00000006, mmSRBM_GFX_CNTL },
+ { 0x54117700, mmCP_MQD_BASE_ADDR },
+ { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
+ { 0xb4540fef, mmCP_HQD_PQ_BASE },
+ { 0x00000000, mmCP_HQD_PQ_BASE_HI },
+ { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
+ { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
+ { 0x00005301, mmCP_HQD_PERSISTENT_STATE },
+ { 0x00010000, mmCP_HQD_VMID },
+ { 0xc8318509, mmCP_HQD_PQ_CONTROL },
+ { 0x00000007, mmSRBM_GFX_CNTL },
+ { 0x54117b00, mmCP_MQD_BASE_ADDR },
+ { 0x000000b4, mmCP_MQD_BASE_ADDR_HI },
+ { 0xb4540fef, mmCP_HQD_PQ_BASE },
+ { 0x00000000, mmCP_HQD_PQ_BASE_HI },
+ { 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR },
+ { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
+ { 0x00005301, mmCP_HQD_PERSISTENT_STATE },
+ { 0x00010000, mmCP_HQD_VMID },
+ { 0xc8318509, mmCP_HQD_PQ_CONTROL },
+ { 0x00000004, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000104, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000204, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000304, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000404, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000504, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000604, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000704, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000005, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000105, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000205, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000305, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000405, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000505, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000605, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000705, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000006, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000106, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000206, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000306, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000406, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000506, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000606, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000706, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000007, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000107, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000207, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000307, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000407, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000507, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000607, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000707, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000008, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000108, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000208, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000308, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000408, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000508, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000608, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000708, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000009, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000109, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000209, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000309, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000409, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000509, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000609, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000709, mmSRBM_GFX_CNTL },
+ { 0x00000000, mmCP_HQD_ACTIVE },
+ { 0x00000000, mmCP_HQD_PQ_RPTR },
+ { 0x00000000, mmCP_HQD_PQ_WPTR },
+ { 0x00000001, mmCP_HQD_ACTIVE },
+ { 0x00000004, mmSRBM_GFX_CNTL },
+ { 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 },
+ { 0x00000000, mmGRBM_STATUS },
+ { 0x00000000, mmGRBM_STATUS },
+ { 0x00000000, mmGRBM_STATUS },
+ { 0x00000000, 0xFFFFFFFF },
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
index 4c3b537..7d1eec5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
@@ -23,22 +23,15 @@
#ifndef _PP_INSTANCE_H_
#define _PP_INSTANCE_H_
-#include "smumgr.h"
#include "hwmgr.h"
-#include "eventmgr.h"
-
-#define PP_VALID 0x1F1F1F1F
struct pp_instance {
- uint32_t pp_valid;
uint32_t chip_family;
uint32_t chip_id;
bool pm_en;
uint32_t feature_mask;
void *device;
- struct pp_smumgr *smu_mgr;
struct pp_hwmgr *hwmgr;
- struct pp_eventmgr *eventmgr;
struct mutex pp_lock;
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 901c960c..2b34971 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -70,7 +70,12 @@
#define PPSMC_MSG_SetPhyclkVoltageByFreq 0x26
#define PPSMC_MSG_SetDppclkVoltageByFreq 0x27
#define PPSMC_MSG_SetSoftMinVcn 0x28
-#define PPSMC_Message_Count 0x29
+#define PPSMC_MSG_GetGfxclkFrequency 0x2A
+#define PPSMC_MSG_GetFclkFrequency 0x2B
+#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
+#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
+#define PPSMC_MSG_SoftReset 0x2E
+#define PPSMC_Message_Count 0x2F
typedef uint16_t PPSMC_Result;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 5d61cc9..b1b27b2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -23,23 +23,13 @@
#ifndef _SMUMGR_H_
#define _SMUMGR_H_
#include <linux/types.h>
-#include "pp_instance.h"
#include "amd_powerplay.h"
-
-struct pp_smumgr;
-struct pp_instance;
-struct pp_hwmgr;
+#include "hwmgr.h"
#define smu_lower_32_bits(n) ((uint32_t)(n))
#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
-extern const struct pp_smumgr_func cz_smu_funcs;
-extern const struct pp_smumgr_func iceland_smu_funcs;
-extern const struct pp_smumgr_func tonga_smu_funcs;
-extern const struct pp_smumgr_func fiji_smu_funcs;
-extern const struct pp_smumgr_func polaris10_smu_funcs;
-extern const struct pp_smumgr_func vega10_smu_funcs;
-extern const struct pp_smumgr_func rv_smu_funcs;
+
enum AVFS_BTC_STATUS {
AVFS_BTC_BOOT = 0,
@@ -85,6 +75,11 @@ enum SMU_MEMBER {
VceBootLevel,
SamuBootLevel,
LowSclkInterruptThreshold,
+ DRAM_LOG_ADDR_H,
+ DRAM_LOG_ADDR_L,
+ DRAM_LOG_PHY_ADDR_H,
+ DRAM_LOG_PHY_ADDR_L,
+ DRAM_LOG_BUFF_SIZE,
};
@@ -100,216 +95,44 @@ enum SMU_MAC_DEFINITION {
SMU_UVD_MCLK_HANDSHAKE_DISABLE,
};
+extern int smum_get_argument(struct pp_hwmgr *hwmgr);
-struct pp_smumgr_func {
- int (*smu_init)(struct pp_smumgr *smumgr);
- int (*smu_fini)(struct pp_smumgr *smumgr);
- int (*start_smu)(struct pp_smumgr *smumgr);
- int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
- uint32_t firmware);
- int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
- int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
- uint32_t firmware);
- int (*get_argument)(struct pp_smumgr *smumgr);
- int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
- int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
- uint16_t msg, uint32_t parameter);
- int (*download_pptable_settings)(struct pp_smumgr *smumgr,
- void **table);
- int (*upload_pptable_settings)(struct pp_smumgr *smumgr);
- int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
- int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
- int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
- int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
- int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
- int (*init_smc_table)(struct pp_hwmgr *hwmgr);
- int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
- int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
- int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
- uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
- uint32_t (*get_mac_definition)(uint32_t value);
- bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
- int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request);
- bool (*is_hw_avfs_present)(struct pp_smumgr *smumgr);
-};
+extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
-struct pp_smumgr {
- uint32_t chip_family;
- uint32_t chip_id;
- void *device;
- void *backend;
- uint32_t usec_timeout;
- bool reload_fw;
- const struct pp_smumgr_func *smumgr_funcs;
- bool is_kicker;
-};
+extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
-extern int smum_early_init(struct pp_instance *handle);
+extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
-extern int smum_get_argument(struct pp_smumgr *smumgr);
-
-extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table);
-
-extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);
-
-extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
-
-extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
+extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
-extern int smum_wait_on_register(struct pp_smumgr *smumgr,
- uint32_t index, uint32_t value, uint32_t mask);
-
-extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
- uint32_t index, uint32_t value, uint32_t mask);
-
-extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
- uint32_t indirect_port, uint32_t index,
- uint32_t value, uint32_t mask);
-
-
-extern void smum_wait_for_indirect_register_unequal(
- struct pp_smumgr *smumgr,
- uint32_t indirect_port, uint32_t index,
- uint32_t value, uint32_t mask);
-
extern int smu_allocate_memory(void *device, uint32_t size,
enum cgs_gpu_mem_type type,
uint32_t byte_align, uint64_t *mc_addr,
void **kptr, void *handle);
extern int smu_free_memory(void *device, void *handle);
-extern int vega10_smum_init(struct pp_smumgr *smumgr);
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
-extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result);
-extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result);
+extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
+extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
-extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr,
+extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
uint32_t type, uint32_t member);
-extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value);
+extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request);
-extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
+extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
-#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
-
-#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
-
-#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
- port, index, value, mask) \
- smum_wait_on_indirect_register(smumgr, \
- mm##port##_INDEX, index, value, mask)
-
-#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
- SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
-
-#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
- SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
- SMUM_FIELD_MASK(reg, field) )
-
-#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
- index, value, mask) \
- smum_wait_for_register_unequal(smumgr, \
- index, value, mask)
-
-#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \
- SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
- mm##reg, value, mask)
-
-#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \
- SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \
- (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
- SMUM_FIELD_MASK(reg, field))
-
-#define SMUM_GET_FIELD(value, reg, field) \
- (((value) & SMUM_FIELD_MASK(reg, field)) \
- >> SMUM_FIELD_SHIFT(reg, field))
-
-#define SMUM_READ_FIELD(device, reg, field) \
- SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
-
-#define SMUM_SET_FIELD(value, reg, field, field_val) \
- (((value) & ~SMUM_FIELD_MASK(reg, field)) | \
- (SMUM_FIELD_MASK(reg, field) & ((field_val) << \
- SMUM_FIELD_SHIFT(reg, field))))
-
-#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
- SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field)
-
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
- port, index, value, mask) \
- smum_wait_on_indirect_register(smumgr, \
- mm##port##_INDEX_0, index, value, mask)
-
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
- port, index, value, mask) \
- smum_wait_for_indirect_register_unequal(smumgr, \
- mm##port##_INDEX_0, index, value, mask)
-
-
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
- SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
-
-#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
- SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
-
-
-/*Operations on named fields.*/
-
-#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
- SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field)
-
-#define SMUM_WRITE_FIELD(device, reg, field, fieldval) \
- cgs_write_register(device, mm##reg, \
- SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval))
-
-#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
- cgs_write_ind_register(device, port, ix##reg, \
- SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field, fieldval))
-
-
-#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
- cgs_write_ind_register(device, port, ix##reg, \
- SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
- reg, field, fieldval))
-
-
-#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
- SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \
- (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
- SMUM_FIELD_MASK(reg, field))
-
-#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
- SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \
- (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
- SMUM_FIELD_MASK(reg, field))
-
-#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \
- smum_wait_for_indirect_register_unequal(smumgr, \
- mm##port##_INDEX, index, value, mask)
-
-#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
- SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
-
-#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
- SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
- SMUM_FIELD_MASK(reg, field) )
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
index cb070eb..247c973 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
@@ -124,12 +124,15 @@ typedef uint16_t PPSMC_Result;
#define PPSMC_MSG_NumOfDisplays 0x56
#define PPSMC_MSG_ReadSerialNumTop32 0x58
#define PPSMC_MSG_ReadSerialNumBottom32 0x59
+#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x5A
+#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x5B
#define PPSMC_MSG_RunAcgBtc 0x5C
#define PPSMC_MSG_RunAcgInClosedLoop 0x5D
#define PPSMC_MSG_RunAcgInOpenLoop 0x5E
#define PPSMC_MSG_InitializeAcg 0x5F
#define PPSMC_MSG_GetCurrPkgPwr 0x61
-#define PPSMC_Message_Count 0x62
+#define PPSMC_MSG_UpdatePkgPwrPidAlpha 0x68
+#define PPSMC_Message_Count 0x69
typedef int PPSMC_Msg;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
index e7ad452..30d3089 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
@@ -3,9 +3,9 @@
# Makefile for the 'smu manager' sub-component of powerplay.
# It provides the smu management services for the driver.
-SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
- polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
- smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o
+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o \
+ polaris10_smumgr.o iceland_smumgr.o \
+ smu7_smumgr.o vega10_smumgr.o rv_smumgr.o ci_smumgr.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
new file mode 100644
index 0000000..4d672cd
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -0,0 +1,2818 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include "linux/delay.h"
+#include <linux/types.h>
+
+#include "smumgr.h"
+#include "pp_debug.h"
+#include "ci_smumgr.h"
+#include "ppsmc.h"
+#include "smu7_hwmgr.h"
+#include "hardwaremanager.h"
+#include "ppatomctrl.h"
+#include "cgs_common.h"
+#include "atombios.h"
+#include "pppcielanes.h"
+
+#include "smu/smu_7_0_1_d.h"
+#include "smu/smu_7_0_1_sh_mask.h"
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "bif/bif_4_1_d.h"
+#include "bif/bif_4_1_sh_mask.h"
+
+#include "gca/gfx_7_2_d.h"
+#include "gca/gfx_7_2_sh_mask.h"
+
+#include "gmc/gmc_7_1_d.h"
+#include "gmc/gmc_7_1_sh_mask.h"
+
+#include "processpptables.h"
+
+#define MC_CG_ARB_FREQ_F0 0x0a
+#define MC_CG_ARB_FREQ_F1 0x0b
+#define MC_CG_ARB_FREQ_F2 0x0c
+#define MC_CG_ARB_FREQ_F3 0x0d
+
+#define SMC_RAM_END 0x40000
+
+#define VOLTAGE_SCALE 4
+#define VOLTAGE_VID_OFFSET_SCALE1 625
+#define VOLTAGE_VID_OFFSET_SCALE2 100
+#define CISLAND_MINIMUM_ENGINE_CLOCK 800
+#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
+
+static const struct ci_pt_defaults defaults_hawaii_xt = {
+ 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
+ { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
+ { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
+};
+
+static const struct ci_pt_defaults defaults_hawaii_pro = {
+ 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
+ { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
+ { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
+};
+
+static const struct ci_pt_defaults defaults_bonaire_xt = {
+ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
+ { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
+ { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
+};
+
+
+static const struct ci_pt_defaults defaults_saturn_xt = {
+ 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
+ { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
+ { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
+};
+
+
+static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
+ uint32_t smc_addr, uint32_t limit)
+{
+ if ((0 != (3 & smc_addr))
+ || ((smc_addr + 3) >= limit)) {
+ pr_err("smc_addr invalid \n");
+ return -EINVAL;
+ }
+
+ cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
+ return 0;
+}
+
+static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
+ const uint8_t *src, uint32_t byte_count, uint32_t limit)
+{
+ int result;
+ uint32_t data = 0;
+ uint32_t original_data;
+ uint32_t addr = 0;
+ uint32_t extra_shift;
+
+ if ((3 & smc_start_address)
+ || ((smc_start_address + byte_count) >= limit)) {
+ pr_err("smc_start_address invalid \n");
+ return -EINVAL;
+ }
+
+ addr = smc_start_address;
+
+ while (byte_count >= 4) {
+ /* Bytes are written into the SMC address space with the MSB first. */
+ data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
+
+ result = ci_set_smc_sram_address(hwmgr, addr, limit);
+
+ if (0 != result)
+ return result;
+
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
+
+ src += 4;
+ byte_count -= 4;
+ addr += 4;
+ }
+
+ if (0 != byte_count) {
+
+ data = 0;
+
+ result = ci_set_smc_sram_address(hwmgr, addr, limit);
+
+ if (0 != result)
+ return result;
+
+
+ original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
+
+ extra_shift = 8 * (4 - byte_count);
+
+ while (byte_count > 0) {
+ /* Bytes are written into the SMC addres space with the MSB first. */
+ data = (0x100 * data) + *src++;
+ byte_count--;
+ }
+
+ data <<= extra_shift;
+
+ data |= (original_data & ~((~0UL) << extra_shift));
+
+ result = ci_set_smc_sram_address(hwmgr, addr, limit);
+
+ if (0 != result)
+ return result;
+
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
+ }
+
+ return 0;
+}
+
+
+static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
+{
+ static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
+
+ ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
+
+ return 0;
+}
+
+bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
+{
+ return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
+ && (0x20100 <= cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, ixSMC_PC_C)));
+}
+
+static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
+ uint32_t *value, uint32_t limit)
+{
+ int result;
+
+ result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
+
+ if (result)
+ return result;
+
+ *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
+ return 0;
+}
+
+static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
+{
+ int ret;
+
+ if (!ci_is_smc_ram_running(hwmgr))
+ return -EINVAL;
+
+ cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
+
+ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
+
+ ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
+
+ if (ret != 1)
+ pr_info("\n failed to send message %x ret is %d\n", msg, ret);
+
+ return 0;
+}
+
+static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
+ uint16_t msg, uint32_t parameter)
+{
+ cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
+ return ci_send_msg_to_smc(hwmgr, msg);
+}
+
+static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ struct cgs_system_info sys_info = {0};
+ uint32_t dev_id;
+
+ sys_info.size = sizeof(struct cgs_system_info);
+ sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
+ cgs_query_system_info(hwmgr->device, &sys_info);
+ dev_id = (uint32_t)sys_info.value;
+
+ switch (dev_id) {
+ case 0x67BA:
+ case 0x66B1:
+ smu_data->power_tune_defaults = &defaults_hawaii_pro;
+ break;
+ case 0x67B8:
+ case 0x66B0:
+ smu_data->power_tune_defaults = &defaults_hawaii_xt;
+ break;
+ case 0x6640:
+ case 0x6641:
+ case 0x6646:
+ case 0x6647:
+ smu_data->power_tune_defaults = &defaults_saturn_xt;
+ break;
+ case 0x6649:
+ case 0x6650:
+ case 0x6651:
+ case 0x6658:
+ case 0x665C:
+ case 0x665D:
+ case 0x67A0:
+ case 0x67A1:
+ case 0x67A2:
+ case 0x67A8:
+ case 0x67A9:
+ case 0x67AA:
+ case 0x67B9:
+ case 0x67BE:
+ default:
+ smu_data->power_tune_defaults = &defaults_bonaire_xt;
+ break;
+ }
+}
+
+static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
+ struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
+ uint32_t clock, uint32_t *vol)
+{
+ uint32_t i = 0;
+
+ if (allowed_clock_voltage_table->count == 0)
+ return -EINVAL;
+
+ for (i = 0; i < allowed_clock_voltage_table->count; i++) {
+ if (allowed_clock_voltage_table->entries[i].clk >= clock) {
+ *vol = allowed_clock_voltage_table->entries[i].v;
+ return 0;
+ }
+ }
+
+ *vol = allowed_clock_voltage_table->entries[i - 1].v;
+ return 0;
+}
+
+static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr,
+ uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ uint32_t ref_clock;
+ uint32_t ref_divider;
+ uint32_t fbdiv;
+ int result;
+
+ /* get the engine clock dividers for this clock value */
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.",
+ return result);
+
+ /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
+ ref_clock = atomctrl_get_reference_clock(hwmgr);
+ ref_divider = 1 + dividers.uc_pll_ref_div;
+
+ /* low 14 bits is fraction and high 12 bits is divider */
+ fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
+
+ /* SPLL_FUNC_CNTL setup */
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_REF_DIV, dividers.uc_pll_ref_div);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_PDIV_A, dividers.uc_pll_post_div);
+
+ /* SPLL_FUNC_CNTL_3 setup*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
+ SPLL_FB_DIV, fbdiv);
+
+ /* set to use fractional accumulation*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
+ SPLL_DITHEN, 1);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
+ struct pp_atomctrl_internal_ss_info ss_info;
+ uint32_t vco_freq = clock * dividers.uc_pll_post_div;
+
+ if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
+ vco_freq, &ss_info)) {
+ uint32_t clk_s = ref_clock * 5 /
+ (ref_divider * ss_info.speed_spectrum_rate);
+ uint32_t clk_v = 4 * ss_info.speed_spectrum_percentage *
+ fbdiv / (clk_s * 10000);
+
+ cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
+ CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
+ cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
+ CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
+ cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
+ CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
+ }
+ }
+
+ sclk->SclkFrequency = clock;
+ sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
+ sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
+ sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
+ sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
+ sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
+
+ return 0;
+}
+
+static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
+ const struct phm_phase_shedding_limits_table *pl,
+ uint32_t sclk, uint32_t *p_shed)
+{
+ unsigned int i;
+
+ /* use the minimum phase shedding */
+ *p_shed = 1;
+
+ for (i = 0; i < pl->count; i++) {
+ if (sclk < pl->entries[i].Sclk) {
+ *p_shed = i;
+ break;
+ }
+ }
+}
+
+static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,
+ uint32_t clock_insr)
+{
+ uint8_t i;
+ uint32_t temp;
+ uint32_t min = min_t(uint32_t, clock_insr, CISLAND_MINIMUM_ENGINE_CLOCK);
+
+ if (clock < min) {
+ pr_info("Engine clock can't satisfy stutter requirement!\n");
+ return 0;
+ }
+ for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
+ temp = clock >> i;
+
+ if (temp >= min || i == 0)
+ break;
+ }
+ return i;
+}
+
+static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ uint32_t clock, uint16_t sclk_al_threshold,
+ struct SMU7_Discrete_GraphicsLevel *level)
+{
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+
+ result = ci_calculate_sclk_params(hwmgr, clock, level);
+
+ /* populate graphics levels */
+ result = ci_get_dependency_volt_by_clk(hwmgr,
+ hwmgr->dyn_state.vddc_dependency_on_sclk, clock,
+ (uint32_t *)(&level->MinVddc));
+ if (result) {
+ pr_err("vdd_dep_on_sclk table is NULL\n");
+ return result;
+ }
+
+ level->SclkFrequency = clock;
+ level->MinVddcPhases = 1;
+
+ if (data->vddc_phase_shed_control)
+ ci_populate_phase_value_based_on_sclk(hwmgr,
+ hwmgr->dyn_state.vddc_phase_shed_limits_table,
+ clock,
+ &level->MinVddcPhases);
+
+ level->ActivityLevel = sclk_al_threshold;
+ level->CcPwrDynRm = 0;
+ level->CcPwrDynRm1 = 0;
+ level->EnabledForActivity = 0;
+ /* this level can be used for throttling.*/
+ level->EnabledForThrottle = 1;
+ level->UpH = 0;
+ level->DownH = 0;
+ level->VoltageDownH = 0;
+ level->PowerThrottle = 0;
+
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkDeepSleep))
+ level->DeepSleepDivId =
+ ci_get_sleep_divider_id_from_clock(clock,
+ CISLAND_MINIMUM_ENGINE_CLOCK);
+
+ /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
+ level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ if (0 == result) {
+ level->MinVddc = PP_HOST_TO_SMC_UL(level->MinVddc * VOLTAGE_SCALE);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
+ }
+
+ return result;
+}
+
+static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ int result = 0;
+ uint32_t array = smu_data->dpm_table_start +
+ offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
+ uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
+ SMU7_MAX_LEVELS_GRAPHICS;
+ struct SMU7_Discrete_GraphicsLevel *levels =
+ smu_data->smc_state_table.GraphicsLevel;
+ uint32_t i;
+
+ for (i = 0; i < dpm_table->sclk_table.count; i++) {
+ result = ci_populate_single_graphic_level(hwmgr,
+ dpm_table->sclk_table.dpm_levels[i].value,
+ (uint16_t)smu_data->activity_target[i],
+ &levels[i]);
+ if (result)
+ return result;
+ if (i > 1)
+ smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
+ if (i == (dpm_table->sclk_table.count - 1))
+ smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
+ PPSMC_DISPLAY_WATERMARK_HIGH;
+ }
+
+ smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
+
+ smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
+ data->dpm_level_enable_mask.sclk_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
+
+ result = ci_copy_bytes_to_smc(hwmgr, array,
+ (u8 *)levels, array_size,
+ SMC_RAM_END);
+
+ return result;
+
+}
+
+static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
+ smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
+ smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
+ smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
+
+ return 0;
+}
+
+static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr)
+{
+ uint16_t tdc_limit;
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
+ smu_data->power_tune_table.TDC_VDDC_PkgLimit =
+ CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
+ smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
+ defaults->tdc_vddc_throttle_release_limit_perc;
+ smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
+
+ return 0;
+}
+
+static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
+ uint32_t temp;
+
+ if (ci_read_smc_sram_dword(hwmgr,
+ fuse_table_offset +
+ offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
+ (uint32_t *)&temp, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
+ return -EINVAL);
+ else
+ smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
+
+ return 0;
+}
+
+static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
+{
+ uint16_t tmp;
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+
+ if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
+ || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
+ tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity;
+ else
+ tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
+
+ smu_data->power_tune_table.FuzzyFan_PwmSetDelta = CONVERT_FROM_HOST_TO_SMC_US(tmp);
+
+ return 0;
+}
+
+static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
+ uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
+ uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2;
+
+ PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
+ "The CAC Leakage table does not exist!", return -EINVAL);
+ PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
+ "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
+ PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
+ "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
+
+ for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
+ lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
+ hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
+ hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3);
+ } else {
+ lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc);
+ hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage);
+ }
+ }
+
+ return 0;
+}
+
+static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ uint8_t *vid = smu_data->power_tune_table.VddCVid;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
+ "There should never be more than 8 entries for VddcVid!!!",
+ return -EINVAL);
+
+ for (i = 0; i < (int)data->vddc_voltage_table.count; i++)
+ vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
+
+ return 0;
+}
+
+static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
+ u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
+ int i, min, max;
+
+ min = max = hi_vid[0];
+ for (i = 0; i < 8; i++) {
+ if (0 != hi_vid[i]) {
+ if (min > hi_vid[i])
+ min = hi_vid[i];
+ if (max < hi_vid[i])
+ max = hi_vid[i];
+ }
+
+ if (0 != lo_vid[i]) {
+ if (min > lo_vid[i])
+ min = lo_vid[i];
+ if (max < lo_vid[i])
+ max = lo_vid[i];
+ }
+ }
+
+ if ((min == 0) || (max == 0))
+ return -EINVAL;
+ smu_data->power_tune_table.GnbLPMLMaxVid = (u8)max;
+ smu_data->power_tune_table.GnbLPMLMinVid = (u8)min;
+
+ return 0;
+}
+
+static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
+ uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
+ struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
+
+ HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
+ LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
+
+ smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
+ smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
+
+ return 0;
+}
+
+static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ uint32_t pm_fuse_table_offset;
+ int ret = 0;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment)) {
+ if (ci_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU7_Firmware_Header, PmFuseTable),
+ &pm_fuse_table_offset, SMC_RAM_END)) {
+ pr_err("Attempt to get pm_fuse_table_offset Failed!\n");
+ return -EINVAL;
+ }
+
+ /* DW0 - DW3 */
+ ret = ci_populate_bapm_vddc_vid_sidd(hwmgr);
+ /* DW4 - DW5 */
+ ret |= ci_populate_vddc_vid(hwmgr);
+ /* DW6 */
+ ret |= ci_populate_svi_load_line(hwmgr);
+ /* DW7 */
+ ret |= ci_populate_tdc_limit(hwmgr);
+ /* DW8 */
+ ret |= ci_populate_dw8(hwmgr, pm_fuse_table_offset);
+
+ ret |= ci_populate_fuzzy_fan(hwmgr, pm_fuse_table_offset);
+
+ ret |= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(hwmgr);
+
+ ret |= ci_populate_bapm_vddc_base_leakage_sidd(hwmgr);
+ if (ret)
+ return ret;
+
+ ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
+ (uint8_t *)&smu_data->power_tune_table,
+ sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END);
+ }
+ return ret;
+}
+
+static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
+ SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
+ struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
+ struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
+ const uint16_t *def1, *def2;
+ int i, j, k;
+
+ dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
+ dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
+
+ dpm_table->DTETjOffset = 0;
+ dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
+ dpm_table->GpuTjHyst = 8;
+
+ dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
+
+ if (ppm) {
+ dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
+ dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
+ } else {
+ dpm_table->PPM_PkgPwrLimit = 0;
+ dpm_table->PPM_TemperatureLimit = 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
+ CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
+
+ dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
+ def1 = defaults->bapmti_r;
+ def2 = defaults->bapmti_rc;
+
+ for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
+ for (j = 0; j < SMU7_DTE_SOURCES; j++) {
+ for (k = 0; k < SMU7_DTE_SINKS; k++) {
+ dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
+ dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
+ def1++;
+ def2++;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
+ pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
+ uint16_t *lo)
+{
+ uint16_t v_index;
+ bool vol_found = false;
+ *hi = tab->value * VOLTAGE_SCALE;
+ *lo = tab->value * VOLTAGE_SCALE;
+
+ PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
+ "The SCLK/VDDC Dependency Table does not exist.\n",
+ return -EINVAL);
+
+ if (NULL == hwmgr->dyn_state.cac_leakage_table) {
+ pr_warn("CAC Leakage Table does not exist, using vddc.\n");
+ return 0;
+ }
+
+ for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
+ if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
+ vol_found = true;
+ if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
+ } else {
+ pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
+ }
+ break;
+ }
+ }
+
+ if (!vol_found) {
+ for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
+ if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
+ vol_found = true;
+ if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
+ } else {
+ pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
+ }
+ break;
+ }
+ }
+
+ if (!vol_found)
+ pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
+ }
+
+ return 0;
+}
+
+static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
+ pp_atomctrl_voltage_table_entry *tab,
+ SMU7_Discrete_VoltageLevel *smc_voltage_tab)
+{
+ int result;
+
+ result = ci_get_std_voltage_value_sidd(hwmgr, tab,
+ &smc_voltage_tab->StdVoltageHiSidd,
+ &smc_voltage_tab->StdVoltageLoSidd);
+ if (result) {
+ smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
+ smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
+ }
+
+ smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
+ CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
+ CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageLoSidd);
+
+ return 0;
+}
+
+static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ unsigned int count;
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ table->VddcLevelCount = data->vddc_voltage_table.count;
+ for (count = 0; count < table->VddcLevelCount; count++) {
+ result = ci_populate_smc_voltage_table(hwmgr,
+ &(data->vddc_voltage_table.entries[count]),
+ &(table->VddcLevel[count]));
+ PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
+
+ /* GPIO voltage control */
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
+ table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
+ else
+ table->VddcLevel[count].Smio = 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
+
+ return 0;
+}
+
+static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t count;
+ int result;
+
+ table->VddciLevelCount = data->vddci_voltage_table.count;
+
+ for (count = 0; count < table->VddciLevelCount; count++) {
+ result = ci_populate_smc_voltage_table(hwmgr,
+ &(data->vddci_voltage_table.entries[count]),
+ &(table->VddciLevel[count]));
+ PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
+ table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
+ else
+ table->VddciLevel[count].Smio |= 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
+
+ return 0;
+}
+
+static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t count;
+ int result;
+
+ table->MvddLevelCount = data->mvdd_voltage_table.count;
+
+ for (count = 0; count < table->MvddLevelCount; count++) {
+ result = ci_populate_smc_voltage_table(hwmgr,
+ &(data->mvdd_voltage_table.entries[count]),
+ &table->MvddLevel[count]);
+ PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
+ table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
+ else
+ table->MvddLevel[count].Smio |= 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
+
+ return 0;
+}
+
+
+static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ int result;
+
+ result = ci_populate_smc_vddc_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "can not populate VDDC voltage table to SMC", return -EINVAL);
+
+ result = ci_populate_smc_vdd_ci_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "can not populate VDDCI voltage table to SMC", return -EINVAL);
+
+ result = ci_populate_smc_mvdd_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "can not populate MVDD voltage table to SMC", return -EINVAL);
+
+ return 0;
+}
+
+static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr,
+ struct SMU7_Discrete_Ulv *state)
+{
+ uint32_t voltage_response_time, ulv_voltage;
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ state->CcPwrDynRm = 0;
+ state->CcPwrDynRm1 = 0;
+
+ result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
+ PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
+
+ if (ulv_voltage == 0) {
+ data->ulv_supported = false;
+ return 0;
+ }
+
+ if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
+ /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
+ if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
+ state->VddcOffset = 0;
+ else
+ /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
+ state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
+ } else {
+ /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
+ if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
+ state->VddcOffsetVid = 0;
+ else /* used in SVI2 Mode */
+ state->VddcOffsetVid = (uint8_t)(
+ (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
+ * VOLTAGE_VID_OFFSET_SCALE2
+ / VOLTAGE_VID_OFFSET_SCALE1);
+ }
+ state->VddcPhase = 1;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
+ CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
+
+ return 0;
+}
+
+static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_Ulv *ulv_level)
+{
+ return ci_populate_ulv_level(hwmgr, ulv_level);
+}
+
+static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ uint32_t i;
+
+/* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/
+ for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
+ table->LinkLevel[i].PcieGenSpeed =
+ (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
+ table->LinkLevel[i].PcieLaneCount =
+ (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
+ table->LinkLevel[i].EnabledForActivity = 1;
+ table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
+ table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
+ }
+
+ smu_data->smc_state_table.LinkLevelCount =
+ (uint8_t)dpm_table->pcie_speed_table.count;
+ data->dpm_level_enable_mask.pcie_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
+
+ return 0;
+}
+
+static int ci_calculate_mclk_params(
+ struct pp_hwmgr *hwmgr,
+ uint32_t memory_clock,
+ SMU7_Discrete_MemoryLevel *mclk,
+ bool strobe_mode,
+ bool dllStateOn
+ )
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
+ uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
+ uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
+ uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
+ uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
+ uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
+ uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
+ uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
+ uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
+
+ pp_atomctrl_memory_clock_param mpll_param;
+ int result;
+
+ result = atomctrl_get_memory_pll_dividers_si(hwmgr,
+ memory_clock, &mpll_param, strobe_mode);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Error retrieving Memory Clock Parameters from VBIOS.", return result);
+
+ mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
+
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
+
+ mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
+ MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
+
+ if (data->is_memory_gddr5) {
+ mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
+ MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
+ mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
+ MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
+ }
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
+ pp_atomctrl_internal_ss_info ss_info;
+ uint32_t freq_nom;
+ uint32_t tmp;
+ uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
+
+ /* for GDDR5 for all modes and DDR3 */
+ if (1 == mpll_param.qdr)
+ freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
+ else
+ freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
+
+ /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
+ tmp = (freq_nom / reference_clock);
+ tmp = tmp * tmp;
+
+ if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
+ uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
+ uint32_t clkv =
+ (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
+ ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
+
+ mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
+ mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
+ }
+ }
+
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
+
+
+ mclk->MclkFrequency = memory_clock;
+ mclk->MpllFuncCntl = mpll_func_cntl;
+ mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
+ mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
+ mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
+ mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
+ mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
+ mclk->DllCntl = dll_cntl;
+ mclk->MpllSs1 = mpll_ss1;
+ mclk->MpllSs2 = mpll_ss2;
+
+ return 0;
+}
+
+static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock,
+ bool strobe_mode)
+{
+ uint8_t mc_para_index;
+
+ if (strobe_mode) {
+ if (memory_clock < 12500)
+ mc_para_index = 0x00;
+ else if (memory_clock > 47500)
+ mc_para_index = 0x0f;
+ else
+ mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
+ } else {
+ if (memory_clock < 65000)
+ mc_para_index = 0x00;
+ else if (memory_clock > 135000)
+ mc_para_index = 0x0f;
+ else
+ mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
+ }
+
+ return mc_para_index;
+}
+
+static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
+{
+ uint8_t mc_para_index;
+
+ if (memory_clock < 10000)
+ mc_para_index = 0;
+ else if (memory_clock >= 80000)
+ mc_para_index = 0x0f;
+ else
+ mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
+
+ return mc_para_index;
+}
+
+static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
+ uint32_t memory_clock, uint32_t *p_shed)
+{
+ unsigned int i;
+
+ *p_shed = 1;
+
+ for (i = 0; i < pl->count; i++) {
+ if (memory_clock < pl->entries[i].Mclk) {
+ *p_shed = i;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int ci_populate_single_memory_level(
+ struct pp_hwmgr *hwmgr,
+ uint32_t memory_clock,
+ SMU7_Discrete_MemoryLevel *memory_level
+ )
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ int result = 0;
+ bool dll_state_on;
+ struct cgs_display_info info = {0};
+ uint32_t mclk_edc_wr_enable_threshold = 40000;
+ uint32_t mclk_edc_enable_threshold = 40000;
+ uint32_t mclk_strobe_mode_threshold = 40000;
+
+ if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
+ result = ci_get_dependency_volt_by_clk(hwmgr,
+ hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
+ }
+
+ if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
+ result = ci_get_dependency_volt_by_clk(hwmgr,
+ hwmgr->dyn_state.vddci_dependency_on_mclk,
+ memory_clock,
+ &memory_level->MinVddci);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
+ }
+
+ if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
+ result = ci_get_dependency_volt_by_clk(hwmgr,
+ hwmgr->dyn_state.mvdd_dependency_on_mclk,
+ memory_clock,
+ &memory_level->MinMvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find MinVddci voltage value from memory MVDD voltage dependency table", return result);
+ }
+
+ memory_level->MinVddcPhases = 1;
+
+ if (data->vddc_phase_shed_control) {
+ ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
+ memory_clock, &memory_level->MinVddcPhases);
+ }
+
+ memory_level->EnabledForThrottle = 1;
+ memory_level->EnabledForActivity = 1;
+ memory_level->UpH = 0;
+ memory_level->DownH = 100;
+ memory_level->VoltageDownH = 0;
+
+ /* Indicates maximum activity level for this performance level.*/
+ memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+ memory_level->StutterEnable = 0;
+ memory_level->StrobeEnable = 0;
+ memory_level->EdcReadEnable = 0;
+ memory_level->EdcWriteEnable = 0;
+ memory_level->RttEnable = 0;
+
+ /* default set to low watermark. Highest level will be set to high later.*/
+ memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ cgs_get_active_displays_info(hwmgr->device, &info);
+ data->display_timing.num_existing_displays = info.display_count;
+
+ /* stutter mode not support on ci */
+
+ /* decide strobe mode*/
+ memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
+ (memory_clock <= mclk_strobe_mode_threshold);
+
+ /* decide EDC mode and memory clock ratio*/
+ if (data->is_memory_gddr5) {
+ memory_level->StrobeRatio = ci_get_mclk_frequency_ratio(memory_clock,
+ memory_level->StrobeEnable);
+
+ if ((mclk_edc_enable_threshold != 0) &&
+ (memory_clock > mclk_edc_enable_threshold)) {
+ memory_level->EdcReadEnable = 1;
+ }
+
+ if ((mclk_edc_wr_enable_threshold != 0) &&
+ (memory_clock > mclk_edc_wr_enable_threshold)) {
+ memory_level->EdcWriteEnable = 1;
+ }
+
+ if (memory_level->StrobeEnable) {
+ if (ci_get_mclk_frequency_ratio(memory_clock, 1) >=
+ ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
+ else
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
+ } else
+ dll_state_on = data->dll_default_on;
+ } else {
+ memory_level->StrobeRatio =
+ ci_get_ddr3_mclk_frequency_ratio(memory_clock);
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
+ }
+
+ result = ci_calculate_mclk_params(hwmgr,
+ memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
+
+ if (0 == result) {
+ memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
+ memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
+ memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
+ /* MCLK frequency in units of 10KHz*/
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
+ /* Indicates maximum activity level for this performance level.*/
+ CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
+ }
+
+ return result;
+}
+
+static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ int result;
+ struct cgs_system_info sys_info = {0};
+ uint32_t dev_id;
+
+ uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
+ uint32_t level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * SMU7_MAX_LEVELS_MEMORY;
+ SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
+ uint32_t i;
+
+ memset(levels, 0x00, level_array_size);
+
+ for (i = 0; i < dpm_table->mclk_table.count; i++) {
+ PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
+ "can not populate memory level as memory clock is zero", return -EINVAL);
+ result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
+ &(smu_data->smc_state_table.MemoryLevel[i]));
+ if (0 != result)
+ return result;
+ }
+
+ smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
+
+ sys_info.size = sizeof(struct cgs_system_info);
+ sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
+ cgs_query_system_info(hwmgr->device, &sys_info);
+ dev_id = (uint32_t)sys_info.value;
+
+ if ((dpm_table->mclk_table.count >= 2)
+ && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) {
+ smu_data->smc_state_table.MemoryLevel[1].MinVddci =
+ smu_data->smc_state_table.MemoryLevel[0].MinVddci;
+ smu_data->smc_state_table.MemoryLevel[1].MinMvdd =
+ smu_data->smc_state_table.MemoryLevel[0].MinMvdd;
+ }
+ smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
+
+ smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
+ data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
+ smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
+
+ result = ci_copy_bytes_to_smc(hwmgr,
+ level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
+ SMC_RAM_END);
+
+ return result;
+}
+
+static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
+ SMU7_Discrete_VoltageLevel *voltage)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ uint32_t i = 0;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
+ /* find mvdd value which clock is more than request */
+ for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
+ if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
+ /* Always round to higher voltage. */
+ voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
+ break;
+ }
+ }
+
+ PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
+ "MVDD Voltage is outside the supported range.", return -EINVAL);
+
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ int result = 0;
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct pp_atomctrl_clock_dividers_vi dividers;
+
+ SMU7_Discrete_VoltageLevel voltage_level;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
+ uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
+ uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
+
+
+ /* The ACPI state should not do DPM on DC (or ever).*/
+ table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
+
+ if (data->acpi_vddc)
+ table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
+ else
+ table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
+
+ table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;
+ /* assign zero for now*/
+ table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
+
+ /* get the engine clock dividers for this clock value*/
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
+ table->ACPILevel.SclkFrequency, ÷rs);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.", return result);
+
+ /* divider ID for required SCLK*/
+ table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
+ table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+ table->ACPILevel.DeepSleepDivId = 0;
+
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
+ spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
+ CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
+
+ table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
+ table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
+ table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ table->ACPILevel.CcPwrDynRm = 0;
+ table->ACPILevel.CcPwrDynRm1 = 0;
+
+ /* For various features to be enabled/disabled while this level is active.*/
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
+ /* SCLK frequency in units of 10KHz*/
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
+
+
+ /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
+ table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
+ table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
+ else {
+ if (data->acpi_vddci != 0)
+ table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
+ else
+ table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
+ }
+
+ if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level))
+ table->MemoryACPILevel.MinMvdd =
+ PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
+ else
+ table->MemoryACPILevel.MinMvdd = 0;
+
+ /* Force reset on DLL*/
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
+
+ /* Disable DLL in ACPIState*/
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
+
+ /* Enable DLL bypass signal*/
+ dll_cntl = PHM_SET_FIELD(dll_cntl,
+ DLL_CNTL, MRDCK0_BYPASS, 0);
+ dll_cntl = PHM_SET_FIELD(dll_cntl,
+ DLL_CNTL, MRDCK1_BYPASS, 0);
+
+ table->MemoryACPILevel.DllCntl =
+ PP_HOST_TO_SMC_UL(dll_cntl);
+ table->MemoryACPILevel.MclkPwrmgtCntl =
+ PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
+ table->MemoryACPILevel.MpllAdFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
+ table->MemoryACPILevel.MpllDqFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
+ table->MemoryACPILevel.MpllFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
+ table->MemoryACPILevel.MpllFuncCntl_1 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
+ table->MemoryACPILevel.MpllFuncCntl_2 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
+ table->MemoryACPILevel.MpllSs1 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
+ table->MemoryACPILevel.MpllSs2 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
+
+ table->MemoryACPILevel.EnabledForThrottle = 0;
+ table->MemoryACPILevel.EnabledForActivity = 0;
+ table->MemoryACPILevel.UpH = 0;
+ table->MemoryACPILevel.DownH = 100;
+ table->MemoryACPILevel.VoltageDownH = 0;
+ /* Indicates maximum activity level for this performance level.*/
+ table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+
+ table->MemoryACPILevel.StutterEnable = 0;
+ table->MemoryACPILevel.StrobeEnable = 0;
+ table->MemoryACPILevel.EdcReadEnable = 0;
+ table->MemoryACPILevel.EdcWriteEnable = 0;
+ table->MemoryACPILevel.RttEnable = 0;
+
+ return result;
+}
+
+static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ int result = 0;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_uvd_clock_voltage_dependency_table *uvd_table =
+ hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
+
+ table->UvdLevelCount = (uint8_t)(uvd_table->count);
+
+ for (count = 0; count < table->UvdLevelCount; count++) {
+ table->UvdLevel[count].VclkFrequency =
+ uvd_table->entries[count].vclk;
+ table->UvdLevel[count].DclkFrequency =
+ uvd_table->entries[count].dclk;
+ table->UvdLevel[count].MinVddc =
+ uvd_table->entries[count].v * VOLTAGE_SCALE;
+ table->UvdLevel[count].MinVddcPhases = 1;
+
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->UvdLevel[count].VclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for Vclk clock", return result);
+
+ table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
+
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->UvdLevel[count].DclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for Dclk clock", return result);
+
+ table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc);
+ }
+
+ return result;
+}
+
+static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_vce_clock_voltage_dependency_table *vce_table =
+ hwmgr->dyn_state.vce_clock_voltage_dependency_table;
+
+ table->VceLevelCount = (uint8_t)(vce_table->count);
+ table->VceBootLevel = 0;
+
+ for (count = 0; count < table->VceLevelCount; count++) {
+ table->VceLevel[count].Frequency = vce_table->entries[count].evclk;
+ table->VceLevel[count].MinVoltage =
+ vce_table->entries[count].v * VOLTAGE_SCALE;
+ table->VceLevel[count].MinPhases = 1;
+
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->VceLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for VCE engine clock",
+ return result);
+
+ table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_acp_clock_voltage_dependency_table *acp_table =
+ hwmgr->dyn_state.acp_clock_voltage_dependency_table;
+
+ table->AcpLevelCount = (uint8_t)(acp_table->count);
+ table->AcpBootLevel = 0;
+
+ for (count = 0; count < table->AcpLevelCount; count++) {
+ table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk;
+ table->AcpLevel[count].MinVoltage = acp_table->entries[count].v;
+ table->AcpLevel[count].MinPhases = 1;
+
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->AcpLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for engine clock", return result);
+
+ table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+static int ci_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_samu_clock_voltage_dependency_table *samu_table =
+ hwmgr->dyn_state.samu_clock_voltage_dependency_table;
+
+ table->SamuBootLevel = 0;
+ table->SamuLevelCount = (uint8_t)(samu_table->count);
+
+ for (count = 0; count < table->SamuLevelCount; count++) {
+ table->SamuLevel[count].Frequency = samu_table->entries[count].samclk;
+ table->SamuLevel[count].MinVoltage = samu_table->entries[count].v * VOLTAGE_SCALE;
+ table->SamuLevel[count].MinPhases = 1;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->SamuLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for samu clock", return result);
+
+ table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_US(table->SamuLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+static int ci_populate_memory_timing_parameters(
+ struct pp_hwmgr *hwmgr,
+ uint32_t engine_clock,
+ uint32_t memory_clock,
+ struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs
+ )
+{
+ uint32_t dramTiming;
+ uint32_t dramTiming2;
+ uint32_t burstTime;
+ int result;
+
+ result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
+ engine_clock, memory_clock);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error calling VBIOS to set DRAM_TIMING.", return result);
+
+ dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
+ dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
+ burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
+
+ arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
+ arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
+ arb_regs->McArbBurstTime = (uint8_t)burstTime;
+
+ return 0;
+}
+
+static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ int result = 0;
+ SMU7_Discrete_MCArbDramTimingTable arb_regs;
+ uint32_t i, j;
+
+ memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable));
+
+ for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
+ for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
+ result = ci_populate_memory_timing_parameters
+ (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
+ data->dpm_table.mclk_table.dpm_levels[j].value,
+ &arb_regs.entries[i][j]);
+
+ if (0 != result)
+ break;
+ }
+ }
+
+ if (0 == result) {
+ result = ci_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->arb_table_start,
+ (uint8_t *)&arb_regs,
+ sizeof(SMU7_Discrete_MCArbDramTimingTable),
+ SMC_RAM_END
+ );
+ }
+
+ return result;
+}
+
+static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+
+ table->GraphicsBootLevel = 0;
+ table->MemoryBootLevel = 0;
+
+ /* find boot level from dpm table*/
+ result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+ data->vbios_boot_state.sclk_bootup_value,
+ (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
+
+ if (0 != result) {
+ smu_data->smc_state_table.GraphicsBootLevel = 0;
+ pr_err("VBIOS did not find boot engine clock value \
+ in dependency table. Using Graphics DPM level 0!");
+ result = 0;
+ }
+
+ result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+ data->vbios_boot_state.mclk_bootup_value,
+ (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
+
+ if (0 != result) {
+ smu_data->smc_state_table.MemoryBootLevel = 0;
+ pr_err("VBIOS did not find boot engine clock value \
+ in dependency table. Using Memory DPM level 0!");
+ result = 0;
+ }
+
+ table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
+ table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
+ table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
+
+ return result;
+}
+
+static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_MCRegisters *mc_reg_table)
+{
+ const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend;
+
+ uint32_t i, j;
+
+ for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
+ if (smu_data->mc_reg_table.validflag & 1<<j) {
+ PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,
+ "Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
+ mc_reg_table->address[i].s0 =
+ PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
+ mc_reg_table->address[i].s1 =
+ PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
+ i++;
+ }
+ }
+
+ mc_reg_table->last = (uint8_t)i;
+
+ return 0;
+}
+
+static void ci_convert_mc_registers(
+ const struct ci_mc_reg_entry *entry,
+ SMU7_Discrete_MCRegisterSet *data,
+ uint32_t num_entries, uint32_t valid_flag)
+{
+ uint32_t i, j;
+
+ for (i = 0, j = 0; j < num_entries; j++) {
+ if (valid_flag & 1<<j) {
+ data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
+ i++;
+ }
+ }
+}
+
+static int ci_convert_mc_reg_table_entry_to_smc(
+ struct pp_hwmgr *hwmgr,
+ const uint32_t memory_clock,
+ SMU7_Discrete_MCRegisterSet *mc_reg_table_data
+ )
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ uint32_t i = 0;
+
+ for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
+ if (memory_clock <=
+ smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
+ break;
+ }
+ }
+
+ if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
+ --i;
+
+ ci_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
+ mc_reg_table_data, smu_data->mc_reg_table.last,
+ smu_data->mc_reg_table.validflag);
+
+ return 0;
+}
+
+static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_MCRegisters *mc_regs)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ int res;
+ uint32_t i;
+
+ for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
+ res = ci_convert_mc_reg_table_entry_to_smc(
+ hwmgr,
+ data->dpm_table.mclk_table.dpm_levels[i].value,
+ &mc_regs->data[i]
+ );
+
+ if (0 != res)
+ result = res;
+ }
+
+ return result;
+}
+
+static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t address;
+ int32_t result;
+
+ if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
+ return 0;
+
+
+ memset(&smu_data->mc_regs, 0, sizeof(SMU7_Discrete_MCRegisters));
+
+ result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
+
+ if (result != 0)
+ return result;
+
+ address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);
+
+ return ci_copy_bytes_to_smc(hwmgr, address,
+ (uint8_t *)&smu_data->mc_regs.data[0],
+ sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
+ SMC_RAM_END);
+}
+
+static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+
+ memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
+ result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize MCRegTable for the MC register addresses!", return result;);
+
+ result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize MCRegTable for driver state!", return result;);
+
+ return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
+ (uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);
+}
+
+static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ uint8_t count, level;
+
+ count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
+
+ for (level = 0; level < count; level++) {
+ if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
+ >= data->vbios_boot_state.sclk_bootup_value) {
+ smu_data->smc_state_table.GraphicsBootLevel = level;
+ break;
+ }
+ }
+
+ count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
+
+ for (level = 0; level < count; level++) {
+ if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
+ >= data->vbios_boot_state.mclk_bootup_value) {
+ smu_data->smc_state_table.MemoryBootLevel = level;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
+ SMU7_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
+ table->SVI2Enable = 1;
+ else
+ table->SVI2Enable = 0;
+ return 0;
+}
+
+static int ci_start_smc(struct pp_hwmgr *hwmgr)
+{
+ /* set smc instruct start point at 0x0 */
+ ci_program_jump_on_start(hwmgr);
+
+ /* enable smc clock */
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
+
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
+
+ PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
+ INTERRUPTS_ENABLED, 1);
+
+ return 0;
+}
+
+static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ struct pp_atomctrl_gpio_pin_assignment gpio_pin;
+ u32 i;
+
+ ci_initialize_power_tune_defaults(hwmgr);
+ memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
+ ci_populate_smc_voltage_tables(hwmgr, table);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
+
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StepVddc))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
+
+ if (data->is_memory_gddr5)
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
+
+ if (data->ulv_supported) {
+ result = ci_populate_ulv_state(hwmgr, &(table->Ulv));
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ULV state!", return result);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_ULV_PARAMETER, 0x40035);
+ }
+
+ result = ci_populate_all_graphic_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Graphics Level!", return result);
+
+ result = ci_populate_all_memory_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Memory Level!", return result);
+
+ result = ci_populate_smc_link_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Link Level!", return result);
+
+ result = ci_populate_smc_acpi_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ACPI Level!", return result);
+
+ result = ci_populate_smc_vce_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize VCE Level!", return result);
+
+ result = ci_populate_smc_acp_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ACP Level!", return result);
+
+ result = ci_populate_smc_samu_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize SAMU Level!", return result);
+
+ /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
+ /* need to populate the ARB settings for the initial state. */
+ result = ci_program_memory_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to Write ARB settings for the initial state.", return result);
+
+ result = ci_populate_smc_uvd_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize UVD Level!", return result);
+
+ table->UvdBootLevel = 0;
+ table->VceBootLevel = 0;
+ table->AcpBootLevel = 0;
+ table->SamuBootLevel = 0;
+
+ table->GraphicsBootLevel = 0;
+ table->MemoryBootLevel = 0;
+
+ result = ci_populate_smc_boot_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Boot Level!", return result);
+
+ result = ci_populate_smc_initial_state(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
+
+ result = ci_populate_bapm_parameters_in_dpm_table(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
+
+ table->UVDInterval = 1;
+ table->VCEInterval = 1;
+ table->ACPInterval = 1;
+ table->SAMUInterval = 1;
+ table->GraphicsVoltageChangeEnable = 1;
+ table->GraphicsThermThrottleEnable = 1;
+ table->GraphicsInterval = 1;
+ table->VoltageInterval = 1;
+ table->ThermalInterval = 1;
+
+ table->TemperatureLimitHigh =
+ (data->thermal_temp_setting.temperature_high *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ table->TemperatureLimitLow =
+ (data->thermal_temp_setting.temperature_low *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ table->MemoryVoltageChangeEnable = 1;
+ table->MemoryInterval = 1;
+ table->VoltageResponseTime = 0;
+ table->VddcVddciDelta = 4000;
+ table->PhaseResponseTime = 0;
+ table->MemoryThermThrottleEnable = 1;
+
+ PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
+ "There must be 1 or more PCIE levels defined in PPTable.",
+ return -EINVAL);
+
+ table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
+ table->PCIeGenInterval = 1;
+
+ ci_populate_smc_svi2_config(hwmgr, table);
+
+ for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++)
+ CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]);
+
+ table->ThermGpio = 17;
+ table->SclkStepSize = 0x4000;
+ if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
+ table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+ } else {
+ table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+ }
+
+ table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
+ table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta);
+ CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
+ CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
+
+ table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
+ table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
+ table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
+
+ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
+ result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
+ offsetof(SMU7_Discrete_DpmTable, SystemFlags),
+ (uint8_t *)&(table->SystemFlags),
+ sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController),
+ SMC_RAM_END);
+
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to upload dpm data to SMC memory!", return result;);
+
+ result = ci_populate_initial_mc_reg_table(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Failed to populate initialize MC Reg table!", return result);
+
+ result = ci_populate_pm_fuses(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate PM fuses to SMC memory!", return result);
+
+ ci_start_smc(hwmgr);
+
+ return 0;
+}
+
+static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+{
+ struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
+ uint32_t duty100;
+ uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
+ uint16_t fdo_min, slope1, slope2;
+ uint32_t reference_clock;
+ int res;
+ uint64_t tmp64;
+
+ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
+ return 0;
+
+ if (hwmgr->thermal_controller.fanInfo.bNoFan) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ if (0 == ci_data->fan_table_start) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
+
+ if (0 == duty100) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
+ do_div(tmp64, 10000);
+ fdo_min = (uint16_t)tmp64;
+
+ t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
+ t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
+
+ pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
+ pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
+
+ slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
+ slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
+
+ fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
+ fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
+ fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
+
+ fan_table.Slope1 = cpu_to_be16(slope1);
+ fan_table.Slope2 = cpu_to_be16(slope2);
+
+ fan_table.FdoMin = cpu_to_be16(fdo_min);
+
+ fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
+
+ fan_table.HystUp = cpu_to_be16(1);
+
+ fan_table.HystSlope = cpu_to_be16(1);
+
+ fan_table.TempRespLim = cpu_to_be16(5);
+
+ reference_clock = smu7_get_xclk(hwmgr);
+
+ fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
+
+ fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
+
+ fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
+
+ res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
+
+ return 0;
+}
+
+static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (data->need_update_smu7_dpm_table &
+ (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
+ return ci_program_memory_timing_parameters(hwmgr);
+
+ return 0;
+}
+
+static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+
+ int result = 0;
+ uint32_t low_sclk_interrupt_threshold = 0;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkThrottleLowNotification)
+ && (hwmgr->gfx_arbiter.sclk_threshold !=
+ data->low_sclk_interrupt_threshold)) {
+ data->low_sclk_interrupt_threshold =
+ hwmgr->gfx_arbiter.sclk_threshold;
+ low_sclk_interrupt_threshold =
+ data->low_sclk_interrupt_threshold;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
+
+ result = ci_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->dpm_table_start +
+ offsetof(SMU7_Discrete_DpmTable,
+ LowSclkInterruptT),
+ (uint8_t *)&low_sclk_interrupt_threshold,
+ sizeof(uint32_t),
+ SMC_RAM_END);
+ }
+
+ result = ci_update_and_upload_mc_reg_table(hwmgr);
+
+ PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
+
+ result = ci_program_mem_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE((result == 0),
+ "Failed to program memory timing parameters!",
+ );
+
+ return result;
+}
+
+static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
+{
+ switch (type) {
+ case SMU_SoftRegisters:
+ switch (member) {
+ case HandshakeDisables:
+ return offsetof(SMU7_SoftRegisters, HandshakeDisables);
+ case VoltageChangeTimeout:
+ return offsetof(SMU7_SoftRegisters, VoltageChangeTimeout);
+ case AverageGraphicsActivity:
+ return offsetof(SMU7_SoftRegisters, AverageGraphicsA);
+ case PreVBlankGap:
+ return offsetof(SMU7_SoftRegisters, PreVBlankGap);
+ case VBlankTimeout:
+ return offsetof(SMU7_SoftRegisters, VBlankTimeout);
+ case DRAM_LOG_ADDR_H:
+ return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_H);
+ case DRAM_LOG_ADDR_L:
+ return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_L);
+ case DRAM_LOG_PHY_ADDR_H:
+ return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+ case DRAM_LOG_PHY_ADDR_L:
+ return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+ case DRAM_LOG_BUFF_SIZE:
+ return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);
+ }
+ case SMU_Discrete_DpmTable:
+ switch (member) {
+ case LowSclkInterruptThreshold:
+ return offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT);
+ }
+ }
+ pr_debug("can't get the offset of type %x member %x\n", type, member);
+ return 0;
+}
+
+static uint32_t ci_get_mac_definition(uint32_t value)
+{
+ switch (value) {
+ case SMU_MAX_LEVELS_GRAPHICS:
+ return SMU7_MAX_LEVELS_GRAPHICS;
+ case SMU_MAX_LEVELS_MEMORY:
+ return SMU7_MAX_LEVELS_MEMORY;
+ case SMU_MAX_LEVELS_LINK:
+ return SMU7_MAX_LEVELS_LINK;
+ case SMU_MAX_ENTRIES_SMIO:
+ return SMU7_MAX_ENTRIES_SMIO;
+ case SMU_MAX_LEVELS_VDDC:
+ return SMU7_MAX_LEVELS_VDDC;
+ case SMU_MAX_LEVELS_VDDCI:
+ return SMU7_MAX_LEVELS_VDDCI;
+ case SMU_MAX_LEVELS_MVDD:
+ return SMU7_MAX_LEVELS_MVDD;
+ }
+
+ pr_debug("can't get the mac of %x\n", value);
+ return 0;
+}
+
+static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
+{
+ uint32_t byte_count, start_addr;
+ uint8_t *src;
+ uint32_t data;
+
+ struct cgs_firmware_info info = {0};
+
+ cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+
+ hwmgr->is_kicker = info.is_kicker;
+ byte_count = info.image_size;
+ src = (uint8_t *)info.kptr;
+ start_addr = info.ucode_start_address;
+
+ if (byte_count > SMC_RAM_END) {
+ pr_err("SMC address is beyond the SMC RAM area.\n");
+ return -EINVAL;
+ }
+
+ cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
+
+ for (; byte_count >= 4; byte_count -= 4) {
+ data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
+ src += 4;
+ }
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
+
+ if (0 != byte_count) {
+ pr_err("SMC size must be divisible by 4\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
+{
+ if (ci_is_smc_ram_running(hwmgr)) {
+ pr_info("smc is running, no need to load smc firmware\n");
+ return 0;
+ }
+ PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
+ boot_seq_done, 1);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL,
+ pre_fetcher_en, 1);
+
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
+ return ci_load_smc_ucode(hwmgr);
+}
+
+static int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+
+ uint32_t tmp = 0;
+ int result;
+ bool error = false;
+
+ if (ci_upload_firmware(hwmgr))
+ return -EINVAL;
+
+ result = ci_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU7_Firmware_Header, DpmTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result)
+ ci_data->dpm_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = ci_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU7_Firmware_Header, SoftRegisters),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ data->soft_regs_start = tmp;
+ ci_data->soft_regs_start = tmp;
+ }
+
+ error |= (0 != result);
+
+ result = ci_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU7_Firmware_Header, mcRegisterTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result)
+ ci_data->mc_reg_table_start = tmp;
+
+ result = ci_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU7_Firmware_Header, FanTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result)
+ ci_data->fan_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = ci_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result)
+ ci_data->arb_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = ci_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU7_Firmware_Header, Version),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result)
+ hwmgr->microcode_version_info.SMC = tmp;
+
+ error |= (0 != result);
+
+ return error ? 1 : 0;
+}
+
+static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr)
+{
+ return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
+}
+
+static bool ci_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
+{
+ bool result = true;
+
+ switch (in_reg) {
+ case mmMC_SEQ_RAS_TIMING:
+ *out_reg = mmMC_SEQ_RAS_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_DLL_STBY:
+ *out_reg = mmMC_SEQ_DLL_STBY_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CMD0:
+ *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CMD1:
+ *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CTRL:
+ *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
+ break;
+
+ case mmMC_SEQ_CAS_TIMING:
+ *out_reg = mmMC_SEQ_CAS_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_MISC_TIMING:
+ *out_reg = mmMC_SEQ_MISC_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_MISC_TIMING2:
+ *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
+ break;
+
+ case mmMC_SEQ_PMG_DVS_CMD:
+ *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
+ break;
+
+ case mmMC_SEQ_PMG_DVS_CTL:
+ *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
+ break;
+
+ case mmMC_SEQ_RD_CTL_D0:
+ *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
+ break;
+
+ case mmMC_SEQ_RD_CTL_D1:
+ *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_D0:
+ *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_D1:
+ *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
+ break;
+
+ case mmMC_PMG_CMD_EMRS:
+ *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS1:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
+ break;
+
+ case mmMC_SEQ_PMG_TIMING:
+ *out_reg = mmMC_SEQ_PMG_TIMING_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS2:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_2:
+ *out_reg = mmMC_SEQ_WR_CTL_2_LP;
+ break;
+
+ default:
+ result = false;
+ break;
+ }
+
+ return result;
+}
+
+static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
+{
+ uint32_t i;
+ uint16_t address;
+
+ for (i = 0; i < table->last; i++) {
+ table->mc_reg_address[i].s0 =
+ ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
+ ? address : table->mc_reg_address[i].s1;
+ }
+ return 0;
+}
+
+static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
+ struct ci_mc_reg_table *ni_table)
+{
+ uint8_t i, j;
+
+ PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ for (i = 0; i < table->last; i++)
+ ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
+
+ ni_table->last = table->last;
+
+ for (i = 0; i < table->num_entries; i++) {
+ ni_table->mc_reg_table_entry[i].mclk_max =
+ table->mc_reg_table_entry[i].mclk_max;
+ for (j = 0; j < table->last; j++) {
+ ni_table->mc_reg_table_entry[i].mc_data[j] =
+ table->mc_reg_table_entry[i].mc_data[j];
+ }
+ }
+
+ ni_table->num_entries = table->num_entries;
+
+ return 0;
+}
+
+static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ struct ci_mc_reg_table *table)
+{
+ uint8_t i, j, k;
+ uint32_t temp_reg;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ for (i = 0, j = table->last; i < table->last; i++) {
+ PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ switch (table->mc_reg_address[i].s1) {
+
+ case mmMC_SEQ_MISC1:
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ ((temp_reg & 0xffff0000)) |
+ ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (temp_reg & 0xffff0000) |
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+
+ if (!data->is_memory_gddr5)
+ table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
+ table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
+ table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ }
+
+ break;
+
+ case mmMC_SEQ_RESERVE_M:
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (temp_reg & 0xffff0000) |
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ break;
+
+ default:
+ break;
+ }
+
+ }
+
+ table->last = j;
+
+ return 0;
+}
+
+static int ci_set_valid_flag(struct ci_mc_reg_table *table)
+{
+ uint8_t i, j;
+
+ for (i = 0; i < table->last; i++) {
+ for (j = 1; j < table->num_entries; j++) {
+ if (table->mc_reg_table_entry[j-1].mc_data[i] !=
+ table->mc_reg_table_entry[j].mc_data[i]) {
+ table->validflag |= (1 << i);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+ pp_atomctrl_mc_reg_table *table;
+ struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table;
+ uint8_t module_index = ci_get_memory_modile_index(hwmgr);
+
+ table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
+
+ if (NULL == table)
+ return -ENOMEM;
+
+ /* Program additional LP registers that are no longer programmed by VBIOS */
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
+
+ memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
+
+ result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
+
+ if (0 == result)
+ result = ci_copy_vbios_smc_reg_table(table, ni_table);
+
+ if (0 == result) {
+ ci_set_s0_mc_reg_index(ni_table);
+ result = ci_set_mc_special_registers(hwmgr, ni_table);
+ }
+
+ if (0 == result)
+ ci_set_valid_flag(ni_table);
+
+ kfree(table);
+
+ return result;
+}
+
+static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
+{
+ return ci_is_smc_ram_running(hwmgr);
+}
+
+static int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
+ struct amd_pp_profile *request)
+{
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)
+ (hwmgr->smu_backend);
+ struct SMU7_Discrete_GraphicsLevel *levels =
+ smu_data->smc_state_table.GraphicsLevel;
+ uint32_t array = smu_data->dpm_table_start +
+ offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
+ uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
+ SMU7_MAX_LEVELS_GRAPHICS;
+ uint32_t i;
+
+ for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+ levels[i].ActivityLevel =
+ cpu_to_be16(request->activity_threshold);
+ levels[i].EnabledForActivity = 1;
+ levels[i].UpH = request->up_hyst;
+ levels[i].DownH = request->down_hyst;
+ }
+
+ return ci_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ array_size, SMC_RAM_END);
+}
+
+
+static int ci_smu_init(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct ci_smumgr *ci_priv = NULL;
+
+ ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
+
+ if (ci_priv == NULL)
+ return -ENOMEM;
+
+ for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
+ ci_priv->activity_target[i] = 30;
+
+ hwmgr->smu_backend = ci_priv;
+
+ return 0;
+}
+
+static int ci_smu_fini(struct pp_hwmgr *hwmgr)
+{
+ kfree(hwmgr->smu_backend);
+ hwmgr->smu_backend = NULL;
+ cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
+ return 0;
+}
+
+static int ci_start_smu(struct pp_hwmgr *hwmgr)
+{
+ return 0;
+}
+
+const struct pp_smumgr_func ci_smu_funcs = {
+ .smu_init = ci_smu_init,
+ .smu_fini = ci_smu_fini,
+ .start_smu = ci_start_smu,
+ .check_fw_load_finish = NULL,
+ .request_smu_load_fw = NULL,
+ .request_smu_load_specific_fw = NULL,
+ .send_msg_to_smc = ci_send_msg_to_smc,
+ .send_msg_to_smc_with_parameter = ci_send_msg_to_smc_with_parameter,
+ .download_pptable_settings = NULL,
+ .upload_pptable_settings = NULL,
+ .get_offsetof = ci_get_offsetof,
+ .process_firmware_header = ci_process_firmware_header,
+ .init_smc_table = ci_init_smc_table,
+ .update_sclk_threshold = ci_update_sclk_threshold,
+ .thermal_setup_fan_table = ci_thermal_setup_fan_table,
+ .populate_all_graphic_levels = ci_populate_all_graphic_levels,
+ .populate_all_memory_levels = ci_populate_all_memory_levels,
+ .get_mac_definition = ci_get_mac_definition,
+ .initialize_mc_reg_table = ci_initialize_mc_reg_table,
+ .is_dpm_running = ci_is_dpm_running,
+ .populate_requested_graphic_levels = ci_populate_requested_graphic_levels,
+};
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h
new file mode 100644
index 0000000..8189cfa
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _CI_SMUMANAGER_H_
+#define _CI_SMUMANAGER_H_
+
+#define SMU__NUM_SCLK_DPM_STATE 8
+#define SMU__NUM_MCLK_DPM_LEVELS 6
+#define SMU__NUM_LCLK_DPM_LEVELS 8
+#define SMU__NUM_PCIE_DPM_LEVELS 8
+
+#include "smu7_discrete.h"
+#include <pp_endian.h>
+#include "ppatomctrl.h"
+
+struct ci_pt_defaults {
+ u8 svi_load_line_en;
+ u8 svi_load_line_vddc;
+ u8 tdc_vddc_throttle_release_limit_perc;
+ u8 tdc_mawt;
+ u8 tdc_waterfall_ctl;
+ u8 dte_ambient_temp_base;
+ u32 display_cac;
+ u32 bapm_temp_gradient;
+ u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
+ u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
+};
+
+struct ci_mc_reg_entry {
+ uint32_t mclk_max;
+ uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
+};
+
+struct ci_mc_reg_table {
+ uint8_t last;
+ uint8_t num_entries;
+ uint16_t validflag;
+ struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
+ SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
+};
+
+struct ci_smumgr {
+ uint32_t soft_regs_start;
+ uint32_t dpm_table_start;
+ uint32_t mc_reg_table_start;
+ uint32_t fan_table_start;
+ uint32_t arb_table_start;
+ uint32_t ulv_setting_starts;
+ struct SMU7_Discrete_DpmTable smc_state_table;
+ struct SMU7_Discrete_PmFuses power_tune_table;
+ const struct ci_pt_defaults *power_tune_defaults;
+ SMU7_Discrete_MCRegisters mc_regs;
+ struct ci_mc_reg_table mc_reg_table;
+ uint32_t activity_target[SMU7_MAX_LEVELS_GRAPHICS];
+
+};
+
+#endif
+
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 652aaa4..78ab055 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -52,53 +52,52 @@ static const enum cz_scratch_entry firmware_list[] = {
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
};
-static int cz_smum_get_argument(struct pp_smumgr *smumgr)
+static int cz_smum_get_argument(struct pp_hwmgr *hwmgr)
{
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- return cgs_read_register(smumgr->device,
+ return cgs_read_register(hwmgr->device,
mmSMU_MP1_SRBM2P_ARG_0);
}
-static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr,
- uint16_t msg)
+static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
{
int result = 0;
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
+ result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
if (result != 0) {
pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
return result;
}
- cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
- cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
+ cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
+ cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
return 0;
}
/* Send a message to the SMC, and wait for its response.*/
-static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
int result = 0;
- result = cz_send_msg_to_smc_async(smumgr, msg);
+ result = cz_send_msg_to_smc_async(hwmgr, msg);
if (result != 0)
return result;
- return SMUM_WAIT_FIELD_UNEQUAL(smumgr,
+ return PHM_WAIT_FIELD_UNEQUAL(hwmgr,
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
}
-static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
+static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr,
uint32_t smc_address, uint32_t limit)
{
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
if (0 != (3 & smc_address)) {
@@ -111,39 +110,39 @@ static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
return -EINVAL;
}
- cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX_0,
+ cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,
SMN_MP1_SRAM_START_ADDR + smc_address);
return 0;
}
-static int cz_write_smc_sram_dword(struct pp_smumgr *smumgr,
+static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
uint32_t smc_address, uint32_t value, uint32_t limit)
{
int result;
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- result = cz_set_smc_sram_address(smumgr, smc_address, limit);
+ result = cz_set_smc_sram_address(hwmgr, smc_address, limit);
if (!result)
- cgs_write_register(smumgr->device, mmMP0PUB_IND_DATA_0, value);
+ cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
return result;
}
-static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
+static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter)
{
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
+ cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
- return cz_send_msg_to_smc(smumgr, msg);
+ return cz_send_msg_to_smc(hwmgr, msg);
}
-static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
+static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr,
uint32_t firmware)
{
int i;
@@ -151,19 +150,19 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
SMU8_FIRMWARE_HEADER_LOCATION +
offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX, index);
+ cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
- for (i = 0; i < smumgr->usec_timeout; i++) {
+ for (i = 0; i < hwmgr->usec_timeout; i++) {
if (firmware ==
- (cgs_read_register(smumgr->device, mmMP0PUB_IND_DATA) & firmware))
+ (cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware))
break;
udelay(1);
}
- if (i >= smumgr->usec_timeout) {
+ if (i >= hwmgr->usec_timeout) {
pr_err("SMU check loaded firmware failed.\n");
return -EINVAL;
}
@@ -171,7 +170,7 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
return 0;
}
-static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
+static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
{
uint32_t reg_data;
uint32_t tmp;
@@ -179,44 +178,44 @@ static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
struct cgs_firmware_info info = {0};
struct cz_smumgr *cz_smu;
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- cz_smu = (struct cz_smumgr *)smumgr->backend;
- ret = cgs_get_firmware_info(smumgr->device,
+ cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ ret = cgs_get_firmware_info(hwmgr->device,
CGS_UCODE_ID_CP_MEC, &info);
if (ret)
return -EINVAL;
/* Disable MEC parsing/prefetching */
- tmp = cgs_read_register(smumgr->device,
+ tmp = cgs_read_register(hwmgr->device,
mmCP_MEC_CNTL);
- tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
- tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
- cgs_write_register(smumgr->device, mmCP_MEC_CNTL, tmp);
+ tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
+ tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
+ cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
- tmp = cgs_read_register(smumgr->device,
+ tmp = cgs_read_register(hwmgr->device,
mmCP_CPC_IC_BASE_CNTL);
- tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
- tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
- tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
- tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
- cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
+ tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
+ tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
+ tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
+ tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
+ cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
reg_data = smu_lower_32_bits(info.mc_addr) &
- SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
- cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
+ PHM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
+ cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
reg_data = smu_upper_32_bits(info.mc_addr) &
- SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
- cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
+ PHM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
+ cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
return 0;
}
-static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
+static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
enum cz_scratch_entry firmware_enum)
{
uint8_t ret = 0;
@@ -226,7 +225,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
ret = UCODE_ID_SDMA0;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
- if (smumgr->chip_id == CHIP_STONEY)
+ if (hwmgr->chip_id == CHIP_STONEY)
ret = UCODE_ID_SDMA0;
else
ret = UCODE_ID_SDMA1;
@@ -244,7 +243,7 @@ static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
ret = UCODE_ID_CP_MEC_JT1;
break;
case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
- if (smumgr->chip_id == CHIP_STONEY)
+ if (hwmgr->chip_id == CHIP_STONEY)
ret = UCODE_ID_CP_MEC_JT1;
else
ret = UCODE_ID_CP_MEC_JT2;
@@ -326,17 +325,17 @@ static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
}
static int cz_smu_populate_single_scratch_task(
- struct pp_smumgr *smumgr,
+ struct pp_hwmgr *hwmgr,
enum cz_scratch_entry fw_enum,
uint8_t type, bool is_last)
{
uint8_t i;
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
task->type = type;
- task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
+ task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
for (i = 0; i < cz_smu->scratch_buffer_length; i++)
@@ -363,17 +362,17 @@ static int cz_smu_populate_single_scratch_task(
}
static int cz_smu_populate_single_ucode_load_task(
- struct pp_smumgr *smumgr,
+ struct pp_hwmgr *hwmgr,
enum cz_scratch_entry fw_enum,
bool is_last)
{
uint8_t i;
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
task->type = TASK_TYPE_UCODE_LOAD;
- task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
+ task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
for (i = 0; i < cz_smu->driver_buffer_length; i++)
@@ -392,22 +391,22 @@ static int cz_smu_populate_single_ucode_load_task(
return 0;
}
-static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_smumgr *smumgr)
+static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
TASK_TYPE_UCODE_SAVE, true);
return 0;
}
-static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr)
+static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
{
int i;
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
@@ -416,17 +415,17 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr)
return 0;
}
-static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr)
+static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
TASK_TYPE_UCODE_SAVE, false);
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
TASK_TYPE_UCODE_SAVE, true);
@@ -434,121 +433,120 @@ static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr)
}
-static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr)
+static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
- if (smumgr->chip_id == CHIP_STONEY)
- cz_smu_populate_single_ucode_load_task(smumgr,
+ if (hwmgr->chip_id == CHIP_STONEY)
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
else
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
/* populate scratch */
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
TASK_TYPE_UCODE_LOAD, false);
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
TASK_TYPE_UCODE_LOAD, false);
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
TASK_TYPE_UCODE_LOAD, true);
return 0;
}
-static int cz_smu_construct_toc_for_power_profiling(
- struct pp_smumgr *smumgr)
+static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
TASK_TYPE_INITIALIZE, true);
return 0;
}
-static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
+static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
- if (smumgr->chip_id != CHIP_STONEY)
- cz_smu_populate_single_ucode_load_task(smumgr,
+ if (hwmgr->chip_id != CHIP_STONEY)
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
- if (smumgr->chip_id != CHIP_STONEY)
- cz_smu_populate_single_ucode_load_task(smumgr,
+ if (hwmgr->chip_id != CHIP_STONEY)
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
- cz_smu_populate_single_ucode_load_task(smumgr,
+ cz_smu_populate_single_ucode_load_task(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
return 0;
}
-static int cz_smu_construct_toc_for_clock_table(struct pp_smumgr *smumgr)
+static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
- cz_smu_populate_single_scratch_task(smumgr,
+ cz_smu_populate_single_scratch_task(hwmgr,
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
TASK_TYPE_INITIALIZE, true);
return 0;
}
-static int cz_smu_construct_toc(struct pp_smumgr *smumgr)
+static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
cz_smu->toc_entry_used_count = 0;
- cz_smu_initialize_toc_empty_job_list(smumgr);
- cz_smu_construct_toc_for_rlc_aram_save(smumgr);
- cz_smu_construct_toc_for_vddgfx_enter(smumgr);
- cz_smu_construct_toc_for_vddgfx_exit(smumgr);
- cz_smu_construct_toc_for_power_profiling(smumgr);
- cz_smu_construct_toc_for_bootup(smumgr);
- cz_smu_construct_toc_for_clock_table(smumgr);
+ cz_smu_initialize_toc_empty_job_list(hwmgr);
+ cz_smu_construct_toc_for_rlc_aram_save(hwmgr);
+ cz_smu_construct_toc_for_vddgfx_enter(hwmgr);
+ cz_smu_construct_toc_for_vddgfx_exit(hwmgr);
+ cz_smu_construct_toc_for_power_profiling(hwmgr);
+ cz_smu_construct_toc_for_bootup(hwmgr);
+ cz_smu_construct_toc_for_clock_table(hwmgr);
return 0;
}
-static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
+static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
uint32_t firmware_type;
uint32_t i;
int ret;
@@ -559,12 +557,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
- firmware_type = cz_translate_firmware_enum_to_arg(smumgr,
+ firmware_type = cz_translate_firmware_enum_to_arg(hwmgr,
firmware_list[i]);
ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
- ret = cgs_get_firmware_info(smumgr->device,
+ ret = cgs_get_firmware_info(hwmgr->device,
ucode_id, &info);
if (ret == 0) {
@@ -585,12 +583,12 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
}
static int cz_smu_populate_single_scratch_entry(
- struct pp_smumgr *smumgr,
+ struct pp_hwmgr *hwmgr,
enum cz_scratch_entry scratch_type,
uint32_t ulsize_byte,
struct cz_buffer_entry *entry)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
long long mc_addr =
((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
| cz_smu->smu_buffer.mc_addr_low;
@@ -611,9 +609,9 @@ static int cz_smu_populate_single_scratch_entry(
return 0;
}
-static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table)
+static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
@@ -624,25 +622,25 @@ static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table)
*table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
- cz_send_msg_to_smc_with_parameter(smumgr,
+ cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi,
cz_smu->scratch_buffer[i].mc_addr_high);
- cz_send_msg_to_smc_with_parameter(smumgr,
+ cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo,
cz_smu->scratch_buffer[i].mc_addr_low);
- cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
+ cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table);
- cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToDram);
+ cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
return 0;
}
-static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
+static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
@@ -651,63 +649,63 @@ static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
break;
}
- cz_send_msg_to_smc_with_parameter(smumgr,
+ cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrHi,
cz_smu->scratch_buffer[i].mc_addr_high);
- cz_send_msg_to_smc_with_parameter(smumgr,
+ cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetClkTableAddrLo,
cz_smu->scratch_buffer[i].mc_addr_low);
- cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
+ cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_clock_table);
- cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToSmu);
+ cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
return 0;
}
-static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
+static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend);
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smu_backend);
uint32_t smc_address;
- if (!smumgr->reload_fw) {
+ if (!hwmgr->reload_fw) {
pr_info("skip reloading...\n");
return 0;
}
- cz_smu_populate_firmware_entries(smumgr);
+ cz_smu_populate_firmware_entries(hwmgr);
- cz_smu_construct_toc(smumgr);
+ cz_smu_construct_toc(hwmgr);
smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
- cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4);
+ cz_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
- cz_send_msg_to_smc_with_parameter(smumgr,
+ cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrHi,
cz_smu->toc_buffer.mc_addr_high);
- cz_send_msg_to_smc_with_parameter(smumgr,
+ cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DriverDramAddrLo,
cz_smu->toc_buffer.mc_addr_low);
- cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs);
+ cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
- cz_send_msg_to_smc_with_parameter(smumgr,
+ cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_aram);
- cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
+ cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_power_profiling_index);
- return cz_send_msg_to_smc_with_parameter(smumgr,
+ return cz_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_ExecuteJob,
cz_smu->toc_entry_initialize_index);
}
-static int cz_start_smu(struct pp_smumgr *smumgr)
+static int cz_start_smu(struct pp_hwmgr *hwmgr)
{
int ret = 0;
uint32_t fw_to_check = 0;
@@ -721,23 +719,23 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
UCODE_ID_CP_MEC_JT1_MASK |
UCODE_ID_CP_MEC_JT2_MASK;
- if (smumgr->chip_id == CHIP_STONEY)
+ if (hwmgr->chip_id == CHIP_STONEY)
fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
- ret = cz_request_smu_load_fw(smumgr);
+ ret = cz_request_smu_load_fw(hwmgr);
if (ret)
pr_err("SMU firmware load failed\n");
- cz_check_fw_load_finish(smumgr, fw_to_check);
+ cz_check_fw_load_finish(hwmgr, fw_to_check);
- ret = cz_load_mec_firmware(smumgr);
+ ret = cz_load_mec_firmware(hwmgr);
if (ret)
pr_err("Mec Firmware load failed\n");
return ret;
}
-static int cz_smu_init(struct pp_smumgr *smumgr)
+static int cz_smu_init(struct pp_hwmgr *hwmgr)
{
uint64_t mc_addr = 0;
int ret = 0;
@@ -747,7 +745,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
if (cz_smu == NULL)
return -ENOMEM;
- smumgr->backend = cz_smu;
+ hwmgr->smu_backend = cz_smu;
cz_smu->toc_buffer.data_size = 4096;
cz_smu->smu_buffer.data_size =
@@ -757,7 +755,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
- ret = smu_allocate_memory(smumgr->device,
+ ret = smu_allocate_memory(hwmgr->device,
cz_smu->toc_buffer.data_size,
CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE,
@@ -770,7 +768,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
- ret = smu_allocate_memory(smumgr->device,
+ ret = smu_allocate_memory(hwmgr->device,
cz_smu->smu_buffer.data_size,
CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE,
@@ -783,7 +781,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
- if (0 != cz_smu_populate_single_scratch_entry(smumgr,
+ if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -791,14 +789,14 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return -1;
}
- if (0 != cz_smu_populate_single_scratch_entry(smumgr,
+ if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
pr_err("Error when Populate Firmware Entry.\n");
return -1;
}
- if (0 != cz_smu_populate_single_scratch_entry(smumgr,
+ if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -806,7 +804,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return -1;
}
- if (0 != cz_smu_populate_single_scratch_entry(smumgr,
+ if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
sizeof(struct SMU8_MultimediaPowerLogData),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -814,7 +812,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return -1;
}
- if (0 != cz_smu_populate_single_scratch_entry(smumgr,
+ if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
sizeof(struct SMU8_Fusion_ClkTable),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
@@ -825,18 +823,18 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
return 0;
}
-static int cz_smu_fini(struct pp_smumgr *smumgr)
+static int cz_smu_fini(struct pp_hwmgr *hwmgr)
{
struct cz_smumgr *cz_smu;
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- cz_smu = (struct cz_smumgr *)smumgr->backend;
+ cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
if (cz_smu) {
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
cz_smu->toc_buffer.handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
cz_smu->smu_buffer.handle);
kfree(cz_smu);
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
deleted file mode 100644
index 8712f09..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ /dev/null
@@ -1,2498 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "pp_debug.h"
-#include "fiji_smc.h"
-#include "smu7_dyn_defaults.h"
-
-#include "smu7_hwmgr.h"
-#include "hardwaremanager.h"
-#include "ppatomctrl.h"
-#include "cgs_common.h"
-#include "atombios.h"
-#include "fiji_smumgr.h"
-#include "pppcielanes.h"
-#include "smu7_ppsmc.h"
-#include "smu73.h"
-#include "smu/smu_7_1_3_d.h"
-#include "smu/smu_7_1_3_sh_mask.h"
-#include "gmc/gmc_8_1_d.h"
-#include "gmc/gmc_8_1_sh_mask.h"
-#include "bif/bif_5_0_d.h"
-#include "bif/bif_5_0_sh_mask.h"
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-#include "smu7_smumgr.h"
-
-#define VOLTAGE_SCALE 4
-#define POWERTUNE_DEFAULT_SET_MAX 1
-#define VOLTAGE_VID_OFFSET_SCALE1 625
-#define VOLTAGE_VID_OFFSET_SCALE2 100
-#define VDDC_VDDCI_DELTA 300
-#define MC_CG_ARB_FREQ_F1 0x0b
-
-/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
- * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
- */
-static const uint16_t fiji_clock_stretcher_lookup_table[2][4] = {
- {600, 1050, 3, 0}, {600, 1050, 6, 1} };
-
-/* [FF, SS] type, [] 4 voltage ranges, and
- * [Floor Freq, Boundary Freq, VID min , VID max]
- */
-static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = {
- { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
- { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
-
-/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
- * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
- */
-static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = {
- {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
-
-static const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
- /*sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
- {1, 0xF, 0xFD,
- /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
- 0x19, 5, 45}
-};
-
-/* PPGen has the gain setting generated in x * 100 unit
- * This function is to convert the unit to x * 4096(0x1000) unit.
- * This is the unit expected by SMC firmware
- */
-static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
- struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
- uint32_t clock, uint32_t *voltage, uint32_t *mvdd)
-{
- uint32_t i;
- uint16_t vddci;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- *voltage = *mvdd = 0;
-
-
- /* clock - voltage dependency table is empty table */
- if (dep_table->count == 0)
- return -EINVAL;
-
- for (i = 0; i < dep_table->count; i++) {
- /* find first sclk bigger than request */
- if (dep_table->entries[i].clk >= clock) {
- *voltage |= (dep_table->entries[i].vddc *
- VOLTAGE_SCALE) << VDDC_SHIFT;
- if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
- *voltage |= (data->vbios_boot_state.vddci_bootup_value *
- VOLTAGE_SCALE) << VDDCI_SHIFT;
- else if (dep_table->entries[i].vddci)
- *voltage |= (dep_table->entries[i].vddci *
- VOLTAGE_SCALE) << VDDCI_SHIFT;
- else {
- vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
- (dep_table->entries[i].vddc -
- VDDC_VDDCI_DELTA));
- *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
- }
-
- if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
- *mvdd = data->vbios_boot_state.mvdd_bootup_value *
- VOLTAGE_SCALE;
- else if (dep_table->entries[i].mvdd)
- *mvdd = (uint32_t) dep_table->entries[i].mvdd *
- VOLTAGE_SCALE;
-
- *voltage |= 1 << PHASES_SHIFT;
- return 0;
- }
- }
-
- /* sclk is bigger than max sclk in the dependence table */
- *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-
- if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
- *voltage |= (data->vbios_boot_state.vddci_bootup_value *
- VOLTAGE_SCALE) << VDDCI_SHIFT;
- else if (dep_table->entries[i-1].vddci) {
- vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
- (dep_table->entries[i].vddc -
- VDDC_VDDCI_DELTA));
- *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
- }
-
- if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
- *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
- else if (dep_table->entries[i].mvdd)
- *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
-
- return 0;
-}
-
-
-static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
-{
- uint32_t tmp;
- tmp = raw_setting * 4096 / 100;
- return (uint16_t)tmp;
-}
-
-static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)
-{
- switch (line) {
- case SMU7_I2CLineID_DDC1:
- *scl = SMU7_I2C_DDC1CLK;
- *sda = SMU7_I2C_DDC1DATA;
- break;
- case SMU7_I2CLineID_DDC2:
- *scl = SMU7_I2C_DDC2CLK;
- *sda = SMU7_I2C_DDC2DATA;
- break;
- case SMU7_I2CLineID_DDC3:
- *scl = SMU7_I2C_DDC3CLK;
- *sda = SMU7_I2C_DDC3DATA;
- break;
- case SMU7_I2CLineID_DDC4:
- *scl = SMU7_I2C_DDC4CLK;
- *sda = SMU7_I2C_DDC4DATA;
- break;
- case SMU7_I2CLineID_DDC5:
- *scl = SMU7_I2C_DDC5CLK;
- *sda = SMU7_I2C_DDC5DATA;
- break;
- case SMU7_I2CLineID_DDC6:
- *scl = SMU7_I2C_DDC6CLK;
- *sda = SMU7_I2C_DDC6DATA;
- break;
- case SMU7_I2CLineID_SCLSDA:
- *scl = SMU7_I2C_SCL;
- *sda = SMU7_I2C_SDA;
- break;
- case SMU7_I2CLineID_DDCVGA:
- *scl = SMU7_I2C_DDCVGACLK;
- *sda = SMU7_I2C_DDCVGADATA;
- break;
- default:
- *scl = 0;
- *sda = 0;
- break;
- }
-}
-
-static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- if (table_info &&
- table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
- table_info->cac_dtp_table->usPowerTuneDataSetID)
- smu_data->power_tune_defaults =
- &fiji_power_tune_data_set_array
- [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
- else
- smu_data->power_tune_defaults = &fiji_power_tune_data_set_array[0];
-
-}
-
-static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-{
-
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
-
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
- struct pp_advance_fan_control_parameters *fan_table =
- &hwmgr->thermal_controller.advanceFanControlParameters;
- uint8_t uc_scl, uc_sda;
-
- /* TDP number of fraction bits are changed from 8 to 7 for Fiji
- * as requested by SMC team
- */
- dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
- (uint16_t)(cac_dtp_table->usTDP * 128));
- dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
- (uint16_t)(cac_dtp_table->usTDP * 128));
-
- PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
- "Target Operating Temp is out of Range!",
- );
-
- dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
- dpm_table->GpuTjHyst = 8;
-
- dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
-
- /* The following are for new Fiji Multi-input fan/thermal control */
- dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTargetOperatingTemp * 256);
- dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTemperatureLimitHotspot * 256);
- dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTemperatureLimitLiquid1 * 256);
- dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTemperatureLimitLiquid2 * 256);
- dpm_table->TemperatureLimitVrVddc = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTemperatureLimitVrVddc * 256);
- dpm_table->TemperatureLimitVrMvdd = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTemperatureLimitVrMvdd * 256);
- dpm_table->TemperatureLimitPlx = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTemperatureLimitPlx * 256);
-
- dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainEdge));
- dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainHotspot));
- dpm_table->FanGainLiquid = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainLiquid));
- dpm_table->FanGainVrVddc = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainVrVddc));
- dpm_table->FanGainVrMvdd = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainVrMvdd));
- dpm_table->FanGainPlx = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainPlx));
- dpm_table->FanGainHbm = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainHbm));
-
- dpm_table->Liquid1_I2C_address = cac_dtp_table->ucLiquid1_I2C_address;
- dpm_table->Liquid2_I2C_address = cac_dtp_table->ucLiquid2_I2C_address;
- dpm_table->Vr_I2C_address = cac_dtp_table->ucVr_I2C_address;
- dpm_table->Plx_I2C_address = cac_dtp_table->ucPlx_I2C_address;
-
- get_scl_sda_value(cac_dtp_table->ucLiquid_I2C_Line, &uc_scl, &uc_sda);
- dpm_table->Liquid_I2C_LineSCL = uc_scl;
- dpm_table->Liquid_I2C_LineSDA = uc_sda;
-
- get_scl_sda_value(cac_dtp_table->ucVr_I2C_Line, &uc_scl, &uc_sda);
- dpm_table->Vr_I2C_LineSCL = uc_scl;
- dpm_table->Vr_I2C_LineSDA = uc_sda;
-
- get_scl_sda_value(cac_dtp_table->ucPlx_I2C_Line, &uc_scl, &uc_sda);
- dpm_table->Plx_I2C_LineSCL = uc_scl;
- dpm_table->Plx_I2C_LineSDA = uc_sda;
-
- return 0;
-}
-
-
-static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
- smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
- smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
- smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-
- return 0;
-}
-
-
-static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-{
- uint16_t tdc_limit;
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- /* TDC number of fraction bits are changed from 8 to 7
- * for Fiji as requested by SMC team
- */
- tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
- smu_data->power_tune_table.TDC_VDDC_PkgLimit =
- CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
- smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
- defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
- smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
-
- return 0;
-}
-
-static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
- uint32_t temp;
-
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- fuse_table_offset +
- offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
- (uint32_t *)&temp, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
- return -EINVAL);
- else {
- smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
- smu_data->power_tune_table.LPMLTemperatureMin =
- (uint8_t)((temp >> 16) & 0xff);
- smu_data->power_tune_table.LPMLTemperatureMax =
- (uint8_t)((temp >> 8) & 0xff);
- smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
- }
- return 0;
-}
-
-static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-
- /* Currently not used. Set all to zero. */
- for (i = 0; i < 16; i++)
- smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-
- return 0;
-}
-
-static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-
- if ((hwmgr->thermal_controller.advanceFanControlParameters.
- usFanOutputSensitivity & (1 << 15)) ||
- 0 == hwmgr->thermal_controller.advanceFanControlParameters.
- usFanOutputSensitivity)
- hwmgr->thermal_controller.advanceFanControlParameters.
- usFanOutputSensitivity = hwmgr->thermal_controller.
- advanceFanControlParameters.usDefaultFanOutputSensitivity;
-
- smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
- PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
- advanceFanControlParameters.usFanOutputSensitivity);
- return 0;
-}
-
-static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-
- /* Currently not used. Set all to zero. */
- for (i = 0; i < 16; i++)
- smu_data->power_tune_table.GnbLPML[i] = 0;
-
- return 0;
-}
-
-static int fiji_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
- return 0;
-}
-
-static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
- uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
- struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-
- HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
- LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-
- smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
- CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
- smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
- CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
-
- return 0;
-}
-
-static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-{
- uint32_t pm_fuse_table_offset;
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU73_Firmware_Header, PmFuseTable),
- &pm_fuse_table_offset, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to get pm_fuse_table_offset Failed!",
- return -EINVAL);
-
- /* DW6 */
- if (fiji_populate_svi_load_line(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate SviLoadLine Failed!",
- return -EINVAL);
- /* DW7 */
- if (fiji_populate_tdc_limit(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TDCLimit Failed!", return -EINVAL);
- /* DW8 */
- if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TdcWaterfallCtl, "
- "LPMLTemperature Min and Max Failed!",
- return -EINVAL);
-
- /* DW9-DW12 */
- if (0 != fiji_populate_temperature_scaler(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate LPMLTemperatureScaler Failed!",
- return -EINVAL);
-
- /* DW13-DW14 */
- if (fiji_populate_fuzzy_fan(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate Fuzzy Fan Control parameters Failed!",
- return -EINVAL);
-
- /* DW15-DW18 */
- if (fiji_populate_gnb_lpml(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML Failed!",
- return -EINVAL);
-
- /* DW19 */
- if (fiji_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML Min and Max Vid Failed!",
- return -EINVAL);
-
- /* DW20 */
- if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
- "Sidd Failed!", return -EINVAL);
-
- if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
- (uint8_t *)&smu_data->power_tune_table,
- sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to download PmFuseTable Failed!",
- return -EINVAL);
- }
- return 0;
-}
-
-/**
-* Preparation of vddc and vddgfx CAC tables for SMC.
-*
-* @param hwmgr the address of the hardware manager
-* @param table the SMC DPM table structure to be populated
-* @return always 0
-*/
-static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_DpmTable *table)
-{
- uint32_t count;
- uint8_t index;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_voltage_lookup_table *lookup_table =
- table_info->vddc_lookup_table;
- /* tables is already swapped, so in order to use the value from it,
- * we need to swap it back.
- * We are populating vddc CAC data to BapmVddc table
- * in split and merged mode
- */
-
- for (count = 0; count < lookup_table->count; count++) {
- index = phm_get_voltage_index(lookup_table,
- data->vddc_voltage_table.entries[count].value);
- table->BapmVddcVidLoSidd[count] =
- convert_to_vid(lookup_table->entries[index].us_cac_low);
- table->BapmVddcVidHiSidd[count] =
- convert_to_vid(lookup_table->entries[index].us_cac_high);
- }
-
- return 0;
-}
-
-/**
-* Preparation of voltage tables for SMC.
-*
-* @param hwmgr the address of the hardware manager
-* @param table the SMC DPM table structure to be populated
-* @return always 0
-*/
-
-static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_DpmTable *table)
-{
- int result;
-
- result = fiji_populate_cac_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "can not populate CAC voltage tables to SMC",
- return -EINVAL);
-
- return 0;
-}
-
-static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_Ulv *state)
-{
- int result = 0;
-
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- state->CcPwrDynRm = 0;
- state->CcPwrDynRm1 = 0;
-
- state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
- state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
- VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-
- state->VddcPhase = 1;
-
- if (!result) {
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
- CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
- }
- return result;
-}
-
-static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_DpmTable *table)
-{
- return fiji_populate_ulv_level(hwmgr, &table->Ulv);
-}
-
-static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- int i;
-
- /* Index (dpm_table->pcie_speed_table.count)
- * is reserved for PCIE boot level. */
- for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
- table->LinkLevel[i].PcieGenSpeed =
- (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
- table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
- dpm_table->pcie_speed_table.dpm_levels[i].param1);
- table->LinkLevel[i].EnabledForActivity = 1;
- table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
- table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
- table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
- }
-
- smu_data->smc_state_table.LinkLevelCount =
- (uint8_t)dpm_table->pcie_speed_table.count;
- data->dpm_level_enable_mask.pcie_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-
- return 0;
-}
-
-
-/**
-* Calculates the SCLK dividers using the provided engine clock
-*
-* @param hwmgr the address of the hardware manager
-* @param clock the engine clock to use to populate the structure
-* @param sclk the SMC SCLK structure to be populated
-*/
-static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
-{
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct pp_atomctrl_clock_dividers_vi dividers;
- uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
- uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
- uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
- uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
- uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
- uint32_t ref_clock;
- uint32_t ref_divider;
- uint32_t fbdiv;
- int result;
-
- /* get the engine clock dividers for this clock value */
- result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs);
-
- PP_ASSERT_WITH_CODE(result == 0,
- "Error retrieving Engine Clock dividers from VBIOS.",
- return result);
-
- /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
- ref_clock = atomctrl_get_reference_clock(hwmgr);
- ref_divider = 1 + dividers.uc_pll_ref_div;
-
- /* low 14 bits is fraction and high 12 bits is divider */
- fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-
- /* SPLL_FUNC_CNTL setup */
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
- SPLL_REF_DIV, dividers.uc_pll_ref_div);
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
- SPLL_PDIV_A, dividers.uc_pll_post_div);
-
- /* SPLL_FUNC_CNTL_3 setup*/
- spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
- SPLL_FB_DIV, fbdiv);
-
- /* set to use fractional accumulation*/
- spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
- SPLL_DITHEN, 1);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
- struct pp_atomctrl_internal_ss_info ssInfo;
-
- uint32_t vco_freq = clock * dividers.uc_pll_post_div;
- if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
- vco_freq, &ssInfo)) {
- /*
- * ss_info.speed_spectrum_percentage -- in unit of 0.01%
- * ss_info.speed_spectrum_rate -- in unit of khz
- *
- * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
- */
- uint32_t clk_s = ref_clock * 5 /
- (ref_divider * ssInfo.speed_spectrum_rate);
- /* clkv = 2 * D * fbdiv / NS */
- uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
- fbdiv / (clk_s * 10000);
-
- cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
- CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
- cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
- CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
- cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
- CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
- }
- }
-
- sclk->SclkFrequency = clock;
- sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
- sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
- sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
- sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
- sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
-
- return 0;
-}
-
-/**
-* Populates single SMC SCLK structure using the provided engine clock
-*
-* @param hwmgr the address of the hardware manager
-* @param clock the engine clock to use to populate the structure
-* @param sclk the SMC SCLK structure to be populated
-*/
-
-static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
- uint32_t clock, uint16_t sclk_al_threshold,
- struct SMU73_Discrete_GraphicsLevel *level)
-{
- int result;
- /* PP_Clocks minClocks; */
- uint32_t threshold, mvdd;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- result = fiji_calculate_sclk_params(hwmgr, clock, level);
-
- /* populate graphics levels */
- result = fiji_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_sclk, clock,
- (uint32_t *)(&level->MinVoltage), &mvdd);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find VDDC voltage value for "
- "VDDC engine clock dependency table",
- return result);
-
- level->SclkFrequency = clock;
- level->ActivityLevel = sclk_al_threshold;
- level->CcPwrDynRm = 0;
- level->CcPwrDynRm1 = 0;
- level->EnabledForActivity = 0;
- level->EnabledForThrottle = 1;
- level->UpHyst = 10;
- level->DownHyst = 0;
- level->VoltageDownHyst = 0;
- level->PowerThrottle = 0;
-
- threshold = clock * data->fast_watermark_threshold / 100;
-
- data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
- level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
- hwmgr->display_config.min_core_set_clock_in_sr);
-
-
- /* Default to slow, highest DPM level will be
- * set to PPSMC_DISPLAY_WATERMARK_LOW later.
- */
- level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
- CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
- CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
- CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
- CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
- CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
- CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
-
- return 0;
-}
-/**
-* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
-*
-* @param hwmgr the address of the hardware manager
-*/
-int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
- uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
- int result = 0;
- uint32_t array = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
- uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
- SMU73_MAX_LEVELS_GRAPHICS;
- struct SMU73_Discrete_GraphicsLevel *levels =
- smu_data->smc_state_table.GraphicsLevel;
- uint32_t i, max_entry;
- uint8_t hightest_pcie_level_enabled = 0,
- lowest_pcie_level_enabled = 0,
- mid_pcie_level_enabled = 0,
- count = 0;
-
- for (i = 0; i < dpm_table->sclk_table.count; i++) {
- result = fiji_populate_single_graphic_level(hwmgr,
- dpm_table->sclk_table.dpm_levels[i].value,
- (uint16_t)smu_data->activity_target[i],
- &levels[i]);
- if (result)
- return result;
-
- /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
- if (i > 1)
- levels[i].DeepSleepDivId = 0;
- }
-
- /* Only enable level 0 for now.*/
- levels[0].EnabledForActivity = 1;
-
- /* set highest level watermark to high */
- levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
- PPSMC_DISPLAY_WATERMARK_HIGH;
-
- smu_data->smc_state_table.GraphicsDpmLevelCount =
- (uint8_t)dpm_table->sclk_table.count;
- data->dpm_level_enable_mask.sclk_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-
- if (pcie_table != NULL) {
- PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
- "There must be 1 or more PCIE levels defined in PPTable.",
- return -EINVAL);
- max_entry = pcie_entry_cnt - 1;
- for (i = 0; i < dpm_table->sclk_table.count; i++)
- levels[i].pcieDpmLevel =
- (uint8_t) ((i < max_entry) ? i : max_entry);
- } else {
- while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
- ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << (hightest_pcie_level_enabled + 1))) != 0))
- hightest_pcie_level_enabled++;
-
- while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
- ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << lowest_pcie_level_enabled)) == 0))
- lowest_pcie_level_enabled++;
-
- while ((count < hightest_pcie_level_enabled) &&
- ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
- count++;
-
- mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
- hightest_pcie_level_enabled ?
- (lowest_pcie_level_enabled + 1 + count) :
- hightest_pcie_level_enabled;
-
- /* set pcieDpmLevel to hightest_pcie_level_enabled */
- for (i = 2; i < dpm_table->sclk_table.count; i++)
- levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
-
- /* set pcieDpmLevel to lowest_pcie_level_enabled */
- levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
-
- /* set pcieDpmLevel to mid_pcie_level_enabled */
- levels[1].pcieDpmLevel = mid_pcie_level_enabled;
- }
- /* level count will send to smc once at init smc table and never change */
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
- (uint32_t)array_size, SMC_RAM_END);
-
- return result;
-}
-
-
-/**
- * MCLK Frequency Ratio
- * SEQ_CG_RESP Bit[31:24] - 0x0
- * Bit[27:24] \96 DDR3 Frequency ratio
- * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
- * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
- * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
- * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
- * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
- * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
- * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
- * 400 < 0x7 <= 450MHz, 800 < 0xF
- */
-static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
-{
- if (mem_clock <= 10000)
- return 0x0;
- if (mem_clock <= 15000)
- return 0x1;
- if (mem_clock <= 20000)
- return 0x2;
- if (mem_clock <= 25000)
- return 0x3;
- if (mem_clock <= 30000)
- return 0x4;
- if (mem_clock <= 35000)
- return 0x5;
- if (mem_clock <= 40000)
- return 0x6;
- if (mem_clock <= 45000)
- return 0x7;
- if (mem_clock <= 50000)
- return 0x8;
- if (mem_clock <= 55000)
- return 0x9;
- if (mem_clock <= 60000)
- return 0xa;
- if (mem_clock <= 65000)
- return 0xb;
- if (mem_clock <= 70000)
- return 0xc;
- if (mem_clock <= 75000)
- return 0xd;
- if (mem_clock <= 80000)
- return 0xe;
- /* mem_clock > 800MHz */
- return 0xf;
-}
-
-/**
-* Populates the SMC MCLK structure using the provided memory clock
-*
-* @param hwmgr the address of the hardware manager
-* @param clock the memory clock to use to populate the structure
-* @param sclk the SMC SCLK structure to be populated
-*/
-static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
- uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
-{
- struct pp_atomctrl_memory_clock_param mem_param;
- int result;
-
- result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
- PP_ASSERT_WITH_CODE((0 == result),
- "Failed to get Memory PLL Dividers.",
- );
-
- /* Save the result data to outpupt memory level structure */
- mclk->MclkFrequency = clock;
- mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;
- mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);
-
- return result;
-}
-
-static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
- uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- int result = 0;
- uint32_t mclk_stutter_mode_threshold = 60000;
-
- if (table_info->vdd_dep_on_mclk) {
- result = fiji_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_mclk, clock,
- (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find MinVddc voltage value from memory "
- "VDDC voltage dependency table", return result);
- }
-
- mem_level->EnabledForThrottle = 1;
- mem_level->EnabledForActivity = 0;
- mem_level->UpHyst = 0;
- mem_level->DownHyst = 100;
- mem_level->VoltageDownHyst = 0;
- mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
- mem_level->StutterEnable = false;
-
- mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
- /* enable stutter mode if all the follow condition applied
- * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
- * &(data->DisplayTiming.numExistingDisplays));
- */
- data->display_timing.num_existing_displays = 1;
-
- if (mclk_stutter_mode_threshold &&
- (clock <= mclk_stutter_mode_threshold) &&
- (!data->is_uvd_enabled) &&
- (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
- STUTTER_ENABLE) & 0x1))
- mem_level->StutterEnable = true;
-
- result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
- if (!result) {
- CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
- CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
- }
- return result;
-}
-
-/**
-* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
-*
-* @param hwmgr the address of the hardware manager
-*/
-int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- int result;
- /* populate MCLK dpm table to SMU7 */
- uint32_t array = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
- uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
- SMU73_MAX_LEVELS_MEMORY;
- struct SMU73_Discrete_MemoryLevel *levels =
- smu_data->smc_state_table.MemoryLevel;
- uint32_t i;
-
- for (i = 0; i < dpm_table->mclk_table.count; i++) {
- PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
- "can not populate memory level as memory clock is zero",
- return -EINVAL);
- result = fiji_populate_single_memory_level(hwmgr,
- dpm_table->mclk_table.dpm_levels[i].value,
- &levels[i]);
- if (result)
- return result;
- }
-
- /* Only enable level 0 for now. */
- levels[0].EnabledForActivity = 1;
-
- /* in order to prevent MC activity from stutter mode to push DPM up.
- * the UVD change complements this by putting the MCLK in
- * a higher state by default such that we are not effected by
- * up threshold or and MCLK DPM latency.
- */
- levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
- CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-
- smu_data->smc_state_table.MemoryDpmLevelCount =
- (uint8_t)dpm_table->mclk_table.count;
- data->dpm_level_enable_mask.mclk_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
- /* set highest level watermark to high */
- levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
- PPSMC_DISPLAY_WATERMARK_HIGH;
-
- /* level count will send to smc once at init smc table and never change */
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
- (uint32_t)array_size, SMC_RAM_END);
-
- return result;
-}
-
-
-/**
-* Populates the SMC MVDD structure using the provided memory clock.
-*
-* @param hwmgr the address of the hardware manager
-* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
-* @param voltage the SMC VOLTAGE structure to be populated
-*/
-static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
- uint32_t mclk, SMIO_Pattern *smio_pat)
-{
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint32_t i = 0;
-
- if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
- /* find mvdd value which clock is more than request */
- for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
- if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
- smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
- break;
- }
- }
- PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
- "MVDD Voltage is outside the supported range.",
- return -EINVAL);
- } else
- return -EINVAL;
-
- return 0;
-}
-
-static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
- SMU73_Discrete_DpmTable *table)
-{
- int result = 0;
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct pp_atomctrl_clock_dividers_vi dividers;
- SMIO_Pattern vol_level;
- uint32_t mvdd;
- uint16_t us_mvdd;
- uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
- uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
-
- table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-
- if (!data->sclk_dpm_key_disabled) {
- /* Get MinVoltage and Frequency from DPM0,
- * already converted to SMC_UL */
- table->ACPILevel.SclkFrequency =
- data->dpm_table.sclk_table.dpm_levels[0].value;
- result = fiji_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_sclk,
- table->ACPILevel.SclkFrequency,
- (uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);
- PP_ASSERT_WITH_CODE((0 == result),
- "Cannot find ACPI VDDC voltage value " \
- "in Clock Dependency Table",
- );
- } else {
- table->ACPILevel.SclkFrequency =
- data->vbios_boot_state.sclk_bootup_value;
- table->ACPILevel.MinVoltage =
- data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
- }
-
- /* get the engine clock dividers for this clock value */
- result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
- table->ACPILevel.SclkFrequency, ÷rs);
- PP_ASSERT_WITH_CODE(result == 0,
- "Error retrieving Engine Clock dividers from VBIOS.",
- return result);
-
- table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
- table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
- table->ACPILevel.DeepSleepDivId = 0;
-
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
- SPLL_PWRON, 0);
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
- SPLL_RESET, 1);
- spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
- SCLK_MUX_SEL, 4);
-
- table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
- table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
- table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
- table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
- table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
- table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
- table->ACPILevel.CcPwrDynRm = 0;
- table->ACPILevel.CcPwrDynRm1 = 0;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-
- if (!data->mclk_dpm_key_disabled) {
- /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
- table->MemoryACPILevel.MclkFrequency =
- data->dpm_table.mclk_table.dpm_levels[0].value;
- result = fiji_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_mclk,
- table->MemoryACPILevel.MclkFrequency,
- (uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd);
- PP_ASSERT_WITH_CODE((0 == result),
- "Cannot find ACPI VDDCI voltage value in Clock Dependency Table",
- );
- } else {
- table->MemoryACPILevel.MclkFrequency =
- data->vbios_boot_state.mclk_bootup_value;
- table->MemoryACPILevel.MinVoltage =
- data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
- }
-
- us_mvdd = 0;
- if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
- (data->mclk_dpm_key_disabled))
- us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
- else {
- if (!fiji_populate_mvdd_value(hwmgr,
- data->dpm_table.mclk_table.dpm_levels[0].value,
- &vol_level))
- us_mvdd = vol_level.Voltage;
- }
-
- table->MemoryACPILevel.MinMvdd =
- PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
-
- table->MemoryACPILevel.EnabledForThrottle = 0;
- table->MemoryACPILevel.EnabledForActivity = 0;
- table->MemoryACPILevel.UpHyst = 0;
- table->MemoryACPILevel.DownHyst = 100;
- table->MemoryACPILevel.VoltageDownHyst = 0;
- table->MemoryACPILevel.ActivityLevel =
- PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-
- table->MemoryACPILevel.StutterEnable = false;
- CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
-
- return result;
-}
-
-static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- SMU73_Discrete_DpmTable *table)
-{
- int result = -EINVAL;
- uint8_t count;
- struct pp_atomctrl_clock_dividers_vi dividers;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- table_info->mm_dep_table;
-
- table->VceLevelCount = (uint8_t)(mm_table->count);
- table->VceBootLevel = 0;
-
- for (count = 0; count < table->VceLevelCount; count++) {
- table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
- table->VceLevel[count].MinVoltage = 0;
- table->VceLevel[count].MinVoltage |=
- (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
- table->VceLevel[count].MinVoltage |=
- ((mm_table->entries[count].vddc - VDDC_VDDCI_DELTA) *
- VOLTAGE_SCALE) << VDDCI_SHIFT;
- table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
- /*retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->VceLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for VCE engine clock",
- return result);
-
- table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
- }
- return result;
-}
-
-static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
- SMU73_Discrete_DpmTable *table)
-{
- int result = -EINVAL;
- uint8_t count;
- struct pp_atomctrl_clock_dividers_vi dividers;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- table_info->mm_dep_table;
-
- table->AcpLevelCount = (uint8_t)(mm_table->count);
- table->AcpBootLevel = 0;
-
- for (count = 0; count < table->AcpLevelCount; count++) {
- table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
- table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
- VOLTAGE_SCALE) << VDDC_SHIFT;
- table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
- VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
- table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->AcpLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for engine clock", return result);
-
- table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
- }
- return result;
-}
-
-static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
- SMU73_Discrete_DpmTable *table)
-{
- int result = -EINVAL;
- uint8_t count;
- struct pp_atomctrl_clock_dividers_vi dividers;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- table_info->mm_dep_table;
-
- table->SamuBootLevel = 0;
- table->SamuLevelCount = (uint8_t)(mm_table->count);
-
- for (count = 0; count < table->SamuLevelCount; count++) {
- /* not sure whether we need evclk or not */
- table->SamuLevel[count].MinVoltage = 0;
- table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
- table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
- VOLTAGE_SCALE) << VDDC_SHIFT;
- table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
- VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
- table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->SamuLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for samu clock", return result);
-
- table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
- }
- return result;
-}
-
-static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
- int32_t eng_clock, int32_t mem_clock,
- struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
-{
- uint32_t dram_timing;
- uint32_t dram_timing2;
- uint32_t burstTime;
- ULONG state, trrds, trrdl;
- int result;
-
- result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
- eng_clock, mem_clock);
- PP_ASSERT_WITH_CODE(result == 0,
- "Error calling VBIOS to set DRAM_TIMING.", return result);
-
- dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
- dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
- burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
-
- state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
- trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
- trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
-
- arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
- arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
- arb_regs->McArbBurstTime = (uint8_t)burstTime;
- arb_regs->TRRDS = (uint8_t)trrds;
- arb_regs->TRRDL = (uint8_t)trrdl;
-
- return 0;
-}
-
-static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
- uint32_t i, j;
- int result = 0;
-
- for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
- for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
- result = fiji_populate_memory_timing_parameters(hwmgr,
- data->dpm_table.sclk_table.dpm_levels[i].value,
- data->dpm_table.mclk_table.dpm_levels[j].value,
- &arb_regs.entries[i][j]);
- if (result)
- break;
- }
- }
-
- if (!result)
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.arb_table_start,
- (uint8_t *)&arb_regs,
- sizeof(SMU73_Discrete_MCArbDramTimingTable),
- SMC_RAM_END);
- return result;
-}
-
-static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_DpmTable *table)
-{
- int result = -EINVAL;
- uint8_t count;
- struct pp_atomctrl_clock_dividers_vi dividers;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- table_info->mm_dep_table;
-
- table->UvdLevelCount = (uint8_t)(mm_table->count);
- table->UvdBootLevel = 0;
-
- for (count = 0; count < table->UvdLevelCount; count++) {
- table->UvdLevel[count].MinVoltage = 0;
- table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
- table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
- table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
- VOLTAGE_SCALE) << VDDC_SHIFT;
- table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
- VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
- table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->UvdLevel[count].VclkFrequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for Vclk clock", return result);
-
- table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->UvdLevel[count].DclkFrequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for Dclk clock", return result);
-
- table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
-
- }
- return result;
-}
-
-static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_DpmTable *table)
-{
- int result = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- table->GraphicsBootLevel = 0;
- table->MemoryBootLevel = 0;
-
- /* find boot level from dpm table */
- result = phm_find_boot_level(&(data->dpm_table.sclk_table),
- data->vbios_boot_state.sclk_bootup_value,
- (uint32_t *)&(table->GraphicsBootLevel));
-
- result = phm_find_boot_level(&(data->dpm_table.mclk_table),
- data->vbios_boot_state.mclk_bootup_value,
- (uint32_t *)&(table->MemoryBootLevel));
-
- table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
- VOLTAGE_SCALE;
- table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
- VOLTAGE_SCALE;
- table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
- VOLTAGE_SCALE;
-
- CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
- CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
- CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-
- return 0;
-}
-
-static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint8_t count, level;
-
- count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
- for (level = 0; level < count; level++) {
- if (table_info->vdd_dep_on_sclk->entries[level].clk >=
- data->vbios_boot_state.sclk_bootup_value) {
- smu_data->smc_state_table.GraphicsBootLevel = level;
- break;
- }
- }
-
- count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
- for (level = 0; level < count; level++) {
- if (table_info->vdd_dep_on_mclk->entries[level].clk >=
- data->vbios_boot_state.mclk_bootup_value) {
- smu_data->smc_state_table.MemoryBootLevel = level;
- break;
- }
- }
-
- return 0;
-}
-
-static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-{
- uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
- volt_with_cks, value;
- uint16_t clock_freq_u16;
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
- volt_offset = 0;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
- table_info->vdd_dep_on_sclk;
-
- stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-
- /* Read SMU_Eefuse to read and calculate RO and determine
- * if the part is SS or FF. if RO >= 1660MHz, part is FF.
- */
- efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixSMU_EFUSE_0 + (146 * 4));
- efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixSMU_EFUSE_0 + (148 * 4));
- efuse &= 0xFF000000;
- efuse = efuse >> 24;
- efuse2 &= 0xF;
-
- if (efuse2 == 1)
- ro = (2300 - 1350) * efuse / 255 + 1350;
- else
- ro = (2500 - 1000) * efuse / 255 + 1000;
-
- if (ro >= 1660)
- type = 0;
- else
- type = 1;
-
- /* Populate Stretch amount */
- smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
-
- /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
- for (i = 0; i < sclk_table->count; i++) {
- smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
- sclk_table->entries[i].cks_enable << i;
- volt_without_cks = (uint32_t)((14041 *
- (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
- (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
- volt_with_cks = (uint32_t)((13946 *
- (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
- (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
- if (volt_without_cks >= volt_with_cks)
- volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
- sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
- smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
- }
-
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- STRETCH_ENABLE, 0x0);
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- masterReset, 0x1);
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- staticEnable, 0x1);
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- masterReset, 0x0);
-
- /* Populate CKS Lookup Table */
- if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
- stretch_amount2 = 0;
- else if (stretch_amount == 3 || stretch_amount == 4)
- stretch_amount2 = 1;
- else {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ClockStretcher);
- PP_ASSERT_WITH_CODE(false,
- "Stretch Amount in PPTable not supported\n",
- return -EINVAL);
- }
-
- value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixPWR_CKS_CNTL);
- value &= 0xFFC2FF87;
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
- fiji_clock_stretcher_lookup_table[stretch_amount2][0];
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
- fiji_clock_stretcher_lookup_table[stretch_amount2][1];
- clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
- GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
- SclkFrequency) / 100);
- if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
- clock_freq_u16 &&
- fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
- clock_freq_u16) {
- /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
- value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
- /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
- value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
- /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
- value |= (fiji_clock_stretch_amount_conversion
- [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
- [stretch_amount]) << 3;
- }
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
- CKS_LOOKUPTableEntry[0].minFreq);
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
- CKS_LOOKUPTableEntry[0].maxFreq);
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
- fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
- (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixPWR_CKS_CNTL, value);
-
- /* Populate DDT Lookup Table */
- for (i = 0; i < 4; i++) {
- /* Assign the minimum and maximum VID stored
- * in the last row of Clock Stretcher Voltage Table.
- */
- smu_data->smc_state_table.ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].minVID =
- (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
- smu_data->smc_state_table.ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].maxVID =
- (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
- /* Loop through each SCLK and check the frequency
- * to see if it lies within the frequency for clock stretcher.
- */
- for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
- cks_setting = 0;
- clock_freq = PP_SMC_TO_HOST_UL(
- smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
- /* Check the allowed frequency against the sclk level[j].
- * Sclk's endianness has already been converted,
- * and it's in 10Khz unit,
- * as opposed to Data table, which is in Mhz unit.
- */
- if (clock_freq >=
- (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
- cks_setting |= 0x2;
- if (clock_freq <
- (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
- cks_setting |= 0x1;
- }
- smu_data->smc_state_table.ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
- }
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
- ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].setting);
- }
-
- value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
- value &= 0xFFFFFFFE;
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
-
- return 0;
-}
-
-/**
-* Populates the SMC VRConfig field in DPM table.
-*
-* @param hwmgr the address of the hardware manager
-* @param table the SMC DPM table structure to be populated
-* @return always 0
-*/
-static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
- struct SMU73_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint16_t config;
-
- config = VR_MERGED_WITH_VDDC;
- table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
-
- /* Set Vddc Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
- config = VR_SVI2_PLANE_1;
- table->VRConfig |= config;
- } else {
- PP_ASSERT_WITH_CODE(false,
- "VDDC should be on SVI2 control in merged mode!",
- );
- }
- /* Set Vddci Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
- config = VR_SVI2_PLANE_2; /* only in merged mode */
- table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
- } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
- config = VR_SMIO_PATTERN_1;
- table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
- } else {
- config = VR_STATIC_VOLTAGE;
- table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
- }
- /* Set Mvdd Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
- config = VR_SVI2_PLANE_2;
- table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
- } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
- config = VR_SMIO_PATTERN_2;
- table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
- } else {
- config = VR_STATIC_VOLTAGE;
- table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
- }
-
- return 0;
-}
-
-static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(smumgr->backend);
- uint32_t tmp;
- int result;
-
- /* This is a read-modify-write on the first byte of the ARB table.
- * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
- * is the field 'current'.
- * This solution is ugly, but we never write the whole table only
- * individual fields in it.
- * In reality this field should not be in that structure
- * but in a soft register.
- */
- result = smu7_read_smc_sram_dword(smumgr,
- smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
-
- if (result)
- return result;
-
- tmp &= 0x00FFFFFF;
- tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-
- return smu7_write_smc_sram_dword(smumgr,
- smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
-}
-
-static int fiji_save_default_power_profile(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct SMU73_Discrete_GraphicsLevel *levels =
- data->smc_state_table.GraphicsLevel;
- unsigned min_level = 1;
-
- hwmgr->default_gfx_power_profile.activity_threshold =
- be16_to_cpu(levels[0].ActivityLevel);
- hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
- hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
- hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
-
- hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
- hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
-
- /* Workaround compute SDMA instability: disable lowest SCLK
- * DPM level. Optimize compute power profile: Use only highest
- * 2 power levels (if more than 2 are available), Hysteresis:
- * 0ms up, 5ms down
- */
- if (data->smc_state_table.GraphicsDpmLevelCount > 2)
- min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
- else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
- min_level = 1;
- else
- min_level = 0;
- hwmgr->default_compute_power_profile.min_sclk =
- be32_to_cpu(levels[min_level].SclkFrequency);
- hwmgr->default_compute_power_profile.up_hyst = 0;
- hwmgr->default_compute_power_profile.down_hyst = 5;
-
- hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
- hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
-
- return 0;
-}
-
-static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
-{
- pp_atomctrl_voltage_table param_led_dpm;
- int result = 0;
- u32 mask = 0;
-
- result = atomctrl_get_voltage_table_v3(hwmgr,
- VOLTAGE_TYPE_LEDDPM, VOLTAGE_OBJ_GPIO_LUT,
- ¶m_led_dpm);
- if (result == 0) {
- int i, j;
- u32 tmp = param_led_dpm.mask_low;
-
- for (i = 0, j = 0; i < 32; i++) {
- if (tmp & 1) {
- mask |= (i << (8 * j));
- if (++j >= 3)
- break;
- }
- tmp >>= 1;
- }
- }
- if (mask)
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_LedConfig,
- mask);
- return 0;
-}
-
-/**
-* Initializes the SMC table and uploads it
-*
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data (PowerState)
-* @return always 0
-*/
-int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);
- uint8_t i;
- struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-
- fiji_initialize_power_tune_defaults(hwmgr);
-
- if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
- fiji_populate_smc_voltage_tables(hwmgr, table);
-
- table->SystemFlags = 0;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StepVddc))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-
- if (data->is_memory_gddr5)
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-
- if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
- result = fiji_populate_ulv_state(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ULV state!", return result);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_ULV_PARAMETER, 0x40035);
- }
-
- result = fiji_populate_smc_link_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Link Level!", return result);
-
- result = fiji_populate_all_graphic_levels(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Graphics Level!", return result);
-
- result = fiji_populate_all_memory_levels(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Memory Level!", return result);
-
- result = fiji_populate_smc_acpi_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ACPI Level!", return result);
-
- result = fiji_populate_smc_vce_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize VCE Level!", return result);
-
- result = fiji_populate_smc_acp_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ACP Level!", return result);
-
- result = fiji_populate_smc_samu_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize SAMU Level!", return result);
-
- /* Since only the initial state is completely set up at this point
- * (the other states are just copies of the boot state) we only
- * need to populate the ARB settings for the initial state.
- */
- result = fiji_program_memory_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to Write ARB settings for the initial state.", return result);
-
- result = fiji_populate_smc_uvd_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize UVD Level!", return result);
-
- result = fiji_populate_smc_boot_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Boot Level!", return result);
-
- result = fiji_populate_smc_initailial_state(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Boot State!", return result);
-
- result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate BAPM Parameters!", return result);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ClockStretcher)) {
- result = fiji_populate_clock_stretcher_data_table(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate Clock Stretcher Data Table!",
- return result);
- }
-
- table->GraphicsVoltageChangeEnable = 1;
- table->GraphicsThermThrottleEnable = 1;
- table->GraphicsInterval = 1;
- table->VoltageInterval = 1;
- table->ThermalInterval = 1;
- table->TemperatureLimitHigh =
- table_info->cac_dtp_table->usTargetOperatingTemp *
- SMU7_Q88_FORMAT_CONVERSION_UNIT;
- table->TemperatureLimitLow =
- (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
- SMU7_Q88_FORMAT_CONVERSION_UNIT;
- table->MemoryVoltageChangeEnable = 1;
- table->MemoryInterval = 1;
- table->VoltageResponseTime = 0;
- table->PhaseResponseTime = 0;
- table->MemoryThermThrottleEnable = 1;
- table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
- table->PCIeGenInterval = 1;
- table->VRConfig = 0;
-
- result = fiji_populate_vr_config(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate VRConfig setting!", return result);
-
- table->ThermGpio = 17;
- table->SclkStepSize = 0x4000;
-
- if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
- table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot);
- } else {
- table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot);
- }
-
- if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
- &gpio_pin)) {
- table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition);
- } else {
- table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition);
- }
-
- /* Thermal Output GPIO */
- if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
- &gpio_pin)) {
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ThermalOutGPIO);
-
- table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
-
- /* For porlarity read GPIOPAD_A with assigned Gpio pin
- * since VBIOS will program this register to set 'inactive state',
- * driver can then determine 'active state' from this and
- * program SMU with correct polarity
- */
- table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
- (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
- table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-
- /* if required, combine VRHot/PCC with thermal out GPIO */
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot) &&
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_CombinePCCWithThermalSignal))
- table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
- } else {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ThermalOutGPIO);
- table->ThermOutGpio = 17;
- table->ThermOutPolarity = 1;
- table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
- }
-
- for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
- table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
- CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
- CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
- CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-
- /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
- smu_data->smu7_data.dpm_table_start +
- offsetof(SMU73_Discrete_DpmTable, SystemFlags),
- (uint8_t *)&(table->SystemFlags),
- sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
- SMC_RAM_END);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to upload dpm data to SMC memory!", return result);
-
- result = fiji_init_arb_table_index(hwmgr->smumgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to upload arb data to SMC memory!", return result);
-
- result = fiji_populate_pm_fuses(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate PM fuses to SMC memory!", return result);
-
- result = fiji_setup_dpm_led_config(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to setup dpm led config", return result);
-
- fiji_save_default_power_profile(hwmgr);
-
- return 0;
-}
-
-/**
-* Set up the fan table to control the fan using the SMC.
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from set temperature range routine
-*/
-int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-
- SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
- uint32_t duty100;
- uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
- uint16_t fdo_min, slope1, slope2;
- uint32_t reference_clock;
- int res;
- uint64_t tmp64;
-
- if (hwmgr->thermal_controller.fanInfo.bNoFan) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- if (smu_data->smu7_data.fan_table_start == 0) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- CG_FDO_CTRL1, FMAX_DUTY100);
-
- if (duty100 == 0) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
- usPWMMin * duty100;
- do_div(tmp64, 10000);
- fdo_min = (uint16_t)tmp64;
-
- t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
- hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
- t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
- hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-
- pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
- hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
- pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
- hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-
- slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
- slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-
- fan_table.TempMin = cpu_to_be16((50 + hwmgr->
- thermal_controller.advanceFanControlParameters.usTMin) / 100);
- fan_table.TempMed = cpu_to_be16((50 + hwmgr->
- thermal_controller.advanceFanControlParameters.usTMed) / 100);
- fan_table.TempMax = cpu_to_be16((50 + hwmgr->
- thermal_controller.advanceFanControlParameters.usTMax) / 100);
-
- fan_table.Slope1 = cpu_to_be16(slope1);
- fan_table.Slope2 = cpu_to_be16(slope2);
-
- fan_table.FdoMin = cpu_to_be16(fdo_min);
-
- fan_table.HystDown = cpu_to_be16(hwmgr->
- thermal_controller.advanceFanControlParameters.ucTHyst);
-
- fan_table.HystUp = cpu_to_be16(1);
-
- fan_table.HystSlope = cpu_to_be16(1);
-
- fan_table.TempRespLim = cpu_to_be16(5);
-
- reference_clock = smu7_get_xclk(hwmgr);
-
- fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
- thermal_controller.advanceFanControlParameters.ulCycleDelay *
- reference_clock) / 1600);
-
- fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-
- fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
- hwmgr->device, CGS_IND_REG__SMC,
- CG_MULT_THERMAL_CTRL, TEMP_SEL);
-
- res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start,
- (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
- SMC_RAM_END);
-
- if (!res && hwmgr->thermal_controller.
- advanceFanControlParameters.ucMinimumPWMLimit)
- res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetFanMinPwm,
- hwmgr->thermal_controller.
- advanceFanControlParameters.ucMinimumPWMLimit);
-
- if (!res && hwmgr->thermal_controller.
- advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
- res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetFanSclkTarget,
- hwmgr->thermal_controller.
- advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
-
- if (res)
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
-
- return 0;
-}
-
-
-int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
-{
- int ret;
- struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-
- if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
- return 0;
-
- ret = smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs);
-
- if (!ret)
- /* If this param is not changed, this function could fire unnecessarily */
- smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
-
- return ret;
-}
-
-static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (data->need_update_smu7_dpm_table &
- (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
- return fiji_program_memory_timing_parameters(hwmgr);
-
- return 0;
-}
-
-int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-
- int result = 0;
- uint32_t low_sclk_interrupt_threshold = 0;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
- low_sclk_interrupt_threshold =
- data->low_sclk_interrupt_threshold;
-
- CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.dpm_table_start +
- offsetof(SMU73_Discrete_DpmTable,
- LowSclkInterruptThreshold),
- (uint8_t *)&low_sclk_interrupt_threshold,
- sizeof(uint32_t),
- SMC_RAM_END);
- }
- result = fiji_program_mem_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE((result == 0),
- "Failed to program memory timing parameters!",
- );
- return result;
-}
-
-uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
-{
- switch (type) {
- case SMU_SoftRegisters:
- switch (member) {
- case HandshakeDisables:
- return offsetof(SMU73_SoftRegisters, HandshakeDisables);
- case VoltageChangeTimeout:
- return offsetof(SMU73_SoftRegisters, VoltageChangeTimeout);
- case AverageGraphicsActivity:
- return offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
- case PreVBlankGap:
- return offsetof(SMU73_SoftRegisters, PreVBlankGap);
- case VBlankTimeout:
- return offsetof(SMU73_SoftRegisters, VBlankTimeout);
- case UcodeLoadStatus:
- return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
- }
- case SMU_Discrete_DpmTable:
- switch (member) {
- case UvdBootLevel:
- return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
- case VceBootLevel:
- return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
- case SamuBootLevel:
- return offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
- case LowSclkInterruptThreshold:
- return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
- }
- }
- pr_warn("can't get the offset of type %x member %x\n", type, member);
- return 0;
-}
-
-uint32_t fiji_get_mac_definition(uint32_t value)
-{
- switch (value) {
- case SMU_MAX_LEVELS_GRAPHICS:
- return SMU73_MAX_LEVELS_GRAPHICS;
- case SMU_MAX_LEVELS_MEMORY:
- return SMU73_MAX_LEVELS_MEMORY;
- case SMU_MAX_LEVELS_LINK:
- return SMU73_MAX_LEVELS_LINK;
- case SMU_MAX_ENTRIES_SMIO:
- return SMU73_MAX_ENTRIES_SMIO;
- case SMU_MAX_LEVELS_VDDC:
- return SMU73_MAX_LEVELS_VDDC;
- case SMU_MAX_LEVELS_VDDGFX:
- return SMU73_MAX_LEVELS_VDDGFX;
- case SMU_MAX_LEVELS_VDDCI:
- return SMU73_MAX_LEVELS_VDDCI;
- case SMU_MAX_LEVELS_MVDD:
- return SMU73_MAX_LEVELS_MVDD;
- }
-
- pr_warn("can't get the mac of %x\n", value);
- return 0;
-}
-
-
-static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- smu_data->smc_state_table.UvdBootLevel = 0;
- if (table_info->mm_dep_table->count > 0)
- smu_data->smc_state_table.UvdBootLevel =
- (uint8_t) (table_info->mm_dep_table->count - 1);
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
- UvdBootLevel);
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0x00FFFFFF;
- mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDDPM) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_UVDDPM_SetEnabledMask,
- (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
- return 0;
-}
-
-static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smu_data->smc_state_table.VceBootLevel =
- (uint8_t) (table_info->mm_dep_table->count - 1);
- else
- smu_data->smc_state_table.VceBootLevel = 0;
-
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0xFF00FFFF;
- mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_VCEDPM_SetEnabledMask,
- (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
- return 0;
-}
-
-static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
-
-
- smu_data->smc_state_table.SamuBootLevel = 0;
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
-
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0xFFFFFF00;
- mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SAMUDPM_SetEnabledMask,
- (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
- return 0;
-}
-
-int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
-{
- switch (type) {
- case SMU_UVD_TABLE:
- fiji_update_uvd_smc_table(hwmgr);
- break;
- case SMU_VCE_TABLE:
- fiji_update_vce_smc_table(hwmgr);
- break;
- case SMU_SAMU_TABLE:
- fiji_update_samu_smc_table(hwmgr);
- break;
- default:
- break;
- }
- return 0;
-}
-
-
-/**
-* Get the location of various tables inside the FW image.
-*
-* @param hwmgr the address of the powerplay hardware manager.
-* @return always 0
-*/
-int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
- uint32_t tmp;
- int result;
- bool error = false;
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU73_Firmware_Header, DpmTable),
- &tmp, SMC_RAM_END);
-
- if (0 == result)
- smu_data->smu7_data.dpm_table_start = tmp;
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU73_Firmware_Header, SoftRegisters),
- &tmp, SMC_RAM_END);
-
- if (!result) {
- data->soft_regs_start = tmp;
- smu_data->smu7_data.soft_regs_start = tmp;
- }
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU73_Firmware_Header, mcRegisterTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.mc_reg_table_start = tmp;
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU73_Firmware_Header, FanTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.fan_table_start = tmp;
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.arb_table_start = tmp;
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU73_Firmware_Header, Version),
- &tmp, SMC_RAM_END);
-
- if (!result)
- hwmgr->microcode_version_info.SMC = tmp;
-
- error |= (0 != result);
-
- return error ? -1 : 0;
-}
-
-int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-{
-
- /* Program additional LP registers
- * that are no longer programmed by VBIOS
- */
- cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
- cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
- cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
-
- return 0;
-}
-
-bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
-{
- return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
- ? true : false;
-}
-
-int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request)
-{
- struct fiji_smumgr *smu_data = (struct fiji_smumgr *)
- (hwmgr->smumgr->backend);
- struct SMU73_Discrete_GraphicsLevel *levels =
- smu_data->smc_state_table.GraphicsLevel;
- uint32_t array = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
- uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
- SMU73_MAX_LEVELS_GRAPHICS;
- uint32_t i;
-
- for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
- levels[i].ActivityLevel =
- cpu_to_be16(request->activity_threshold);
- levels[i].EnabledForActivity = 1;
- levels[i].UpHyst = request->up_hyst;
- levels[i].DownHyst = request->down_hyst;
- }
-
- return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
- array_size, SMC_RAM_END);
-}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.h
deleted file mode 100644
index d9c72d9..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef FIJI_SMC_H
-#define FIJI_SMC_H
-
-#include "smumgr.h"
-#include "smu73.h"
-
-struct fiji_pt_defaults {
- uint8_t SviLoadLineEn;
- uint8_t SviLoadLineVddC;
- uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
- uint8_t TDC_MAWt;
- uint8_t TdcWaterfallCtl;
- uint8_t DTEAmbientTempBase;
-};
-
-int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
-int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
-int fiji_init_smc_table(struct pp_hwmgr *hwmgr);
-int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
-int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
-int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr);
-uint32_t fiji_get_offsetof(uint32_t type, uint32_t member);
-uint32_t fiji_get_mac_definition(uint32_t value);
-int fiji_process_firmware_header(struct pp_hwmgr *hwmgr);
-int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
-bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr);
-int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request);
-int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
-#endif
-
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 6ae948f..f572bef 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -23,6 +23,7 @@
#include "pp_debug.h"
#include "smumgr.h"
+#include "smu7_dyn_defaults.h"
#include "smu73.h"
#include "smu_ucode_xfer_vi.h"
#include "fiji_smumgr.h"
@@ -37,14 +38,54 @@
#include "gca/gfx_8_0_d.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
-#include "fiji_pwrvirus.h"
-#include "fiji_smc.h"
+#include "dce/dce_10_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+#include "hardwaremanager.h"
+#include "cgs_common.h"
+#include "atombios.h"
+#include "pppcielanes.h"
+#include "hwmgr.h"
+#include "smu7_hwmgr.h"
+
#define AVFS_EN_MSB 1568
#define AVFS_EN_LSB 1568
#define FIJI_SMC_SIZE 0x20000
+#define VOLTAGE_SCALE 4
+#define POWERTUNE_DEFAULT_SET_MAX 1
+#define VOLTAGE_VID_OFFSET_SCALE1 625
+#define VOLTAGE_VID_OFFSET_SCALE2 100
+#define VDDC_VDDCI_DELTA 300
+#define MC_CG_ARB_FREQ_F1 0x0b
+
+/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
+ * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
+ */
+static const uint16_t fiji_clock_stretcher_lookup_table[2][4] = {
+ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
+
+/* [FF, SS] type, [] 4 voltage ranges, and
+ * [Floor Freq, Boundary Freq, VID min , VID max]
+ */
+static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = {
+ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
+ { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
+
+/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
+ * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
+ */
+static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = {
+ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
+
+static const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
+ /*sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
+ {1, 0xF, 0xFD,
+ /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
+ 0x19, 5, 45}
+};
+
static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
/* Min Sclk pcie DeepSleep Activity CgSpll CgSpll spllSpread SpllSpread CcPwr CcPwr Sclk Display Enabled Enabled Voltage Power */
/* Voltage, Frequency, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, Spectrum, Spectrum2, DynRm, DynRm1 Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
@@ -58,147 +99,114 @@ static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
{ 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 }
};
-static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
+static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* Wait for smc boot up */
- /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
+ /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- result = smu7_upload_smu_firmware_image(smumgr);
+ result = smu7_upload_smu_firmware_image(hwmgr);
if (result)
return result;
/* Clear status */
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_STATUS, 0);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for ROM firmware to initialize interrupt hendler */
- /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
+ /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND,
SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
/* Set SMU Auto Start */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_INPUT_DATA, AUTO_START, 1);
/* Clear firmware interrupt enable flag */
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS,
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
INTERRUPTS_ENABLED, 1);
- cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
- cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
+ cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
+ cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
+ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
/* Wait for done bit to be set */
- SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
SMU_STATUS, SMU_DONE, 0);
/* Check pass/failed indicator */
- if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_STATUS, SMU_PASS) != 1) {
PP_ASSERT_WITH_CODE(false,
"SMU Firmware start failed!", return -1);
}
/* Wait for firmware to initialize */
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
-static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
+static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* wait for smc boot up */
- SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
/* Clear firmware interrupt enable flag */
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
/* Assert reset */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- result = smu7_upload_smu_firmware_image(smumgr);
+ result = smu7_upload_smu_firmware_image(hwmgr);
if (result)
return result;
/* Set smc instruct start point at 0x0 */
- smu7_program_jump_on_start(smumgr);
+ smu7_program_jump_on_start(hwmgr);
/* Enable clock */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
-static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
-{
- int i;
- int result = -EINVAL;
- uint32_t reg, data;
-
- const PWR_Command_Table *pvirus = PwrVirusTable;
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-
- for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
- switch (pvirus->command) {
- case PwrCmdWrite:
- reg = pvirus->reg;
- data = pvirus->data;
- cgs_write_register(smumgr->device, reg, data);
- break;
-
- case PwrCmdEnd:
- result = 0;
- break;
-
- default:
- pr_info("Table Exit with Invalid Command!");
- smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
- result = -EINVAL;
- break;
- }
- pvirus++;
- }
-
- return result;
-}
-
-static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
+static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
{
int result = 0;
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
if (0 != smu_data->avfs.avfs_btc_param) {
- if (0 != smu7_send_msg_to_smc_with_parameter(smumgr,
+ if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
result = -EINVAL;
@@ -206,23 +214,23 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
}
/* Soft-Reset to reset the engine before loading uCode */
/* halt */
- cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
+ cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
/* reset everything */
- cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
+ cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
/* clear reset */
- cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
+ cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
return result;
}
-static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
+static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
{
int32_t vr_config;
uint32_t table_start;
uint32_t level_addr, vr_config_addr;
uint32_t level_size = sizeof(avfs_graphics_level);
- PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, DpmTable),
&table_start, 0x40000),
@@ -237,7 +245,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
vr_config_addr = table_start +
offsetof(SMU73_Discrete_DpmTable, VRConfig);
- PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr,
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
(uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
"[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
"vr_config value over to SMC",
@@ -245,7 +253,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
- PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr,
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
(uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
"[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
return -1;);
@@ -253,9 +261,9 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
return 0;
}
-static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
+static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started)
{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
switch (smu_data->avfs.avfs_btc_status) {
case AVFS_BTC_COMPLETED_PREVIOUSLY:
@@ -265,17 +273,17 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
if (!smu_started)
break;
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
- PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr),
+ PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
" table over to SMU",
return -EINVAL;);
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
- PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr),
+ PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Could not setup "
"Pwr Virus for AVFS ",
return -EINVAL;);
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
- PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr),
+ PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Failure at "
"fiji_start_avfs_btc. AVFS Disabled",
return -EINVAL;);
@@ -293,64 +301,64 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
return 0;
}
-static int fiji_start_smu(struct pp_smumgr *smumgr)
+static int fiji_start_smu(struct pp_hwmgr *hwmgr)
{
int result = 0;
- struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
+ struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
/* Only start SMC if SMC RAM is not running */
- if (!(smu7_is_smc_ram_running(smumgr)
- || cgs_is_virtualization_enabled(smumgr->device))) {
- fiji_avfs_event_mgr(smumgr, false);
+ if (!(smu7_is_smc_ram_running(hwmgr)
+ || cgs_is_virtualization_enabled(hwmgr->device))) {
+ fiji_avfs_event_mgr(hwmgr, false);
/* Check if SMU is running in protected mode */
- if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
+ if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) {
- result = fiji_start_smu_in_non_protection_mode(smumgr);
+ result = fiji_start_smu_in_non_protection_mode(hwmgr);
if (result)
return result;
} else {
- result = fiji_start_smu_in_protection_mode(smumgr);
+ result = fiji_start_smu_in_protection_mode(hwmgr);
if (result)
return result;
}
- fiji_avfs_event_mgr(smumgr, true);
+ fiji_avfs_event_mgr(hwmgr, true);
}
/* To initialize all clock gating before RLC loaded and running.*/
- cgs_set_clockgating_state(smumgr->device,
+ cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
- cgs_set_clockgating_state(smumgr->device,
+ cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
- cgs_set_clockgating_state(smumgr->device,
+ cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
- cgs_set_clockgating_state(smumgr->device,
+ cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
/* Setup SoftRegsStart here for register lookup in case
* DummyBackEnd is used and ProcessFirmwareHeader is not executed
*/
- smu7_read_smc_sram_dword(smumgr,
+ smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, SoftRegisters),
&(priv->smu7_data.soft_regs_start), 0x40000);
- result = smu7_request_smu_load_fw(smumgr);
+ result = smu7_request_smu_load_fw(hwmgr);
return result;
}
-static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
+static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
{
uint32_t efuse = 0;
uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
- if (cgs_is_virtualization_enabled(smumgr->device))
+ if (cgs_is_virtualization_enabled(hwmgr->device))
return 0;
- if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
+ if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
mask, &efuse)) {
if (efuse)
return true;
@@ -358,14 +366,7 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
return false;
}
-/**
-* Write a 32bit value to the SMC SRAM space.
-* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-* @param smumgr the address of the powerplay hardware manager.
-* @param smc_addr the address in the SMC RAM to access.
-* @param value to write to the SMC SRAM.
-*/
-static int fiji_smu_init(struct pp_smumgr *smumgr)
+static int fiji_smu_init(struct pp_hwmgr *hwmgr)
{
int i;
struct fiji_smumgr *fiji_priv = NULL;
@@ -375,9 +376,9 @@ static int fiji_smu_init(struct pp_smumgr *smumgr)
if (fiji_priv == NULL)
return -ENOMEM;
- smumgr->backend = fiji_priv;
+ hwmgr->smu_backend = fiji_priv;
- if (smu7_init(smumgr))
+ if (smu7_init(hwmgr))
return -EINVAL;
for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
@@ -386,6 +387,2334 @@ static int fiji_smu_init(struct pp_smumgr *smumgr)
return 0;
}
+static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
+ uint32_t clock, uint32_t *voltage, uint32_t *mvdd)
+{
+ uint32_t i;
+ uint16_t vddci;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ *voltage = *mvdd = 0;
+
+
+ /* clock - voltage dependency table is empty table */
+ if (dep_table->count == 0)
+ return -EINVAL;
+
+ for (i = 0; i < dep_table->count; i++) {
+ /* find first sclk bigger than request */
+ if (dep_table->entries[i].clk >= clock) {
+ *voltage |= (dep_table->entries[i].vddc *
+ VOLTAGE_SCALE) << VDDC_SHIFT;
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ *voltage |= (data->vbios_boot_state.vddci_bootup_value *
+ VOLTAGE_SCALE) << VDDCI_SHIFT;
+ else if (dep_table->entries[i].vddci)
+ *voltage |= (dep_table->entries[i].vddci *
+ VOLTAGE_SCALE) << VDDCI_SHIFT;
+ else {
+ vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
+ (dep_table->entries[i].vddc -
+ VDDC_VDDCI_DELTA));
+ *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ }
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
+ *mvdd = data->vbios_boot_state.mvdd_bootup_value *
+ VOLTAGE_SCALE;
+ else if (dep_table->entries[i].mvdd)
+ *mvdd = (uint32_t) dep_table->entries[i].mvdd *
+ VOLTAGE_SCALE;
+
+ *voltage |= 1 << PHASES_SHIFT;
+ return 0;
+ }
+ }
+
+ /* sclk is bigger than max sclk in the dependence table */
+ *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ *voltage |= (data->vbios_boot_state.vddci_bootup_value *
+ VOLTAGE_SCALE) << VDDCI_SHIFT;
+ else if (dep_table->entries[i-1].vddci) {
+ vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
+ (dep_table->entries[i].vddc -
+ VDDC_VDDCI_DELTA));
+ *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ }
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
+ *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
+ else if (dep_table->entries[i].mvdd)
+ *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
+
+ return 0;
+}
+
+
+static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
+{
+ uint32_t tmp;
+ tmp = raw_setting * 4096 / 100;
+ return (uint16_t)tmp;
+}
+
+static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)
+{
+ switch (line) {
+ case SMU7_I2CLineID_DDC1:
+ *scl = SMU7_I2C_DDC1CLK;
+ *sda = SMU7_I2C_DDC1DATA;
+ break;
+ case SMU7_I2CLineID_DDC2:
+ *scl = SMU7_I2C_DDC2CLK;
+ *sda = SMU7_I2C_DDC2DATA;
+ break;
+ case SMU7_I2CLineID_DDC3:
+ *scl = SMU7_I2C_DDC3CLK;
+ *sda = SMU7_I2C_DDC3DATA;
+ break;
+ case SMU7_I2CLineID_DDC4:
+ *scl = SMU7_I2C_DDC4CLK;
+ *sda = SMU7_I2C_DDC4DATA;
+ break;
+ case SMU7_I2CLineID_DDC5:
+ *scl = SMU7_I2C_DDC5CLK;
+ *sda = SMU7_I2C_DDC5DATA;
+ break;
+ case SMU7_I2CLineID_DDC6:
+ *scl = SMU7_I2C_DDC6CLK;
+ *sda = SMU7_I2C_DDC6DATA;
+ break;
+ case SMU7_I2CLineID_SCLSDA:
+ *scl = SMU7_I2C_SCL;
+ *sda = SMU7_I2C_SDA;
+ break;
+ case SMU7_I2CLineID_DDCVGA:
+ *scl = SMU7_I2C_DDCVGACLK;
+ *sda = SMU7_I2C_DDCVGADATA;
+ break;
+ default:
+ *scl = 0;
+ *sda = 0;
+ break;
+ }
+}
+
+static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ if (table_info &&
+ table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
+ table_info->cac_dtp_table->usPowerTuneDataSetID)
+ smu_data->power_tune_defaults =
+ &fiji_power_tune_data_set_array
+ [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
+ else
+ smu_data->power_tune_defaults = &fiji_power_tune_data_set_array[0];
+
+}
+
+static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
+{
+
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
+
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
+ struct pp_advance_fan_control_parameters *fan_table =
+ &hwmgr->thermal_controller.advanceFanControlParameters;
+ uint8_t uc_scl, uc_sda;
+
+ /* TDP number of fraction bits are changed from 8 to 7 for Fiji
+ * as requested by SMC team
+ */
+ dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
+ (uint16_t)(cac_dtp_table->usTDP * 128));
+ dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
+ (uint16_t)(cac_dtp_table->usTDP * 128));
+
+ PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
+ "Target Operating Temp is out of Range!",
+ );
+
+ dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
+ dpm_table->GpuTjHyst = 8;
+
+ dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
+
+ /* The following are for new Fiji Multi-input fan/thermal control */
+ dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTargetOperatingTemp * 256);
+ dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitHotspot * 256);
+ dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitLiquid1 * 256);
+ dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitLiquid2 * 256);
+ dpm_table->TemperatureLimitVrVddc = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitVrVddc * 256);
+ dpm_table->TemperatureLimitVrMvdd = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitVrMvdd * 256);
+ dpm_table->TemperatureLimitPlx = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitPlx * 256);
+
+ dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainEdge));
+ dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainHotspot));
+ dpm_table->FanGainLiquid = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainLiquid));
+ dpm_table->FanGainVrVddc = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainVrVddc));
+ dpm_table->FanGainVrMvdd = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainVrMvdd));
+ dpm_table->FanGainPlx = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainPlx));
+ dpm_table->FanGainHbm = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainHbm));
+
+ dpm_table->Liquid1_I2C_address = cac_dtp_table->ucLiquid1_I2C_address;
+ dpm_table->Liquid2_I2C_address = cac_dtp_table->ucLiquid2_I2C_address;
+ dpm_table->Vr_I2C_address = cac_dtp_table->ucVr_I2C_address;
+ dpm_table->Plx_I2C_address = cac_dtp_table->ucPlx_I2C_address;
+
+ get_scl_sda_value(cac_dtp_table->ucLiquid_I2C_Line, &uc_scl, &uc_sda);
+ dpm_table->Liquid_I2C_LineSCL = uc_scl;
+ dpm_table->Liquid_I2C_LineSDA = uc_sda;
+
+ get_scl_sda_value(cac_dtp_table->ucVr_I2C_Line, &uc_scl, &uc_sda);
+ dpm_table->Vr_I2C_LineSCL = uc_scl;
+ dpm_table->Vr_I2C_LineSDA = uc_sda;
+
+ get_scl_sda_value(cac_dtp_table->ucPlx_I2C_Line, &uc_scl, &uc_sda);
+ dpm_table->Plx_I2C_LineSCL = uc_scl;
+ dpm_table->Plx_I2C_LineSDA = uc_sda;
+
+ return 0;
+}
+
+
+static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
+ smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
+ smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
+ smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
+
+ return 0;
+}
+
+
+static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
+{
+ uint16_t tdc_limit;
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ /* TDC number of fraction bits are changed from 8 to 7
+ * for Fiji as requested by SMC team
+ */
+ tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
+ smu_data->power_tune_table.TDC_VDDC_PkgLimit =
+ CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
+ smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
+ defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
+ smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
+
+ return 0;
+}
+
+static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
+ uint32_t temp;
+
+ if (smu7_read_smc_sram_dword(hwmgr,
+ fuse_table_offset +
+ offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
+ (uint32_t *)&temp, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
+ return -EINVAL);
+ else {
+ smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
+ smu_data->power_tune_table.LPMLTemperatureMin =
+ (uint8_t)((temp >> 16) & 0xff);
+ smu_data->power_tune_table.LPMLTemperatureMax =
+ (uint8_t)((temp >> 8) & 0xff);
+ smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
+ }
+ return 0;
+}
+
+static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+
+ /* Currently not used. Set all to zero. */
+ for (i = 0; i < 16; i++)
+ smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
+
+ return 0;
+}
+
+static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+
+ if ((hwmgr->thermal_controller.advanceFanControlParameters.
+ usFanOutputSensitivity & (1 << 15)) ||
+ 0 == hwmgr->thermal_controller.advanceFanControlParameters.
+ usFanOutputSensitivity)
+ hwmgr->thermal_controller.advanceFanControlParameters.
+ usFanOutputSensitivity = hwmgr->thermal_controller.
+ advanceFanControlParameters.usDefaultFanOutputSensitivity;
+
+ smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
+ PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
+ advanceFanControlParameters.usFanOutputSensitivity);
+ return 0;
+}
+
+static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+
+ /* Currently not used. Set all to zero. */
+ for (i = 0; i < 16; i++)
+ smu_data->power_tune_table.GnbLPML[i] = 0;
+
+ return 0;
+}
+
+static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
+ uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
+ struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
+
+ HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
+ LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
+
+ smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
+ smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
+
+ return 0;
+}
+
+static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
+{
+ uint32_t pm_fuse_table_offset;
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment)) {
+ if (smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU73_Firmware_Header, PmFuseTable),
+ &pm_fuse_table_offset, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to get pm_fuse_table_offset Failed!",
+ return -EINVAL);
+
+ /* DW6 */
+ if (fiji_populate_svi_load_line(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate SviLoadLine Failed!",
+ return -EINVAL);
+ /* DW7 */
+ if (fiji_populate_tdc_limit(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TDCLimit Failed!", return -EINVAL);
+ /* DW8 */
+ if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TdcWaterfallCtl, "
+ "LPMLTemperature Min and Max Failed!",
+ return -EINVAL);
+
+ /* DW9-DW12 */
+ if (0 != fiji_populate_temperature_scaler(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate LPMLTemperatureScaler Failed!",
+ return -EINVAL);
+
+ /* DW13-DW14 */
+ if (fiji_populate_fuzzy_fan(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate Fuzzy Fan Control parameters Failed!",
+ return -EINVAL);
+
+ /* DW15-DW18 */
+ if (fiji_populate_gnb_lpml(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate GnbLPML Failed!",
+ return -EINVAL);
+
+ /* DW20 */
+ if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
+ "Sidd Failed!", return -EINVAL);
+
+ if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
+ (uint8_t *)&smu_data->power_tune_table,
+ sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to download PmFuseTable Failed!",
+ return -EINVAL);
+ }
+ return 0;
+}
+
+static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_DpmTable *table)
+{
+ uint32_t count;
+ uint8_t index;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_voltage_lookup_table *lookup_table =
+ table_info->vddc_lookup_table;
+ /* tables is already swapped, so in order to use the value from it,
+ * we need to swap it back.
+ * We are populating vddc CAC data to BapmVddc table
+ * in split and merged mode
+ */
+
+ for (count = 0; count < lookup_table->count; count++) {
+ index = phm_get_voltage_index(lookup_table,
+ data->vddc_voltage_table.entries[count].value);
+ table->BapmVddcVidLoSidd[count] =
+ convert_to_vid(lookup_table->entries[index].us_cac_low);
+ table->BapmVddcVidHiSidd[count] =
+ convert_to_vid(lookup_table->entries[index].us_cac_high);
+ }
+
+ return 0;
+}
+
+static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_DpmTable *table)
+{
+ int result;
+
+ result = fiji_populate_cac_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "can not populate CAC voltage tables to SMC",
+ return -EINVAL);
+
+ return 0;
+}
+
+static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_Ulv *state)
+{
+ int result = 0;
+
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ state->CcPwrDynRm = 0;
+ state->CcPwrDynRm1 = 0;
+
+ state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
+ state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
+ VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
+
+ state->VddcPhase = 1;
+
+ if (!result) {
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
+ CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
+ }
+ return result;
+}
+
+static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_DpmTable *table)
+{
+ return fiji_populate_ulv_level(hwmgr, &table->Ulv);
+}
+
+static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ int i;
+
+ /* Index (dpm_table->pcie_speed_table.count)
+ * is reserved for PCIE boot level. */
+ for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
+ table->LinkLevel[i].PcieGenSpeed =
+ (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
+ table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
+ dpm_table->pcie_speed_table.dpm_levels[i].param1);
+ table->LinkLevel[i].EnabledForActivity = 1;
+ table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
+ table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
+ table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
+ }
+
+ smu_data->smc_state_table.LinkLevelCount =
+ (uint8_t)dpm_table->pcie_speed_table.count;
+ data->dpm_level_enable_mask.pcie_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
+
+ return 0;
+}
+
+static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
+ uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ uint32_t ref_clock;
+ uint32_t ref_divider;
+ uint32_t fbdiv;
+ int result;
+
+ /* get the engine clock dividers for this clock value */
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.",
+ return result);
+
+ /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
+ ref_clock = atomctrl_get_reference_clock(hwmgr);
+ ref_divider = 1 + dividers.uc_pll_ref_div;
+
+ /* low 14 bits is fraction and high 12 bits is divider */
+ fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
+
+ /* SPLL_FUNC_CNTL setup */
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_REF_DIV, dividers.uc_pll_ref_div);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_PDIV_A, dividers.uc_pll_post_div);
+
+ /* SPLL_FUNC_CNTL_3 setup*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
+ SPLL_FB_DIV, fbdiv);
+
+ /* set to use fractional accumulation*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
+ SPLL_DITHEN, 1);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
+ struct pp_atomctrl_internal_ss_info ssInfo;
+
+ uint32_t vco_freq = clock * dividers.uc_pll_post_div;
+ if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
+ vco_freq, &ssInfo)) {
+ /*
+ * ss_info.speed_spectrum_percentage -- in unit of 0.01%
+ * ss_info.speed_spectrum_rate -- in unit of khz
+ *
+ * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
+ */
+ uint32_t clk_s = ref_clock * 5 /
+ (ref_divider * ssInfo.speed_spectrum_rate);
+ /* clkv = 2 * D * fbdiv / NS */
+ uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
+ fbdiv / (clk_s * 10000);
+
+ cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
+ CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
+ cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
+ CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
+ cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
+ CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
+ }
+ }
+
+ sclk->SclkFrequency = clock;
+ sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
+ sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
+ sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
+ sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
+ sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
+
+ return 0;
+}
+
+static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ uint32_t clock, uint16_t sclk_al_threshold,
+ struct SMU73_Discrete_GraphicsLevel *level)
+{
+ int result;
+ /* PP_Clocks minClocks; */
+ uint32_t threshold, mvdd;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ result = fiji_calculate_sclk_params(hwmgr, clock, level);
+
+ /* populate graphics levels */
+ result = fiji_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_sclk, clock,
+ (uint32_t *)(&level->MinVoltage), &mvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find VDDC voltage value for "
+ "VDDC engine clock dependency table",
+ return result);
+
+ level->SclkFrequency = clock;
+ level->ActivityLevel = sclk_al_threshold;
+ level->CcPwrDynRm = 0;
+ level->CcPwrDynRm1 = 0;
+ level->EnabledForActivity = 0;
+ level->EnabledForThrottle = 1;
+ level->UpHyst = 10;
+ level->DownHyst = 0;
+ level->VoltageDownHyst = 0;
+ level->PowerThrottle = 0;
+
+ threshold = clock * data->fast_watermark_threshold / 100;
+
+ data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
+ level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
+ hwmgr->display_config.min_core_set_clock_in_sr);
+
+
+ /* Default to slow, highest DPM level will be
+ * set to PPSMC_DISPLAY_WATERMARK_LOW later.
+ */
+ level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
+
+ return 0;
+}
+
+static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
+ uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
+ int result = 0;
+ uint32_t array = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
+ uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
+ SMU73_MAX_LEVELS_GRAPHICS;
+ struct SMU73_Discrete_GraphicsLevel *levels =
+ smu_data->smc_state_table.GraphicsLevel;
+ uint32_t i, max_entry;
+ uint8_t hightest_pcie_level_enabled = 0,
+ lowest_pcie_level_enabled = 0,
+ mid_pcie_level_enabled = 0,
+ count = 0;
+
+ for (i = 0; i < dpm_table->sclk_table.count; i++) {
+ result = fiji_populate_single_graphic_level(hwmgr,
+ dpm_table->sclk_table.dpm_levels[i].value,
+ (uint16_t)smu_data->activity_target[i],
+ &levels[i]);
+ if (result)
+ return result;
+
+ /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
+ if (i > 1)
+ levels[i].DeepSleepDivId = 0;
+ }
+
+ /* Only enable level 0 for now.*/
+ levels[0].EnabledForActivity = 1;
+
+ /* set highest level watermark to high */
+ levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
+ PPSMC_DISPLAY_WATERMARK_HIGH;
+
+ smu_data->smc_state_table.GraphicsDpmLevelCount =
+ (uint8_t)dpm_table->sclk_table.count;
+ data->dpm_level_enable_mask.sclk_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
+
+ if (pcie_table != NULL) {
+ PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
+ "There must be 1 or more PCIE levels defined in PPTable.",
+ return -EINVAL);
+ max_entry = pcie_entry_cnt - 1;
+ for (i = 0; i < dpm_table->sclk_table.count; i++)
+ levels[i].pcieDpmLevel =
+ (uint8_t) ((i < max_entry) ? i : max_entry);
+ } else {
+ while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
+ ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << (hightest_pcie_level_enabled + 1))) != 0))
+ hightest_pcie_level_enabled++;
+
+ while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
+ ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << lowest_pcie_level_enabled)) == 0))
+ lowest_pcie_level_enabled++;
+
+ while ((count < hightest_pcie_level_enabled) &&
+ ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
+ count++;
+
+ mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
+ hightest_pcie_level_enabled ?
+ (lowest_pcie_level_enabled + 1 + count) :
+ hightest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to hightest_pcie_level_enabled */
+ for (i = 2; i < dpm_table->sclk_table.count; i++)
+ levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to lowest_pcie_level_enabled */
+ levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to mid_pcie_level_enabled */
+ levels[1].pcieDpmLevel = mid_pcie_level_enabled;
+ }
+ /* level count will send to smc once at init smc table and never change */
+ result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ (uint32_t)array_size, SMC_RAM_END);
+
+ return result;
+}
+
+
+/**
+ * MCLK Frequency Ratio
+ * SEQ_CG_RESP Bit[31:24] - 0x0
+ * Bit[27:24] \96 DDR3 Frequency ratio
+ * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
+ * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
+ * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
+ * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
+ * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
+ * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
+ * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
+ * 400 < 0x7 <= 450MHz, 800 < 0xF
+ */
+static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
+{
+ if (mem_clock <= 10000)
+ return 0x0;
+ if (mem_clock <= 15000)
+ return 0x1;
+ if (mem_clock <= 20000)
+ return 0x2;
+ if (mem_clock <= 25000)
+ return 0x3;
+ if (mem_clock <= 30000)
+ return 0x4;
+ if (mem_clock <= 35000)
+ return 0x5;
+ if (mem_clock <= 40000)
+ return 0x6;
+ if (mem_clock <= 45000)
+ return 0x7;
+ if (mem_clock <= 50000)
+ return 0x8;
+ if (mem_clock <= 55000)
+ return 0x9;
+ if (mem_clock <= 60000)
+ return 0xa;
+ if (mem_clock <= 65000)
+ return 0xb;
+ if (mem_clock <= 70000)
+ return 0xc;
+ if (mem_clock <= 75000)
+ return 0xd;
+ if (mem_clock <= 80000)
+ return 0xe;
+ /* mem_clock > 800MHz */
+ return 0xf;
+}
+
+static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
+ uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
+{
+ struct pp_atomctrl_memory_clock_param mem_param;
+ int result;
+
+ result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Failed to get Memory PLL Dividers.",
+ );
+
+ /* Save the result data to outpupt memory level structure */
+ mclk->MclkFrequency = clock;
+ mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;
+ mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);
+
+ return result;
+}
+
+static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
+ uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ int result = 0;
+ uint32_t mclk_stutter_mode_threshold = 60000;
+
+ if (table_info->vdd_dep_on_mclk) {
+ result = fiji_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_mclk, clock,
+ (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find MinVddc voltage value from memory "
+ "VDDC voltage dependency table", return result);
+ }
+
+ mem_level->EnabledForThrottle = 1;
+ mem_level->EnabledForActivity = 0;
+ mem_level->UpHyst = 0;
+ mem_level->DownHyst = 100;
+ mem_level->VoltageDownHyst = 0;
+ mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+ mem_level->StutterEnable = false;
+
+ mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ /* enable stutter mode if all the follow condition applied
+ * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
+ * &(data->DisplayTiming.numExistingDisplays));
+ */
+ data->display_timing.num_existing_displays = 1;
+
+ if (mclk_stutter_mode_threshold &&
+ (clock <= mclk_stutter_mode_threshold) &&
+ (!data->is_uvd_enabled) &&
+ (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
+ STUTTER_ENABLE) & 0x1))
+ mem_level->StutterEnable = true;
+
+ result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
+ if (!result) {
+ CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
+ CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
+ }
+ return result;
+}
+
+static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ int result;
+ /* populate MCLK dpm table to SMU7 */
+ uint32_t array = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
+ uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
+ SMU73_MAX_LEVELS_MEMORY;
+ struct SMU73_Discrete_MemoryLevel *levels =
+ smu_data->smc_state_table.MemoryLevel;
+ uint32_t i;
+
+ for (i = 0; i < dpm_table->mclk_table.count; i++) {
+ PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
+ "can not populate memory level as memory clock is zero",
+ return -EINVAL);
+ result = fiji_populate_single_memory_level(hwmgr,
+ dpm_table->mclk_table.dpm_levels[i].value,
+ &levels[i]);
+ if (result)
+ return result;
+ }
+
+ /* Only enable level 0 for now. */
+ levels[0].EnabledForActivity = 1;
+
+ /* in order to prevent MC activity from stutter mode to push DPM up.
+ * the UVD change complements this by putting the MCLK in
+ * a higher state by default such that we are not effected by
+ * up threshold or and MCLK DPM latency.
+ */
+ levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
+ CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
+
+ smu_data->smc_state_table.MemoryDpmLevelCount =
+ (uint8_t)dpm_table->mclk_table.count;
+ data->dpm_level_enable_mask.mclk_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
+ /* set highest level watermark to high */
+ levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
+ PPSMC_DISPLAY_WATERMARK_HIGH;
+
+ /* level count will send to smc once at init smc table and never change */
+ result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ (uint32_t)array_size, SMC_RAM_END);
+
+ return result;
+}
+
+static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
+ uint32_t mclk, SMIO_Pattern *smio_pat)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint32_t i = 0;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
+ /* find mvdd value which clock is more than request */
+ for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
+ if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
+ smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
+ break;
+ }
+ }
+ PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
+ "MVDD Voltage is outside the supported range.",
+ return -EINVAL);
+ } else
+ return -EINVAL;
+
+ return 0;
+}
+
+static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ SMU73_Discrete_DpmTable *table)
+{
+ int result = 0;
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ SMIO_Pattern vol_level;
+ uint32_t mvdd;
+ uint16_t us_mvdd;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
+
+ table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
+
+ if (!data->sclk_dpm_key_disabled) {
+ /* Get MinVoltage and Frequency from DPM0,
+ * already converted to SMC_UL */
+ table->ACPILevel.SclkFrequency =
+ data->dpm_table.sclk_table.dpm_levels[0].value;
+ result = fiji_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_sclk,
+ table->ACPILevel.SclkFrequency,
+ (uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Cannot find ACPI VDDC voltage value " \
+ "in Clock Dependency Table",
+ );
+ } else {
+ table->ACPILevel.SclkFrequency =
+ data->vbios_boot_state.sclk_bootup_value;
+ table->ACPILevel.MinVoltage =
+ data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
+ }
+
+ /* get the engine clock dividers for this clock value */
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
+ table->ACPILevel.SclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.",
+ return result);
+
+ table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
+ table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+ table->ACPILevel.DeepSleepDivId = 0;
+
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_PWRON, 0);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_RESET, 1);
+ spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
+ SCLK_MUX_SEL, 4);
+
+ table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
+ table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
+ table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ table->ACPILevel.CcPwrDynRm = 0;
+ table->ACPILevel.CcPwrDynRm1 = 0;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
+
+ if (!data->mclk_dpm_key_disabled) {
+ /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
+ table->MemoryACPILevel.MclkFrequency =
+ data->dpm_table.mclk_table.dpm_levels[0].value;
+ result = fiji_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_mclk,
+ table->MemoryACPILevel.MclkFrequency,
+ (uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Cannot find ACPI VDDCI voltage value in Clock Dependency Table",
+ );
+ } else {
+ table->MemoryACPILevel.MclkFrequency =
+ data->vbios_boot_state.mclk_bootup_value;
+ table->MemoryACPILevel.MinVoltage =
+ data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
+ }
+
+ us_mvdd = 0;
+ if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
+ (data->mclk_dpm_key_disabled))
+ us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
+ else {
+ if (!fiji_populate_mvdd_value(hwmgr,
+ data->dpm_table.mclk_table.dpm_levels[0].value,
+ &vol_level))
+ us_mvdd = vol_level.Voltage;
+ }
+
+ table->MemoryACPILevel.MinMvdd =
+ PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
+
+ table->MemoryACPILevel.EnabledForThrottle = 0;
+ table->MemoryACPILevel.EnabledForActivity = 0;
+ table->MemoryACPILevel.UpHyst = 0;
+ table->MemoryACPILevel.DownHyst = 100;
+ table->MemoryACPILevel.VoltageDownHyst = 0;
+ table->MemoryACPILevel.ActivityLevel =
+ PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+
+ table->MemoryACPILevel.StutterEnable = false;
+ CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
+
+ return result;
+}
+
+static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
+ SMU73_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ table_info->mm_dep_table;
+
+ table->VceLevelCount = (uint8_t)(mm_table->count);
+ table->VceBootLevel = 0;
+
+ for (count = 0; count < table->VceLevelCount; count++) {
+ table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
+ table->VceLevel[count].MinVoltage = 0;
+ table->VceLevel[count].MinVoltage |=
+ (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
+ table->VceLevel[count].MinVoltage |=
+ ((mm_table->entries[count].vddc - VDDC_VDDCI_DELTA) *
+ VOLTAGE_SCALE) << VDDCI_SHIFT;
+ table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+ /*retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->VceLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for VCE engine clock",
+ return result);
+
+ table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
+ SMU73_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ table_info->mm_dep_table;
+
+ table->AcpLevelCount = (uint8_t)(mm_table->count);
+ table->AcpBootLevel = 0;
+
+ for (count = 0; count < table->AcpLevelCount; count++) {
+ table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
+ table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
+ VOLTAGE_SCALE) << VDDC_SHIFT;
+ table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
+ VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->AcpLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for engine clock", return result);
+
+ table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
+ SMU73_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ table_info->mm_dep_table;
+
+ table->SamuBootLevel = 0;
+ table->SamuLevelCount = (uint8_t)(mm_table->count);
+
+ for (count = 0; count < table->SamuLevelCount; count++) {
+ /* not sure whether we need evclk or not */
+ table->SamuLevel[count].MinVoltage = 0;
+ table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
+ table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
+ VOLTAGE_SCALE) << VDDC_SHIFT;
+ table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
+ VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->SamuLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for samu clock", return result);
+
+ table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
+ int32_t eng_clock, int32_t mem_clock,
+ struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
+{
+ uint32_t dram_timing;
+ uint32_t dram_timing2;
+ uint32_t burstTime;
+ ULONG state, trrds, trrdl;
+ int result;
+
+ result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
+ eng_clock, mem_clock);
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error calling VBIOS to set DRAM_TIMING.", return result);
+
+ dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
+ dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
+ burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
+
+ state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
+ trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
+ trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
+
+ arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
+ arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
+ arb_regs->McArbBurstTime = (uint8_t)burstTime;
+ arb_regs->TRRDS = (uint8_t)trrds;
+ arb_regs->TRRDL = (uint8_t)trrdl;
+
+ return 0;
+}
+
+static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
+ uint32_t i, j;
+ int result = 0;
+
+ for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
+ for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
+ result = fiji_populate_memory_timing_parameters(hwmgr,
+ data->dpm_table.sclk_table.dpm_levels[i].value,
+ data->dpm_table.mclk_table.dpm_levels[j].value,
+ &arb_regs.entries[i][j]);
+ if (result)
+ break;
+ }
+ }
+
+ if (!result)
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.arb_table_start,
+ (uint8_t *)&arb_regs,
+ sizeof(SMU73_Discrete_MCArbDramTimingTable),
+ SMC_RAM_END);
+ return result;
+}
+
+static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ table_info->mm_dep_table;
+
+ table->UvdLevelCount = (uint8_t)(mm_table->count);
+ table->UvdBootLevel = 0;
+
+ for (count = 0; count < table->UvdLevelCount; count++) {
+ table->UvdLevel[count].MinVoltage = 0;
+ table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
+ table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
+ table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
+ VOLTAGE_SCALE) << VDDC_SHIFT;
+ table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
+ VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->UvdLevel[count].VclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for Vclk clock", return result);
+
+ table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
+
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->UvdLevel[count].DclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for Dclk clock", return result);
+
+ table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
+
+ }
+ return result;
+}
+
+static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_DpmTable *table)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ table->GraphicsBootLevel = 0;
+ table->MemoryBootLevel = 0;
+
+ /* find boot level from dpm table */
+ result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+ data->vbios_boot_state.sclk_bootup_value,
+ (uint32_t *)&(table->GraphicsBootLevel));
+
+ result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+ data->vbios_boot_state.mclk_bootup_value,
+ (uint32_t *)&(table->MemoryBootLevel));
+
+ table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
+ VOLTAGE_SCALE;
+ table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
+ VOLTAGE_SCALE;
+ table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
+ VOLTAGE_SCALE;
+
+ CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
+ CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
+ CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
+
+ return 0;
+}
+
+static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint8_t count, level;
+
+ count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
+ for (level = 0; level < count; level++) {
+ if (table_info->vdd_dep_on_sclk->entries[level].clk >=
+ data->vbios_boot_state.sclk_bootup_value) {
+ smu_data->smc_state_table.GraphicsBootLevel = level;
+ break;
+ }
+ }
+
+ count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
+ for (level = 0; level < count; level++) {
+ if (table_info->vdd_dep_on_mclk->entries[level].clk >=
+ data->vbios_boot_state.mclk_bootup_value) {
+ smu_data->smc_state_table.MemoryBootLevel = level;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+{
+ uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
+ volt_with_cks, value;
+ uint16_t clock_freq_u16;
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
+ volt_offset = 0;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+ table_info->vdd_dep_on_sclk;
+
+ stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
+
+ /* Read SMU_Eefuse to read and calculate RO and determine
+ * if the part is SS or FF. if RO >= 1660MHz, part is FF.
+ */
+ efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixSMU_EFUSE_0 + (146 * 4));
+ efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixSMU_EFUSE_0 + (148 * 4));
+ efuse &= 0xFF000000;
+ efuse = efuse >> 24;
+ efuse2 &= 0xF;
+
+ if (efuse2 == 1)
+ ro = (2300 - 1350) * efuse / 255 + 1350;
+ else
+ ro = (2500 - 1000) * efuse / 255 + 1000;
+
+ if (ro >= 1660)
+ type = 0;
+ else
+ type = 1;
+
+ /* Populate Stretch amount */
+ smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
+
+ /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
+ for (i = 0; i < sclk_table->count; i++) {
+ smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
+ sclk_table->entries[i].cks_enable << i;
+ volt_without_cks = (uint32_t)((14041 *
+ (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
+ (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
+ volt_with_cks = (uint32_t)((13946 *
+ (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
+ (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
+ if (volt_without_cks >= volt_with_cks)
+ volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
+ sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
+ smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
+ }
+
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ STRETCH_ENABLE, 0x0);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ masterReset, 0x1);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ staticEnable, 0x1);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ masterReset, 0x0);
+
+ /* Populate CKS Lookup Table */
+ if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
+ stretch_amount2 = 0;
+ else if (stretch_amount == 3 || stretch_amount == 4)
+ stretch_amount2 = 1;
+ else {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ClockStretcher);
+ PP_ASSERT_WITH_CODE(false,
+ "Stretch Amount in PPTable not supported\n",
+ return -EINVAL);
+ }
+
+ value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixPWR_CKS_CNTL);
+ value &= 0xFFC2FF87;
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
+ fiji_clock_stretcher_lookup_table[stretch_amount2][0];
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
+ fiji_clock_stretcher_lookup_table[stretch_amount2][1];
+ clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
+ GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
+ SclkFrequency) / 100);
+ if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
+ clock_freq_u16 &&
+ fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
+ clock_freq_u16) {
+ /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
+ value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
+ /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
+ value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
+ /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
+ value |= (fiji_clock_stretch_amount_conversion
+ [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
+ [stretch_amount]) << 3;
+ }
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
+ CKS_LOOKUPTableEntry[0].minFreq);
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
+ CKS_LOOKUPTableEntry[0].maxFreq);
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
+ fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
+ (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixPWR_CKS_CNTL, value);
+
+ /* Populate DDT Lookup Table */
+ for (i = 0; i < 4; i++) {
+ /* Assign the minimum and maximum VID stored
+ * in the last row of Clock Stretcher Voltage Table.
+ */
+ smu_data->smc_state_table.ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].minVID =
+ (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
+ smu_data->smc_state_table.ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].maxVID =
+ (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
+ /* Loop through each SCLK and check the frequency
+ * to see if it lies within the frequency for clock stretcher.
+ */
+ for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
+ cks_setting = 0;
+ clock_freq = PP_SMC_TO_HOST_UL(
+ smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
+ /* Check the allowed frequency against the sclk level[j].
+ * Sclk's endianness has already been converted,
+ * and it's in 10Khz unit,
+ * as opposed to Data table, which is in Mhz unit.
+ */
+ if (clock_freq >=
+ (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
+ cks_setting |= 0x2;
+ if (clock_freq <
+ (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
+ cks_setting |= 0x1;
+ }
+ smu_data->smc_state_table.ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
+ }
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
+ ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].setting);
+ }
+
+ value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
+ value &= 0xFFFFFFFE;
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
+
+ return 0;
+}
+
+static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
+ struct SMU73_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint16_t config;
+
+ config = VR_MERGED_WITH_VDDC;
+ table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
+
+ /* Set Vddc Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
+ config = VR_SVI2_PLANE_1;
+ table->VRConfig |= config;
+ } else {
+ PP_ASSERT_WITH_CODE(false,
+ "VDDC should be on SVI2 control in merged mode!",
+ );
+ }
+ /* Set Vddci Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
+ config = VR_SVI2_PLANE_2; /* only in merged mode */
+ table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
+ } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ config = VR_SMIO_PATTERN_1;
+ table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
+ } else {
+ config = VR_STATIC_VOLTAGE;
+ table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
+ }
+ /* Set Mvdd Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
+ config = VR_SVI2_PLANE_2;
+ table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+ } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+ config = VR_SMIO_PATTERN_2;
+ table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+ } else {
+ config = VR_STATIC_VOLTAGE;
+ table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+ }
+
+ return 0;
+}
+
+static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ uint32_t tmp;
+ int result;
+
+ /* This is a read-modify-write on the first byte of the ARB table.
+ * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
+ * is the field 'current'.
+ * This solution is ugly, but we never write the whole table only
+ * individual fields in it.
+ * In reality this field should not be in that structure
+ * but in a soft register.
+ */
+ result = smu7_read_smc_sram_dword(hwmgr,
+ smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
+
+ if (result)
+ return result;
+
+ tmp &= 0x00FFFFFF;
+ tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
+
+ return smu7_write_smc_sram_dword(hwmgr,
+ smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
+}
+
+static int fiji_save_default_power_profile(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct SMU73_Discrete_GraphicsLevel *levels =
+ data->smc_state_table.GraphicsLevel;
+ unsigned min_level = 1;
+
+ hwmgr->default_gfx_power_profile.activity_threshold =
+ be16_to_cpu(levels[0].ActivityLevel);
+ hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
+ hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
+ hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
+
+ hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
+ hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
+
+ /* Workaround compute SDMA instability: disable lowest SCLK
+ * DPM level. Optimize compute power profile: Use only highest
+ * 2 power levels (if more than 2 are available), Hysteresis:
+ * 0ms up, 5ms down
+ */
+ if (data->smc_state_table.GraphicsDpmLevelCount > 2)
+ min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
+ else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
+ min_level = 1;
+ else
+ min_level = 0;
+ hwmgr->default_compute_power_profile.min_sclk =
+ be32_to_cpu(levels[min_level].SclkFrequency);
+ hwmgr->default_compute_power_profile.up_hyst = 0;
+ hwmgr->default_compute_power_profile.down_hyst = 5;
+
+ hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
+ hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
+
+ return 0;
+}
+
+static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
+{
+ pp_atomctrl_voltage_table param_led_dpm;
+ int result = 0;
+ u32 mask = 0;
+
+ result = atomctrl_get_voltage_table_v3(hwmgr,
+ VOLTAGE_TYPE_LEDDPM, VOLTAGE_OBJ_GPIO_LUT,
+ ¶m_led_dpm);
+ if (result == 0) {
+ int i, j;
+ u32 tmp = param_led_dpm.mask_low;
+
+ for (i = 0, j = 0; i < 32; i++) {
+ if (tmp & 1) {
+ mask |= (i << (8 * j));
+ if (++j >= 3)
+ break;
+ }
+ tmp >>= 1;
+ }
+ }
+ if (mask)
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_LedConfig,
+ mask);
+ return 0;
+}
+
+static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ uint8_t i;
+ struct pp_atomctrl_gpio_pin_assignment gpio_pin;
+
+ fiji_initialize_power_tune_defaults(hwmgr);
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
+ fiji_populate_smc_voltage_tables(hwmgr, table);
+
+ table->SystemFlags = 0;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StepVddc))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
+
+ if (data->is_memory_gddr5)
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
+
+ if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
+ result = fiji_populate_ulv_state(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ULV state!", return result);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_ULV_PARAMETER, 0x40035);
+ }
+
+ result = fiji_populate_smc_link_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Link Level!", return result);
+
+ result = fiji_populate_all_graphic_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Graphics Level!", return result);
+
+ result = fiji_populate_all_memory_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Memory Level!", return result);
+
+ result = fiji_populate_smc_acpi_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ACPI Level!", return result);
+
+ result = fiji_populate_smc_vce_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize VCE Level!", return result);
+
+ result = fiji_populate_smc_acp_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ACP Level!", return result);
+
+ result = fiji_populate_smc_samu_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize SAMU Level!", return result);
+
+ /* Since only the initial state is completely set up at this point
+ * (the other states are just copies of the boot state) we only
+ * need to populate the ARB settings for the initial state.
+ */
+ result = fiji_program_memory_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to Write ARB settings for the initial state.", return result);
+
+ result = fiji_populate_smc_uvd_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize UVD Level!", return result);
+
+ result = fiji_populate_smc_boot_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Boot Level!", return result);
+
+ result = fiji_populate_smc_initailial_state(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Boot State!", return result);
+
+ result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate BAPM Parameters!", return result);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ClockStretcher)) {
+ result = fiji_populate_clock_stretcher_data_table(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate Clock Stretcher Data Table!",
+ return result);
+ }
+
+ table->GraphicsVoltageChangeEnable = 1;
+ table->GraphicsThermThrottleEnable = 1;
+ table->GraphicsInterval = 1;
+ table->VoltageInterval = 1;
+ table->ThermalInterval = 1;
+ table->TemperatureLimitHigh =
+ table_info->cac_dtp_table->usTargetOperatingTemp *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT;
+ table->TemperatureLimitLow =
+ (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT;
+ table->MemoryVoltageChangeEnable = 1;
+ table->MemoryInterval = 1;
+ table->VoltageResponseTime = 0;
+ table->PhaseResponseTime = 0;
+ table->MemoryThermThrottleEnable = 1;
+ table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
+ table->PCIeGenInterval = 1;
+ table->VRConfig = 0;
+
+ result = fiji_populate_vr_config(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate VRConfig setting!", return result);
+
+ table->ThermGpio = 17;
+ table->SclkStepSize = 0x4000;
+
+ if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
+ table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+ } else {
+ table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+ }
+
+ if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
+ &gpio_pin)) {
+ table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+ } else {
+ table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+ }
+
+ /* Thermal Output GPIO */
+ if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
+ &gpio_pin)) {
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ThermalOutGPIO);
+
+ table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
+
+ /* For porlarity read GPIOPAD_A with assigned Gpio pin
+ * since VBIOS will program this register to set 'inactive state',
+ * driver can then determine 'active state' from this and
+ * program SMU with correct polarity
+ */
+ table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
+ (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
+
+ /* if required, combine VRHot/PCC with thermal out GPIO */
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot) &&
+ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_CombinePCCWithThermalSignal))
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
+ } else {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ThermalOutGPIO);
+ table->ThermOutGpio = 17;
+ table->ThermOutPolarity = 1;
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
+ }
+
+ for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
+ table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
+ CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
+ CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
+
+ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
+ result = smu7_copy_bytes_to_smc(hwmgr,
+ smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU73_Discrete_DpmTable, SystemFlags),
+ (uint8_t *)&(table->SystemFlags),
+ sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
+ SMC_RAM_END);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to upload dpm data to SMC memory!", return result);
+
+ result = fiji_init_arb_table_index(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to upload arb data to SMC memory!", return result);
+
+ result = fiji_populate_pm_fuses(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate PM fuses to SMC memory!", return result);
+
+ result = fiji_setup_dpm_led_config(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to setup dpm led config", return result);
+
+ fiji_save_default_power_profile(hwmgr);
+
+ return 0;
+}
+
+static int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+
+ SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
+ uint32_t duty100;
+ uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
+ uint16_t fdo_min, slope1, slope2;
+ uint32_t reference_clock;
+ int res;
+ uint64_t tmp64;
+
+ if (hwmgr->thermal_controller.fanInfo.bNoFan) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ if (smu_data->smu7_data.fan_table_start == 0) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+ CG_FDO_CTRL1, FMAX_DUTY100);
+
+ if (duty100 == 0) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
+ usPWMMin * duty100;
+ do_div(tmp64, 10000);
+ fdo_min = (uint16_t)tmp64;
+
+ t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
+ hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
+ t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
+ hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
+
+ pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
+ hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
+ pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
+ hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
+
+ slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
+ slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
+
+ fan_table.TempMin = cpu_to_be16((50 + hwmgr->
+ thermal_controller.advanceFanControlParameters.usTMin) / 100);
+ fan_table.TempMed = cpu_to_be16((50 + hwmgr->
+ thermal_controller.advanceFanControlParameters.usTMed) / 100);
+ fan_table.TempMax = cpu_to_be16((50 + hwmgr->
+ thermal_controller.advanceFanControlParameters.usTMax) / 100);
+
+ fan_table.Slope1 = cpu_to_be16(slope1);
+ fan_table.Slope2 = cpu_to_be16(slope2);
+
+ fan_table.FdoMin = cpu_to_be16(fdo_min);
+
+ fan_table.HystDown = cpu_to_be16(hwmgr->
+ thermal_controller.advanceFanControlParameters.ucTHyst);
+
+ fan_table.HystUp = cpu_to_be16(1);
+
+ fan_table.HystSlope = cpu_to_be16(1);
+
+ fan_table.TempRespLim = cpu_to_be16(5);
+
+ reference_clock = smu7_get_xclk(hwmgr);
+
+ fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
+ thermal_controller.advanceFanControlParameters.ulCycleDelay *
+ reference_clock) / 1600);
+
+ fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
+
+ fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
+ hwmgr->device, CGS_IND_REG__SMC,
+ CG_MULT_THERMAL_CTRL, TEMP_SEL);
+
+ res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
+ (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
+ SMC_RAM_END);
+
+ if (!res && hwmgr->thermal_controller.
+ advanceFanControlParameters.ucMinimumPWMLimit)
+ res = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetFanMinPwm,
+ hwmgr->thermal_controller.
+ advanceFanControlParameters.ucMinimumPWMLimit);
+
+ if (!res && hwmgr->thermal_controller.
+ advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
+ res = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetFanSclkTarget,
+ hwmgr->thermal_controller.
+ advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
+
+ if (res)
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+
+ return 0;
+}
+
+
+static int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
+{
+ int ret;
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+ if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
+ return 0;
+
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
+
+ if (!ret)
+ /* If this param is not changed, this function could fire unnecessarily */
+ smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
+
+ return ret;
+}
+
+static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (data->need_update_smu7_dpm_table &
+ (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
+ return fiji_program_memory_timing_parameters(hwmgr);
+
+ return 0;
+}
+
+static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+
+ int result = 0;
+ uint32_t low_sclk_interrupt_threshold = 0;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkThrottleLowNotification)
+ && (hwmgr->gfx_arbiter.sclk_threshold !=
+ data->low_sclk_interrupt_threshold)) {
+ data->low_sclk_interrupt_threshold =
+ hwmgr->gfx_arbiter.sclk_threshold;
+ low_sclk_interrupt_threshold =
+ data->low_sclk_interrupt_threshold;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
+
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU73_Discrete_DpmTable,
+ LowSclkInterruptThreshold),
+ (uint8_t *)&low_sclk_interrupt_threshold,
+ sizeof(uint32_t),
+ SMC_RAM_END);
+ }
+ result = fiji_program_mem_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE((result == 0),
+ "Failed to program memory timing parameters!",
+ );
+ return result;
+}
+
+static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
+{
+ switch (type) {
+ case SMU_SoftRegisters:
+ switch (member) {
+ case HandshakeDisables:
+ return offsetof(SMU73_SoftRegisters, HandshakeDisables);
+ case VoltageChangeTimeout:
+ return offsetof(SMU73_SoftRegisters, VoltageChangeTimeout);
+ case AverageGraphicsActivity:
+ return offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
+ case PreVBlankGap:
+ return offsetof(SMU73_SoftRegisters, PreVBlankGap);
+ case VBlankTimeout:
+ return offsetof(SMU73_SoftRegisters, VBlankTimeout);
+ case UcodeLoadStatus:
+ return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
+ case DRAM_LOG_ADDR_H:
+ return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);
+ case DRAM_LOG_ADDR_L:
+ return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);
+ case DRAM_LOG_PHY_ADDR_H:
+ return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+ case DRAM_LOG_PHY_ADDR_L:
+ return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+ case DRAM_LOG_BUFF_SIZE:
+ return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);
+ }
+ case SMU_Discrete_DpmTable:
+ switch (member) {
+ case UvdBootLevel:
+ return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
+ case VceBootLevel:
+ return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
+ case SamuBootLevel:
+ return offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
+ case LowSclkInterruptThreshold:
+ return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
+ }
+ }
+ pr_warn("can't get the offset of type %x member %x\n", type, member);
+ return 0;
+}
+
+static uint32_t fiji_get_mac_definition(uint32_t value)
+{
+ switch (value) {
+ case SMU_MAX_LEVELS_GRAPHICS:
+ return SMU73_MAX_LEVELS_GRAPHICS;
+ case SMU_MAX_LEVELS_MEMORY:
+ return SMU73_MAX_LEVELS_MEMORY;
+ case SMU_MAX_LEVELS_LINK:
+ return SMU73_MAX_LEVELS_LINK;
+ case SMU_MAX_ENTRIES_SMIO:
+ return SMU73_MAX_ENTRIES_SMIO;
+ case SMU_MAX_LEVELS_VDDC:
+ return SMU73_MAX_LEVELS_VDDC;
+ case SMU_MAX_LEVELS_VDDGFX:
+ return SMU73_MAX_LEVELS_VDDGFX;
+ case SMU_MAX_LEVELS_VDDCI:
+ return SMU73_MAX_LEVELS_VDDCI;
+ case SMU_MAX_LEVELS_MVDD:
+ return SMU73_MAX_LEVELS_MVDD;
+ }
+
+ pr_warn("can't get the mac of %x\n", value);
+ return 0;
+}
+
+
+static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ smu_data->smc_state_table.UvdBootLevel = 0;
+ if (table_info->mm_dep_table->count > 0)
+ smu_data->smc_state_table.UvdBootLevel =
+ (uint8_t) (table_info->mm_dep_table->count - 1);
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
+ UvdBootLevel);
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0x00FFFFFF;
+ mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDDPM) ||
+ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_UVDDPM_SetEnabledMask,
+ (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
+ return 0;
+}
+
+static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smu_data->smc_state_table.VceBootLevel =
+ (uint8_t) (table_info->mm_dep_table->count - 1);
+ else
+ smu_data->smc_state_table.VceBootLevel = 0;
+
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0xFF00FFFF;
+ mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_VCEDPM_SetEnabledMask,
+ (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
+ return 0;
+}
+
+static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+
+
+ smu_data->smc_state_table.SamuBootLevel = 0;
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
+
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0xFFFFFF00;
+ mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SAMUDPM_SetEnabledMask,
+ (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
+ return 0;
+}
+
+static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
+{
+ switch (type) {
+ case SMU_UVD_TABLE:
+ fiji_update_uvd_smc_table(hwmgr);
+ break;
+ case SMU_VCE_TABLE:
+ fiji_update_vce_smc_table(hwmgr);
+ break;
+ case SMU_SAMU_TABLE:
+ fiji_update_samu_smc_table(hwmgr);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
+ uint32_t tmp;
+ int result;
+ bool error = false;
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU73_Firmware_Header, DpmTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result)
+ smu_data->smu7_data.dpm_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU73_Firmware_Header, SoftRegisters),
+ &tmp, SMC_RAM_END);
+
+ if (!result) {
+ data->soft_regs_start = tmp;
+ smu_data->smu7_data.soft_regs_start = tmp;
+ }
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU73_Firmware_Header, mcRegisterTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.mc_reg_table_start = tmp;
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU73_Firmware_Header, FanTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.fan_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.arb_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU73_Firmware_Header, Version),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ hwmgr->microcode_version_info.SMC = tmp;
+
+ error |= (0 != result);
+
+ return error ? -1 : 0;
+}
+
+static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+
+ /* Program additional LP registers
+ * that are no longer programmed by VBIOS
+ */
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
+
+ return 0;
+}
+
+static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
+{
+ return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
+ ? true : false;
+}
+
+static int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
+ struct amd_pp_profile *request)
+{
+ struct fiji_smumgr *smu_data = (struct fiji_smumgr *)
+ (hwmgr->smu_backend);
+ struct SMU73_Discrete_GraphicsLevel *levels =
+ smu_data->smc_state_table.GraphicsLevel;
+ uint32_t array = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
+ uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
+ SMU73_MAX_LEVELS_GRAPHICS;
+ uint32_t i;
+
+ for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+ levels[i].ActivityLevel =
+ cpu_to_be16(request->activity_threshold);
+ levels[i].EnabledForActivity = 1;
+ levels[i].UpHyst = request->up_hyst;
+ levels[i].DownHyst = request->down_hyst;
+ }
+
+ return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ array_size, SMC_RAM_END);
+}
const struct pp_smumgr_func fiji_smu_funcs = {
.smu_init = &fiji_smu_init,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
index 175bf9f..2796477 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
@@ -28,6 +28,15 @@
#include "smu7_smumgr.h"
+struct fiji_pt_defaults {
+ uint8_t SviLoadLineEn;
+ uint8_t SviLoadLineVddC;
+ uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
+ uint8_t TDC_MAWt;
+ uint8_t TdcWaterfallCtl;
+ uint8_t DTEAmbientTempBase;
+};
+
struct fiji_smumgr {
struct smu7_smumgr smu7_data;
struct SMU73_Discrete_DpmTable smc_state_table;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
deleted file mode 100644
index 51adf04..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ /dev/null
@@ -1,2582 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- *
- */
-
-#include "pp_debug.h"
-#include "iceland_smc.h"
-#include "smu7_dyn_defaults.h"
-
-#include "smu7_hwmgr.h"
-#include "hardwaremanager.h"
-#include "ppatomctrl.h"
-#include "cgs_common.h"
-#include "atombios.h"
-#include "pppcielanes.h"
-#include "pp_endian.h"
-#include "smu7_ppsmc.h"
-
-#include "smu71_discrete.h"
-
-#include "smu/smu_7_1_1_d.h"
-#include "smu/smu_7_1_1_sh_mask.h"
-
-#include "gmc/gmc_8_1_d.h"
-#include "gmc/gmc_8_1_sh_mask.h"
-
-#include "bif/bif_5_0_d.h"
-#include "bif/bif_5_0_sh_mask.h"
-
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-#include "processpptables.h"
-
-#include "iceland_smumgr.h"
-
-#define VOLTAGE_SCALE 4
-#define POWERTUNE_DEFAULT_SET_MAX 1
-#define VOLTAGE_VID_OFFSET_SCALE1 625
-#define VOLTAGE_VID_OFFSET_SCALE2 100
-#define MC_CG_ARB_FREQ_F1 0x0b
-#define VDDC_VDDCI_DELTA 200
-
-#define DEVICE_ID_VI_ICELAND_M_6900 0x6900
-#define DEVICE_ID_VI_ICELAND_M_6901 0x6901
-#define DEVICE_ID_VI_ICELAND_M_6902 0x6902
-#define DEVICE_ID_VI_ICELAND_M_6903 0x6903
-
-static const struct iceland_pt_defaults defaults_iceland = {
- /*
- * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
- * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
- */
- 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
- { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
- { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
-};
-
-/* 35W - XT, XTL */
-static const struct iceland_pt_defaults defaults_icelandxt = {
- /*
- * sviLoadLIneEn, SviLoadLineVddC,
- * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
- * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
- * BAPM_TEMP_GRADIENT
- */
- 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
- { 0xA7, 0x0, 0x0, 0xB5, 0x0, 0x0, 0x9F, 0x0, 0x0, 0xD6, 0x0, 0x0, 0xD7, 0x0, 0x0},
- { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
-};
-
-/* 25W - PRO, LE */
-static const struct iceland_pt_defaults defaults_icelandpro = {
- /*
- * sviLoadLIneEn, SviLoadLineVddC,
- * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
- * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
- * BAPM_TEMP_GRADIENT
- */
- 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
- { 0xB7, 0x0, 0x0, 0xC3, 0x0, 0x0, 0xB5, 0x0, 0x0, 0xEA, 0x0, 0x0, 0xE6, 0x0, 0x0},
- { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
-};
-
-static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-{
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- struct cgs_system_info sys_info = {0};
- uint32_t dev_id;
-
- sys_info.size = sizeof(struct cgs_system_info);
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
- cgs_query_system_info(hwmgr->device, &sys_info);
- dev_id = (uint32_t)sys_info.value;
-
- switch (dev_id) {
- case DEVICE_ID_VI_ICELAND_M_6900:
- case DEVICE_ID_VI_ICELAND_M_6903:
- smu_data->power_tune_defaults = &defaults_icelandxt;
- break;
-
- case DEVICE_ID_VI_ICELAND_M_6901:
- case DEVICE_ID_VI_ICELAND_M_6902:
- smu_data->power_tune_defaults = &defaults_icelandpro;
- break;
- default:
- smu_data->power_tune_defaults = &defaults_iceland;
- pr_warn("Unknown V.I. Device ID.\n");
- break;
- }
- return;
-}
-
-static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-{
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
- smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
- smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
- smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-
- return 0;
-}
-
-static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-{
- uint16_t tdc_limit;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
- smu_data->power_tune_table.TDC_VDDC_PkgLimit =
- CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
- smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
- defaults->tdc_vddc_throttle_release_limit_perc;
- smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
-
- return 0;
-}
-
-static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-{
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
- uint32_t temp;
-
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- fuse_table_offset +
- offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
- (uint32_t *)&temp, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
- return -EINVAL);
- else
- smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
-
- return 0;
-}
-
-static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-{
- return 0;
-}
-
-static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
-
- /* Currently not used. Set all to zero. */
- for (i = 0; i < 8; i++)
- smu_data->power_tune_table.GnbLPML[i] = 0;
-
- return 0;
-}
-
-static int iceland_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
- return 0;
-}
-
-static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-{
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
- uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
- struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
-
- HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
- LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-
- smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
- CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
- smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
- CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
-
- return 0;
-}
-
-static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
- uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
-
- PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
- "The CAC Leakage table does not exist!", return -EINVAL);
- PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
- "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
- PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
- "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
- for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
- lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
- hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
- }
- } else {
- PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
- }
-
- return 0;
-}
-
-static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- uint8_t *vid = smu_data->power_tune_table.VddCVid;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
- "There should never be more than 8 entries for VddcVid!!!",
- return -EINVAL);
-
- for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
- vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
- }
-
- return 0;
-}
-
-
-
-static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-{
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- uint32_t pm_fuse_table_offset;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, PmFuseTable),
- &pm_fuse_table_offset, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to get pm_fuse_table_offset Failed!",
- return -EINVAL);
-
- /* DW0 - DW3 */
- if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate bapm vddc vid Failed!",
- return -EINVAL);
-
- /* DW4 - DW5 */
- if (iceland_populate_vddc_vid(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate vddc vid Failed!",
- return -EINVAL);
-
- /* DW6 */
- if (iceland_populate_svi_load_line(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate SviLoadLine Failed!",
- return -EINVAL);
- /* DW7 */
- if (iceland_populate_tdc_limit(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TDCLimit Failed!", return -EINVAL);
- /* DW8 */
- if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TdcWaterfallCtl, "
- "LPMLTemperature Min and Max Failed!",
- return -EINVAL);
-
- /* DW9-DW12 */
- if (0 != iceland_populate_temperature_scaler(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate LPMLTemperatureScaler Failed!",
- return -EINVAL);
-
- /* DW13-DW16 */
- if (iceland_populate_gnb_lpml(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML Failed!",
- return -EINVAL);
-
- /* DW17 */
- if (iceland_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML Min and Max Vid Failed!",
- return -EINVAL);
-
- /* DW18 */
- if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
- return -EINVAL);
-
- if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
- (uint8_t *)&smu_data->power_tune_table,
- sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to download PmFuseTable Failed!",
- return -EINVAL);
- }
- return 0;
-}
-
-static int iceland_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
- struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
- uint32_t clock, uint32_t *vol)
-{
- uint32_t i = 0;
-
- /* clock - voltage dependency table is empty table */
- if (allowed_clock_voltage_table->count == 0)
- return -EINVAL;
-
- for (i = 0; i < allowed_clock_voltage_table->count; i++) {
- /* find first sclk bigger than request */
- if (allowed_clock_voltage_table->entries[i].clk >= clock) {
- *vol = allowed_clock_voltage_table->entries[i].v;
- return 0;
- }
- }
-
- /* sclk is bigger than max sclk in the dependence table */
- *vol = allowed_clock_voltage_table->entries[i - 1].v;
-
- return 0;
-}
-
-static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
- pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
- uint16_t *lo)
-{
- uint16_t v_index;
- bool vol_found = false;
- *hi = tab->value * VOLTAGE_SCALE;
- *lo = tab->value * VOLTAGE_SCALE;
-
- /* SCLK/VDDC Dependency Table has to exist. */
- PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
- "The SCLK/VDDC Dependency Table does not exist.\n",
- return -EINVAL);
-
- if (NULL == hwmgr->dyn_state.cac_leakage_table) {
- pr_warn("CAC Leakage Table does not exist, using vddc.\n");
- return 0;
- }
-
- /*
- * Since voltage in the sclk/vddc dependency table is not
- * necessarily in ascending order because of ELB voltage
- * patching, loop through entire list to find exact voltage.
- */
- for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
- if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
- vol_found = true;
- if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
- *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
- *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
- } else {
- pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
- *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
- *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
- }
- break;
- }
- }
-
- /*
- * If voltage is not found in the first pass, loop again to
- * find the best match, equal or higher value.
- */
- if (!vol_found) {
- for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
- if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
- vol_found = true;
- if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
- *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
- *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
- } else {
- pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
- *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
- *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
- }
- break;
- }
- }
-
- if (!vol_found)
- pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
- }
-
- return 0;
-}
-
-static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
- pp_atomctrl_voltage_table_entry *tab,
- SMU71_Discrete_VoltageLevel *smc_voltage_tab)
-{
- int result;
-
- result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
- &smc_voltage_tab->StdVoltageHiSidd,
- &smc_voltage_tab->StdVoltageLoSidd);
- if (0 != result) {
- smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
- smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
- }
-
- smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
- CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
- CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
-
- return 0;
-}
-
-static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- unsigned int count;
- int result;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- table->VddcLevelCount = data->vddc_voltage_table.count;
- for (count = 0; count < table->VddcLevelCount; count++) {
- result = iceland_populate_smc_voltage_table(hwmgr,
- &(data->vddc_voltage_table.entries[count]),
- &(table->VddcLevel[count]));
- PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
-
- /* GPIO voltage control */
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
- table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
- else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
- table->VddcLevel[count].Smio = 0;
- }
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
-
- return 0;
-}
-
-static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t count;
- int result;
-
- table->VddciLevelCount = data->vddci_voltage_table.count;
-
- for (count = 0; count < table->VddciLevelCount; count++) {
- result = iceland_populate_smc_voltage_table(hwmgr,
- &(data->vddci_voltage_table.entries[count]),
- &(table->VddciLevel[count]));
- PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
- table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
- else
- table->VddciLevel[count].Smio |= 0;
- }
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
-
- return 0;
-}
-
-static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t count;
- int result;
-
- table->MvddLevelCount = data->mvdd_voltage_table.count;
-
- for (count = 0; count < table->VddciLevelCount; count++) {
- result = iceland_populate_smc_voltage_table(hwmgr,
- &(data->mvdd_voltage_table.entries[count]),
- &table->MvddLevel[count]);
- PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
- table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
- else
- table->MvddLevel[count].Smio |= 0;
- }
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
-
- return 0;
-}
-
-
-static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- int result;
-
- result = iceland_populate_smc_vddc_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "can not populate VDDC voltage table to SMC", return -EINVAL);
-
- result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "can not populate VDDCI voltage table to SMC", return -EINVAL);
-
- result = iceland_populate_smc_mvdd_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "can not populate MVDD voltage table to SMC", return -EINVAL);
-
- return 0;
-}
-
-static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
- struct SMU71_Discrete_Ulv *state)
-{
- uint32_t voltage_response_time, ulv_voltage;
- int result;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- state->CcPwrDynRm = 0;
- state->CcPwrDynRm1 = 0;
-
- result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
- PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
-
- if (ulv_voltage == 0) {
- data->ulv_supported = false;
- return 0;
- }
-
- if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
- /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
- if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
- state->VddcOffset = 0;
- else
- /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
- state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
- } else {
- /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
- if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
- state->VddcOffsetVid = 0;
- else /* used in SVI2 Mode */
- state->VddcOffsetVid = (uint8_t)(
- (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
- * VOLTAGE_VID_OFFSET_SCALE2
- / VOLTAGE_VID_OFFSET_SCALE1);
- }
- state->VddcPhase = 1;
-
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
- CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-
- return 0;
-}
-
-static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_Ulv *ulv_level)
-{
- return iceland_populate_ulv_level(hwmgr, ulv_level);
-}
-
-static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- uint32_t i;
-
- /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
- for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
- table->LinkLevel[i].PcieGenSpeed =
- (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
- table->LinkLevel[i].PcieLaneCount =
- (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
- table->LinkLevel[i].EnabledForActivity =
- 1;
- table->LinkLevel[i].SPC =
- (uint8_t)(data->pcie_spc_cap & 0xff);
- table->LinkLevel[i].DownThreshold =
- PP_HOST_TO_SMC_UL(5);
- table->LinkLevel[i].UpThreshold =
- PP_HOST_TO_SMC_UL(30);
- }
-
- smu_data->smc_state_table.LinkLevelCount =
- (uint8_t)dpm_table->pcie_speed_table.count;
- data->dpm_level_enable_mask.pcie_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-
- return 0;
-}
-
-/**
- * Calculates the SCLK dividers using the provided engine clock
- *
- * @param hwmgr the address of the hardware manager
- * @param engine_clock the engine clock to use to populate the structure
- * @param sclk the SMC SCLK structure to be populated
- */
-static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
-{
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- pp_atomctrl_clock_dividers_vi dividers;
- uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
- uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
- uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
- uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
- uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
- uint32_t reference_clock;
- uint32_t reference_divider;
- uint32_t fbdiv;
- int result;
-
- /* get the engine clock dividers for this clock value*/
- result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
-
- PP_ASSERT_WITH_CODE(result == 0,
- "Error retrieving Engine Clock dividers from VBIOS.", return result);
-
- /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
- reference_clock = atomctrl_get_reference_clock(hwmgr);
-
- reference_divider = 1 + dividers.uc_pll_ref_div;
-
- /* low 14 bits is fraction and high 12 bits is divider*/
- fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-
- /* SPLL_FUNC_CNTL setup*/
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
- CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
- CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
-
- /* SPLL_FUNC_CNTL_3 setup*/
- spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
- CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
-
- /* set to use fractional accumulation*/
- spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
- CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
- pp_atomctrl_internal_ss_info ss_info;
-
- uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
- if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
- /*
- * ss_info.speed_spectrum_percentage -- in unit of 0.01%
- * ss_info.speed_spectrum_rate -- in unit of khz
- */
- /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
- uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
-
- /* clkv = 2 * D * fbdiv / NS */
- uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
-
- cg_spll_spread_spectrum =
- PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
- cg_spll_spread_spectrum =
- PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
- cg_spll_spread_spectrum_2 =
- PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
- }
- }
-
- sclk->SclkFrequency = engine_clock;
- sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
- sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
- sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
- sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
- sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
-
- return 0;
-}
-
-static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
- const struct phm_phase_shedding_limits_table *pl,
- uint32_t sclk, uint32_t *p_shed)
-{
- unsigned int i;
-
- /* use the minimum phase shedding */
- *p_shed = 1;
-
- for (i = 0; i < pl->count; i++) {
- if (sclk < pl->entries[i].Sclk) {
- *p_shed = i;
- break;
- }
- }
- return 0;
-}
-
-/**
- * Populates single SMC SCLK structure using the provided engine clock
- *
- * @param hwmgr the address of the hardware manager
- * @param engine_clock the engine clock to use to populate the structure
- * @param sclk the SMC SCLK structure to be populated
- */
-static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
- uint32_t engine_clock,
- uint16_t sclk_activity_level_threshold,
- SMU71_Discrete_GraphicsLevel *graphic_level)
-{
- int result;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
-
- /* populate graphics levels*/
- result = iceland_get_dependecy_volt_by_clk(hwmgr,
- hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
- &graphic_level->MinVddc);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find VDDC voltage value for VDDC \
- engine clock dependency table", return result);
-
- /* SCLK frequency in units of 10KHz*/
- graphic_level->SclkFrequency = engine_clock;
- graphic_level->MinVddcPhases = 1;
-
- if (data->vddc_phase_shed_control)
- iceland_populate_phase_value_based_on_sclk(hwmgr,
- hwmgr->dyn_state.vddc_phase_shed_limits_table,
- engine_clock,
- &graphic_level->MinVddcPhases);
-
- /* Indicates maximum activity level for this performance level. 50% for now*/
- graphic_level->ActivityLevel = sclk_activity_level_threshold;
-
- graphic_level->CcPwrDynRm = 0;
- graphic_level->CcPwrDynRm1 = 0;
- /* this level can be used if activity is high enough.*/
- graphic_level->EnabledForActivity = 0;
- /* this level can be used for throttling.*/
- graphic_level->EnabledForThrottle = 1;
- graphic_level->UpHyst = 0;
- graphic_level->DownHyst = 100;
- graphic_level->VoltageDownHyst = 0;
- graphic_level->PowerThrottle = 0;
-
- data->display_timing.min_clock_in_sr =
- hwmgr->display_config.min_core_set_clock_in_sr;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkDeepSleep))
- graphic_level->DeepSleepDivId =
- smu7_get_sleep_divider_id_from_clock(engine_clock,
- data->display_timing.min_clock_in_sr);
-
- /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
- graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
- if (0 == result) {
- graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
- }
-
- return result;
-}
-
-/**
- * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
- *
- * @param hwmgr the address of the hardware manager
- */
-int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
-
- uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *
- SMU71_MAX_LEVELS_GRAPHICS;
-
- SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
-
- uint32_t i;
- uint8_t highest_pcie_level_enabled = 0;
- uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
- uint8_t count = 0;
- int result = 0;
-
- memset(levels, 0x00, level_array_size);
-
- for (i = 0; i < dpm_table->sclk_table.count; i++) {
- result = iceland_populate_single_graphic_level(hwmgr,
- dpm_table->sclk_table.dpm_levels[i].value,
- (uint16_t)smu_data->activity_target[i],
- &(smu_data->smc_state_table.GraphicsLevel[i]));
- if (result != 0)
- return result;
-
- /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
- if (i > 1)
- smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
- }
-
- /* Only enable level 0 for now. */
- smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-
- /* set highest level watermark to high */
- if (dpm_table->sclk_table.count > 1)
- smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
- PPSMC_DISPLAY_WATERMARK_HIGH;
-
- smu_data->smc_state_table.GraphicsDpmLevelCount =
- (uint8_t)dpm_table->sclk_table.count;
- data->dpm_level_enable_mask.sclk_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-
- while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << (highest_pcie_level_enabled + 1))) != 0) {
- highest_pcie_level_enabled++;
- }
-
- while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << lowest_pcie_level_enabled)) == 0) {
- lowest_pcie_level_enabled++;
- }
-
- while ((count < highest_pcie_level_enabled) &&
- ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
- count++;
- }
-
- mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
- (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
-
-
- /* set pcieDpmLevel to highest_pcie_level_enabled*/
- for (i = 2; i < dpm_table->sclk_table.count; i++) {
- smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
- }
-
- /* set pcieDpmLevel to lowest_pcie_level_enabled*/
- smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
-
- /* set pcieDpmLevel to mid_pcie_level_enabled*/
- smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
-
- /* level count will send to smc once at init smc table and never change*/
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress,
- (uint8_t *)levels, (uint32_t)level_array_size,
- SMC_RAM_END);
-
- return result;
-}
-
-/**
- * Populates the SMC MCLK structure using the provided memory clock
- *
- * @param hwmgr the address of the hardware manager
- * @param memory_clock the memory clock to use to populate the structure
- * @param sclk the SMC SCLK structure to be populated
- */
-static int iceland_calculate_mclk_params(
- struct pp_hwmgr *hwmgr,
- uint32_t memory_clock,
- SMU71_Discrete_MemoryLevel *mclk,
- bool strobe_mode,
- bool dllStateOn
- )
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
- uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
- uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
- uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
- uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
- uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
- uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
- uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
- uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
-
- pp_atomctrl_memory_clock_param mpll_param;
- int result;
-
- result = atomctrl_get_memory_pll_dividers_si(hwmgr,
- memory_clock, &mpll_param, strobe_mode);
- PP_ASSERT_WITH_CODE(0 == result,
- "Error retrieving Memory Clock Parameters from VBIOS.", return result);
-
- /* MPLL_FUNC_CNTL setup*/
- mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
-
- /* MPLL_FUNC_CNTL_1 setup*/
- mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
- MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
- mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
- MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
- mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
- MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
-
- /* MPLL_AD_FUNC_CNTL setup*/
- mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
- MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
-
- if (data->is_memory_gddr5) {
- /* MPLL_DQ_FUNC_CNTL setup*/
- mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
- MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
- mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
- MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
- }
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
- /*
- ************************************
- Fref = Reference Frequency
- NF = Feedback divider ratio
- NR = Reference divider ratio
- Fnom = Nominal VCO output frequency = Fref * NF / NR
- Fs = Spreading Rate
- D = Percentage down-spread / 2
- Fint = Reference input frequency to PFD = Fref / NR
- NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
- CLKS = NS - 1 = ISS_STEP_NUM[11:0]
- NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
- CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
- *************************************
- */
- pp_atomctrl_internal_ss_info ss_info;
- uint32_t freq_nom;
- uint32_t tmp;
- uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
-
- /* for GDDR5 for all modes and DDR3 */
- if (1 == mpll_param.qdr)
- freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
- else
- freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
-
- /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
- tmp = (freq_nom / reference_clock);
- tmp = tmp * tmp;
-
- if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
- /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
- /* ss.Info.speed_spectrum_rate -- in unit of khz */
- /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
- /* = reference_clock * 5 / speed_spectrum_rate */
- uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
-
- /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
- /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
- uint32_t clkv =
- (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
- ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
-
- mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
- mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
- }
- }
-
- /* MCLK_PWRMGT_CNTL setup */
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
-
-
- /* Save the result data to outpupt memory level structure */
- mclk->MclkFrequency = memory_clock;
- mclk->MpllFuncCntl = mpll_func_cntl;
- mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
- mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
- mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
- mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
- mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
- mclk->DllCntl = dll_cntl;
- mclk->MpllSs1 = mpll_ss1;
- mclk->MpllSs2 = mpll_ss2;
-
- return 0;
-}
-
-static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
- bool strobe_mode)
-{
- uint8_t mc_para_index;
-
- if (strobe_mode) {
- if (memory_clock < 12500) {
- mc_para_index = 0x00;
- } else if (memory_clock > 47500) {
- mc_para_index = 0x0f;
- } else {
- mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
- }
- } else {
- if (memory_clock < 65000) {
- mc_para_index = 0x00;
- } else if (memory_clock > 135000) {
- mc_para_index = 0x0f;
- } else {
- mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
- }
- }
-
- return mc_para_index;
-}
-
-static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
-{
- uint8_t mc_para_index;
-
- if (memory_clock < 10000) {
- mc_para_index = 0;
- } else if (memory_clock >= 80000) {
- mc_para_index = 0x0f;
- } else {
- mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
- }
-
- return mc_para_index;
-}
-
-static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
- uint32_t memory_clock, uint32_t *p_shed)
-{
- unsigned int i;
-
- *p_shed = 1;
-
- for (i = 0; i < pl->count; i++) {
- if (memory_clock < pl->entries[i].Mclk) {
- *p_shed = i;
- break;
- }
- }
-
- return 0;
-}
-
-static int iceland_populate_single_memory_level(
- struct pp_hwmgr *hwmgr,
- uint32_t memory_clock,
- SMU71_Discrete_MemoryLevel *memory_level
- )
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- int result = 0;
- bool dll_state_on;
- struct cgs_display_info info = {0};
- uint32_t mclk_edc_wr_enable_threshold = 40000;
- uint32_t mclk_edc_enable_threshold = 40000;
- uint32_t mclk_strobe_mode_threshold = 40000;
-
- if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
- result = iceland_get_dependecy_volt_by_clk(hwmgr,
- hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
- }
-
- if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
- memory_level->MinVddci = memory_level->MinVddc;
- } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
- result = iceland_get_dependecy_volt_by_clk(hwmgr,
- hwmgr->dyn_state.vddci_dependency_on_mclk,
- memory_clock,
- &memory_level->MinVddci);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
- }
-
- memory_level->MinVddcPhases = 1;
-
- if (data->vddc_phase_shed_control) {
- iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
- memory_clock, &memory_level->MinVddcPhases);
- }
-
- memory_level->EnabledForThrottle = 1;
- memory_level->EnabledForActivity = 0;
- memory_level->UpHyst = 0;
- memory_level->DownHyst = 100;
- memory_level->VoltageDownHyst = 0;
-
- /* Indicates maximum activity level for this performance level.*/
- memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
- memory_level->StutterEnable = 0;
- memory_level->StrobeEnable = 0;
- memory_level->EdcReadEnable = 0;
- memory_level->EdcWriteEnable = 0;
- memory_level->RttEnable = 0;
-
- /* default set to low watermark. Highest level will be set to high later.*/
- memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
- cgs_get_active_displays_info(hwmgr->device, &info);
- data->display_timing.num_existing_displays = info.display_count;
-
- /* stutter mode not support on iceland */
-
- /* decide strobe mode*/
- memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
- (memory_clock <= mclk_strobe_mode_threshold);
-
- /* decide EDC mode and memory clock ratio*/
- if (data->is_memory_gddr5) {
- memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
- memory_level->StrobeEnable);
-
- if ((mclk_edc_enable_threshold != 0) &&
- (memory_clock > mclk_edc_enable_threshold)) {
- memory_level->EdcReadEnable = 1;
- }
-
- if ((mclk_edc_wr_enable_threshold != 0) &&
- (memory_clock > mclk_edc_wr_enable_threshold)) {
- memory_level->EdcWriteEnable = 1;
- }
-
- if (memory_level->StrobeEnable) {
- if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
- ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
- dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
- else
- dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
- } else
- dll_state_on = data->dll_default_on;
- } else {
- memory_level->StrobeRatio =
- iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
- dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
- }
-
- result = iceland_calculate_mclk_params(hwmgr,
- memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
-
- if (0 == result) {
- memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
- memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
- memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
- /* MCLK frequency in units of 10KHz*/
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
- /* Indicates maximum activity level for this performance level.*/
- CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
- }
-
- return result;
-}
-
-/**
- * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
- *
- * @param hwmgr the address of the hardware manager
- */
-
-int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- int result;
-
- /* populate MCLK dpm table to SMU7 */
- uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
- uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
- SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
- uint32_t i;
-
- memset(levels, 0x00, level_array_size);
-
- for (i = 0; i < dpm_table->mclk_table.count; i++) {
- PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
- "can not populate memory level as memory clock is zero", return -EINVAL);
- result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
- &(smu_data->smc_state_table.MemoryLevel[i]));
- if (0 != result) {
- return result;
- }
- }
-
- /* Only enable level 0 for now.*/
- smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-
- /*
- * in order to prevent MC activity from stutter mode to push DPM up.
- * the UVD change complements this by putting the MCLK in a higher state
- * by default such that we are not effected by up threshold or and MCLK DPM latency.
- */
- smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
-
- smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
- data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
- /* set highest level watermark to high*/
- smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-
- /* level count will send to smc once at init smc table and never change*/
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
- level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
- SMC_RAM_END);
-
- return result;
-}
-
-static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
- SMU71_Discrete_VoltageLevel *voltage)
-{
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- uint32_t i = 0;
-
- if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
- /* find mvdd value which clock is more than request */
- for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
- if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
- /* Always round to higher voltage. */
- voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
- break;
- }
- }
-
- PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
- "MVDD Voltage is outside the supported range.", return -EINVAL);
-
- } else {
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- int result = 0;
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct pp_atomctrl_clock_dividers_vi dividers;
- uint32_t vddc_phase_shed_control = 0;
-
- SMU71_Discrete_VoltageLevel voltage_level;
- uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
- uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
- uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
- uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
-
-
- /* The ACPI state should not do DPM on DC (or ever).*/
- table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-
- if (data->acpi_vddc)
- table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
- else
- table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
-
- table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
- /* assign zero for now*/
- table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
-
- /* get the engine clock dividers for this clock value*/
- result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
- table->ACPILevel.SclkFrequency, ÷rs);
-
- PP_ASSERT_WITH_CODE(result == 0,
- "Error retrieving Engine Clock dividers from VBIOS.", return result);
-
- /* divider ID for required SCLK*/
- table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
- table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
- table->ACPILevel.DeepSleepDivId = 0;
-
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
- CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
- CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
- spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
- CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
-
- table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
- table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
- table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
- table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
- table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
- table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
- table->ACPILevel.CcPwrDynRm = 0;
- table->ACPILevel.CcPwrDynRm1 = 0;
-
-
- /* For various features to be enabled/disabled while this level is active.*/
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
- /* SCLK frequency in units of 10KHz*/
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-
- /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
- table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
- table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
-
- if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
- table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
- else {
- if (data->acpi_vddci != 0)
- table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
- else
- table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
- }
-
- if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
- table->MemoryACPILevel.MinMvdd =
- PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
- else
- table->MemoryACPILevel.MinMvdd = 0;
-
- /* Force reset on DLL*/
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
-
- /* Disable DLL in ACPIState*/
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
-
- /* Enable DLL bypass signal*/
- dll_cntl = PHM_SET_FIELD(dll_cntl,
- DLL_CNTL, MRDCK0_BYPASS, 0);
- dll_cntl = PHM_SET_FIELD(dll_cntl,
- DLL_CNTL, MRDCK1_BYPASS, 0);
-
- table->MemoryACPILevel.DllCntl =
- PP_HOST_TO_SMC_UL(dll_cntl);
- table->MemoryACPILevel.MclkPwrmgtCntl =
- PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
- table->MemoryACPILevel.MpllAdFuncCntl =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
- table->MemoryACPILevel.MpllDqFuncCntl =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
- table->MemoryACPILevel.MpllFuncCntl =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
- table->MemoryACPILevel.MpllFuncCntl_1 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
- table->MemoryACPILevel.MpllFuncCntl_2 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
- table->MemoryACPILevel.MpllSs1 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
- table->MemoryACPILevel.MpllSs2 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
-
- table->MemoryACPILevel.EnabledForThrottle = 0;
- table->MemoryACPILevel.EnabledForActivity = 0;
- table->MemoryACPILevel.UpHyst = 0;
- table->MemoryACPILevel.DownHyst = 100;
- table->MemoryACPILevel.VoltageDownHyst = 0;
- /* Indicates maximum activity level for this performance level.*/
- table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-
- table->MemoryACPILevel.StutterEnable = 0;
- table->MemoryACPILevel.StrobeEnable = 0;
- table->MemoryACPILevel.EdcReadEnable = 0;
- table->MemoryACPILevel.EdcWriteEnable = 0;
- table->MemoryACPILevel.RttEnable = 0;
-
- return result;
-}
-
-static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- return 0;
-}
-
-static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- return 0;
-}
-
-static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- return 0;
-}
-
-static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- return 0;
-}
-
-static int iceland_populate_memory_timing_parameters(
- struct pp_hwmgr *hwmgr,
- uint32_t engine_clock,
- uint32_t memory_clock,
- struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
- )
-{
- uint32_t dramTiming;
- uint32_t dramTiming2;
- uint32_t burstTime;
- int result;
-
- result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
- engine_clock, memory_clock);
-
- PP_ASSERT_WITH_CODE(result == 0,
- "Error calling VBIOS to set DRAM_TIMING.", return result);
-
- dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
- dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
- burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-
- arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
- arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
- arb_regs->McArbBurstTime = (uint8_t)burstTime;
-
- return 0;
-}
-
-/**
- * Setup parameters for the MC ARB.
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @return always 0
- * This function is to be called from the SetPowerState table.
- */
-static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- int result = 0;
- SMU71_Discrete_MCArbDramTimingTable arb_regs;
- uint32_t i, j;
-
- memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
-
- for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
- for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
- result = iceland_populate_memory_timing_parameters
- (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
- data->dpm_table.mclk_table.dpm_levels[j].value,
- &arb_regs.entries[i][j]);
-
- if (0 != result) {
- break;
- }
- }
- }
-
- if (0 == result) {
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.arb_table_start,
- (uint8_t *)&arb_regs,
- sizeof(SMU71_Discrete_MCArbDramTimingTable),
- SMC_RAM_END
- );
- }
-
- return result;
-}
-
-static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *table)
-{
- int result = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- table->GraphicsBootLevel = 0;
- table->MemoryBootLevel = 0;
-
- /* find boot level from dpm table*/
- result = phm_find_boot_level(&(data->dpm_table.sclk_table),
- data->vbios_boot_state.sclk_bootup_value,
- (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
-
- if (0 != result) {
- smu_data->smc_state_table.GraphicsBootLevel = 0;
- pr_err("VBIOS did not find boot engine clock value \
- in dependency table. Using Graphics DPM level 0!");
- result = 0;
- }
-
- result = phm_find_boot_level(&(data->dpm_table.mclk_table),
- data->vbios_boot_state.mclk_bootup_value,
- (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
-
- if (0 != result) {
- smu_data->smc_state_table.MemoryBootLevel = 0;
- pr_err("VBIOS did not find boot engine clock value \
- in dependency table. Using Memory DPM level 0!");
- result = 0;
- }
-
- table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
- if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
- table->BootVddci = table->BootVddc;
- else
- table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
-
- table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
-
- return result;
-}
-
-static int iceland_populate_mc_reg_address(struct pp_smumgr *smumgr,
- SMU71_Discrete_MCRegisters *mc_reg_table)
-{
- const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)smumgr->backend;
-
- uint32_t i, j;
-
- for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
- if (smu_data->mc_reg_table.validflag & 1<<j) {
- PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
- "Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
- mc_reg_table->address[i].s0 =
- PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
- mc_reg_table->address[i].s1 =
- PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
- i++;
- }
- }
-
- mc_reg_table->last = (uint8_t)i;
-
- return 0;
-}
-
-/*convert register values from driver to SMC format */
-static void iceland_convert_mc_registers(
- const struct iceland_mc_reg_entry *entry,
- SMU71_Discrete_MCRegisterSet *data,
- uint32_t num_entries, uint32_t valid_flag)
-{
- uint32_t i, j;
-
- for (i = 0, j = 0; j < num_entries; j++) {
- if (valid_flag & 1<<j) {
- data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
- i++;
- }
- }
-}
-
-static int iceland_convert_mc_reg_table_entry_to_smc(
- struct pp_smumgr *smumgr,
- const uint32_t memory_clock,
- SMU71_Discrete_MCRegisterSet *mc_reg_table_data
- )
-{
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
- uint32_t i = 0;
-
- for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
- if (memory_clock <=
- smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
- break;
- }
- }
-
- if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
- --i;
-
- iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
- mc_reg_table_data, smu_data->mc_reg_table.last,
- smu_data->mc_reg_table.validflag);
-
- return 0;
-}
-
-static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_MCRegisters *mc_regs)
-{
- int result = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- int res;
- uint32_t i;
-
- for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
- res = iceland_convert_mc_reg_table_entry_to_smc(
- hwmgr->smumgr,
- data->dpm_table.mclk_table.dpm_levels[i].value,
- &mc_regs->data[i]
- );
-
- if (0 != res)
- result = res;
- }
-
- return result;
-}
-
-static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t address;
- int32_t result;
-
- if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
- return 0;
-
-
- memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
-
- result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
-
- if (result != 0)
- return result;
-
-
- address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
-
- return smu7_copy_bytes_to_smc(hwmgr->smumgr, address,
- (uint8_t *)&smu_data->mc_regs.data[0],
- sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
- SMC_RAM_END);
-}
-
-static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
-
- memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
- result = iceland_populate_mc_reg_address(smumgr, &(smu_data->mc_regs));
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize MCRegTable for the MC register addresses!", return result;);
-
- result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize MCRegTable for driver state!", return result;);
-
- return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start,
- (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
-}
-
-static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- uint8_t count, level;
-
- count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
-
- for (level = 0; level < count; level++) {
- if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
- >= data->vbios_boot_state.sclk_bootup_value) {
- smu_data->smc_state_table.GraphicsBootLevel = level;
- break;
- }
- }
-
- count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
-
- for (level = 0; level < count; level++) {
- if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
- >= data->vbios_boot_state.mclk_bootup_value) {
- smu_data->smc_state_table.MemoryBootLevel = level;
- break;
- }
- }
-
- return 0;
-}
-
-static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
- SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
- struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
- struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
- const uint16_t *def1, *def2;
- int i, j, k;
-
-
- /*
- * TDP number of fraction bits are changed from 8 to 7 for Iceland
- * as requested by SMC team
- */
-
- dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
- dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
-
-
- dpm_table->DTETjOffset = 0;
-
- dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
- dpm_table->GpuTjHyst = 8;
-
- dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
-
- /* The following are for new Iceland Multi-input fan/thermal control */
- if (NULL != ppm) {
- dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
- dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
- } else {
- dpm_table->PPM_PkgPwrLimit = 0;
- dpm_table->PPM_TemperatureLimit = 0;
- }
-
- CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
- CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
-
- dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient);
- def1 = defaults->bapmti_r;
- def2 = defaults->bapmti_rc;
-
- for (i = 0; i < SMU71_DTE_ITERATIONS; i++) {
- for (j = 0; j < SMU71_DTE_SOURCES; j++) {
- for (k = 0; k < SMU71_DTE_SINKS; k++) {
- dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
- dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
- def1++;
- def2++;
- }
- }
- }
-
- return 0;
-}
-
-static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
- SMU71_Discrete_DpmTable *tab)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
- tab->SVI2Enable |= VDDC_ON_SVI2;
-
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
- tab->SVI2Enable |= VDDCI_ON_SVI2;
- else
- tab->MergedVddci = 1;
-
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
- tab->SVI2Enable |= MVDD_ON_SVI2;
-
- PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
- (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
-
- return 0;
-}
-
-/**
- * Initializes the SMC table and uploads it
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @param pInput the pointer to input data (PowerState)
- * @return always 0
- */
-int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table);
-
-
- iceland_initialize_power_tune_defaults(hwmgr);
- memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
-
- if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) {
- iceland_populate_smc_voltage_tables(hwmgr, table);
- }
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StepVddc))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-
- if (data->is_memory_gddr5)
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-
-
- if (data->ulv_supported) {
- result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ULV state!", return result;);
-
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_ULV_PARAMETER, 0x40035);
- }
-
- result = iceland_populate_smc_link_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Link Level!", return result;);
-
- result = iceland_populate_all_graphic_levels(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Graphics Level!", return result;);
-
- result = iceland_populate_all_memory_levels(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Memory Level!", return result;);
-
- result = iceland_populate_smc_acpi_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ACPI Level!", return result;);
-
- result = iceland_populate_smc_vce_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize VCE Level!", return result;);
-
- result = iceland_populate_smc_acp_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ACP Level!", return result;);
-
- result = iceland_populate_smc_samu_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize SAMU Level!", return result;);
-
- /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
- /* need to populate the ARB settings for the initial state. */
- result = iceland_program_memory_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to Write ARB settings for the initial state.", return result;);
-
- result = iceland_populate_smc_uvd_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize UVD Level!", return result;);
-
- table->GraphicsBootLevel = 0;
- table->MemoryBootLevel = 0;
-
- result = iceland_populate_smc_boot_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Boot Level!", return result;);
-
- result = iceland_populate_smc_initial_state(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
-
- result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
-
- table->GraphicsVoltageChangeEnable = 1;
- table->GraphicsThermThrottleEnable = 1;
- table->GraphicsInterval = 1;
- table->VoltageInterval = 1;
- table->ThermalInterval = 1;
-
- table->TemperatureLimitHigh =
- (data->thermal_temp_setting.temperature_high *
- SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- table->TemperatureLimitLow =
- (data->thermal_temp_setting.temperature_low *
- SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-
- table->MemoryVoltageChangeEnable = 1;
- table->MemoryInterval = 1;
- table->VoltageResponseTime = 0;
- table->PhaseResponseTime = 0;
- table->MemoryThermThrottleEnable = 1;
- table->PCIeBootLinkLevel = 0;
- table->PCIeGenInterval = 1;
-
- result = iceland_populate_smc_svi2_config(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate SVI2 setting!", return result);
-
- table->ThermGpio = 17;
- table->SclkStepSize = 0x4000;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
- CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
- CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-
- table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
- table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
- table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
-
- /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.dpm_table_start +
- offsetof(SMU71_Discrete_DpmTable, SystemFlags),
- (uint8_t *)&(table->SystemFlags),
- sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
- SMC_RAM_END);
-
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to upload dpm data to SMC memory!", return result;);
-
- /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
- smu_data->smu7_data.ulv_setting_starts,
- (uint8_t *)&(smu_data->ulv_setting),
- sizeof(SMU71_Discrete_Ulv),
- SMC_RAM_END);
-
-
- result = iceland_populate_initial_mc_reg_table(hwmgr);
- PP_ASSERT_WITH_CODE((0 == result),
- "Failed to populate initialize MC Reg table!", return result);
-
- result = iceland_populate_pm_fuses(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate PM fuses to SMC memory!", return result);
-
- return 0;
-}
-
-/**
-* Set up the fan table to control the fan using the SMC.
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from set temperature range routine
-*/
-int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-{
- struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
- SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
- uint32_t duty100;
- uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
- uint16_t fdo_min, slope1, slope2;
- uint32_t reference_clock;
- int res;
- uint64_t tmp64;
-
- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
- return 0;
-
- if (hwmgr->thermal_controller.fanInfo.bNoFan) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- if (0 == smu7_data->fan_table_start) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
-
- if (0 == duty100) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
- do_div(tmp64, 10000);
- fdo_min = (uint16_t)tmp64;
-
- t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
- t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-
- pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
- pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-
- slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
- slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-
- fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
- fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
- fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
-
- fan_table.Slope1 = cpu_to_be16(slope1);
- fan_table.Slope2 = cpu_to_be16(slope2);
-
- fan_table.FdoMin = cpu_to_be16(fdo_min);
-
- fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
-
- fan_table.HystUp = cpu_to_be16(1);
-
- fan_table.HystSlope = cpu_to_be16(1);
-
- fan_table.TempRespLim = cpu_to_be16(5);
-
- reference_clock = smu7_get_xclk(hwmgr);
-
- fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
-
- fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-
- fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
-
- /* fan_table.FanControl_GL_Flag = 1; */
-
- res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
-
- return 0;
-}
-
-
-static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (data->need_update_smu7_dpm_table &
- (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
- return iceland_program_memory_timing_parameters(hwmgr);
-
- return 0;
-}
-
-int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
-
- int result = 0;
- uint32_t low_sclk_interrupt_threshold = 0;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
- low_sclk_interrupt_threshold =
- data->low_sclk_interrupt_threshold;
-
- CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.dpm_table_start +
- offsetof(SMU71_Discrete_DpmTable,
- LowSclkInterruptThreshold),
- (uint8_t *)&low_sclk_interrupt_threshold,
- sizeof(uint32_t),
- SMC_RAM_END);
- }
-
- result = iceland_update_and_upload_mc_reg_table(hwmgr);
-
- PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
-
- result = iceland_program_mem_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE((result == 0),
- "Failed to program memory timing parameters!",
- );
-
- return result;
-}
-
-uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
-{
- switch (type) {
- case SMU_SoftRegisters:
- switch (member) {
- case HandshakeDisables:
- return offsetof(SMU71_SoftRegisters, HandshakeDisables);
- case VoltageChangeTimeout:
- return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout);
- case AverageGraphicsActivity:
- return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
- case PreVBlankGap:
- return offsetof(SMU71_SoftRegisters, PreVBlankGap);
- case VBlankTimeout:
- return offsetof(SMU71_SoftRegisters, VBlankTimeout);
- case UcodeLoadStatus:
- return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
- }
- case SMU_Discrete_DpmTable:
- switch (member) {
- case LowSclkInterruptThreshold:
- return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
- }
- }
- pr_warn("can't get the offset of type %x member %x\n", type, member);
- return 0;
-}
-
-uint32_t iceland_get_mac_definition(uint32_t value)
-{
- switch (value) {
- case SMU_MAX_LEVELS_GRAPHICS:
- return SMU71_MAX_LEVELS_GRAPHICS;
- case SMU_MAX_LEVELS_MEMORY:
- return SMU71_MAX_LEVELS_MEMORY;
- case SMU_MAX_LEVELS_LINK:
- return SMU71_MAX_LEVELS_LINK;
- case SMU_MAX_ENTRIES_SMIO:
- return SMU71_MAX_ENTRIES_SMIO;
- case SMU_MAX_LEVELS_VDDC:
- return SMU71_MAX_LEVELS_VDDC;
- case SMU_MAX_LEVELS_VDDCI:
- return SMU71_MAX_LEVELS_VDDCI;
- case SMU_MAX_LEVELS_MVDD:
- return SMU71_MAX_LEVELS_MVDD;
- }
-
- pr_warn("can't get the mac of %x\n", value);
- return 0;
-}
-
-/**
- * Get the location of various tables inside the FW image.
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @return always 0
- */
-int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
-
- uint32_t tmp;
- int result;
- bool error = false;
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, DpmTable),
- &tmp, SMC_RAM_END);
-
- if (0 == result) {
- smu7_data->dpm_table_start = tmp;
- }
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, SoftRegisters),
- &tmp, SMC_RAM_END);
-
- if (0 == result) {
- data->soft_regs_start = tmp;
- smu7_data->soft_regs_start = tmp;
- }
-
- error |= (0 != result);
-
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, mcRegisterTable),
- &tmp, SMC_RAM_END);
-
- if (0 == result) {
- smu7_data->mc_reg_table_start = tmp;
- }
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, FanTable),
- &tmp, SMC_RAM_END);
-
- if (0 == result) {
- smu7_data->fan_table_start = tmp;
- }
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
- &tmp, SMC_RAM_END);
-
- if (0 == result) {
- smu7_data->arb_table_start = tmp;
- }
-
- error |= (0 != result);
-
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, Version),
- &tmp, SMC_RAM_END);
-
- if (0 == result) {
- hwmgr->microcode_version_info.SMC = tmp;
- }
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU71_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU71_Firmware_Header, UlvSettings),
- &tmp, SMC_RAM_END);
-
- if (0 == result) {
- smu7_data->ulv_setting_starts = tmp;
- }
-
- error |= (0 != result);
-
- return error ? 1 : 0;
-}
-
-/*---------------------------MC----------------------------*/
-
-static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
-{
- return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
-}
-
-static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
-{
- bool result = true;
-
- switch (in_reg) {
- case mmMC_SEQ_RAS_TIMING:
- *out_reg = mmMC_SEQ_RAS_TIMING_LP;
- break;
-
- case mmMC_SEQ_DLL_STBY:
- *out_reg = mmMC_SEQ_DLL_STBY_LP;
- break;
-
- case mmMC_SEQ_G5PDX_CMD0:
- *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
- break;
-
- case mmMC_SEQ_G5PDX_CMD1:
- *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
- break;
-
- case mmMC_SEQ_G5PDX_CTRL:
- *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
- break;
-
- case mmMC_SEQ_CAS_TIMING:
- *out_reg = mmMC_SEQ_CAS_TIMING_LP;
- break;
-
- case mmMC_SEQ_MISC_TIMING:
- *out_reg = mmMC_SEQ_MISC_TIMING_LP;
- break;
-
- case mmMC_SEQ_MISC_TIMING2:
- *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
- break;
-
- case mmMC_SEQ_PMG_DVS_CMD:
- *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
- break;
-
- case mmMC_SEQ_PMG_DVS_CTL:
- *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
- break;
-
- case mmMC_SEQ_RD_CTL_D0:
- *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
- break;
-
- case mmMC_SEQ_RD_CTL_D1:
- *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
- break;
-
- case mmMC_SEQ_WR_CTL_D0:
- *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
- break;
-
- case mmMC_SEQ_WR_CTL_D1:
- *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
- break;
-
- case mmMC_PMG_CMD_EMRS:
- *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
- break;
-
- case mmMC_PMG_CMD_MRS:
- *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
- break;
-
- case mmMC_PMG_CMD_MRS1:
- *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
- break;
-
- case mmMC_SEQ_PMG_TIMING:
- *out_reg = mmMC_SEQ_PMG_TIMING_LP;
- break;
-
- case mmMC_PMG_CMD_MRS2:
- *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
- break;
-
- case mmMC_SEQ_WR_CTL_2:
- *out_reg = mmMC_SEQ_WR_CTL_2_LP;
- break;
-
- default:
- result = false;
- break;
- }
-
- return result;
-}
-
-static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)
-{
- uint32_t i;
- uint16_t address;
-
- for (i = 0; i < table->last; i++) {
- table->mc_reg_address[i].s0 =
- iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
- ? address : table->mc_reg_address[i].s1;
- }
- return 0;
-}
-
-static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
- struct iceland_mc_reg_table *ni_table)
-{
- uint8_t i, j;
-
- PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
- "Invalid VramInfo table.", return -EINVAL);
-
- for (i = 0; i < table->last; i++) {
- ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
- }
- ni_table->last = table->last;
-
- for (i = 0; i < table->num_entries; i++) {
- ni_table->mc_reg_table_entry[i].mclk_max =
- table->mc_reg_table_entry[i].mclk_max;
- for (j = 0; j < table->last; j++) {
- ni_table->mc_reg_table_entry[i].mc_data[j] =
- table->mc_reg_table_entry[i].mc_data[j];
- }
- }
-
- ni_table->num_entries = table->num_entries;
-
- return 0;
-}
-
-/**
- * VBIOS omits some information to reduce size, we need to recover them here.
- * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
- * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
- * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
- * 3. need to set these data for each clock range
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @param table the address of MCRegTable
- * @return always 0
- */
-static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
- struct iceland_mc_reg_table *table)
-{
- uint8_t i, j, k;
- uint32_t temp_reg;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- for (i = 0, j = table->last; i < table->last; i++) {
- PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
-
- switch (table->mc_reg_address[i].s1) {
-
- case mmMC_SEQ_MISC1:
- temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
- table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
- table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
- for (k = 0; k < table->num_entries; k++) {
- table->mc_reg_table_entry[k].mc_data[j] =
- ((temp_reg & 0xffff0000)) |
- ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
- }
- j++;
- PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
-
- temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
- table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
- table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
- for (k = 0; k < table->num_entries; k++) {
- table->mc_reg_table_entry[k].mc_data[j] =
- (temp_reg & 0xffff0000) |
- (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-
- if (!data->is_memory_gddr5) {
- table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
- }
- }
- j++;
- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
-
- if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
- table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
- table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
- for (k = 0; k < table->num_entries; k++) {
- table->mc_reg_table_entry[k].mc_data[j] =
- (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
- }
- j++;
- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- }
-
- break;
-
- case mmMC_SEQ_RESERVE_M:
- temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
- table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
- table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
- for (k = 0; k < table->num_entries; k++) {
- table->mc_reg_table_entry[k].mc_data[j] =
- (temp_reg & 0xffff0000) |
- (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
- }
- j++;
- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- break;
-
- default:
- break;
- }
-
- }
-
- table->last = j;
-
- return 0;
-}
-
-static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
-{
- uint8_t i, j;
- for (i = 0; i < table->last; i++) {
- for (j = 1; j < table->num_entries; j++) {
- if (table->mc_reg_table_entry[j-1].mc_data[i] !=
- table->mc_reg_table_entry[j].mc_data[i]) {
- table->validflag |= (1<<i);
- break;
- }
- }
- }
-
- return 0;
-}
-
-int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
- pp_atomctrl_mc_reg_table *table;
- struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
- uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
-
- table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
-
- if (NULL == table)
- return -ENOMEM;
-
- /* Program additional LP registers that are no longer programmed by VBIOS */
- cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
- cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
- cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
- cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
- cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
- cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
- cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
-
- memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-
- result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
-
- if (0 == result)
- result = iceland_copy_vbios_smc_reg_table(table, ni_table);
-
- if (0 == result) {
- iceland_set_s0_mc_reg_index(ni_table);
- result = iceland_set_mc_special_registers(hwmgr, ni_table);
- }
-
- if (0 == result)
- iceland_set_valid_flag(ni_table);
-
- kfree(table);
-
- return result;
-}
-
-bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
-{
- return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
- ? true : false;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.h
deleted file mode 100644
index 13c8dbb..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _ICELAND_SMC_H
-#define _ICELAND_SMC_H
-
-#include "smumgr.h"
-
-
-int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
-int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
-int iceland_init_smc_table(struct pp_hwmgr *hwmgr);
-int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
-int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr);
-uint32_t iceland_get_offsetof(uint32_t type, uint32_t member);
-uint32_t iceland_get_mac_definition(uint32_t value);
-int iceland_process_firmware_header(struct pp_hwmgr *hwmgr);
-int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
-bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr);
-#endif
-
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 0bf2def..3412882 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -30,64 +30,133 @@
#include "smumgr.h"
#include "iceland_smumgr.h"
-#include "smu_ucode_xfer_vi.h"
+
#include "ppsmc.h"
+
+#include "cgs_common.h"
+
+#include "smu7_dyn_defaults.h"
+#include "smu7_hwmgr.h"
+#include "hardwaremanager.h"
+#include "ppatomctrl.h"
+#include "atombios.h"
+#include "pppcielanes.h"
+#include "pp_endian.h"
+#include "processpptables.h"
+
+
#include "smu/smu_7_1_1_d.h"
#include "smu/smu_7_1_1_sh_mask.h"
-#include "cgs_common.h"
-#include "iceland_smc.h"
+#include "smu71_discrete.h"
+
+#include "smu_ucode_xfer_vi.h"
+#include "gmc/gmc_8_1_d.h"
+#include "gmc/gmc_8_1_sh_mask.h"
+#include "bif/bif_5_0_d.h"
+#include "bif/bif_5_0_sh_mask.h"
+#include "dce/dce_10_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+
#define ICELAND_SMC_SIZE 0x20000
-static int iceland_start_smc(struct pp_smumgr *smumgr)
+#define VOLTAGE_SCALE 4
+#define POWERTUNE_DEFAULT_SET_MAX 1
+#define VOLTAGE_VID_OFFSET_SCALE1 625
+#define VOLTAGE_VID_OFFSET_SCALE2 100
+#define MC_CG_ARB_FREQ_F1 0x0b
+#define VDDC_VDDCI_DELTA 200
+
+#define DEVICE_ID_VI_ICELAND_M_6900 0x6900
+#define DEVICE_ID_VI_ICELAND_M_6901 0x6901
+#define DEVICE_ID_VI_ICELAND_M_6902 0x6902
+#define DEVICE_ID_VI_ICELAND_M_6903 0x6903
+
+static const struct iceland_pt_defaults defaults_iceland = {
+ /*
+ * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
+ * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
+ */
+ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
+ { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
+ { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
+};
+
+/* 35W - XT, XTL */
+static const struct iceland_pt_defaults defaults_icelandxt = {
+ /*
+ * sviLoadLIneEn, SviLoadLineVddC,
+ * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
+ * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
+ * BAPM_TEMP_GRADIENT
+ */
+ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
+ { 0xA7, 0x0, 0x0, 0xB5, 0x0, 0x0, 0x9F, 0x0, 0x0, 0xD6, 0x0, 0x0, 0xD7, 0x0, 0x0},
+ { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
+};
+
+/* 25W - PRO, LE */
+static const struct iceland_pt_defaults defaults_icelandpro = {
+ /*
+ * sviLoadLIneEn, SviLoadLineVddC,
+ * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
+ * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
+ * BAPM_TEMP_GRADIENT
+ */
+ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
+ { 0xB7, 0x0, 0x0, 0xC3, 0x0, 0x0, 0xB5, 0x0, 0x0, 0xEA, 0x0, 0x0, 0xE6, 0x0, 0x0},
+ { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
+};
+
+static int iceland_start_smc(struct pp_hwmgr *hwmgr)
{
- SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
return 0;
}
-static void iceland_reset_smc(struct pp_smumgr *smumgr)
+static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
{
- SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL,
rst_reg, 1);
}
-static void iceland_stop_smc_clock(struct pp_smumgr *smumgr)
+static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
{
- SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0,
ck_disable, 1);
}
-static void iceland_start_smc_clock(struct pp_smumgr *smumgr)
+static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
{
- SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0,
ck_disable, 0);
}
-static int iceland_smu_start_smc(struct pp_smumgr *smumgr)
+static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
{
/* set smc instruct start point at 0x0 */
- smu7_program_jump_on_start(smumgr);
+ smu7_program_jump_on_start(hwmgr);
/* enable smc clock */
- iceland_start_smc_clock(smumgr);
+ iceland_start_smc_clock(hwmgr);
/* de-assert reset */
- iceland_start_smc(smumgr);
+ iceland_start_smc(hwmgr);
- SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS,
+ PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
INTERRUPTS_ENABLED, 1);
return 0;
}
-static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
+static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
uint32_t length, const uint8_t *src,
uint32_t limit, uint32_t start_addr)
{
@@ -96,34 +165,34 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
- cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr);
- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
+ cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
while (byte_count >= 4) {
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
- cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4;
byte_count -= 4;
}
- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
- PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
+ PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
return 0;
}
-static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
+static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
{
uint32_t val;
struct cgs_firmware_info info = {0};
- if (smumgr == NULL || smumgr->device == NULL)
+ if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
/* load SMC firmware */
- cgs_get_firmware_info(smumgr->device,
+ cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
if (info.image_size & 3) {
@@ -137,68 +206,61 @@ static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
}
/* wait for smc boot up */
- SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
+ PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
/* clear firmware interrupt enable flag */
- val = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMC_SYSCON_MISC_CNTL);
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMC_SYSCON_MISC_CNTL, val | 1);
/* stop smc clock */
- iceland_stop_smc_clock(smumgr);
+ iceland_stop_smc_clock(hwmgr);
/* reset smc */
- iceland_reset_smc(smumgr);
- iceland_upload_smc_firmware_data(smumgr, info.image_size,
+ iceland_reset_smc(hwmgr);
+ iceland_upload_smc_firmware_data(hwmgr, info.image_size,
(uint8_t *)info.kptr, ICELAND_SMC_SIZE,
info.ucode_start_address);
return 0;
}
-static int iceland_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
+static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
uint32_t firmwareType)
{
return 0;
}
-static int iceland_start_smu(struct pp_smumgr *smumgr)
+static int iceland_start_smu(struct pp_hwmgr *hwmgr)
{
int result;
- result = iceland_smu_upload_firmware_image(smumgr);
+ result = iceland_smu_upload_firmware_image(hwmgr);
if (result)
return result;
- result = iceland_smu_start_smc(smumgr);
+ result = iceland_smu_start_smc(hwmgr);
if (result)
return result;
- if (!smu7_is_smc_ram_running(smumgr)) {
+ if (!smu7_is_smc_ram_running(hwmgr)) {
pr_info("smu not running, upload firmware again \n");
- result = iceland_smu_upload_firmware_image(smumgr);
+ result = iceland_smu_upload_firmware_image(hwmgr);
if (result)
return result;
- result = iceland_smu_start_smc(smumgr);
+ result = iceland_smu_start_smc(hwmgr);
if (result)
return result;
}
- result = smu7_request_smu_load_fw(smumgr);
+ result = smu7_request_smu_load_fw(hwmgr);
return result;
}
-/**
- * Write a 32bit value to the SMC SRAM space.
- * ALL PARAMETERS ARE IN HOST BYTE ORDER.
- * @param smumgr the address of the powerplay hardware manager.
- * @param smcAddress the address in the SMC RAM to access.
- * @param value to write to the SMC SRAM.
- */
-static int iceland_smu_init(struct pp_smumgr *smumgr)
+static int iceland_smu_init(struct pp_hwmgr *hwmgr)
{
int i;
struct iceland_smumgr *iceland_priv = NULL;
@@ -208,9 +270,9 @@ static int iceland_smu_init(struct pp_smumgr *smumgr)
if (iceland_priv == NULL)
return -ENOMEM;
- smumgr->backend = iceland_priv;
+ hwmgr->smu_backend = iceland_priv;
- if (smu7_init(smumgr))
+ if (smu7_init(hwmgr))
return -EINVAL;
for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
@@ -219,6 +281,2413 @@ static int iceland_smu_init(struct pp_smumgr *smumgr)
return 0;
}
+
+static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
+{
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ struct cgs_system_info sys_info = {0};
+ uint32_t dev_id;
+
+ sys_info.size = sizeof(struct cgs_system_info);
+ sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
+ cgs_query_system_info(hwmgr->device, &sys_info);
+ dev_id = (uint32_t)sys_info.value;
+
+ switch (dev_id) {
+ case DEVICE_ID_VI_ICELAND_M_6900:
+ case DEVICE_ID_VI_ICELAND_M_6903:
+ smu_data->power_tune_defaults = &defaults_icelandxt;
+ break;
+
+ case DEVICE_ID_VI_ICELAND_M_6901:
+ case DEVICE_ID_VI_ICELAND_M_6902:
+ smu_data->power_tune_defaults = &defaults_icelandpro;
+ break;
+ default:
+ smu_data->power_tune_defaults = &defaults_iceland;
+ pr_warn("Unknown V.I. Device ID.\n");
+ break;
+ }
+ return;
+}
+
+static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
+{
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
+ smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
+ smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
+ smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
+
+ return 0;
+}
+
+static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
+{
+ uint16_t tdc_limit;
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
+ smu_data->power_tune_table.TDC_VDDC_PkgLimit =
+ CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
+ smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
+ defaults->tdc_vddc_throttle_release_limit_perc;
+ smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
+
+ return 0;
+}
+
+static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
+{
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
+ uint32_t temp;
+
+ if (smu7_read_smc_sram_dword(hwmgr,
+ fuse_table_offset +
+ offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
+ (uint32_t *)&temp, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
+ return -EINVAL);
+ else
+ smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
+
+ return 0;
+}
+
+static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
+{
+ return 0;
+}
+
+static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+
+ /* Currently not used. Set all to zero. */
+ for (i = 0; i < 8; i++)
+ smu_data->power_tune_table.GnbLPML[i] = 0;
+
+ return 0;
+}
+
+static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+{
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
+ uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
+ struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
+
+ HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
+ LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
+
+ smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
+ smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
+
+ return 0;
+}
+
+static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
+ uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
+
+ PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
+ "The CAC Leakage table does not exist!", return -EINVAL);
+ PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
+ "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
+ PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
+ "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
+ for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
+ lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
+ hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
+ }
+ } else {
+ PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
+ }
+
+ return 0;
+}
+
+static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ uint8_t *vid = smu_data->power_tune_table.VddCVid;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
+ "There should never be more than 8 entries for VddcVid!!!",
+ return -EINVAL);
+
+ for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
+ vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
+ }
+
+ return 0;
+}
+
+
+
+static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
+{
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ uint32_t pm_fuse_table_offset;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment)) {
+ if (smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, PmFuseTable),
+ &pm_fuse_table_offset, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to get pm_fuse_table_offset Failed!",
+ return -EINVAL);
+
+ /* DW0 - DW3 */
+ if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate bapm vddc vid Failed!",
+ return -EINVAL);
+
+ /* DW4 - DW5 */
+ if (iceland_populate_vddc_vid(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate vddc vid Failed!",
+ return -EINVAL);
+
+ /* DW6 */
+ if (iceland_populate_svi_load_line(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate SviLoadLine Failed!",
+ return -EINVAL);
+ /* DW7 */
+ if (iceland_populate_tdc_limit(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TDCLimit Failed!", return -EINVAL);
+ /* DW8 */
+ if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TdcWaterfallCtl, "
+ "LPMLTemperature Min and Max Failed!",
+ return -EINVAL);
+
+ /* DW9-DW12 */
+ if (0 != iceland_populate_temperature_scaler(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate LPMLTemperatureScaler Failed!",
+ return -EINVAL);
+
+ /* DW13-DW16 */
+ if (iceland_populate_gnb_lpml(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate GnbLPML Failed!",
+ return -EINVAL);
+
+ /* DW18 */
+ if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
+ return -EINVAL);
+
+ if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
+ (uint8_t *)&smu_data->power_tune_table,
+ sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to download PmFuseTable Failed!",
+ return -EINVAL);
+ }
+ return 0;
+}
+
+static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
+ struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
+ uint32_t clock, uint32_t *vol)
+{
+ uint32_t i = 0;
+
+ /* clock - voltage dependency table is empty table */
+ if (allowed_clock_voltage_table->count == 0)
+ return -EINVAL;
+
+ for (i = 0; i < allowed_clock_voltage_table->count; i++) {
+ /* find first sclk bigger than request */
+ if (allowed_clock_voltage_table->entries[i].clk >= clock) {
+ *vol = allowed_clock_voltage_table->entries[i].v;
+ return 0;
+ }
+ }
+
+ /* sclk is bigger than max sclk in the dependence table */
+ *vol = allowed_clock_voltage_table->entries[i - 1].v;
+
+ return 0;
+}
+
+static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
+ pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
+ uint16_t *lo)
+{
+ uint16_t v_index;
+ bool vol_found = false;
+ *hi = tab->value * VOLTAGE_SCALE;
+ *lo = tab->value * VOLTAGE_SCALE;
+
+ /* SCLK/VDDC Dependency Table has to exist. */
+ PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
+ "The SCLK/VDDC Dependency Table does not exist.\n",
+ return -EINVAL);
+
+ if (NULL == hwmgr->dyn_state.cac_leakage_table) {
+ pr_warn("CAC Leakage Table does not exist, using vddc.\n");
+ return 0;
+ }
+
+ /*
+ * Since voltage in the sclk/vddc dependency table is not
+ * necessarily in ascending order because of ELB voltage
+ * patching, loop through entire list to find exact voltage.
+ */
+ for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
+ if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
+ vol_found = true;
+ if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
+ } else {
+ pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
+ }
+ break;
+ }
+ }
+
+ /*
+ * If voltage is not found in the first pass, loop again to
+ * find the best match, equal or higher value.
+ */
+ if (!vol_found) {
+ for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
+ if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
+ vol_found = true;
+ if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
+ } else {
+ pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
+ *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
+ *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
+ }
+ break;
+ }
+ }
+
+ if (!vol_found)
+ pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
+ }
+
+ return 0;
+}
+
+static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
+ pp_atomctrl_voltage_table_entry *tab,
+ SMU71_Discrete_VoltageLevel *smc_voltage_tab)
+{
+ int result;
+
+ result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
+ &smc_voltage_tab->StdVoltageHiSidd,
+ &smc_voltage_tab->StdVoltageLoSidd);
+ if (0 != result) {
+ smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
+ smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
+ }
+
+ smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
+ CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
+ CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
+
+ return 0;
+}
+
+static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ unsigned int count;
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ table->VddcLevelCount = data->vddc_voltage_table.count;
+ for (count = 0; count < table->VddcLevelCount; count++) {
+ result = iceland_populate_smc_voltage_table(hwmgr,
+ &(data->vddc_voltage_table.entries[count]),
+ &(table->VddcLevel[count]));
+ PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
+
+ /* GPIO voltage control */
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
+ table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
+ else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
+ table->VddcLevel[count].Smio = 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
+
+ return 0;
+}
+
+static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t count;
+ int result;
+
+ table->VddciLevelCount = data->vddci_voltage_table.count;
+
+ for (count = 0; count < table->VddciLevelCount; count++) {
+ result = iceland_populate_smc_voltage_table(hwmgr,
+ &(data->vddci_voltage_table.entries[count]),
+ &(table->VddciLevel[count]));
+ PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
+ table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
+ else
+ table->VddciLevel[count].Smio |= 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
+
+ return 0;
+}
+
+static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t count;
+ int result;
+
+ table->MvddLevelCount = data->mvdd_voltage_table.count;
+
+ for (count = 0; count < table->VddciLevelCount; count++) {
+ result = iceland_populate_smc_voltage_table(hwmgr,
+ &(data->mvdd_voltage_table.entries[count]),
+ &table->MvddLevel[count]);
+ PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
+ table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
+ else
+ table->MvddLevel[count].Smio |= 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
+
+ return 0;
+}
+
+
+static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ int result;
+
+ result = iceland_populate_smc_vddc_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "can not populate VDDC voltage table to SMC", return -EINVAL);
+
+ result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "can not populate VDDCI voltage table to SMC", return -EINVAL);
+
+ result = iceland_populate_smc_mvdd_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "can not populate MVDD voltage table to SMC", return -EINVAL);
+
+ return 0;
+}
+
+static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
+ struct SMU71_Discrete_Ulv *state)
+{
+ uint32_t voltage_response_time, ulv_voltage;
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ state->CcPwrDynRm = 0;
+ state->CcPwrDynRm1 = 0;
+
+ result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
+ PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
+
+ if (ulv_voltage == 0) {
+ data->ulv_supported = false;
+ return 0;
+ }
+
+ if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
+ /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
+ if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
+ state->VddcOffset = 0;
+ else
+ /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
+ state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
+ } else {
+ /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
+ if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
+ state->VddcOffsetVid = 0;
+ else /* used in SVI2 Mode */
+ state->VddcOffsetVid = (uint8_t)(
+ (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
+ * VOLTAGE_VID_OFFSET_SCALE2
+ / VOLTAGE_VID_OFFSET_SCALE1);
+ }
+ state->VddcPhase = 1;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
+ CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
+
+ return 0;
+}
+
+static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_Ulv *ulv_level)
+{
+ return iceland_populate_ulv_level(hwmgr, ulv_level);
+}
+
+static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ uint32_t i;
+
+ /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
+ for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
+ table->LinkLevel[i].PcieGenSpeed =
+ (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
+ table->LinkLevel[i].PcieLaneCount =
+ (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
+ table->LinkLevel[i].EnabledForActivity =
+ 1;
+ table->LinkLevel[i].SPC =
+ (uint8_t)(data->pcie_spc_cap & 0xff);
+ table->LinkLevel[i].DownThreshold =
+ PP_HOST_TO_SMC_UL(5);
+ table->LinkLevel[i].UpThreshold =
+ PP_HOST_TO_SMC_UL(30);
+ }
+
+ smu_data->smc_state_table.LinkLevelCount =
+ (uint8_t)dpm_table->pcie_speed_table.count;
+ data->dpm_level_enable_mask.pcie_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
+
+ return 0;
+}
+
+static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
+ uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ pp_atomctrl_clock_dividers_vi dividers;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ uint32_t reference_clock;
+ uint32_t reference_divider;
+ uint32_t fbdiv;
+ int result;
+
+ /* get the engine clock dividers for this clock value*/
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.", return result);
+
+ /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
+ reference_clock = atomctrl_get_reference_clock(hwmgr);
+
+ reference_divider = 1 + dividers.uc_pll_ref_div;
+
+ /* low 14 bits is fraction and high 12 bits is divider*/
+ fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
+
+ /* SPLL_FUNC_CNTL setup*/
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
+
+ /* SPLL_FUNC_CNTL_3 setup*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
+ CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
+
+ /* set to use fractional accumulation*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
+ CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
+ pp_atomctrl_internal_ss_info ss_info;
+
+ uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
+ if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
+ /*
+ * ss_info.speed_spectrum_percentage -- in unit of 0.01%
+ * ss_info.speed_spectrum_rate -- in unit of khz
+ */
+ /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
+ uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
+
+ /* clkv = 2 * D * fbdiv / NS */
+ uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
+
+ cg_spll_spread_spectrum =
+ PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
+ cg_spll_spread_spectrum =
+ PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
+ cg_spll_spread_spectrum_2 =
+ PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
+ }
+ }
+
+ sclk->SclkFrequency = engine_clock;
+ sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
+ sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
+ sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
+ sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
+ sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
+
+ return 0;
+}
+
+static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
+ const struct phm_phase_shedding_limits_table *pl,
+ uint32_t sclk, uint32_t *p_shed)
+{
+ unsigned int i;
+
+ /* use the minimum phase shedding */
+ *p_shed = 1;
+
+ for (i = 0; i < pl->count; i++) {
+ if (sclk < pl->entries[i].Sclk) {
+ *p_shed = i;
+ break;
+ }
+ }
+ return 0;
+}
+
+static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ uint32_t engine_clock,
+ uint16_t sclk_activity_level_threshold,
+ SMU71_Discrete_GraphicsLevel *graphic_level)
+{
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
+
+ /* populate graphics levels*/
+ result = iceland_get_dependency_volt_by_clk(hwmgr,
+ hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
+ &graphic_level->MinVddc);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find VDDC voltage value for VDDC \
+ engine clock dependency table", return result);
+
+ /* SCLK frequency in units of 10KHz*/
+ graphic_level->SclkFrequency = engine_clock;
+ graphic_level->MinVddcPhases = 1;
+
+ if (data->vddc_phase_shed_control)
+ iceland_populate_phase_value_based_on_sclk(hwmgr,
+ hwmgr->dyn_state.vddc_phase_shed_limits_table,
+ engine_clock,
+ &graphic_level->MinVddcPhases);
+
+ /* Indicates maximum activity level for this performance level. 50% for now*/
+ graphic_level->ActivityLevel = sclk_activity_level_threshold;
+
+ graphic_level->CcPwrDynRm = 0;
+ graphic_level->CcPwrDynRm1 = 0;
+ /* this level can be used if activity is high enough.*/
+ graphic_level->EnabledForActivity = 0;
+ /* this level can be used for throttling.*/
+ graphic_level->EnabledForThrottle = 1;
+ graphic_level->UpHyst = 0;
+ graphic_level->DownHyst = 100;
+ graphic_level->VoltageDownHyst = 0;
+ graphic_level->PowerThrottle = 0;
+
+ data->display_timing.min_clock_in_sr =
+ hwmgr->display_config.min_core_set_clock_in_sr;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkDeepSleep))
+ graphic_level->DeepSleepDivId =
+ smu7_get_sleep_divider_id_from_clock(engine_clock,
+ data->display_timing.min_clock_in_sr);
+
+ /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
+ graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ if (0 == result) {
+ graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
+ }
+
+ return result;
+}
+
+static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
+
+ uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *
+ SMU71_MAX_LEVELS_GRAPHICS;
+
+ SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
+
+ uint32_t i;
+ uint8_t highest_pcie_level_enabled = 0;
+ uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
+ uint8_t count = 0;
+ int result = 0;
+
+ memset(levels, 0x00, level_array_size);
+
+ for (i = 0; i < dpm_table->sclk_table.count; i++) {
+ result = iceland_populate_single_graphic_level(hwmgr,
+ dpm_table->sclk_table.dpm_levels[i].value,
+ (uint16_t)smu_data->activity_target[i],
+ &(smu_data->smc_state_table.GraphicsLevel[i]));
+ if (result != 0)
+ return result;
+
+ /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
+ if (i > 1)
+ smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
+ }
+
+ /* Only enable level 0 for now. */
+ smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
+
+ /* set highest level watermark to high */
+ if (dpm_table->sclk_table.count > 1)
+ smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
+ PPSMC_DISPLAY_WATERMARK_HIGH;
+
+ smu_data->smc_state_table.GraphicsDpmLevelCount =
+ (uint8_t)dpm_table->sclk_table.count;
+ data->dpm_level_enable_mask.sclk_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
+
+ while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << (highest_pcie_level_enabled + 1))) != 0) {
+ highest_pcie_level_enabled++;
+ }
+
+ while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << lowest_pcie_level_enabled)) == 0) {
+ lowest_pcie_level_enabled++;
+ }
+
+ while ((count < highest_pcie_level_enabled) &&
+ ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
+ count++;
+ }
+
+ mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
+ (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
+
+
+ /* set pcieDpmLevel to highest_pcie_level_enabled*/
+ for (i = 2; i < dpm_table->sclk_table.count; i++) {
+ smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
+ }
+
+ /* set pcieDpmLevel to lowest_pcie_level_enabled*/
+ smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to mid_pcie_level_enabled*/
+ smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
+
+ /* level count will send to smc once at init smc table and never change*/
+ result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
+ (uint8_t *)levels, (uint32_t)level_array_size,
+ SMC_RAM_END);
+
+ return result;
+}
+
+static int iceland_calculate_mclk_params(
+ struct pp_hwmgr *hwmgr,
+ uint32_t memory_clock,
+ SMU71_Discrete_MemoryLevel *mclk,
+ bool strobe_mode,
+ bool dllStateOn
+ )
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
+ uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
+ uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
+ uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
+ uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
+ uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
+ uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
+ uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
+ uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
+
+ pp_atomctrl_memory_clock_param mpll_param;
+ int result;
+
+ result = atomctrl_get_memory_pll_dividers_si(hwmgr,
+ memory_clock, &mpll_param, strobe_mode);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Error retrieving Memory Clock Parameters from VBIOS.", return result);
+
+ /* MPLL_FUNC_CNTL setup*/
+ mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
+
+ /* MPLL_FUNC_CNTL_1 setup*/
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
+
+ /* MPLL_AD_FUNC_CNTL setup*/
+ mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
+ MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
+
+ if (data->is_memory_gddr5) {
+ /* MPLL_DQ_FUNC_CNTL setup*/
+ mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
+ MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
+ mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
+ MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
+ }
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
+ /*
+ ************************************
+ Fref = Reference Frequency
+ NF = Feedback divider ratio
+ NR = Reference divider ratio
+ Fnom = Nominal VCO output frequency = Fref * NF / NR
+ Fs = Spreading Rate
+ D = Percentage down-spread / 2
+ Fint = Reference input frequency to PFD = Fref / NR
+ NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
+ CLKS = NS - 1 = ISS_STEP_NUM[11:0]
+ NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
+ CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
+ *************************************
+ */
+ pp_atomctrl_internal_ss_info ss_info;
+ uint32_t freq_nom;
+ uint32_t tmp;
+ uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
+
+ /* for GDDR5 for all modes and DDR3 */
+ if (1 == mpll_param.qdr)
+ freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
+ else
+ freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
+
+ /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
+ tmp = (freq_nom / reference_clock);
+ tmp = tmp * tmp;
+
+ if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
+ /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
+ /* ss.Info.speed_spectrum_rate -- in unit of khz */
+ /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
+ /* = reference_clock * 5 / speed_spectrum_rate */
+ uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
+
+ /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
+ /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
+ uint32_t clkv =
+ (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
+ ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
+
+ mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
+ mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
+ }
+ }
+
+ /* MCLK_PWRMGT_CNTL setup */
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
+
+
+ /* Save the result data to outpupt memory level structure */
+ mclk->MclkFrequency = memory_clock;
+ mclk->MpllFuncCntl = mpll_func_cntl;
+ mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
+ mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
+ mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
+ mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
+ mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
+ mclk->DllCntl = dll_cntl;
+ mclk->MpllSs1 = mpll_ss1;
+ mclk->MpllSs2 = mpll_ss2;
+
+ return 0;
+}
+
+static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
+ bool strobe_mode)
+{
+ uint8_t mc_para_index;
+
+ if (strobe_mode) {
+ if (memory_clock < 12500) {
+ mc_para_index = 0x00;
+ } else if (memory_clock > 47500) {
+ mc_para_index = 0x0f;
+ } else {
+ mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
+ }
+ } else {
+ if (memory_clock < 65000) {
+ mc_para_index = 0x00;
+ } else if (memory_clock > 135000) {
+ mc_para_index = 0x0f;
+ } else {
+ mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
+ }
+ }
+
+ return mc_para_index;
+}
+
+static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
+{
+ uint8_t mc_para_index;
+
+ if (memory_clock < 10000) {
+ mc_para_index = 0;
+ } else if (memory_clock >= 80000) {
+ mc_para_index = 0x0f;
+ } else {
+ mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
+ }
+
+ return mc_para_index;
+}
+
+static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
+ uint32_t memory_clock, uint32_t *p_shed)
+{
+ unsigned int i;
+
+ *p_shed = 1;
+
+ for (i = 0; i < pl->count; i++) {
+ if (memory_clock < pl->entries[i].Mclk) {
+ *p_shed = i;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int iceland_populate_single_memory_level(
+ struct pp_hwmgr *hwmgr,
+ uint32_t memory_clock,
+ SMU71_Discrete_MemoryLevel *memory_level
+ )
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ int result = 0;
+ bool dll_state_on;
+ struct cgs_display_info info = {0};
+ uint32_t mclk_edc_wr_enable_threshold = 40000;
+ uint32_t mclk_edc_enable_threshold = 40000;
+ uint32_t mclk_strobe_mode_threshold = 40000;
+
+ if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
+ result = iceland_get_dependency_volt_by_clk(hwmgr,
+ hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
+ }
+
+ if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
+ memory_level->MinVddci = memory_level->MinVddc;
+ } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
+ result = iceland_get_dependency_volt_by_clk(hwmgr,
+ hwmgr->dyn_state.vddci_dependency_on_mclk,
+ memory_clock,
+ &memory_level->MinVddci);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
+ }
+
+ memory_level->MinVddcPhases = 1;
+
+ if (data->vddc_phase_shed_control) {
+ iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
+ memory_clock, &memory_level->MinVddcPhases);
+ }
+
+ memory_level->EnabledForThrottle = 1;
+ memory_level->EnabledForActivity = 0;
+ memory_level->UpHyst = 0;
+ memory_level->DownHyst = 100;
+ memory_level->VoltageDownHyst = 0;
+
+ /* Indicates maximum activity level for this performance level.*/
+ memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+ memory_level->StutterEnable = 0;
+ memory_level->StrobeEnable = 0;
+ memory_level->EdcReadEnable = 0;
+ memory_level->EdcWriteEnable = 0;
+ memory_level->RttEnable = 0;
+
+ /* default set to low watermark. Highest level will be set to high later.*/
+ memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ cgs_get_active_displays_info(hwmgr->device, &info);
+ data->display_timing.num_existing_displays = info.display_count;
+
+ /* stutter mode not support on iceland */
+
+ /* decide strobe mode*/
+ memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
+ (memory_clock <= mclk_strobe_mode_threshold);
+
+ /* decide EDC mode and memory clock ratio*/
+ if (data->is_memory_gddr5) {
+ memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
+ memory_level->StrobeEnable);
+
+ if ((mclk_edc_enable_threshold != 0) &&
+ (memory_clock > mclk_edc_enable_threshold)) {
+ memory_level->EdcReadEnable = 1;
+ }
+
+ if ((mclk_edc_wr_enable_threshold != 0) &&
+ (memory_clock > mclk_edc_wr_enable_threshold)) {
+ memory_level->EdcWriteEnable = 1;
+ }
+
+ if (memory_level->StrobeEnable) {
+ if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
+ ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
+ else
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
+ } else
+ dll_state_on = data->dll_default_on;
+ } else {
+ memory_level->StrobeRatio =
+ iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
+ }
+
+ result = iceland_calculate_mclk_params(hwmgr,
+ memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
+
+ if (0 == result) {
+ memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
+ memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
+ memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
+ /* MCLK frequency in units of 10KHz*/
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
+ /* Indicates maximum activity level for this performance level.*/
+ CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
+ }
+
+ return result;
+}
+
+static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ int result;
+
+ /* populate MCLK dpm table to SMU7 */
+ uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
+ uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
+ SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
+ uint32_t i;
+
+ memset(levels, 0x00, level_array_size);
+
+ for (i = 0; i < dpm_table->mclk_table.count; i++) {
+ PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
+ "can not populate memory level as memory clock is zero", return -EINVAL);
+ result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
+ &(smu_data->smc_state_table.MemoryLevel[i]));
+ if (0 != result) {
+ return result;
+ }
+ }
+
+ /* Only enable level 0 for now.*/
+ smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
+
+ /*
+ * in order to prevent MC activity from stutter mode to push DPM up.
+ * the UVD change complements this by putting the MCLK in a higher state
+ * by default such that we are not effected by up threshold or and MCLK DPM latency.
+ */
+ smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
+
+ smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
+ data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
+ /* set highest level watermark to high*/
+ smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
+
+ /* level count will send to smc once at init smc table and never change*/
+ result = smu7_copy_bytes_to_smc(hwmgr,
+ level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
+ SMC_RAM_END);
+
+ return result;
+}
+
+static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
+ SMU71_Discrete_VoltageLevel *voltage)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ uint32_t i = 0;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
+ /* find mvdd value which clock is more than request */
+ for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
+ if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
+ /* Always round to higher voltage. */
+ voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
+ break;
+ }
+ }
+
+ PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
+ "MVDD Voltage is outside the supported range.", return -EINVAL);
+
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ int result = 0;
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ uint32_t vddc_phase_shed_control = 0;
+
+ SMU71_Discrete_VoltageLevel voltage_level;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
+ uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
+ uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
+
+
+ /* The ACPI state should not do DPM on DC (or ever).*/
+ table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
+
+ if (data->acpi_vddc)
+ table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
+ else
+ table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
+
+ table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
+ /* assign zero for now*/
+ table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
+
+ /* get the engine clock dividers for this clock value*/
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
+ table->ACPILevel.SclkFrequency, ÷rs);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.", return result);
+
+ /* divider ID for required SCLK*/
+ table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
+ table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+ table->ACPILevel.DeepSleepDivId = 0;
+
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
+ spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
+ CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
+
+ table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
+ table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
+ table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ table->ACPILevel.CcPwrDynRm = 0;
+ table->ACPILevel.CcPwrDynRm1 = 0;
+
+
+ /* For various features to be enabled/disabled while this level is active.*/
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
+ /* SCLK frequency in units of 10KHz*/
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
+
+ /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
+ table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
+ table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
+ else {
+ if (data->acpi_vddci != 0)
+ table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
+ else
+ table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
+ }
+
+ if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
+ table->MemoryACPILevel.MinMvdd =
+ PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
+ else
+ table->MemoryACPILevel.MinMvdd = 0;
+
+ /* Force reset on DLL*/
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
+
+ /* Disable DLL in ACPIState*/
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
+
+ /* Enable DLL bypass signal*/
+ dll_cntl = PHM_SET_FIELD(dll_cntl,
+ DLL_CNTL, MRDCK0_BYPASS, 0);
+ dll_cntl = PHM_SET_FIELD(dll_cntl,
+ DLL_CNTL, MRDCK1_BYPASS, 0);
+
+ table->MemoryACPILevel.DllCntl =
+ PP_HOST_TO_SMC_UL(dll_cntl);
+ table->MemoryACPILevel.MclkPwrmgtCntl =
+ PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
+ table->MemoryACPILevel.MpllAdFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
+ table->MemoryACPILevel.MpllDqFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
+ table->MemoryACPILevel.MpllFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
+ table->MemoryACPILevel.MpllFuncCntl_1 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
+ table->MemoryACPILevel.MpllFuncCntl_2 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
+ table->MemoryACPILevel.MpllSs1 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
+ table->MemoryACPILevel.MpllSs2 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
+
+ table->MemoryACPILevel.EnabledForThrottle = 0;
+ table->MemoryACPILevel.EnabledForActivity = 0;
+ table->MemoryACPILevel.UpHyst = 0;
+ table->MemoryACPILevel.DownHyst = 100;
+ table->MemoryACPILevel.VoltageDownHyst = 0;
+ /* Indicates maximum activity level for this performance level.*/
+ table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+
+ table->MemoryACPILevel.StutterEnable = 0;
+ table->MemoryACPILevel.StrobeEnable = 0;
+ table->MemoryACPILevel.EdcReadEnable = 0;
+ table->MemoryACPILevel.EdcWriteEnable = 0;
+ table->MemoryACPILevel.RttEnable = 0;
+
+ return result;
+}
+
+static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ return 0;
+}
+
+static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ return 0;
+}
+
+static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ return 0;
+}
+
+static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ return 0;
+}
+
+static int iceland_populate_memory_timing_parameters(
+ struct pp_hwmgr *hwmgr,
+ uint32_t engine_clock,
+ uint32_t memory_clock,
+ struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
+ )
+{
+ uint32_t dramTiming;
+ uint32_t dramTiming2;
+ uint32_t burstTime;
+ int result;
+
+ result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
+ engine_clock, memory_clock);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error calling VBIOS to set DRAM_TIMING.", return result);
+
+ dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
+ dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
+ burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
+
+ arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
+ arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
+ arb_regs->McArbBurstTime = (uint8_t)burstTime;
+
+ return 0;
+}
+
+static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ int result = 0;
+ SMU71_Discrete_MCArbDramTimingTable arb_regs;
+ uint32_t i, j;
+
+ memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
+
+ for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
+ for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
+ result = iceland_populate_memory_timing_parameters
+ (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
+ data->dpm_table.mclk_table.dpm_levels[j].value,
+ &arb_regs.entries[i][j]);
+
+ if (0 != result) {
+ break;
+ }
+ }
+ }
+
+ if (0 == result) {
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.arb_table_start,
+ (uint8_t *)&arb_regs,
+ sizeof(SMU71_Discrete_MCArbDramTimingTable),
+ SMC_RAM_END
+ );
+ }
+
+ return result;
+}
+
+static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *table)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ table->GraphicsBootLevel = 0;
+ table->MemoryBootLevel = 0;
+
+ /* find boot level from dpm table*/
+ result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+ data->vbios_boot_state.sclk_bootup_value,
+ (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
+
+ if (0 != result) {
+ smu_data->smc_state_table.GraphicsBootLevel = 0;
+ pr_err("VBIOS did not find boot engine clock value \
+ in dependency table. Using Graphics DPM level 0!");
+ result = 0;
+ }
+
+ result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+ data->vbios_boot_state.mclk_bootup_value,
+ (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
+
+ if (0 != result) {
+ smu_data->smc_state_table.MemoryBootLevel = 0;
+ pr_err("VBIOS did not find boot engine clock value \
+ in dependency table. Using Memory DPM level 0!");
+ result = 0;
+ }
+
+ table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ table->BootVddci = table->BootVddc;
+ else
+ table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
+
+ table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
+
+ return result;
+}
+
+static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_MCRegisters *mc_reg_table)
+{
+ const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
+
+ uint32_t i, j;
+
+ for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
+ if (smu_data->mc_reg_table.validflag & 1<<j) {
+ PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
+ "Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
+ mc_reg_table->address[i].s0 =
+ PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
+ mc_reg_table->address[i].s1 =
+ PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
+ i++;
+ }
+ }
+
+ mc_reg_table->last = (uint8_t)i;
+
+ return 0;
+}
+
+/*convert register values from driver to SMC format */
+static void iceland_convert_mc_registers(
+ const struct iceland_mc_reg_entry *entry,
+ SMU71_Discrete_MCRegisterSet *data,
+ uint32_t num_entries, uint32_t valid_flag)
+{
+ uint32_t i, j;
+
+ for (i = 0, j = 0; j < num_entries; j++) {
+ if (valid_flag & 1<<j) {
+ data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
+ i++;
+ }
+ }
+}
+
+static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
+ const uint32_t memory_clock,
+ SMU71_Discrete_MCRegisterSet *mc_reg_table_data
+ )
+{
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ uint32_t i = 0;
+
+ for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
+ if (memory_clock <=
+ smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
+ break;
+ }
+ }
+
+ if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
+ --i;
+
+ iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
+ mc_reg_table_data, smu_data->mc_reg_table.last,
+ smu_data->mc_reg_table.validflag);
+
+ return 0;
+}
+
+static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_MCRegisters *mc_regs)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ int res;
+ uint32_t i;
+
+ for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
+ res = iceland_convert_mc_reg_table_entry_to_smc(
+ hwmgr,
+ data->dpm_table.mclk_table.dpm_levels[i].value,
+ &mc_regs->data[i]
+ );
+
+ if (0 != res)
+ result = res;
+ }
+
+ return result;
+}
+
+static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t address;
+ int32_t result;
+
+ if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
+ return 0;
+
+
+ memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
+
+ result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
+
+ if (result != 0)
+ return result;
+
+
+ address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
+
+ return smu7_copy_bytes_to_smc(hwmgr, address,
+ (uint8_t *)&smu_data->mc_regs.data[0],
+ sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
+ SMC_RAM_END);
+}
+
+static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+
+ memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
+ result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize MCRegTable for the MC register addresses!", return result;);
+
+ result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize MCRegTable for driver state!", return result;);
+
+ return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
+ (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
+}
+
+static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ uint8_t count, level;
+
+ count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
+
+ for (level = 0; level < count; level++) {
+ if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
+ >= data->vbios_boot_state.sclk_bootup_value) {
+ smu_data->smc_state_table.GraphicsBootLevel = level;
+ break;
+ }
+ }
+
+ count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
+
+ for (level = 0; level < count; level++) {
+ if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
+ >= data->vbios_boot_state.mclk_bootup_value) {
+ smu_data->smc_state_table.MemoryBootLevel = level;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
+ SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
+ struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
+ struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
+ const uint16_t *def1, *def2;
+ int i, j, k;
+
+
+ /*
+ * TDP number of fraction bits are changed from 8 to 7 for Iceland
+ * as requested by SMC team
+ */
+
+ dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
+ dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
+
+
+ dpm_table->DTETjOffset = 0;
+
+ dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
+ dpm_table->GpuTjHyst = 8;
+
+ dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
+
+ /* The following are for new Iceland Multi-input fan/thermal control */
+ if (NULL != ppm) {
+ dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
+ dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
+ } else {
+ dpm_table->PPM_PkgPwrLimit = 0;
+ dpm_table->PPM_TemperatureLimit = 0;
+ }
+
+ CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
+ CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
+
+ dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
+ def1 = defaults->bapmti_r;
+ def2 = defaults->bapmti_rc;
+
+ for (i = 0; i < SMU71_DTE_ITERATIONS; i++) {
+ for (j = 0; j < SMU71_DTE_SOURCES; j++) {
+ for (k = 0; k < SMU71_DTE_SINKS; k++) {
+ dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
+ dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
+ def1++;
+ def2++;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
+ SMU71_Discrete_DpmTable *tab)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
+ tab->SVI2Enable |= VDDC_ON_SVI2;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
+ tab->SVI2Enable |= VDDCI_ON_SVI2;
+ else
+ tab->MergedVddci = 1;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
+ tab->SVI2Enable |= MVDD_ON_SVI2;
+
+ PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
+ (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
+
+ return 0;
+}
+
+static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+
+
+ iceland_initialize_power_tune_defaults(hwmgr);
+ memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) {
+ iceland_populate_smc_voltage_tables(hwmgr, table);
+ }
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
+
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StepVddc))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
+
+ if (data->is_memory_gddr5)
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
+
+
+ if (data->ulv_supported) {
+ result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ULV state!", return result;);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_ULV_PARAMETER, 0x40035);
+ }
+
+ result = iceland_populate_smc_link_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Link Level!", return result;);
+
+ result = iceland_populate_all_graphic_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Graphics Level!", return result;);
+
+ result = iceland_populate_all_memory_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Memory Level!", return result;);
+
+ result = iceland_populate_smc_acpi_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ACPI Level!", return result;);
+
+ result = iceland_populate_smc_vce_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize VCE Level!", return result;);
+
+ result = iceland_populate_smc_acp_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ACP Level!", return result;);
+
+ result = iceland_populate_smc_samu_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize SAMU Level!", return result;);
+
+ /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
+ /* need to populate the ARB settings for the initial state. */
+ result = iceland_program_memory_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to Write ARB settings for the initial state.", return result;);
+
+ result = iceland_populate_smc_uvd_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize UVD Level!", return result;);
+
+ table->GraphicsBootLevel = 0;
+ table->MemoryBootLevel = 0;
+
+ result = iceland_populate_smc_boot_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Boot Level!", return result;);
+
+ result = iceland_populate_smc_initial_state(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
+
+ result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
+
+ table->GraphicsVoltageChangeEnable = 1;
+ table->GraphicsThermThrottleEnable = 1;
+ table->GraphicsInterval = 1;
+ table->VoltageInterval = 1;
+ table->ThermalInterval = 1;
+
+ table->TemperatureLimitHigh =
+ (data->thermal_temp_setting.temperature_high *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ table->TemperatureLimitLow =
+ (data->thermal_temp_setting.temperature_low *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ table->MemoryVoltageChangeEnable = 1;
+ table->MemoryInterval = 1;
+ table->VoltageResponseTime = 0;
+ table->PhaseResponseTime = 0;
+ table->MemoryThermThrottleEnable = 1;
+ table->PCIeBootLinkLevel = 0;
+ table->PCIeGenInterval = 1;
+
+ result = iceland_populate_smc_svi2_config(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate SVI2 setting!", return result);
+
+ table->ThermGpio = 17;
+ table->SclkStepSize = 0x4000;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
+ CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
+ CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
+
+ table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
+ table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
+ table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
+
+ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
+ result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU71_Discrete_DpmTable, SystemFlags),
+ (uint8_t *)&(table->SystemFlags),
+ sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
+ SMC_RAM_END);
+
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to upload dpm data to SMC memory!", return result;);
+
+ /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
+ result = smu7_copy_bytes_to_smc(hwmgr,
+ smu_data->smu7_data.ulv_setting_starts,
+ (uint8_t *)&(smu_data->ulv_setting),
+ sizeof(SMU71_Discrete_Ulv),
+ SMC_RAM_END);
+
+
+ result = iceland_populate_initial_mc_reg_table(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Failed to populate initialize MC Reg table!", return result);
+
+ result = iceland_populate_pm_fuses(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate PM fuses to SMC memory!", return result);
+
+ return 0;
+}
+
+int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+ SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
+ uint32_t duty100;
+ uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
+ uint16_t fdo_min, slope1, slope2;
+ uint32_t reference_clock;
+ int res;
+ uint64_t tmp64;
+
+ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
+ return 0;
+
+ if (hwmgr->thermal_controller.fanInfo.bNoFan) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ if (0 == smu7_data->fan_table_start) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
+
+ if (0 == duty100) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
+ do_div(tmp64, 10000);
+ fdo_min = (uint16_t)tmp64;
+
+ t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
+ t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
+
+ pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
+ pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
+
+ slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
+ slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
+
+ fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
+ fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
+ fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
+
+ fan_table.Slope1 = cpu_to_be16(slope1);
+ fan_table.Slope2 = cpu_to_be16(slope2);
+
+ fan_table.FdoMin = cpu_to_be16(fdo_min);
+
+ fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
+
+ fan_table.HystUp = cpu_to_be16(1);
+
+ fan_table.HystSlope = cpu_to_be16(1);
+
+ fan_table.TempRespLim = cpu_to_be16(5);
+
+ reference_clock = smu7_get_xclk(hwmgr);
+
+ fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
+
+ fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
+
+ fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
+
+ /* fan_table.FanControl_GL_Flag = 1; */
+
+ res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
+
+ return 0;
+}
+
+
+static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (data->need_update_smu7_dpm_table &
+ (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
+ return iceland_program_memory_timing_parameters(hwmgr);
+
+ return 0;
+}
+
+static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+
+ int result = 0;
+ uint32_t low_sclk_interrupt_threshold = 0;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkThrottleLowNotification)
+ && (hwmgr->gfx_arbiter.sclk_threshold !=
+ data->low_sclk_interrupt_threshold)) {
+ data->low_sclk_interrupt_threshold =
+ hwmgr->gfx_arbiter.sclk_threshold;
+ low_sclk_interrupt_threshold =
+ data->low_sclk_interrupt_threshold;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
+
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU71_Discrete_DpmTable,
+ LowSclkInterruptThreshold),
+ (uint8_t *)&low_sclk_interrupt_threshold,
+ sizeof(uint32_t),
+ SMC_RAM_END);
+ }
+
+ result = iceland_update_and_upload_mc_reg_table(hwmgr);
+
+ PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
+
+ result = iceland_program_mem_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE((result == 0),
+ "Failed to program memory timing parameters!",
+ );
+
+ return result;
+}
+
+static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
+{
+ switch (type) {
+ case SMU_SoftRegisters:
+ switch (member) {
+ case HandshakeDisables:
+ return offsetof(SMU71_SoftRegisters, HandshakeDisables);
+ case VoltageChangeTimeout:
+ return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout);
+ case AverageGraphicsActivity:
+ return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
+ case PreVBlankGap:
+ return offsetof(SMU71_SoftRegisters, PreVBlankGap);
+ case VBlankTimeout:
+ return offsetof(SMU71_SoftRegisters, VBlankTimeout);
+ case UcodeLoadStatus:
+ return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
+ case DRAM_LOG_ADDR_H:
+ return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
+ case DRAM_LOG_ADDR_L:
+ return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
+ case DRAM_LOG_PHY_ADDR_H:
+ return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+ case DRAM_LOG_PHY_ADDR_L:
+ return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+ case DRAM_LOG_BUFF_SIZE:
+ return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
+ }
+ case SMU_Discrete_DpmTable:
+ switch (member) {
+ case LowSclkInterruptThreshold:
+ return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
+ }
+ }
+ pr_warn("can't get the offset of type %x member %x\n", type, member);
+ return 0;
+}
+
+static uint32_t iceland_get_mac_definition(uint32_t value)
+{
+ switch (value) {
+ case SMU_MAX_LEVELS_GRAPHICS:
+ return SMU71_MAX_LEVELS_GRAPHICS;
+ case SMU_MAX_LEVELS_MEMORY:
+ return SMU71_MAX_LEVELS_MEMORY;
+ case SMU_MAX_LEVELS_LINK:
+ return SMU71_MAX_LEVELS_LINK;
+ case SMU_MAX_ENTRIES_SMIO:
+ return SMU71_MAX_ENTRIES_SMIO;
+ case SMU_MAX_LEVELS_VDDC:
+ return SMU71_MAX_LEVELS_VDDC;
+ case SMU_MAX_LEVELS_VDDCI:
+ return SMU71_MAX_LEVELS_VDDCI;
+ case SMU_MAX_LEVELS_MVDD:
+ return SMU71_MAX_LEVELS_MVDD;
+ }
+
+ pr_warn("can't get the mac of %x\n", value);
+ return 0;
+}
+
+static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+ uint32_t tmp;
+ int result;
+ bool error = false;
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, DpmTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ smu7_data->dpm_table_start = tmp;
+ }
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, SoftRegisters),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ data->soft_regs_start = tmp;
+ smu7_data->soft_regs_start = tmp;
+ }
+
+ error |= (0 != result);
+
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, mcRegisterTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ smu7_data->mc_reg_table_start = tmp;
+ }
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, FanTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ smu7_data->fan_table_start = tmp;
+ }
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ smu7_data->arb_table_start = tmp;
+ }
+
+ error |= (0 != result);
+
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, Version),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ hwmgr->microcode_version_info.SMC = tmp;
+ }
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, UlvSettings),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result) {
+ smu7_data->ulv_setting_starts = tmp;
+ }
+
+ error |= (0 != result);
+
+ return error ? 1 : 0;
+}
+
+/*---------------------------MC----------------------------*/
+
+static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
+{
+ return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
+}
+
+static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
+{
+ bool result = true;
+
+ switch (in_reg) {
+ case mmMC_SEQ_RAS_TIMING:
+ *out_reg = mmMC_SEQ_RAS_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_DLL_STBY:
+ *out_reg = mmMC_SEQ_DLL_STBY_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CMD0:
+ *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CMD1:
+ *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CTRL:
+ *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
+ break;
+
+ case mmMC_SEQ_CAS_TIMING:
+ *out_reg = mmMC_SEQ_CAS_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_MISC_TIMING:
+ *out_reg = mmMC_SEQ_MISC_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_MISC_TIMING2:
+ *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
+ break;
+
+ case mmMC_SEQ_PMG_DVS_CMD:
+ *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
+ break;
+
+ case mmMC_SEQ_PMG_DVS_CTL:
+ *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
+ break;
+
+ case mmMC_SEQ_RD_CTL_D0:
+ *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
+ break;
+
+ case mmMC_SEQ_RD_CTL_D1:
+ *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_D0:
+ *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_D1:
+ *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
+ break;
+
+ case mmMC_PMG_CMD_EMRS:
+ *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS1:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
+ break;
+
+ case mmMC_SEQ_PMG_TIMING:
+ *out_reg = mmMC_SEQ_PMG_TIMING_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS2:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_2:
+ *out_reg = mmMC_SEQ_WR_CTL_2_LP;
+ break;
+
+ default:
+ result = false;
+ break;
+ }
+
+ return result;
+}
+
+static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)
+{
+ uint32_t i;
+ uint16_t address;
+
+ for (i = 0; i < table->last; i++) {
+ table->mc_reg_address[i].s0 =
+ iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
+ ? address : table->mc_reg_address[i].s1;
+ }
+ return 0;
+}
+
+static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
+ struct iceland_mc_reg_table *ni_table)
+{
+ uint8_t i, j;
+
+ PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ for (i = 0; i < table->last; i++) {
+ ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
+ }
+ ni_table->last = table->last;
+
+ for (i = 0; i < table->num_entries; i++) {
+ ni_table->mc_reg_table_entry[i].mclk_max =
+ table->mc_reg_table_entry[i].mclk_max;
+ for (j = 0; j < table->last; j++) {
+ ni_table->mc_reg_table_entry[i].mc_data[j] =
+ table->mc_reg_table_entry[i].mc_data[j];
+ }
+ }
+
+ ni_table->num_entries = table->num_entries;
+
+ return 0;
+}
+
+static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ struct iceland_mc_reg_table *table)
+{
+ uint8_t i, j, k;
+ uint32_t temp_reg;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ for (i = 0, j = table->last; i < table->last; i++) {
+ PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ switch (table->mc_reg_address[i].s1) {
+
+ case mmMC_SEQ_MISC1:
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ ((temp_reg & 0xffff0000)) |
+ ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (temp_reg & 0xffff0000) |
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+
+ if (!data->is_memory_gddr5) {
+ table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
+ }
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
+ table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
+ table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ }
+
+ break;
+
+ case mmMC_SEQ_RESERVE_M:
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (temp_reg & 0xffff0000) |
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ break;
+
+ default:
+ break;
+ }
+
+ }
+
+ table->last = j;
+
+ return 0;
+}
+
+static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
+{
+ uint8_t i, j;
+ for (i = 0; i < table->last; i++) {
+ for (j = 1; j < table->num_entries; j++) {
+ if (table->mc_reg_table_entry[j-1].mc_data[i] !=
+ table->mc_reg_table_entry[j].mc_data[i]) {
+ table->validflag |= (1<<i);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
+ pp_atomctrl_mc_reg_table *table;
+ struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
+ uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
+
+ table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
+
+ if (NULL == table)
+ return -ENOMEM;
+
+ /* Program additional LP registers that are no longer programmed by VBIOS */
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
+
+ memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
+
+ result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
+
+ if (0 == result)
+ result = iceland_copy_vbios_smc_reg_table(table, ni_table);
+
+ if (0 == result) {
+ iceland_set_s0_mc_reg_index(ni_table);
+ result = iceland_set_mc_special_registers(hwmgr, ni_table);
+ }
+
+ if (0 == result)
+ iceland_set_valid_flag(ni_table);
+
+ kfree(table);
+
+ return result;
+}
+
+static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
+{
+ return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
+ ? true : false;
+}
+
const struct pp_smumgr_func iceland_smu_funcs = {
.smu_init = &iceland_smu_init,
.smu_fini = &smu7_smu_fini,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
index 8eae01b..8024725 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
@@ -39,7 +39,7 @@ struct iceland_pt_defaults {
uint8_t tdc_waterfall_ctl;
uint8_t dte_ambient_temp_base;
uint32_t display_cac;
- uint32_t bamp_temp_gradient;
+ uint32_t bapm_temp_gradient;
uint16_t bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
uint16_t bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
};
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
deleted file mode 100644
index 99a00bd..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ /dev/null
@@ -1,2364 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "pp_debug.h"
-#include "polaris10_smc.h"
-#include "smu7_dyn_defaults.h"
-
-#include "smu7_hwmgr.h"
-#include "hardwaremanager.h"
-#include "ppatomctrl.h"
-#include "cgs_common.h"
-#include "atombios.h"
-#include "polaris10_smumgr.h"
-#include "pppcielanes.h"
-
-#include "smu_ucode_xfer_vi.h"
-#include "smu74_discrete.h"
-#include "smu/smu_7_1_3_d.h"
-#include "smu/smu_7_1_3_sh_mask.h"
-#include "gmc/gmc_8_1_d.h"
-#include "gmc/gmc_8_1_sh_mask.h"
-#include "oss/oss_3_0_d.h"
-#include "gca/gfx_8_0_d.h"
-#include "bif/bif_5_0_d.h"
-#include "bif/bif_5_0_sh_mask.h"
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-#include "polaris10_pwrvirus.h"
-#include "smu7_ppsmc.h"
-#include "smu7_smumgr.h"
-
-#define POLARIS10_SMC_SIZE 0x20000
-#define VOLTAGE_VID_OFFSET_SCALE1 625
-#define VOLTAGE_VID_OFFSET_SCALE2 100
-#define POWERTUNE_DEFAULT_SET_MAX 1
-#define VDDC_VDDCI_DELTA 200
-#define MC_CG_ARB_FREQ_F1 0x0b
-
-static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
- /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
- * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
- { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
- { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
- { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
-};
-
-static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
- {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
- {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
- {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
- {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
- {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
- {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
- {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
- {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
-
-static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
- struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
- uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-{
- uint32_t i;
- uint16_t vddci;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- *voltage = *mvdd = 0;
-
- /* clock - voltage dependency table is empty table */
- if (dep_table->count == 0)
- return -EINVAL;
-
- for (i = 0; i < dep_table->count; i++) {
- /* find first sclk bigger than request */
- if (dep_table->entries[i].clk >= clock) {
- *voltage |= (dep_table->entries[i].vddc *
- VOLTAGE_SCALE) << VDDC_SHIFT;
- if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
- *voltage |= (data->vbios_boot_state.vddci_bootup_value *
- VOLTAGE_SCALE) << VDDCI_SHIFT;
- else if (dep_table->entries[i].vddci)
- *voltage |= (dep_table->entries[i].vddci *
- VOLTAGE_SCALE) << VDDCI_SHIFT;
- else {
- vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
- (dep_table->entries[i].vddc -
- (uint16_t)VDDC_VDDCI_DELTA));
- *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
- }
-
- if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
- *mvdd = data->vbios_boot_state.mvdd_bootup_value *
- VOLTAGE_SCALE;
- else if (dep_table->entries[i].mvdd)
- *mvdd = (uint32_t) dep_table->entries[i].mvdd *
- VOLTAGE_SCALE;
-
- *voltage |= 1 << PHASES_SHIFT;
- return 0;
- }
- }
-
- /* sclk is bigger than max sclk in the dependence table */
- *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-
- if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
- *voltage |= (data->vbios_boot_state.vddci_bootup_value *
- VOLTAGE_SCALE) << VDDCI_SHIFT;
- else if (dep_table->entries[i-1].vddci) {
- vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
- (dep_table->entries[i].vddc -
- (uint16_t)VDDC_VDDCI_DELTA));
- *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
- }
-
- if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
- *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
- else if (dep_table->entries[i].mvdd)
- *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
-
- return 0;
-}
-
-static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
-{
- uint32_t tmp;
- tmp = raw_setting * 4096 / 100;
- return (uint16_t)tmp;
-}
-
-static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
-
- const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
- SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
- struct pp_advance_fan_control_parameters *fan_table =
- &hwmgr->thermal_controller.advanceFanControlParameters;
- int i, j, k;
- const uint16_t *pdef1;
- const uint16_t *pdef2;
-
- table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
- table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-
- PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
- "Target Operating Temp is out of Range!",
- );
-
- table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTargetOperatingTemp * 256);
- table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
- cac_dtp_table->usTemperatureLimitHotspot * 256);
- table->FanGainEdge = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainEdge));
- table->FanGainHotspot = PP_HOST_TO_SMC_US(
- scale_fan_gain_settings(fan_table->usFanGainHotspot));
-
- pdef1 = defaults->BAPMTI_R;
- pdef2 = defaults->BAPMTI_RC;
-
- for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
- for (j = 0; j < SMU74_DTE_SOURCES; j++) {
- for (k = 0; k < SMU74_DTE_SINKS; k++) {
- table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
- table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
- pdef1++;
- pdef2++;
- }
- }
- }
-
- return 0;
-}
-
-static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
- smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
- smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
- smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-
- return 0;
-}
-
-static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-{
- uint16_t tdc_limit;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
- smu_data->power_tune_table.TDC_VDDC_PkgLimit =
- CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
- smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
- defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
- smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
-
- return 0;
-}
-
-static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
- uint32_t temp;
-
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- fuse_table_offset +
- offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
- (uint32_t *)&temp, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
- return -EINVAL);
- else {
- smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
- smu_data->power_tune_table.LPMLTemperatureMin =
- (uint8_t)((temp >> 16) & 0xff);
- smu_data->power_tune_table.LPMLTemperatureMax =
- (uint8_t)((temp >> 8) & 0xff);
- smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
- }
- return 0;
-}
-
-static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
-
- /* Currently not used. Set all to zero. */
- for (i = 0; i < 16; i++)
- smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-
- return 0;
-}
-
-static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
-
-/* TO DO move to hwmgr */
- if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
- || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
- hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
- hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
-
- smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
- hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
- return 0;
-}
-
-static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
-
- /* Currently not used. Set all to zero. */
- for (i = 0; i < 16; i++)
- smu_data->power_tune_table.GnbLPML[i] = 0;
-
- return 0;
-}
-
-static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
- return 0;
-}
-
-static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
- uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
- struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-
- hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
- lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-
- smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
- CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
- smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
- CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
-
- return 0;
-}
-
-static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- uint32_t pm_fuse_table_offset;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU74_Firmware_Header, PmFuseTable),
- &pm_fuse_table_offset, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to get pm_fuse_table_offset Failed!",
- return -EINVAL);
-
- if (polaris10_populate_svi_load_line(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate SviLoadLine Failed!",
- return -EINVAL);
-
- if (polaris10_populate_tdc_limit(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TDCLimit Failed!", return -EINVAL);
-
- if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TdcWaterfallCtl, "
- "LPMLTemperature Min and Max Failed!",
- return -EINVAL);
-
- if (0 != polaris10_populate_temperature_scaler(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate LPMLTemperatureScaler Failed!",
- return -EINVAL);
-
- if (polaris10_populate_fuzzy_fan(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate Fuzzy Fan Control parameters Failed!",
- return -EINVAL);
-
- if (polaris10_populate_gnb_lpml(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML Failed!",
- return -EINVAL);
-
- if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML Min and Max Vid Failed!",
- return -EINVAL);
-
- if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
- "Sidd Failed!", return -EINVAL);
-
- if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
- (uint8_t *)&smu_data->power_tune_table,
- (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to download PmFuseTable Failed!",
- return -EINVAL);
- }
- return 0;
-}
-
-/**
- * Mvdd table preparation for SMC.
- *
- * @param *hwmgr The address of the hardware manager.
- * @param *table The SMC DPM table structure to be populated.
- * @return 0
- */
-static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
- SMU74_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t count, level;
-
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
- count = data->mvdd_voltage_table.count;
- if (count > SMU_MAX_SMIO_LEVELS)
- count = SMU_MAX_SMIO_LEVELS;
- for (level = 0; level < count; level++) {
- table->SmioTable2.Pattern[level].Voltage =
- PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
- /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
- table->SmioTable2.Pattern[level].Smio =
- (uint8_t) level;
- table->Smio[level] |=
- data->mvdd_voltage_table.entries[level].smio_low;
- }
- table->SmioMask2 = data->mvdd_voltage_table.mask_low;
-
- table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
- }
-
- return 0;
-}
-
-static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- uint32_t count, level;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- count = data->vddci_voltage_table.count;
-
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
- if (count > SMU_MAX_SMIO_LEVELS)
- count = SMU_MAX_SMIO_LEVELS;
- for (level = 0; level < count; ++level) {
- table->SmioTable1.Pattern[level].Voltage =
- PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
- table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
-
- table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
- }
- }
-
- table->SmioMask1 = data->vddci_voltage_table.mask_low;
-
- return 0;
-}
-
-/**
-* Preparation of vddc and vddgfx CAC tables for SMC.
-*
-* @param hwmgr the address of the hardware manager
-* @param table the SMC DPM table structure to be populated
-* @return always 0
-*/
-static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- uint32_t count;
- uint8_t index;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_voltage_lookup_table *lookup_table =
- table_info->vddc_lookup_table;
- /* tables is already swapped, so in order to use the value from it,
- * we need to swap it back.
- * We are populating vddc CAC data to BapmVddc table
- * in split and merged mode
- */
- for (count = 0; count < lookup_table->count; count++) {
- index = phm_get_voltage_index(lookup_table,
- data->vddc_voltage_table.entries[count].value);
- table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
- table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
- table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
- }
-
- return 0;
-}
-
-/**
-* Preparation of voltage tables for SMC.
-*
-* @param hwmgr the address of the hardware manager
-* @param table the SMC DPM table structure to be populated
-* @return always 0
-*/
-
-static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- polaris10_populate_smc_vddci_table(hwmgr, table);
- polaris10_populate_smc_mvdd_table(hwmgr, table);
- polaris10_populate_cac_table(hwmgr, table);
-
- return 0;
-}
-
-static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_Ulv *state)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct pp_smumgr *smumgr = hwmgr->smumgr;
-
- state->CcPwrDynRm = 0;
- state->CcPwrDynRm1 = 0;
-
- state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
- state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
- VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-
- if (smumgr->chip_id == CHIP_POLARIS12 || smumgr->is_kicker)
- state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
- else
- state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
-
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
- CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-
- return 0;
-}
-
-static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
-}
-
-static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- int i;
-
- /* Index (dpm_table->pcie_speed_table.count)
- * is reserved for PCIE boot level. */
- for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
- table->LinkLevel[i].PcieGenSpeed =
- (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
- table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
- dpm_table->pcie_speed_table.dpm_levels[i].param1);
- table->LinkLevel[i].EnabledForActivity = 1;
- table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
- table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
- table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
- }
-
- smu_data->smc_state_table.LinkLevelCount =
- (uint8_t)dpm_table->pcie_speed_table.count;
-
-/* To Do move to hwmgr */
- data->dpm_level_enable_mask.pcie_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-
- return 0;
-}
-
-
-static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
- SMU74_Discrete_DpmTable *table)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- uint32_t i, ref_clk;
-
- struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
-
- ref_clk = smu7_get_xclk(hwmgr);
-
- if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
- for (i = 0; i < NUM_SCLK_RANGE; i++) {
- table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
- table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
- table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
-
- table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
- table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
-
- CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
- CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
- CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
- }
- return;
- }
-
- for (i = 0; i < NUM_SCLK_RANGE; i++) {
- smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
- smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
-
- table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
- table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
- table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
-
- table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
- table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
-
- CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
- CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
- CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
- }
-}
-
-/**
-* Calculates the SCLK dividers using the provided engine clock
-*
-* @param hwmgr the address of the hardware manager
-* @param clock the engine clock to use to populate the structure
-* @param sclk the SMC SCLK structure to be populated
-*/
-static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- uint32_t clock, SMU_SclkSetting *sclk_setting)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
- struct pp_atomctrl_clock_dividers_ai dividers;
- uint32_t ref_clock;
- uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
- uint8_t i;
- int result;
- uint64_t temp;
-
- sclk_setting->SclkFrequency = clock;
- /* get the engine clock dividers for this clock value */
- result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
- if (result == 0) {
- sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
- sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
- sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
- sclk_setting->PllRange = dividers.ucSclkPllRange;
- sclk_setting->Sclk_slew_rate = 0x400;
- sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
- sclk_setting->Pcc_down_slew_rate = 0xffff;
- sclk_setting->SSc_En = dividers.ucSscEnable;
- sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
- sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
- sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
- return result;
- }
-
- ref_clock = smu7_get_xclk(hwmgr);
-
- for (i = 0; i < NUM_SCLK_RANGE; i++) {
- if (clock > smu_data->range_table[i].trans_lower_frequency
- && clock <= smu_data->range_table[i].trans_upper_frequency) {
- sclk_setting->PllRange = i;
- break;
- }
- }
-
- sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
- temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
- temp <<= 0x10;
- do_div(temp, ref_clock);
- sclk_setting->Fcw_frac = temp & 0xffff;
-
- pcc_target_percent = 10; /* Hardcode 10% for now. */
- pcc_target_freq = clock - (clock * pcc_target_percent / 100);
- sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-
- ss_target_percent = 2; /* Hardcode 2% for now. */
- sclk_setting->SSc_En = 0;
- if (ss_target_percent) {
- sclk_setting->SSc_En = 1;
- ss_target_freq = clock - (clock * ss_target_percent / 100);
- sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
- temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
- temp <<= 0x10;
- do_div(temp, ref_clock);
- sclk_setting->Fcw1_frac = temp & 0xffff;
- }
-
- return 0;
-}
-
-/**
-* Populates single SMC SCLK structure using the provided engine clock
-*
-* @param hwmgr the address of the hardware manager
-* @param clock the engine clock to use to populate the structure
-* @param sclk the SMC SCLK structure to be populated
-*/
-
-static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
- uint32_t clock, uint16_t sclk_al_threshold,
- struct SMU74_Discrete_GraphicsLevel *level)
-{
- int result;
- /* PP_Clocks minClocks; */
- uint32_t mvdd;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- SMU_SclkSetting curr_sclk_setting = { 0 };
-
- result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
-
- /* populate graphics levels */
- result = polaris10_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_sclk, clock,
- &level->MinVoltage, &mvdd);
-
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find VDDC voltage value for "
- "VDDC engine clock dependency table",
- return result);
- level->ActivityLevel = sclk_al_threshold;
-
- level->CcPwrDynRm = 0;
- level->CcPwrDynRm1 = 0;
- level->EnabledForActivity = 0;
- level->EnabledForThrottle = 1;
- level->UpHyst = 10;
- level->DownHyst = 0;
- level->VoltageDownHyst = 0;
- level->PowerThrottle = 0;
- data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
- level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
- hwmgr->display_config.min_core_set_clock_in_sr);
-
- /* Default to slow, highest DPM level will be
- * set to PPSMC_DISPLAY_WATERMARK_LOW later.
- */
- if (data->update_up_hyst)
- level->UpHyst = (uint8_t)data->up_hyst;
- if (data->update_down_hyst)
- level->DownHyst = (uint8_t)data->down_hyst;
-
- level->SclkSetting = curr_sclk_setting;
-
- CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
- CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
- CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
- CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
- return 0;
-}
-
-/**
-* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
-*
-* @param hwmgr the address of the hardware manager
-*/
-int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
- uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
- int result = 0;
- uint32_t array = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
- uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
- SMU74_MAX_LEVELS_GRAPHICS;
- struct SMU74_Discrete_GraphicsLevel *levels =
- smu_data->smc_state_table.GraphicsLevel;
- uint32_t i, max_entry;
- uint8_t hightest_pcie_level_enabled = 0,
- lowest_pcie_level_enabled = 0,
- mid_pcie_level_enabled = 0,
- count = 0;
-
- polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
-
- for (i = 0; i < dpm_table->sclk_table.count; i++) {
-
- result = polaris10_populate_single_graphic_level(hwmgr,
- dpm_table->sclk_table.dpm_levels[i].value,
- (uint16_t)smu_data->activity_target[i],
- &(smu_data->smc_state_table.GraphicsLevel[i]));
- if (result)
- return result;
-
- /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
- if (i > 1)
- levels[i].DeepSleepDivId = 0;
- }
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SPLLShutdownSupport))
- smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
-
- smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
- smu_data->smc_state_table.GraphicsDpmLevelCount =
- (uint8_t)dpm_table->sclk_table.count;
- hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-
-
- if (pcie_table != NULL) {
- PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
- "There must be 1 or more PCIE levels defined in PPTable.",
- return -EINVAL);
- max_entry = pcie_entry_cnt - 1;
- for (i = 0; i < dpm_table->sclk_table.count; i++)
- levels[i].pcieDpmLevel =
- (uint8_t) ((i < max_entry) ? i : max_entry);
- } else {
- while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
- ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << (hightest_pcie_level_enabled + 1))) != 0))
- hightest_pcie_level_enabled++;
-
- while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
- ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << lowest_pcie_level_enabled)) == 0))
- lowest_pcie_level_enabled++;
-
- while ((count < hightest_pcie_level_enabled) &&
- ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
- count++;
-
- mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
- hightest_pcie_level_enabled ?
- (lowest_pcie_level_enabled + 1 + count) :
- hightest_pcie_level_enabled;
-
- /* set pcieDpmLevel to hightest_pcie_level_enabled */
- for (i = 2; i < dpm_table->sclk_table.count; i++)
- levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
-
- /* set pcieDpmLevel to lowest_pcie_level_enabled */
- levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
-
- /* set pcieDpmLevel to mid_pcie_level_enabled */
- levels[1].pcieDpmLevel = mid_pcie_level_enabled;
- }
- /* level count will send to smc once at init smc table and never change */
- result = smu7_copy_bytes_to_smc(smumgr, array, (uint8_t *)levels,
- (uint32_t)array_size, SMC_RAM_END);
-
- return result;
-}
-
-
-static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
- uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- int result = 0;
- struct cgs_display_info info = {0, 0, NULL};
- uint32_t mclk_stutter_mode_threshold = 40000;
-
- cgs_get_active_displays_info(hwmgr->device, &info);
-
- if (table_info->vdd_dep_on_mclk) {
- result = polaris10_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_mclk, clock,
- &mem_level->MinVoltage, &mem_level->MinMvdd);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find MinVddc voltage value from memory "
- "VDDC voltage dependency table", return result);
- }
-
- mem_level->MclkFrequency = clock;
- mem_level->EnabledForThrottle = 1;
- mem_level->EnabledForActivity = 0;
- mem_level->UpHyst = 0;
- mem_level->DownHyst = 100;
- mem_level->VoltageDownHyst = 0;
- mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
- mem_level->StutterEnable = false;
- mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
- data->display_timing.num_existing_displays = info.display_count;
-
- if (mclk_stutter_mode_threshold &&
- (clock <= mclk_stutter_mode_threshold) &&
- (SMUM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
- STUTTER_ENABLE) & 0x1))
- mem_level->StutterEnable = true;
-
- if (!result) {
- CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
- CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
- }
- return result;
-}
-
-/**
-* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
-*
-* @param hwmgr the address of the hardware manager
-*/
-int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
- int result;
- /* populate MCLK dpm table to SMU7 */
- uint32_t array = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
- uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
- SMU74_MAX_LEVELS_MEMORY;
- struct SMU74_Discrete_MemoryLevel *levels =
- smu_data->smc_state_table.MemoryLevel;
- uint32_t i;
-
- for (i = 0; i < dpm_table->mclk_table.count; i++) {
- PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
- "can not populate memory level as memory clock is zero",
- return -EINVAL);
- result = polaris10_populate_single_memory_level(hwmgr,
- dpm_table->mclk_table.dpm_levels[i].value,
- &levels[i]);
- if (i == dpm_table->mclk_table.count - 1) {
- levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
- levels[i].EnabledForActivity = 1;
- }
- if (result)
- return result;
- }
-
- /* In order to prevent MC activity from stutter mode to push DPM up,
- * the UVD change complements this by putting the MCLK in
- * a higher state by default such that we are not affected by
- * up threshold or and MCLK DPM latency.
- */
- levels[0].ActivityLevel = 0x1f;
- CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-
- smu_data->smc_state_table.MemoryDpmLevelCount =
- (uint8_t)dpm_table->mclk_table.count;
- hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-
- /* level count will send to smc once at init smc table and never change */
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
- (uint32_t)array_size, SMC_RAM_END);
-
- return result;
-}
-
-/**
-* Populates the SMC MVDD structure using the provided memory clock.
-*
-* @param hwmgr the address of the hardware manager
-* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
-* @param voltage the SMC VOLTAGE structure to be populated
-*/
-static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
- uint32_t mclk, SMIO_Pattern *smio_pat)
-{
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint32_t i = 0;
-
- if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
- /* find mvdd value which clock is more than request */
- for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
- if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
- smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
- break;
- }
- }
- PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
- "MVDD Voltage is outside the supported range.",
- return -EINVAL);
- } else
- return -EINVAL;
-
- return 0;
-}
-
-static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
- SMU74_Discrete_DpmTable *table)
-{
- int result = 0;
- uint32_t sclk_frequency;
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- SMIO_Pattern vol_level;
- uint32_t mvdd;
- uint16_t us_mvdd;
-
- table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-
- /* Get MinVoltage and Frequency from DPM0,
- * already converted to SMC_UL */
- sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
- result = polaris10_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_sclk,
- sclk_frequency,
- &table->ACPILevel.MinVoltage, &mvdd);
- PP_ASSERT_WITH_CODE((0 == result),
- "Cannot find ACPI VDDC voltage value "
- "in Clock Dependency Table",
- );
-
- result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
- PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
-
- table->ACPILevel.DeepSleepDivId = 0;
- table->ACPILevel.CcPwrDynRm = 0;
- table->ACPILevel.CcPwrDynRm1 = 0;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
- CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
-
-
- /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
- table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
- result = polaris10_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_mclk,
- table->MemoryACPILevel.MclkFrequency,
- &table->MemoryACPILevel.MinVoltage, &mvdd);
- PP_ASSERT_WITH_CODE((0 == result),
- "Cannot find ACPI VDDCI voltage value "
- "in Clock Dependency Table",
- );
-
- us_mvdd = 0;
- if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
- (data->mclk_dpm_key_disabled))
- us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
- else {
- if (!polaris10_populate_mvdd_value(hwmgr,
- data->dpm_table.mclk_table.dpm_levels[0].value,
- &vol_level))
- us_mvdd = vol_level.Voltage;
- }
-
- if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
- table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
- else
- table->MemoryACPILevel.MinMvdd = 0;
-
- table->MemoryACPILevel.StutterEnable = false;
-
- table->MemoryACPILevel.EnabledForThrottle = 0;
- table->MemoryACPILevel.EnabledForActivity = 0;
- table->MemoryACPILevel.UpHyst = 0;
- table->MemoryACPILevel.DownHyst = 100;
- table->MemoryACPILevel.VoltageDownHyst = 0;
- table->MemoryACPILevel.ActivityLevel =
- PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
-
- return result;
-}
-
-static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- SMU74_Discrete_DpmTable *table)
-{
- int result = -EINVAL;
- uint8_t count;
- struct pp_atomctrl_clock_dividers_vi dividers;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- table_info->mm_dep_table;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t vddci;
-
- table->VceLevelCount = (uint8_t)(mm_table->count);
- table->VceBootLevel = 0;
-
- for (count = 0; count < table->VceLevelCount; count++) {
- table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
- table->VceLevel[count].MinVoltage = 0;
- table->VceLevel[count].MinVoltage |=
- (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
- vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
- mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
- else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
- vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
- else
- vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-
-
- table->VceLevel[count].MinVoltage |=
- (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
- table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
- /*retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->VceLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for VCE engine clock",
- return result);
-
- table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
- }
- return result;
-}
-
-
-static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
- SMU74_Discrete_DpmTable *table)
-{
- int result = -EINVAL;
- uint8_t count;
- struct pp_atomctrl_clock_dividers_vi dividers;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- table_info->mm_dep_table;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t vddci;
-
- table->SamuBootLevel = 0;
- table->SamuLevelCount = (uint8_t)(mm_table->count);
-
- for (count = 0; count < table->SamuLevelCount; count++) {
- /* not sure whether we need evclk or not */
- table->SamuLevel[count].MinVoltage = 0;
- table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
- table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
- VOLTAGE_SCALE) << VDDC_SHIFT;
-
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
- vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
- mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
- else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
- vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
- else
- vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-
- table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
- table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->SamuLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for samu clock", return result);
-
- table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
- }
- return result;
-}
-
-static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
- int32_t eng_clock, int32_t mem_clock,
- SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
-{
- uint32_t dram_timing;
- uint32_t dram_timing2;
- uint32_t burst_time;
- int result;
-
- result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
- eng_clock, mem_clock);
- PP_ASSERT_WITH_CODE(result == 0,
- "Error calling VBIOS to set DRAM_TIMING.", return result);
-
- dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
- dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
- burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-
-
- arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
- arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
- arb_regs->McArbBurstTime = (uint8_t)burst_time;
-
- return 0;
-}
-
-static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
- uint32_t i, j;
- int result = 0;
-
- for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
- for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
- result = polaris10_populate_memory_timing_parameters(hwmgr,
- hw_data->dpm_table.sclk_table.dpm_levels[i].value,
- hw_data->dpm_table.mclk_table.dpm_levels[j].value,
- &arb_regs.entries[i][j]);
- if (result == 0)
- result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
- if (result != 0)
- return result;
- }
- }
-
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.arb_table_start,
- (uint8_t *)&arb_regs,
- sizeof(SMU74_Discrete_MCArbDramTimingTable),
- SMC_RAM_END);
- return result;
-}
-
-static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- int result = -EINVAL;
- uint8_t count;
- struct pp_atomctrl_clock_dividers_vi dividers;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- table_info->mm_dep_table;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t vddci;
-
- table->UvdLevelCount = (uint8_t)(mm_table->count);
- table->UvdBootLevel = 0;
-
- for (count = 0; count < table->UvdLevelCount; count++) {
- table->UvdLevel[count].MinVoltage = 0;
- table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
- table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
- table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
- VOLTAGE_SCALE) << VDDC_SHIFT;
-
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
- vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
- mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
- else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
- vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
- else
- vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-
- table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
- table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->UvdLevel[count].VclkFrequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for Vclk clock", return result);
-
- table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->UvdLevel[count].DclkFrequency, ÷rs);
- PP_ASSERT_WITH_CODE((0 == result),
- "can not find divide id for Dclk clock", return result);
-
- table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
- }
-
- return result;
-}
-
-static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- int result = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- table->GraphicsBootLevel = 0;
- table->MemoryBootLevel = 0;
-
- /* find boot level from dpm table */
- result = phm_find_boot_level(&(data->dpm_table.sclk_table),
- data->vbios_boot_state.sclk_bootup_value,
- (uint32_t *)&(table->GraphicsBootLevel));
-
- result = phm_find_boot_level(&(data->dpm_table.mclk_table),
- data->vbios_boot_state.mclk_bootup_value,
- (uint32_t *)&(table->MemoryBootLevel));
-
- table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
- VOLTAGE_SCALE;
- table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
- VOLTAGE_SCALE;
- table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
- VOLTAGE_SCALE;
-
- CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
- CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
- CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-
- return 0;
-}
-
-static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint8_t count, level;
-
- count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
-
- for (level = 0; level < count; level++) {
- if (table_info->vdd_dep_on_sclk->entries[level].clk >=
- hw_data->vbios_boot_state.sclk_bootup_value) {
- smu_data->smc_state_table.GraphicsBootLevel = level;
- break;
- }
- }
-
- count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
- for (level = 0; level < count; level++) {
- if (table_info->vdd_dep_on_mclk->entries[level].clk >=
- hw_data->vbios_boot_state.mclk_bootup_value) {
- smu_data->smc_state_table.MemoryBootLevel = level;
- break;
- }
- }
-
- return 0;
-}
-
-
-static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-{
- uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-
- uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
- table_info->vdd_dep_on_sclk;
-
- stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-
- /* Read SMU_Eefuse to read and calculate RO and determine
- * if the part is SS or FF. if RO >= 1660MHz, part is FF.
- */
- efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixSMU_EFUSE_0 + (67 * 4));
- efuse &= 0xFF000000;
- efuse = efuse >> 24;
-
- if (hwmgr->chip_id == CHIP_POLARIS10) {
- min = 1000;
- max = 2300;
- } else {
- min = 1100;
- max = 2100;
- }
-
- ro = efuse * (max - min) / 255 + min;
-
- /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
- for (i = 0; i < sclk_table->count; i++) {
- smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
- sclk_table->entries[i].cks_enable << i;
- if (hwmgr->chip_id == CHIP_POLARIS10) {
- volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
- (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
- volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
- (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
- } else {
- volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
- (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
- volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
- (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
- }
-
- if (volt_without_cks >= volt_with_cks)
- volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
- sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
-
- smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
- }
-
- smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
- /* Populate CKS Lookup Table */
- if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
- stretch_amount2 = 0;
- else if (stretch_amount == 3 || stretch_amount == 4)
- stretch_amount2 = 1;
- else {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ClockStretcher);
- PP_ASSERT_WITH_CODE(false,
- "Stretch Amount in PPTable not supported\n",
- return -EINVAL);
- }
-
- value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
- value &= 0xFFFFFFFE;
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
-
- return 0;
-}
-
-/**
-* Populates the SMC VRConfig field in DPM table.
-*
-* @param hwmgr the address of the hardware manager
-* @param table the SMC DPM table structure to be populated
-* @return always 0
-*/
-static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
- struct SMU74_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- uint16_t config;
-
- config = VR_MERGED_WITH_VDDC;
- table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
-
- /* Set Vddc Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
- config = VR_SVI2_PLANE_1;
- table->VRConfig |= config;
- } else {
- PP_ASSERT_WITH_CODE(false,
- "VDDC should be on SVI2 control in merged mode!",
- );
- }
- /* Set Vddci Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
- config = VR_SVI2_PLANE_2; /* only in merged mode */
- table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
- } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
- config = VR_SMIO_PATTERN_1;
- table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
- } else {
- config = VR_STATIC_VOLTAGE;
- table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
- }
- /* Set Mvdd Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
- config = VR_SVI2_PLANE_2;
- table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
- offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
- } else {
- config = VR_STATIC_VOLTAGE;
- table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
- }
-
- return 0;
-}
-
-
-static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-
- SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
- int result = 0;
- struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
- AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
- AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
- uint32_t tmp, i;
-
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)hwmgr->pptable;
- struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
- table_info->vdd_dep_on_sclk;
-
-
- if (((struct smu7_smumgr *)smu_data)->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
- return result;
-
- result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
-
- if (0 == result) {
- table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
- table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
- table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
- table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
- table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
- table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
- table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
- table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
- table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
- table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
- table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
- table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
- table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
- table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
- table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
- table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
- table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
- AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
- AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
- AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
- AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
- AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
- AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
- AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
-
- for (i = 0; i < NUM_VFT_COLUMNS; i++) {
- AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
- AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
- }
-
- result = smu7_read_smc_sram_dword(smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
- &tmp, SMC_RAM_END);
-
- smu7_copy_bytes_to_smc(smumgr,
- tmp,
- (uint8_t *)&AVFS_meanNsigma,
- sizeof(AVFS_meanNsigma_t),
- SMC_RAM_END);
-
- result = smu7_read_smc_sram_dword(smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
- &tmp, SMC_RAM_END);
- smu7_copy_bytes_to_smc(smumgr,
- tmp,
- (uint8_t *)&AVFS_SclkOffset,
- sizeof(AVFS_Sclk_Offset_t),
- SMC_RAM_END);
-
- data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
- (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
- (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
- (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
- data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
- }
- return result;
-}
-
-
-/**
-* Initialize the ARB DRAM timing table's index field.
-*
-* @param hwmgr the address of the powerplay hardware manager.
-* @return always 0
-*/
-static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- uint32_t tmp;
- int result;
-
- /* This is a read-modify-write on the first byte of the ARB table.
- * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
- * is the field 'current'.
- * This solution is ugly, but we never write the whole table only
- * individual fields in it.
- * In reality this field should not be in that structure
- * but in a soft register.
- */
- result = smu7_read_smc_sram_dword(smumgr,
- smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
-
- if (result)
- return result;
-
- tmp &= 0x00FFFFFF;
- tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-
- return smu7_write_smc_sram_dword(smumgr,
- smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
-}
-
-static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- if (table_info &&
- table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
- table_info->cac_dtp_table->usPowerTuneDataSetID)
- smu_data->power_tune_defaults =
- &polaris10_power_tune_data_set_array
- [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
- else
- smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
-
-}
-
-static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- struct SMU74_Discrete_GraphicsLevel *levels =
- data->smc_state_table.GraphicsLevel;
- unsigned min_level = 1;
-
- hwmgr->default_gfx_power_profile.activity_threshold =
- be16_to_cpu(levels[0].ActivityLevel);
- hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
- hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
- hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
-
- hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
- hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
-
- /* Workaround compute SDMA instability: disable lowest SCLK
- * DPM level. Optimize compute power profile: Use only highest
- * 2 power levels (if more than 2 are available), Hysteresis:
- * 0ms up, 5ms down
- */
- if (data->smc_state_table.GraphicsDpmLevelCount > 2)
- min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
- else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
- min_level = 1;
- else
- min_level = 0;
- hwmgr->default_compute_power_profile.min_sclk =
- be32_to_cpu(levels[min_level].SclkSetting.SclkFrequency);
- hwmgr->default_compute_power_profile.up_hyst = 0;
- hwmgr->default_compute_power_profile.down_hyst = 5;
-
- hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
- hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
-}
-
-/**
-* Initializes the SMC table and uploads it
-*
-* @param hwmgr the address of the powerplay hardware manager.
-* @return always 0
-*/
-int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
- uint8_t i;
- struct pp_atomctrl_gpio_pin_assignment gpio_pin;
- pp_atomctrl_clock_dividers_vi dividers;
-
- polaris10_initialize_power_tune_defaults(hwmgr);
-
- if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
- polaris10_populate_smc_voltage_tables(hwmgr, table);
-
- table->SystemFlags = 0;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StepVddc))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-
- if (hw_data->is_memory_gddr5)
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-
- if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
- result = polaris10_populate_ulv_state(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ULV state!", return result);
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
- }
-
- result = polaris10_populate_smc_link_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Link Level!", return result);
-
- result = polaris10_populate_all_graphic_levels(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Graphics Level!", return result);
-
- result = polaris10_populate_all_memory_levels(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Memory Level!", return result);
-
- result = polaris10_populate_smc_acpi_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize ACPI Level!", return result);
-
- result = polaris10_populate_smc_vce_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize VCE Level!", return result);
-
- result = polaris10_populate_smc_samu_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize SAMU Level!", return result);
-
- /* Since only the initial state is completely set up at this point
- * (the other states are just copies of the boot state) we only
- * need to populate the ARB settings for the initial state.
- */
- result = polaris10_program_memory_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to Write ARB settings for the initial state.", return result);
-
- result = polaris10_populate_smc_uvd_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize UVD Level!", return result);
-
- result = polaris10_populate_smc_boot_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Boot Level!", return result);
-
- result = polaris10_populate_smc_initailial_state(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to initialize Boot State!", return result);
-
- result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate BAPM Parameters!", return result);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ClockStretcher)) {
- result = polaris10_populate_clock_stretcher_data_table(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate Clock Stretcher Data Table!",
- return result);
- }
-
- result = polaris10_populate_avfs_parameters(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
-
- table->CurrSclkPllRange = 0xff;
- table->GraphicsVoltageChangeEnable = 1;
- table->GraphicsThermThrottleEnable = 1;
- table->GraphicsInterval = 1;
- table->VoltageInterval = 1;
- table->ThermalInterval = 1;
- table->TemperatureLimitHigh =
- table_info->cac_dtp_table->usTargetOperatingTemp *
- SMU7_Q88_FORMAT_CONVERSION_UNIT;
- table->TemperatureLimitLow =
- (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
- SMU7_Q88_FORMAT_CONVERSION_UNIT;
- table->MemoryVoltageChangeEnable = 1;
- table->MemoryInterval = 1;
- table->VoltageResponseTime = 0;
- table->PhaseResponseTime = 0;
- table->MemoryThermThrottleEnable = 1;
- table->PCIeBootLinkLevel = 0;
- table->PCIeGenInterval = 1;
- table->VRConfig = 0;
-
- result = polaris10_populate_vr_config(hwmgr, table);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate VRConfig setting!", return result);
-
- table->ThermGpio = 17;
- table->SclkStepSize = 0x4000;
-
- if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
- table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
- } else {
- table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot);
- }
-
- if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
- &gpio_pin)) {
- table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition);
- } else {
- table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition);
- }
-
- /* Thermal Output GPIO */
- if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
- &gpio_pin)) {
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ThermalOutGPIO);
-
- table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
-
- /* For porlarity read GPIOPAD_A with assigned Gpio pin
- * since VBIOS will program this register to set 'inactive state',
- * driver can then determine 'active state' from this and
- * program SMU with correct polarity
- */
- table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
- & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
- table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-
- /* if required, combine VRHot/PCC with thermal out GPIO */
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
- && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
- table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
- } else {
- table->ThermOutGpio = 17;
- table->ThermOutPolarity = 1;
- table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
- }
-
- /* Populate BIF_SCLK levels into SMC DPM table */
- for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs);
- PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
-
- if (i == 0)
- table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
- else
- table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
- }
-
- for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
- table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
- CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
- CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
- CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
- CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-
- /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
- smu_data->smu7_data.dpm_table_start +
- offsetof(SMU74_Discrete_DpmTable, SystemFlags),
- (uint8_t *)&(table->SystemFlags),
- sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
- SMC_RAM_END);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to upload dpm data to SMC memory!", return result);
-
- result = polaris10_init_arb_table_index(hwmgr->smumgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to upload arb data to SMC memory!", return result);
-
- result = polaris10_populate_pm_fuses(hwmgr);
- PP_ASSERT_WITH_CODE(0 == result,
- "Failed to populate PM fuses to SMC memory!", return result);
-
- polaris10_save_default_power_profile(hwmgr);
-
- return 0;
-}
-
-static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (data->need_update_smu7_dpm_table &
- (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
- return polaris10_program_memory_timing_parameters(hwmgr);
-
- return 0;
-}
-
-int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
-{
- int ret;
- struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
- return 0;
-
- ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
-
- ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ?
- 0 : -1;
-
- if (!ret)
- /* If this param is not changed, this function could fire unnecessarily */
- smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
-
- return ret;
-}
-
-/**
-* Set up the fan table to control the fan using the SMC.
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from set temperature range routine
-*/
-int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
- uint32_t duty100;
- uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
- uint16_t fdo_min, slope1, slope2;
- uint32_t reference_clock;
- int res;
- uint64_t tmp64;
-
- if (hwmgr->thermal_controller.fanInfo.bNoFan) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- if (smu_data->smu7_data.fan_table_start == 0) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- CG_FDO_CTRL1, FMAX_DUTY100);
-
- if (duty100 == 0) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
- usPWMMin * duty100;
- do_div(tmp64, 10000);
- fdo_min = (uint16_t)tmp64;
-
- t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
- hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
- t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
- hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-
- pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
- hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
- pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
- hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-
- slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
- slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-
- fan_table.TempMin = cpu_to_be16((50 + hwmgr->
- thermal_controller.advanceFanControlParameters.usTMin) / 100);
- fan_table.TempMed = cpu_to_be16((50 + hwmgr->
- thermal_controller.advanceFanControlParameters.usTMed) / 100);
- fan_table.TempMax = cpu_to_be16((50 + hwmgr->
- thermal_controller.advanceFanControlParameters.usTMax) / 100);
-
- fan_table.Slope1 = cpu_to_be16(slope1);
- fan_table.Slope2 = cpu_to_be16(slope2);
-
- fan_table.FdoMin = cpu_to_be16(fdo_min);
-
- fan_table.HystDown = cpu_to_be16(hwmgr->
- thermal_controller.advanceFanControlParameters.ucTHyst);
-
- fan_table.HystUp = cpu_to_be16(1);
-
- fan_table.HystSlope = cpu_to_be16(1);
-
- fan_table.TempRespLim = cpu_to_be16(5);
-
- reference_clock = smu7_get_xclk(hwmgr);
-
- fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
- thermal_controller.advanceFanControlParameters.ulCycleDelay *
- reference_clock) / 1600);
-
- fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-
- fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
- hwmgr->device, CGS_IND_REG__SMC,
- CG_MULT_THERMAL_CTRL, TEMP_SEL);
-
- res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start,
- (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
- SMC_RAM_END);
-
- if (!res && hwmgr->thermal_controller.
- advanceFanControlParameters.ucMinimumPWMLimit)
- res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetFanMinPwm,
- hwmgr->thermal_controller.
- advanceFanControlParameters.ucMinimumPWMLimit);
-
- if (!res && hwmgr->thermal_controller.
- advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
- res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SetFanSclkTarget,
- hwmgr->thermal_controller.
- advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
-
- if (res)
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
-
- return 0;
-}
-
-static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- smu_data->smc_state_table.UvdBootLevel = 0;
- if (table_info->mm_dep_table->count > 0)
- smu_data->smc_state_table.UvdBootLevel =
- (uint8_t) (table_info->mm_dep_table->count - 1);
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
- UvdBootLevel);
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0x00FFFFFF;
- mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDDPM) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_UVDDPM_SetEnabledMask,
- (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
- return 0;
-}
-
-static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smu_data->smc_state_table.VceBootLevel =
- (uint8_t) (table_info->mm_dep_table->count - 1);
- else
- smu_data->smc_state_table.VceBootLevel = 0;
-
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0xFF00FFFF;
- mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_VCEDPM_SetEnabledMask,
- (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
- return 0;
-}
-
-static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
-
-
- smu_data->smc_state_table.SamuBootLevel = 0;
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
-
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0xFFFFFF00;
- mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SAMUDPM_SetEnabledMask,
- (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
- return 0;
-}
-
-
-static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
- int max_entry, i;
-
- max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
- SMU74_MAX_LEVELS_LINK :
- pcie_table->count;
- /* Setup BIF_SCLK levels */
- for (i = 0; i < max_entry; i++)
- smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
- return 0;
-}
-
-int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
-{
- switch (type) {
- case SMU_UVD_TABLE:
- polaris10_update_uvd_smc_table(hwmgr);
- break;
- case SMU_VCE_TABLE:
- polaris10_update_vce_smc_table(hwmgr);
- break;
- case SMU_SAMU_TABLE:
- polaris10_update_samu_smc_table(hwmgr);
- break;
- case SMU_BIF_TABLE:
- polaris10_update_bif_smc_table(hwmgr);
- default:
- break;
- }
- return 0;
-}
-
-int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
-
- int result = 0;
- uint32_t low_sclk_interrupt_threshold = 0;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
- low_sclk_interrupt_threshold =
- data->low_sclk_interrupt_threshold;
-
- CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.dpm_table_start +
- offsetof(SMU74_Discrete_DpmTable,
- LowSclkInterruptThreshold),
- (uint8_t *)&low_sclk_interrupt_threshold,
- sizeof(uint32_t),
- SMC_RAM_END);
- }
- PP_ASSERT_WITH_CODE((result == 0),
- "Failed to update SCLK threshold!", return result);
-
- result = polaris10_program_mem_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE((result == 0),
- "Failed to program memory timing parameters!",
- );
-
- return result;
-}
-
-uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
-{
- switch (type) {
- case SMU_SoftRegisters:
- switch (member) {
- case HandshakeDisables:
- return offsetof(SMU74_SoftRegisters, HandshakeDisables);
- case VoltageChangeTimeout:
- return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
- case AverageGraphicsActivity:
- return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
- case PreVBlankGap:
- return offsetof(SMU74_SoftRegisters, PreVBlankGap);
- case VBlankTimeout:
- return offsetof(SMU74_SoftRegisters, VBlankTimeout);
- case UcodeLoadStatus:
- return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
- }
- case SMU_Discrete_DpmTable:
- switch (member) {
- case UvdBootLevel:
- return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
- case VceBootLevel:
- return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
- case SamuBootLevel:
- return offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
- case LowSclkInterruptThreshold:
- return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
- }
- }
- pr_warn("can't get the offset of type %x member %x\n", type, member);
- return 0;
-}
-
-uint32_t polaris10_get_mac_definition(uint32_t value)
-{
- switch (value) {
- case SMU_MAX_LEVELS_GRAPHICS:
- return SMU74_MAX_LEVELS_GRAPHICS;
- case SMU_MAX_LEVELS_MEMORY:
- return SMU74_MAX_LEVELS_MEMORY;
- case SMU_MAX_LEVELS_LINK:
- return SMU74_MAX_LEVELS_LINK;
- case SMU_MAX_ENTRIES_SMIO:
- return SMU74_MAX_ENTRIES_SMIO;
- case SMU_MAX_LEVELS_VDDC:
- return SMU74_MAX_LEVELS_VDDC;
- case SMU_MAX_LEVELS_VDDGFX:
- return SMU74_MAX_LEVELS_VDDGFX;
- case SMU_MAX_LEVELS_VDDCI:
- return SMU74_MAX_LEVELS_VDDCI;
- case SMU_MAX_LEVELS_MVDD:
- return SMU74_MAX_LEVELS_MVDD;
- case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
- return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
- }
-
- pr_warn("can't get the mac of %x\n", value);
- return 0;
-}
-
-/**
-* Get the location of various tables inside the FW image.
-*
-* @param hwmgr the address of the powerplay hardware manager.
-* @return always 0
-*/
-int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t tmp;
- int result;
- bool error = false;
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU74_Firmware_Header, DpmTable),
- &tmp, SMC_RAM_END);
-
- if (0 == result)
- smu_data->smu7_data.dpm_table_start = tmp;
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU74_Firmware_Header, SoftRegisters),
- &tmp, SMC_RAM_END);
-
- if (!result) {
- data->soft_regs_start = tmp;
- smu_data->smu7_data.soft_regs_start = tmp;
- }
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU74_Firmware_Header, mcRegisterTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.mc_reg_table_start = tmp;
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU74_Firmware_Header, FanTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.fan_table_start = tmp;
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.arb_table_start = tmp;
-
- error |= (0 != result);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU7_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU74_Firmware_Header, Version),
- &tmp, SMC_RAM_END);
-
- if (!result)
- hwmgr->microcode_version_info.SMC = tmp;
-
- error |= (0 != result);
-
- return error ? -1 : 0;
-}
-
-bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
-{
- return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
- ? true : false;
-}
-
-int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request)
-{
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
- (hwmgr->smumgr->backend);
- struct SMU74_Discrete_GraphicsLevel *levels =
- smu_data->smc_state_table.GraphicsLevel;
- uint32_t array = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
- uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
- SMU74_MAX_LEVELS_GRAPHICS;
- uint32_t i;
-
- for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
- levels[i].ActivityLevel =
- cpu_to_be16(request->activity_threshold);
- levels[i].EnabledForActivity = 1;
- levels[i].UpHyst = request->up_hyst;
- levels[i].DownHyst = request->down_hyst;
- }
-
- return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
- array_size, SMC_RAM_END);
-}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.h
deleted file mode 100644
index 1df8154..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef POLARIS10_SMC_H
-#define POLARIS10_SMC_H
-
-#include "smumgr.h"
-
-
-int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
-int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
-int polaris10_init_smc_table(struct pp_hwmgr *hwmgr);
-int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
-int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
-int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
-int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr);
-uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member);
-uint32_t polaris10_get_mac_definition(uint32_t value);
-int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr);
-bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr);
-int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request);
-
-#endif
-
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 75f43da..bd6be77 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -35,13 +35,47 @@
#include "gca/gfx_8_0_d.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
-#include "polaris10_pwrvirus.h"
#include "ppatomctrl.h"
#include "cgs_common.h"
-#include "polaris10_smc.h"
#include "smu7_ppsmc.h"
#include "smu7_smumgr.h"
+#include "smu7_dyn_defaults.h"
+
+#include "smu7_hwmgr.h"
+#include "hardwaremanager.h"
+#include "ppatomctrl.h"
+#include "atombios.h"
+#include "pppcielanes.h"
+
+#include "dce/dce_10_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+
+#define POLARIS10_SMC_SIZE 0x20000
+#define VOLTAGE_VID_OFFSET_SCALE1 625
+#define VOLTAGE_VID_OFFSET_SCALE2 100
+#define POWERTUNE_DEFAULT_SET_MAX 1
+#define VDDC_VDDCI_DELTA 200
+#define MC_CG_ARB_FREQ_F1 0x0b
+
+static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
+ /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
+ * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
+ { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
+ { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
+ { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
+};
+
+static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
+ {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
+ {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
+ {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
+ {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
+ {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
+ {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
+ {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
+ {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
+
#define PPPOLARIS10_TARGETACTIVITY_DFLT 50
static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
@@ -60,46 +94,13 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
-static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
-{
- int i;
- int result = -EINVAL;
- uint32_t reg, data;
-
- const PWR_Command_Table *pvirus = pwr_virus_table;
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-
- for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
- switch (pvirus->command) {
- case PwrCmdWrite:
- reg = pvirus->reg;
- data = pvirus->data;
- cgs_write_register(smumgr->device, reg, data);
- break;
-
- case PwrCmdEnd:
- result = 0;
- break;
-
- default:
- pr_info("Table Exit with Invalid Command!");
- smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
- result = -EINVAL;
- break;
- }
- pvirus++;
- }
-
- return result;
-}
-
-static int polaris10_perform_btc(struct pp_smumgr *smumgr)
+static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
{
int result = 0;
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
if (0 != smu_data->avfs.avfs_btc_param) {
- if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
+ if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
result = -1;
}
@@ -107,16 +108,16 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
if (smu_data->avfs.avfs_btc_param > 1) {
/* Soft-Reset to reset the engine before loading uCode */
/* halt */
- cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
+ cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
/* reset everything */
- cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
- cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
+ cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
+ cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
}
return result;
}
-static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
+static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
{
uint32_t vr_config;
uint32_t dpm_table_start;
@@ -127,7 +128,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
graphics_level_size = sizeof(avfs_graphics_level_polaris10);
u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
- PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
&dpm_table_start, 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
@@ -138,14 +139,14 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
- PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address,
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
return -1);
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
- PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
(uint8_t *)(&avfs_graphics_level_polaris10),
graphics_level_size, 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
@@ -153,7 +154,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
- PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
return -1);
@@ -162,7 +163,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
- PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
+ PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
return -1);
@@ -172,9 +173,9 @@ static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
static int
-polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
+polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
switch (smu_data->avfs.avfs_btc_status) {
case AVFS_BTC_COMPLETED_PREVIOUSLY:
@@ -183,20 +184,20 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
- PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
+ PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
return -EINVAL);
if (smu_data->avfs.avfs_btc_param > 1) {
pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
- PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(smumgr),
+ PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
return -EINVAL);
}
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
- PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
+ PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
"[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
return -EINVAL);
smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
@@ -215,146 +216,146 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
return 0;
}
-static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
+static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* Wait for smc boot up */
- /* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
+ /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
/* Assert reset */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- result = smu7_upload_smu_firmware_image(smumgr);
+ result = smu7_upload_smu_firmware_image(hwmgr);
if (result != 0)
return result;
/* Clear status */
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
/* Call Test SMU message with 0x20000 offset to trigger SMU start */
- smu7_send_msg_to_smc_offset(smumgr);
+ smu7_send_msg_to_smc_offset(hwmgr);
/* Wait done bit to be set */
/* Check pass/failed indicator */
- SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
+ PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
- if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_STATUS, SMU_PASS))
PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
-static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
+static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* wait for smc boot up */
- SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
+ PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
/* Clear firmware interrupt enable flag */
- /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL,
rst_reg, 1);
- result = smu7_upload_smu_firmware_image(smumgr);
+ result = smu7_upload_smu_firmware_image(hwmgr);
if (result != 0)
return result;
/* Set smc instruct start point at 0x0 */
- smu7_program_jump_on_start(smumgr);
+ smu7_program_jump_on_start(hwmgr);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
-static int polaris10_start_smu(struct pp_smumgr *smumgr)
+static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
{
int result = 0;
- struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
bool SMU_VFT_INTACT;
/* Only start SMC if SMC RAM is not running */
- if (!smu7_is_smc_ram_running(smumgr)) {
+ if (!smu7_is_smc_ram_running(hwmgr)) {
SMU_VFT_INTACT = false;
- smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
- smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
+ smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
+ smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
/* Check if SMU is running in protected mode */
if (smu_data->protected_mode == 0) {
- result = polaris10_start_smu_in_non_protection_mode(smumgr);
+ result = polaris10_start_smu_in_non_protection_mode(hwmgr);
} else {
- result = polaris10_start_smu_in_protection_mode(smumgr);
+ result = polaris10_start_smu_in_protection_mode(hwmgr);
/* If failed, try with different security Key. */
if (result != 0) {
smu_data->smu7_data.security_hard_key ^= 1;
- cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
- result = polaris10_start_smu_in_protection_mode(smumgr);
+ cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
+ result = polaris10_start_smu_in_protection_mode(hwmgr);
}
}
if (result != 0)
PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
- polaris10_avfs_event_mgr(smumgr, true);
+ polaris10_avfs_event_mgr(hwmgr, true);
} else
SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
- polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
+ polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT);
/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
- smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
+ smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
&(smu_data->smu7_data.soft_regs_start), 0x40000);
- result = smu7_request_smu_load_fw(smumgr);
+ result = smu7_request_smu_load_fw(hwmgr);
return result;
}
-static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
+static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
{
uint32_t efuse;
- efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
+ efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
efuse &= 0x00000001;
if (efuse)
return true;
@@ -362,7 +363,7 @@ static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
return false;
}
-static int polaris10_smu_init(struct pp_smumgr *smumgr)
+static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
{
struct polaris10_smumgr *smu_data;
int i;
@@ -371,9 +372,9 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
if (smu_data == NULL)
return -ENOMEM;
- smumgr->backend = smu_data;
+ hwmgr->smu_backend = smu_data;
- if (smu7_init(smumgr))
+ if (smu7_init(hwmgr))
return -EINVAL;
for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
@@ -382,6 +383,2195 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr)
return 0;
}
+static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
+ uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
+{
+ uint32_t i;
+ uint16_t vddci;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ *voltage = *mvdd = 0;
+
+ /* clock - voltage dependency table is empty table */
+ if (dep_table->count == 0)
+ return -EINVAL;
+
+ for (i = 0; i < dep_table->count; i++) {
+ /* find first sclk bigger than request */
+ if (dep_table->entries[i].clk >= clock) {
+ *voltage |= (dep_table->entries[i].vddc *
+ VOLTAGE_SCALE) << VDDC_SHIFT;
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ *voltage |= (data->vbios_boot_state.vddci_bootup_value *
+ VOLTAGE_SCALE) << VDDCI_SHIFT;
+ else if (dep_table->entries[i].vddci)
+ *voltage |= (dep_table->entries[i].vddci *
+ VOLTAGE_SCALE) << VDDCI_SHIFT;
+ else {
+ vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
+ (dep_table->entries[i].vddc -
+ (uint16_t)VDDC_VDDCI_DELTA));
+ *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ }
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
+ *mvdd = data->vbios_boot_state.mvdd_bootup_value *
+ VOLTAGE_SCALE;
+ else if (dep_table->entries[i].mvdd)
+ *mvdd = (uint32_t) dep_table->entries[i].mvdd *
+ VOLTAGE_SCALE;
+
+ *voltage |= 1 << PHASES_SHIFT;
+ return 0;
+ }
+ }
+
+ /* sclk is bigger than max sclk in the dependence table */
+ *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
+ *voltage |= (data->vbios_boot_state.vddci_bootup_value *
+ VOLTAGE_SCALE) << VDDCI_SHIFT;
+ else if (dep_table->entries[i-1].vddci) {
+ vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
+ (dep_table->entries[i].vddc -
+ (uint16_t)VDDC_VDDCI_DELTA));
+ *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ }
+
+ if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
+ *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
+ else if (dep_table->entries[i].mvdd)
+ *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
+
+ return 0;
+}
+
+static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
+{
+ uint32_t tmp;
+ tmp = raw_setting * 4096 / 100;
+ return (uint16_t)tmp;
+}
+
+static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+ const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
+ SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
+ struct pp_advance_fan_control_parameters *fan_table =
+ &hwmgr->thermal_controller.advanceFanControlParameters;
+ int i, j, k;
+ const uint16_t *pdef1;
+ const uint16_t *pdef2;
+
+ table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
+ table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
+
+ PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
+ "Target Operating Temp is out of Range!",
+ );
+
+ table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTargetOperatingTemp * 256);
+ table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitHotspot * 256);
+ table->FanGainEdge = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainEdge));
+ table->FanGainHotspot = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainHotspot));
+
+ pdef1 = defaults->BAPMTI_R;
+ pdef2 = defaults->BAPMTI_RC;
+
+ for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
+ for (j = 0; j < SMU74_DTE_SOURCES; j++) {
+ for (k = 0; k < SMU74_DTE_SINKS; k++) {
+ table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
+ table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
+ pdef1++;
+ pdef2++;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
+ smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
+ smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
+ smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
+
+ return 0;
+}
+
+static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
+{
+ uint16_t tdc_limit;
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
+ smu_data->power_tune_table.TDC_VDDC_PkgLimit =
+ CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
+ smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
+ defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
+ smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
+
+ return 0;
+}
+
+static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
+ uint32_t temp;
+
+ if (smu7_read_smc_sram_dword(hwmgr,
+ fuse_table_offset +
+ offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
+ (uint32_t *)&temp, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
+ return -EINVAL);
+ else {
+ smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
+ smu_data->power_tune_table.LPMLTemperatureMin =
+ (uint8_t)((temp >> 16) & 0xff);
+ smu_data->power_tune_table.LPMLTemperatureMax =
+ (uint8_t)((temp >> 8) & 0xff);
+ smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
+ }
+ return 0;
+}
+
+static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+ /* Currently not used. Set all to zero. */
+ for (i = 0; i < 16; i++)
+ smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
+
+ return 0;
+}
+
+static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+/* TO DO move to hwmgr */
+ if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
+ || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
+ hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
+
+ smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
+ return 0;
+}
+
+static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+ /* Currently not used. Set all to zero. */
+ for (i = 0; i < 16; i++)
+ smu_data->power_tune_table.GnbLPML[i] = 0;
+
+ return 0;
+}
+
+static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
+ uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
+ struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
+
+ hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
+ lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
+
+ smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
+ smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
+
+ return 0;
+}
+
+static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ uint32_t pm_fuse_table_offset;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment)) {
+ if (smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU74_Firmware_Header, PmFuseTable),
+ &pm_fuse_table_offset, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to get pm_fuse_table_offset Failed!",
+ return -EINVAL);
+
+ if (polaris10_populate_svi_load_line(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate SviLoadLine Failed!",
+ return -EINVAL);
+
+ if (polaris10_populate_tdc_limit(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TDCLimit Failed!", return -EINVAL);
+
+ if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TdcWaterfallCtl, "
+ "LPMLTemperature Min and Max Failed!",
+ return -EINVAL);
+
+ if (0 != polaris10_populate_temperature_scaler(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate LPMLTemperatureScaler Failed!",
+ return -EINVAL);
+
+ if (polaris10_populate_fuzzy_fan(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate Fuzzy Fan Control parameters Failed!",
+ return -EINVAL);
+
+ if (polaris10_populate_gnb_lpml(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate GnbLPML Failed!",
+ return -EINVAL);
+
+ if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
+ "Sidd Failed!", return -EINVAL);
+
+ if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
+ (uint8_t *)&smu_data->power_tune_table,
+ (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to download PmFuseTable Failed!",
+ return -EINVAL);
+ }
+ return 0;
+}
+
+static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ SMU74_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t count, level;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+ count = data->mvdd_voltage_table.count;
+ if (count > SMU_MAX_SMIO_LEVELS)
+ count = SMU_MAX_SMIO_LEVELS;
+ for (level = 0; level < count; level++) {
+ table->SmioTable2.Pattern[level].Voltage =
+ PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
+ /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
+ table->SmioTable2.Pattern[level].Smio =
+ (uint8_t) level;
+ table->Smio[level] |=
+ data->mvdd_voltage_table.entries[level].smio_low;
+ }
+ table->SmioMask2 = data->mvdd_voltage_table.mask_low;
+
+ table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
+ }
+
+ return 0;
+}
+
+static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ uint32_t count, level;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ count = data->vddci_voltage_table.count;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ if (count > SMU_MAX_SMIO_LEVELS)
+ count = SMU_MAX_SMIO_LEVELS;
+ for (level = 0; level < count; ++level) {
+ table->SmioTable1.Pattern[level].Voltage =
+ PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
+ table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
+
+ table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
+ }
+ }
+
+ table->SmioMask1 = data->vddci_voltage_table.mask_low;
+
+ return 0;
+}
+
+static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ uint32_t count;
+ uint8_t index;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_voltage_lookup_table *lookup_table =
+ table_info->vddc_lookup_table;
+ /* tables is already swapped, so in order to use the value from it,
+ * we need to swap it back.
+ * We are populating vddc CAC data to BapmVddc table
+ * in split and merged mode
+ */
+ for (count = 0; count < lookup_table->count; count++) {
+ index = phm_get_voltage_index(lookup_table,
+ data->vddc_voltage_table.entries[count].value);
+ table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
+ table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
+ table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
+ }
+
+ return 0;
+}
+
+static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ polaris10_populate_smc_vddci_table(hwmgr, table);
+ polaris10_populate_smc_mvdd_table(hwmgr, table);
+ polaris10_populate_cac_table(hwmgr, table);
+
+ return 0;
+}
+
+static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_Ulv *state)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ state->CcPwrDynRm = 0;
+ state->CcPwrDynRm1 = 0;
+
+ state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
+ state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
+ VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
+
+ if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
+ state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
+ else
+ state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
+ CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
+
+ return 0;
+}
+
+static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
+}
+
+static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ int i;
+
+ /* Index (dpm_table->pcie_speed_table.count)
+ * is reserved for PCIE boot level. */
+ for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
+ table->LinkLevel[i].PcieGenSpeed =
+ (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
+ table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
+ dpm_table->pcie_speed_table.dpm_levels[i].param1);
+ table->LinkLevel[i].EnabledForActivity = 1;
+ table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
+ table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
+ table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
+ }
+
+ smu_data->smc_state_table.LinkLevelCount =
+ (uint8_t)dpm_table->pcie_speed_table.count;
+
+/* To Do move to hwmgr */
+ data->dpm_level_enable_mask.pcie_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
+
+ return 0;
+}
+
+
+static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
+ SMU74_Discrete_DpmTable *table)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ uint32_t i, ref_clk;
+
+ struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
+
+ ref_clk = smu7_get_xclk(hwmgr);
+
+ if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
+ for (i = 0; i < NUM_SCLK_RANGE; i++) {
+ table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
+ table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
+ table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
+
+ table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
+ table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
+
+ CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
+ CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
+ CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
+ }
+ return;
+ }
+
+ for (i = 0; i < NUM_SCLK_RANGE; i++) {
+ smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
+ smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
+
+ table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
+ table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
+ table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
+
+ table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
+ table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
+
+ CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
+ CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
+ CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
+ }
+}
+
+static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
+ uint32_t clock, SMU_SclkSetting *sclk_setting)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ struct pp_atomctrl_clock_dividers_ai dividers;
+ uint32_t ref_clock;
+ uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
+ uint8_t i;
+ int result;
+ uint64_t temp;
+
+ sclk_setting->SclkFrequency = clock;
+ /* get the engine clock dividers for this clock value */
+ result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
+ if (result == 0) {
+ sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
+ sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
+ sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
+ sclk_setting->PllRange = dividers.ucSclkPllRange;
+ sclk_setting->Sclk_slew_rate = 0x400;
+ sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
+ sclk_setting->Pcc_down_slew_rate = 0xffff;
+ sclk_setting->SSc_En = dividers.ucSscEnable;
+ sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
+ sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
+ sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
+ return result;
+ }
+
+ ref_clock = smu7_get_xclk(hwmgr);
+
+ for (i = 0; i < NUM_SCLK_RANGE; i++) {
+ if (clock > smu_data->range_table[i].trans_lower_frequency
+ && clock <= smu_data->range_table[i].trans_upper_frequency) {
+ sclk_setting->PllRange = i;
+ break;
+ }
+ }
+
+ sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
+ temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
+ temp <<= 0x10;
+ do_div(temp, ref_clock);
+ sclk_setting->Fcw_frac = temp & 0xffff;
+
+ pcc_target_percent = 10; /* Hardcode 10% for now. */
+ pcc_target_freq = clock - (clock * pcc_target_percent / 100);
+ sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
+
+ ss_target_percent = 2; /* Hardcode 2% for now. */
+ sclk_setting->SSc_En = 0;
+ if (ss_target_percent) {
+ sclk_setting->SSc_En = 1;
+ ss_target_freq = clock - (clock * ss_target_percent / 100);
+ sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
+ temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
+ temp <<= 0x10;
+ do_div(temp, ref_clock);
+ sclk_setting->Fcw1_frac = temp & 0xffff;
+ }
+
+ return 0;
+}
+
+static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ uint32_t clock, uint16_t sclk_al_threshold,
+ struct SMU74_Discrete_GraphicsLevel *level)
+{
+ int result;
+ /* PP_Clocks minClocks; */
+ uint32_t mvdd;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ SMU_SclkSetting curr_sclk_setting = { 0 };
+
+ result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
+
+ /* populate graphics levels */
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_sclk, clock,
+ &level->MinVoltage, &mvdd);
+
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find VDDC voltage value for "
+ "VDDC engine clock dependency table",
+ return result);
+ level->ActivityLevel = sclk_al_threshold;
+
+ level->CcPwrDynRm = 0;
+ level->CcPwrDynRm1 = 0;
+ level->EnabledForActivity = 0;
+ level->EnabledForThrottle = 1;
+ level->UpHyst = 10;
+ level->DownHyst = 0;
+ level->VoltageDownHyst = 0;
+ level->PowerThrottle = 0;
+ data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
+ level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
+ hwmgr->display_config.min_core_set_clock_in_sr);
+
+ /* Default to slow, highest DPM level will be
+ * set to PPSMC_DISPLAY_WATERMARK_LOW later.
+ */
+ if (data->update_up_hyst)
+ level->UpHyst = (uint8_t)data->up_hyst;
+ if (data->update_down_hyst)
+ level->DownHyst = (uint8_t)data->down_hyst;
+
+ level->SclkSetting = curr_sclk_setting;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
+ CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
+ CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
+ return 0;
+}
+
+static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
+ uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
+ int result = 0;
+ uint32_t array = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
+ uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
+ SMU74_MAX_LEVELS_GRAPHICS;
+ struct SMU74_Discrete_GraphicsLevel *levels =
+ smu_data->smc_state_table.GraphicsLevel;
+ uint32_t i, max_entry;
+ uint8_t hightest_pcie_level_enabled = 0,
+ lowest_pcie_level_enabled = 0,
+ mid_pcie_level_enabled = 0,
+ count = 0;
+
+ polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
+
+ for (i = 0; i < dpm_table->sclk_table.count; i++) {
+
+ result = polaris10_populate_single_graphic_level(hwmgr,
+ dpm_table->sclk_table.dpm_levels[i].value,
+ (uint16_t)smu_data->activity_target[i],
+ &(smu_data->smc_state_table.GraphicsLevel[i]));
+ if (result)
+ return result;
+
+ /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
+ if (i > 1)
+ levels[i].DeepSleepDivId = 0;
+ }
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SPLLShutdownSupport))
+ smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
+
+ smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
+ smu_data->smc_state_table.GraphicsDpmLevelCount =
+ (uint8_t)dpm_table->sclk_table.count;
+ hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
+
+
+ if (pcie_table != NULL) {
+ PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
+ "There must be 1 or more PCIE levels defined in PPTable.",
+ return -EINVAL);
+ max_entry = pcie_entry_cnt - 1;
+ for (i = 0; i < dpm_table->sclk_table.count; i++)
+ levels[i].pcieDpmLevel =
+ (uint8_t) ((i < max_entry) ? i : max_entry);
+ } else {
+ while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
+ ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << (hightest_pcie_level_enabled + 1))) != 0))
+ hightest_pcie_level_enabled++;
+
+ while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
+ ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << lowest_pcie_level_enabled)) == 0))
+ lowest_pcie_level_enabled++;
+
+ while ((count < hightest_pcie_level_enabled) &&
+ ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
+ count++;
+
+ mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
+ hightest_pcie_level_enabled ?
+ (lowest_pcie_level_enabled + 1 + count) :
+ hightest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to hightest_pcie_level_enabled */
+ for (i = 2; i < dpm_table->sclk_table.count; i++)
+ levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to lowest_pcie_level_enabled */
+ levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to mid_pcie_level_enabled */
+ levels[1].pcieDpmLevel = mid_pcie_level_enabled;
+ }
+ /* level count will send to smc once at init smc table and never change */
+ result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ (uint32_t)array_size, SMC_RAM_END);
+
+ return result;
+}
+
+
+static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
+ uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ int result = 0;
+ struct cgs_display_info info = {0, 0, NULL};
+ uint32_t mclk_stutter_mode_threshold = 40000;
+
+ cgs_get_active_displays_info(hwmgr->device, &info);
+
+ if (table_info->vdd_dep_on_mclk) {
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_mclk, clock,
+ &mem_level->MinVoltage, &mem_level->MinMvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find MinVddc voltage value from memory "
+ "VDDC voltage dependency table", return result);
+ }
+
+ mem_level->MclkFrequency = clock;
+ mem_level->EnabledForThrottle = 1;
+ mem_level->EnabledForActivity = 0;
+ mem_level->UpHyst = 0;
+ mem_level->DownHyst = 100;
+ mem_level->VoltageDownHyst = 0;
+ mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+ mem_level->StutterEnable = false;
+ mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ data->display_timing.num_existing_displays = info.display_count;
+
+ if (mclk_stutter_mode_threshold &&
+ (clock <= mclk_stutter_mode_threshold) &&
+ (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
+ STUTTER_ENABLE) & 0x1))
+ mem_level->StutterEnable = true;
+
+ if (!result) {
+ CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
+ CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
+ }
+ return result;
+}
+
+static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
+ int result;
+ /* populate MCLK dpm table to SMU7 */
+ uint32_t array = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
+ uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
+ SMU74_MAX_LEVELS_MEMORY;
+ struct SMU74_Discrete_MemoryLevel *levels =
+ smu_data->smc_state_table.MemoryLevel;
+ uint32_t i;
+
+ for (i = 0; i < dpm_table->mclk_table.count; i++) {
+ PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
+ "can not populate memory level as memory clock is zero",
+ return -EINVAL);
+ result = polaris10_populate_single_memory_level(hwmgr,
+ dpm_table->mclk_table.dpm_levels[i].value,
+ &levels[i]);
+ if (i == dpm_table->mclk_table.count - 1) {
+ levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
+ levels[i].EnabledForActivity = 1;
+ }
+ if (result)
+ return result;
+ }
+
+ /* In order to prevent MC activity from stutter mode to push DPM up,
+ * the UVD change complements this by putting the MCLK in
+ * a higher state by default such that we are not affected by
+ * up threshold or and MCLK DPM latency.
+ */
+ levels[0].ActivityLevel = 0x1f;
+ CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
+
+ smu_data->smc_state_table.MemoryDpmLevelCount =
+ (uint8_t)dpm_table->mclk_table.count;
+ hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
+
+ /* level count will send to smc once at init smc table and never change */
+ result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ (uint32_t)array_size, SMC_RAM_END);
+
+ return result;
+}
+
+static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
+ uint32_t mclk, SMIO_Pattern *smio_pat)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint32_t i = 0;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
+ /* find mvdd value which clock is more than request */
+ for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
+ if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
+ smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
+ break;
+ }
+ }
+ PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
+ "MVDD Voltage is outside the supported range.",
+ return -EINVAL);
+ } else
+ return -EINVAL;
+
+ return 0;
+}
+
+static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ SMU74_Discrete_DpmTable *table)
+{
+ int result = 0;
+ uint32_t sclk_frequency;
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ SMIO_Pattern vol_level;
+ uint32_t mvdd;
+ uint16_t us_mvdd;
+
+ table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
+
+ /* Get MinVoltage and Frequency from DPM0,
+ * already converted to SMC_UL */
+ sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_sclk,
+ sclk_frequency,
+ &table->ACPILevel.MinVoltage, &mvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Cannot find ACPI VDDC voltage value "
+ "in Clock Dependency Table",
+ );
+
+ result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
+ PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
+
+ table->ACPILevel.DeepSleepDivId = 0;
+ table->ACPILevel.CcPwrDynRm = 0;
+ table->ACPILevel.CcPwrDynRm1 = 0;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
+ CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
+
+
+ /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
+ table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
+ result = polaris10_get_dependency_volt_by_clk(hwmgr,
+ table_info->vdd_dep_on_mclk,
+ table->MemoryACPILevel.MclkFrequency,
+ &table->MemoryACPILevel.MinVoltage, &mvdd);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Cannot find ACPI VDDCI voltage value "
+ "in Clock Dependency Table",
+ );
+
+ us_mvdd = 0;
+ if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
+ (data->mclk_dpm_key_disabled))
+ us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
+ else {
+ if (!polaris10_populate_mvdd_value(hwmgr,
+ data->dpm_table.mclk_table.dpm_levels[0].value,
+ &vol_level))
+ us_mvdd = vol_level.Voltage;
+ }
+
+ if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
+ table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
+ else
+ table->MemoryACPILevel.MinMvdd = 0;
+
+ table->MemoryACPILevel.StutterEnable = false;
+
+ table->MemoryACPILevel.EnabledForThrottle = 0;
+ table->MemoryACPILevel.EnabledForActivity = 0;
+ table->MemoryACPILevel.UpHyst = 0;
+ table->MemoryACPILevel.DownHyst = 100;
+ table->MemoryACPILevel.VoltageDownHyst = 0;
+ table->MemoryACPILevel.ActivityLevel =
+ PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
+
+ return result;
+}
+
+static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
+ SMU74_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ table_info->mm_dep_table;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t vddci;
+
+ table->VceLevelCount = (uint8_t)(mm_table->count);
+ table->VceBootLevel = 0;
+
+ for (count = 0; count < table->VceLevelCount; count++) {
+ table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
+ table->VceLevel[count].MinVoltage = 0;
+ table->VceLevel[count].MinVoltage |=
+ (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
+ vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
+ mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+ else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
+ vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
+ else
+ vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
+
+
+ table->VceLevel[count].MinVoltage |=
+ (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+ /*retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->VceLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for VCE engine clock",
+ return result);
+
+ table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+
+static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
+ SMU74_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ table_info->mm_dep_table;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t vddci;
+
+ table->SamuBootLevel = 0;
+ table->SamuLevelCount = (uint8_t)(mm_table->count);
+
+ for (count = 0; count < table->SamuLevelCount; count++) {
+ /* not sure whether we need evclk or not */
+ table->SamuLevel[count].MinVoltage = 0;
+ table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
+ table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
+ VOLTAGE_SCALE) << VDDC_SHIFT;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
+ vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
+ mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+ else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
+ vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
+ else
+ vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
+
+ table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->SamuLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for samu clock", return result);
+
+ table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
+ }
+ return result;
+}
+
+static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
+ int32_t eng_clock, int32_t mem_clock,
+ SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
+{
+ uint32_t dram_timing;
+ uint32_t dram_timing2;
+ uint32_t burst_time;
+ int result;
+
+ result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
+ eng_clock, mem_clock);
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error calling VBIOS to set DRAM_TIMING.", return result);
+
+ dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
+ dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
+ burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
+
+
+ arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
+ arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
+ arb_regs->McArbBurstTime = (uint8_t)burst_time;
+
+ return 0;
+}
+
+static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
+ uint32_t i, j;
+ int result = 0;
+
+ for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
+ for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
+ result = polaris10_populate_memory_timing_parameters(hwmgr,
+ hw_data->dpm_table.sclk_table.dpm_levels[i].value,
+ hw_data->dpm_table.mclk_table.dpm_levels[j].value,
+ &arb_regs.entries[i][j]);
+ if (result == 0)
+ result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
+ if (result != 0)
+ return result;
+ }
+ }
+
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.arb_table_start,
+ (uint8_t *)&arb_regs,
+ sizeof(SMU74_Discrete_MCArbDramTimingTable),
+ SMC_RAM_END);
+ return result;
+}
+
+static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ int result = -EINVAL;
+ uint8_t count;
+ struct pp_atomctrl_clock_dividers_vi dividers;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ table_info->mm_dep_table;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t vddci;
+
+ table->UvdLevelCount = (uint8_t)(mm_table->count);
+ table->UvdBootLevel = 0;
+
+ for (count = 0; count < table->UvdLevelCount; count++) {
+ table->UvdLevel[count].MinVoltage = 0;
+ table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
+ table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
+ table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
+ VOLTAGE_SCALE) << VDDC_SHIFT;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
+ vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
+ mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+ else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
+ vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
+ else
+ vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
+
+ table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+ table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->UvdLevel[count].VclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for Vclk clock", return result);
+
+ table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
+
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->UvdLevel[count].DclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE((0 == result),
+ "can not find divide id for Dclk clock", return result);
+
+ table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
+ }
+
+ return result;
+}
+
+static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ table->GraphicsBootLevel = 0;
+ table->MemoryBootLevel = 0;
+
+ /* find boot level from dpm table */
+ result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+ data->vbios_boot_state.sclk_bootup_value,
+ (uint32_t *)&(table->GraphicsBootLevel));
+
+ result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+ data->vbios_boot_state.mclk_bootup_value,
+ (uint32_t *)&(table->MemoryBootLevel));
+
+ table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
+ VOLTAGE_SCALE;
+ table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
+ VOLTAGE_SCALE;
+ table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
+ VOLTAGE_SCALE;
+
+ CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
+ CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
+ CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
+
+ return 0;
+}
+
+static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint8_t count, level;
+
+ count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
+
+ for (level = 0; level < count; level++) {
+ if (table_info->vdd_dep_on_sclk->entries[level].clk >=
+ hw_data->vbios_boot_state.sclk_bootup_value) {
+ smu_data->smc_state_table.GraphicsBootLevel = level;
+ break;
+ }
+ }
+
+ count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
+ for (level = 0; level < count; level++) {
+ if (table_info->vdd_dep_on_mclk->entries[level].clk >=
+ hw_data->vbios_boot_state.mclk_bootup_value) {
+ smu_data->smc_state_table.MemoryBootLevel = level;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+{
+ uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+ uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+ table_info->vdd_dep_on_sclk;
+
+ stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
+
+ /* Read SMU_Eefuse to read and calculate RO and determine
+ * if the part is SS or FF. if RO >= 1660MHz, part is FF.
+ */
+ efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixSMU_EFUSE_0 + (67 * 4));
+ efuse &= 0xFF000000;
+ efuse = efuse >> 24;
+
+ if (hwmgr->chip_id == CHIP_POLARIS10) {
+ min = 1000;
+ max = 2300;
+ } else {
+ min = 1100;
+ max = 2100;
+ }
+
+ ro = efuse * (max - min) / 255 + min;
+
+ /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
+ for (i = 0; i < sclk_table->count; i++) {
+ smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
+ sclk_table->entries[i].cks_enable << i;
+ if (hwmgr->chip_id == CHIP_POLARIS10) {
+ volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
+ (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
+ volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
+ (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
+ } else {
+ volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
+ (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
+ volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
+ (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
+ }
+
+ if (volt_without_cks >= volt_with_cks)
+ volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
+ sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
+
+ smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
+ }
+
+ smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
+ /* Populate CKS Lookup Table */
+ if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
+ stretch_amount2 = 0;
+ else if (stretch_amount == 3 || stretch_amount == 4)
+ stretch_amount2 = 1;
+ else {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ClockStretcher);
+ PP_ASSERT_WITH_CODE(false,
+ "Stretch Amount in PPTable not supported\n",
+ return -EINVAL);
+ }
+
+ value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
+ value &= 0xFFFFFFFE;
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
+
+ return 0;
+}
+
+static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
+ struct SMU74_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ uint16_t config;
+
+ config = VR_MERGED_WITH_VDDC;
+ table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
+
+ /* Set Vddc Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
+ config = VR_SVI2_PLANE_1;
+ table->VRConfig |= config;
+ } else {
+ PP_ASSERT_WITH_CODE(false,
+ "VDDC should be on SVI2 control in merged mode!",
+ );
+ }
+ /* Set Vddci Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
+ config = VR_SVI2_PLANE_2; /* only in merged mode */
+ table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
+ } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ config = VR_SMIO_PATTERN_1;
+ table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
+ } else {
+ config = VR_STATIC_VOLTAGE;
+ table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
+ }
+ /* Set Mvdd Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
+ config = VR_SVI2_PLANE_2;
+ table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
+ offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
+ } else {
+ config = VR_STATIC_VOLTAGE;
+ table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+ }
+
+ return 0;
+}
+
+
+static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+ SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ int result = 0;
+ struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
+ AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
+ AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
+ uint32_t tmp, i;
+
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)hwmgr->pptable;
+ struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+ table_info->vdd_dep_on_sclk;
+
+
+ if (((struct smu7_smumgr *)smu_data)->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return result;
+
+ result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
+
+ if (0 == result) {
+ table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
+ table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
+ table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
+ table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
+ table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
+ table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
+ table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
+ table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
+ table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
+ table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
+ table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
+ table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
+ table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
+ table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
+ table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
+ table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
+ table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
+ AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
+ AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
+ AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
+ AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
+ AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
+ AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
+ AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
+
+ for (i = 0; i < NUM_VFT_COLUMNS; i++) {
+ AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
+ AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
+ }
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
+ &tmp, SMC_RAM_END);
+
+ smu7_copy_bytes_to_smc(hwmgr,
+ tmp,
+ (uint8_t *)&AVFS_meanNsigma,
+ sizeof(AVFS_meanNsigma_t),
+ SMC_RAM_END);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
+ &tmp, SMC_RAM_END);
+ smu7_copy_bytes_to_smc(hwmgr,
+ tmp,
+ (uint8_t *)&AVFS_SclkOffset,
+ sizeof(AVFS_Sclk_Offset_t),
+ SMC_RAM_END);
+
+ data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
+ (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
+ (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
+ (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
+ data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
+ }
+ return result;
+}
+
+static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ uint32_t tmp;
+ int result;
+
+ /* This is a read-modify-write on the first byte of the ARB table.
+ * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
+ * is the field 'current'.
+ * This solution is ugly, but we never write the whole table only
+ * individual fields in it.
+ * In reality this field should not be in that structure
+ * but in a soft register.
+ */
+ result = smu7_read_smc_sram_dword(hwmgr,
+ smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
+
+ if (result)
+ return result;
+
+ tmp &= 0x00FFFFFF;
+ tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
+
+ return smu7_write_smc_sram_dword(hwmgr,
+ smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
+}
+
+static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ if (table_info &&
+ table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
+ table_info->cac_dtp_table->usPowerTuneDataSetID)
+ smu_data->power_tune_defaults =
+ &polaris10_power_tune_data_set_array
+ [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
+ else
+ smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
+
+}
+
+static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct SMU74_Discrete_GraphicsLevel *levels =
+ data->smc_state_table.GraphicsLevel;
+ unsigned min_level = 1;
+
+ hwmgr->default_gfx_power_profile.activity_threshold =
+ be16_to_cpu(levels[0].ActivityLevel);
+ hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
+ hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
+ hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
+
+ hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
+ hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
+
+ /* Workaround compute SDMA instability: disable lowest SCLK
+ * DPM level. Optimize compute power profile: Use only highest
+ * 2 power levels (if more than 2 are available), Hysteresis:
+ * 0ms up, 5ms down
+ */
+ if (data->smc_state_table.GraphicsDpmLevelCount > 2)
+ min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
+ else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
+ min_level = 1;
+ else
+ min_level = 0;
+ hwmgr->default_compute_power_profile.min_sclk =
+ be32_to_cpu(levels[min_level].SclkSetting.SclkFrequency);
+ hwmgr->default_compute_power_profile.up_hyst = 0;
+ hwmgr->default_compute_power_profile.down_hyst = 5;
+
+ hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
+ hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
+}
+
+static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ uint8_t i;
+ struct pp_atomctrl_gpio_pin_assignment gpio_pin;
+ pp_atomctrl_clock_dividers_vi dividers;
+
+ polaris10_initialize_power_tune_defaults(hwmgr);
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
+ polaris10_populate_smc_voltage_tables(hwmgr, table);
+
+ table->SystemFlags = 0;
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StepVddc))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
+
+ if (hw_data->is_memory_gddr5)
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
+
+ if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
+ result = polaris10_populate_ulv_state(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ULV state!", return result);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
+ }
+
+ result = polaris10_populate_smc_link_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Link Level!", return result);
+
+ result = polaris10_populate_all_graphic_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Graphics Level!", return result);
+
+ result = polaris10_populate_all_memory_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Memory Level!", return result);
+
+ result = polaris10_populate_smc_acpi_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize ACPI Level!", return result);
+
+ result = polaris10_populate_smc_vce_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize VCE Level!", return result);
+
+ result = polaris10_populate_smc_samu_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize SAMU Level!", return result);
+
+ /* Since only the initial state is completely set up at this point
+ * (the other states are just copies of the boot state) we only
+ * need to populate the ARB settings for the initial state.
+ */
+ result = polaris10_program_memory_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to Write ARB settings for the initial state.", return result);
+
+ result = polaris10_populate_smc_uvd_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize UVD Level!", return result);
+
+ result = polaris10_populate_smc_boot_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Boot Level!", return result);
+
+ result = polaris10_populate_smc_initailial_state(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to initialize Boot State!", return result);
+
+ result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate BAPM Parameters!", return result);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ClockStretcher)) {
+ result = polaris10_populate_clock_stretcher_data_table(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate Clock Stretcher Data Table!",
+ return result);
+ }
+
+ result = polaris10_populate_avfs_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
+
+ table->CurrSclkPllRange = 0xff;
+ table->GraphicsVoltageChangeEnable = 1;
+ table->GraphicsThermThrottleEnable = 1;
+ table->GraphicsInterval = 1;
+ table->VoltageInterval = 1;
+ table->ThermalInterval = 1;
+ table->TemperatureLimitHigh =
+ table_info->cac_dtp_table->usTargetOperatingTemp *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT;
+ table->TemperatureLimitLow =
+ (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT;
+ table->MemoryVoltageChangeEnable = 1;
+ table->MemoryInterval = 1;
+ table->VoltageResponseTime = 0;
+ table->PhaseResponseTime = 0;
+ table->MemoryThermThrottleEnable = 1;
+ table->PCIeBootLinkLevel = 0;
+ table->PCIeGenInterval = 1;
+ table->VRConfig = 0;
+
+ result = polaris10_populate_vr_config(hwmgr, table);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate VRConfig setting!", return result);
+
+ table->ThermGpio = 17;
+ table->SclkStepSize = 0x4000;
+
+ if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
+ table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
+ } else {
+ table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+ }
+
+ if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
+ &gpio_pin)) {
+ table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+ } else {
+ table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+ }
+
+ /* Thermal Output GPIO */
+ if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
+ &gpio_pin)) {
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ThermalOutGPIO);
+
+ table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
+
+ /* For porlarity read GPIOPAD_A with assigned Gpio pin
+ * since VBIOS will program this register to set 'inactive state',
+ * driver can then determine 'active state' from this and
+ * program SMU with correct polarity
+ */
+ table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
+ & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
+
+ /* if required, combine VRHot/PCC with thermal out GPIO */
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
+ && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
+ } else {
+ table->ThermOutGpio = 17;
+ table->ThermOutPolarity = 1;
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
+ }
+
+ /* Populate BIF_SCLK levels into SMC DPM table */
+ for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs);
+ PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
+
+ if (i == 0)
+ table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
+ else
+ table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
+ }
+
+ for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
+ table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
+ CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
+ CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
+
+ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
+ result = smu7_copy_bytes_to_smc(hwmgr,
+ smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU74_Discrete_DpmTable, SystemFlags),
+ (uint8_t *)&(table->SystemFlags),
+ sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
+ SMC_RAM_END);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to upload dpm data to SMC memory!", return result);
+
+ result = polaris10_init_arb_table_index(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to upload arb data to SMC memory!", return result);
+
+ result = polaris10_populate_pm_fuses(hwmgr);
+ PP_ASSERT_WITH_CODE(0 == result,
+ "Failed to populate PM fuses to SMC memory!", return result);
+
+ polaris10_save_default_power_profile(hwmgr);
+
+ return 0;
+}
+
+static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (data->need_update_smu7_dpm_table &
+ (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
+ return polaris10_program_memory_timing_parameters(hwmgr);
+
+ return 0;
+}
+
+int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
+{
+ int ret;
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return 0;
+
+ ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
+
+ ret = (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs) == 0) ?
+ 0 : -1;
+
+ if (!ret)
+ /* If this param is not changed, this function could fire unnecessarily */
+ smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
+
+ return ret;
+}
+
+static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
+ uint32_t duty100;
+ uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
+ uint16_t fdo_min, slope1, slope2;
+ uint32_t reference_clock;
+ int res;
+ uint64_t tmp64;
+
+ if (hwmgr->thermal_controller.fanInfo.bNoFan) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ if (smu_data->smu7_data.fan_table_start == 0) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+ CG_FDO_CTRL1, FMAX_DUTY100);
+
+ if (duty100 == 0) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
+ usPWMMin * duty100;
+ do_div(tmp64, 10000);
+ fdo_min = (uint16_t)tmp64;
+
+ t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
+ hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
+ t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
+ hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
+
+ pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
+ hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
+ pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
+ hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
+
+ slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
+ slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
+
+ fan_table.TempMin = cpu_to_be16((50 + hwmgr->
+ thermal_controller.advanceFanControlParameters.usTMin) / 100);
+ fan_table.TempMed = cpu_to_be16((50 + hwmgr->
+ thermal_controller.advanceFanControlParameters.usTMed) / 100);
+ fan_table.TempMax = cpu_to_be16((50 + hwmgr->
+ thermal_controller.advanceFanControlParameters.usTMax) / 100);
+
+ fan_table.Slope1 = cpu_to_be16(slope1);
+ fan_table.Slope2 = cpu_to_be16(slope2);
+
+ fan_table.FdoMin = cpu_to_be16(fdo_min);
+
+ fan_table.HystDown = cpu_to_be16(hwmgr->
+ thermal_controller.advanceFanControlParameters.ucTHyst);
+
+ fan_table.HystUp = cpu_to_be16(1);
+
+ fan_table.HystSlope = cpu_to_be16(1);
+
+ fan_table.TempRespLim = cpu_to_be16(5);
+
+ reference_clock = smu7_get_xclk(hwmgr);
+
+ fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
+ thermal_controller.advanceFanControlParameters.ulCycleDelay *
+ reference_clock) / 1600);
+
+ fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
+
+ fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
+ hwmgr->device, CGS_IND_REG__SMC,
+ CG_MULT_THERMAL_CTRL, TEMP_SEL);
+
+ res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
+ (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
+ SMC_RAM_END);
+
+ if (!res && hwmgr->thermal_controller.
+ advanceFanControlParameters.ucMinimumPWMLimit)
+ res = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetFanMinPwm,
+ hwmgr->thermal_controller.
+ advanceFanControlParameters.ucMinimumPWMLimit);
+
+ if (!res && hwmgr->thermal_controller.
+ advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
+ res = smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetFanSclkTarget,
+ hwmgr->thermal_controller.
+ advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
+
+ if (res)
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+
+ return 0;
+}
+
+static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ smu_data->smc_state_table.UvdBootLevel = 0;
+ if (table_info->mm_dep_table->count > 0)
+ smu_data->smc_state_table.UvdBootLevel =
+ (uint8_t) (table_info->mm_dep_table->count - 1);
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
+ UvdBootLevel);
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0x00FFFFFF;
+ mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDDPM) ||
+ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_UVDDPM_SetEnabledMask,
+ (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
+ return 0;
+}
+
+static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smu_data->smc_state_table.VceBootLevel =
+ (uint8_t) (table_info->mm_dep_table->count - 1);
+ else
+ smu_data->smc_state_table.VceBootLevel = 0;
+
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0xFF00FFFF;
+ mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_VCEDPM_SetEnabledMask,
+ (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
+ return 0;
+}
+
+static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+
+
+ smu_data->smc_state_table.SamuBootLevel = 0;
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
+
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0xFFFFFF00;
+ mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SAMUDPM_SetEnabledMask,
+ (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
+ return 0;
+}
+
+
+static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
+ int max_entry, i;
+
+ max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
+ SMU74_MAX_LEVELS_LINK :
+ pcie_table->count;
+ /* Setup BIF_SCLK levels */
+ for (i = 0; i < max_entry; i++)
+ smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
+ return 0;
+}
+
+static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
+{
+ switch (type) {
+ case SMU_UVD_TABLE:
+ polaris10_update_uvd_smc_table(hwmgr);
+ break;
+ case SMU_VCE_TABLE:
+ polaris10_update_vce_smc_table(hwmgr);
+ break;
+ case SMU_SAMU_TABLE:
+ polaris10_update_samu_smc_table(hwmgr);
+ break;
+ case SMU_BIF_TABLE:
+ polaris10_update_bif_smc_table(hwmgr);
+ default:
+ break;
+ }
+ return 0;
+}
+
+static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+
+ int result = 0;
+ uint32_t low_sclk_interrupt_threshold = 0;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkThrottleLowNotification)
+ && (hwmgr->gfx_arbiter.sclk_threshold !=
+ data->low_sclk_interrupt_threshold)) {
+ data->low_sclk_interrupt_threshold =
+ hwmgr->gfx_arbiter.sclk_threshold;
+ low_sclk_interrupt_threshold =
+ data->low_sclk_interrupt_threshold;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
+
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU74_Discrete_DpmTable,
+ LowSclkInterruptThreshold),
+ (uint8_t *)&low_sclk_interrupt_threshold,
+ sizeof(uint32_t),
+ SMC_RAM_END);
+ }
+ PP_ASSERT_WITH_CODE((result == 0),
+ "Failed to update SCLK threshold!", return result);
+
+ result = polaris10_program_mem_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE((result == 0),
+ "Failed to program memory timing parameters!",
+ );
+
+ return result;
+}
+
+static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
+{
+ switch (type) {
+ case SMU_SoftRegisters:
+ switch (member) {
+ case HandshakeDisables:
+ return offsetof(SMU74_SoftRegisters, HandshakeDisables);
+ case VoltageChangeTimeout:
+ return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
+ case AverageGraphicsActivity:
+ return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
+ case PreVBlankGap:
+ return offsetof(SMU74_SoftRegisters, PreVBlankGap);
+ case VBlankTimeout:
+ return offsetof(SMU74_SoftRegisters, VBlankTimeout);
+ case UcodeLoadStatus:
+ return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
+ case DRAM_LOG_ADDR_H:
+ return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
+ case DRAM_LOG_ADDR_L:
+ return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
+ case DRAM_LOG_PHY_ADDR_H:
+ return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+ case DRAM_LOG_PHY_ADDR_L:
+ return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+ case DRAM_LOG_BUFF_SIZE:
+ return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
+ }
+ case SMU_Discrete_DpmTable:
+ switch (member) {
+ case UvdBootLevel:
+ return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
+ case VceBootLevel:
+ return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
+ case SamuBootLevel:
+ return offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
+ case LowSclkInterruptThreshold:
+ return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
+ }
+ }
+ pr_warn("can't get the offset of type %x member %x\n", type, member);
+ return 0;
+}
+
+static uint32_t polaris10_get_mac_definition(uint32_t value)
+{
+ switch (value) {
+ case SMU_MAX_LEVELS_GRAPHICS:
+ return SMU74_MAX_LEVELS_GRAPHICS;
+ case SMU_MAX_LEVELS_MEMORY:
+ return SMU74_MAX_LEVELS_MEMORY;
+ case SMU_MAX_LEVELS_LINK:
+ return SMU74_MAX_LEVELS_LINK;
+ case SMU_MAX_ENTRIES_SMIO:
+ return SMU74_MAX_ENTRIES_SMIO;
+ case SMU_MAX_LEVELS_VDDC:
+ return SMU74_MAX_LEVELS_VDDC;
+ case SMU_MAX_LEVELS_VDDGFX:
+ return SMU74_MAX_LEVELS_VDDGFX;
+ case SMU_MAX_LEVELS_VDDCI:
+ return SMU74_MAX_LEVELS_VDDCI;
+ case SMU_MAX_LEVELS_MVDD:
+ return SMU74_MAX_LEVELS_MVDD;
+ case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
+ return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
+ }
+
+ pr_warn("can't get the mac of %x\n", value);
+ return 0;
+}
+
+static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t tmp;
+ int result;
+ bool error = false;
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU74_Firmware_Header, DpmTable),
+ &tmp, SMC_RAM_END);
+
+ if (0 == result)
+ smu_data->smu7_data.dpm_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU74_Firmware_Header, SoftRegisters),
+ &tmp, SMC_RAM_END);
+
+ if (!result) {
+ data->soft_regs_start = tmp;
+ smu_data->smu7_data.soft_regs_start = tmp;
+ }
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU74_Firmware_Header, mcRegisterTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.mc_reg_table_start = tmp;
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU74_Firmware_Header, FanTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.fan_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.arb_table_start = tmp;
+
+ error |= (0 != result);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU7_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU74_Firmware_Header, Version),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ hwmgr->microcode_version_info.SMC = tmp;
+
+ error |= (0 != result);
+
+ return error ? -1 : 0;
+}
+
+static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
+{
+ return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
+ ? true : false;
+}
+
+static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
+ struct amd_pp_profile *request)
+{
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
+ (hwmgr->smu_backend);
+ struct SMU74_Discrete_GraphicsLevel *levels =
+ smu_data->smc_state_table.GraphicsLevel;
+ uint32_t array = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
+ uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
+ SMU74_MAX_LEVELS_GRAPHICS;
+ uint32_t i;
+
+ for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+ levels[i].ActivityLevel =
+ cpu_to_be16(request->activity_threshold);
+ levels[i].EnabledForActivity = 1;
+ levels[i].UpHyst = request->up_hyst;
+ levels[i].DownHyst = request->down_hyst;
+ }
+
+ return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ array_size, SMC_RAM_END);
+}
+
const struct pp_smumgr_func polaris10_smu_funcs = {
.smu_init = polaris10_smu_init,
.smu_fini = smu7_smu_fini,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index ce0a303..b98ade6 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -48,20 +48,20 @@
#define smnMP1_FIRMWARE_FLAGS 0x3010028
-bool rv_is_smc_ram_running(struct pp_smumgr *smumgr)
+bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{
uint32_t mp1_fw_flags, reg;
reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
- cgs_write_register(smumgr->device, reg,
+ cgs_write_register(hwmgr->device, reg,
(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
- mp1_fw_flags = cgs_read_register(smumgr->device, reg);
+ mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
return true;
@@ -69,97 +69,97 @@ bool rv_is_smc_ram_running(struct pp_smumgr *smumgr)
return false;
}
-static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr)
+static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
{
uint32_t reg;
- if (!rv_is_smc_ram_running(smumgr))
+ if (!rv_is_smc_ram_running(hwmgr))
return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- smum_wait_for_register_unequal(smumgr, reg,
+ phm_wait_for_register_unequal(hwmgr, reg,
0, MP1_C2PMSG_90__CONTENT_MASK);
- return cgs_read_register(smumgr->device, reg);
+ return cgs_read_register(hwmgr->device, reg);
}
-int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
+int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg)
{
uint32_t reg;
- if (!rv_is_smc_ram_running(smumgr))
+ if (!rv_is_smc_ram_running(hwmgr))
return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
- cgs_write_register(smumgr->device, reg, msg);
+ cgs_write_register(hwmgr->device, reg, msg);
return 0;
}
-int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
+int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
{
uint32_t reg;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
- *arg = cgs_read_register(smumgr->device, reg);
+ *arg = cgs_read_register(hwmgr->device, reg);
return 0;
}
-int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
uint32_t reg;
- rv_wait_for_response(smumgr);
+ rv_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- cgs_write_register(smumgr->device, reg, 0);
+ cgs_write_register(hwmgr->device, reg, 0);
- rv_send_msg_to_smc_without_waiting(smumgr, msg);
+ rv_send_msg_to_smc_without_waiting(hwmgr, msg);
- if (rv_wait_for_response(smumgr) == 0)
+ if (rv_wait_for_response(hwmgr) == 0)
printk("Failed to send Message %x.\n", msg);
return 0;
}
-int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
+int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter)
{
uint32_t reg;
- rv_wait_for_response(smumgr);
+ rv_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- cgs_write_register(smumgr->device, reg, 0);
+ cgs_write_register(hwmgr->device, reg, 0);
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
- cgs_write_register(smumgr->device, reg, parameter);
+ cgs_write_register(hwmgr->device, reg, parameter);
- rv_send_msg_to_smc_without_waiting(smumgr, msg);
+ rv_send_msg_to_smc_without_waiting(hwmgr, msg);
- if (rv_wait_for_response(smumgr) == 0)
+ if (rv_wait_for_response(hwmgr) == 0)
printk("Failed to send Message %x.\n", msg);
return 0;
}
-int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
+int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id)
{
struct rv_smumgr *priv =
- (struct rv_smumgr *)(smumgr->backend);
+ (struct rv_smumgr *)(hwmgr->smu_backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL;);
@@ -167,16 +167,16 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
"Invalid SMU Table version!", return -EINVAL;);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
"Invalid SMU Table Length!", return -EINVAL;);
- PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
- PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL;);
- PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableSmu2Dram,
priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
@@ -188,11 +188,11 @@ int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
return 0;
}
-int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
+int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id)
{
struct rv_smumgr *priv =
- (struct rv_smumgr *)(smumgr->backend);
+ (struct rv_smumgr *)(hwmgr->smu_backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL;);
@@ -204,17 +204,17 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
memcpy(priv->smu_tables.entry[table_id].table, table,
priv->smu_tables.entry[table_id].size);
- PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
return -EINVAL;);
- PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL;);
- PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableDram2Smu,
priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
@@ -223,15 +223,15 @@ int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
return 0;
}
-static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
+static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
{
uint32_t smc_driver_if_version;
- PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetDriverIfVersion),
"Attempt to get SMC IF Version Number Failed!",
return -EINVAL);
- PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr,
+ PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
&smc_driver_if_version),
"Attempt to read SMC IF Version Number Failed!",
return -EINVAL);
@@ -243,9 +243,9 @@ static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
}
/* sdma is disabled by default in vbios, need to re-enable in driver */
-static int rv_smc_enable_sdma(struct pp_smumgr *smumgr)
+static int rv_smc_enable_sdma(struct pp_hwmgr *hwmgr)
{
- PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
PPSMC_MSG_PowerUpSdma),
"Attempt to power up sdma Failed!",
return -EINVAL);
@@ -253,9 +253,9 @@ static int rv_smc_enable_sdma(struct pp_smumgr *smumgr)
return 0;
}
-static int rv_smc_disable_sdma(struct pp_smumgr *smumgr)
+static int rv_smc_disable_sdma(struct pp_hwmgr *hwmgr)
{
- PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
PPSMC_MSG_PowerDownSdma),
"Attempt to power down sdma Failed!",
return -EINVAL);
@@ -264,9 +264,9 @@ static int rv_smc_disable_sdma(struct pp_smumgr *smumgr)
}
/* vcn is disabled by default in vbios, need to re-enable in driver */
-static int rv_smc_enable_vcn(struct pp_smumgr *smumgr)
+static int rv_smc_enable_vcn(struct pp_hwmgr *hwmgr)
{
- PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerUpVcn, 0),
"Attempt to power up vcn Failed!",
return -EINVAL);
@@ -274,9 +274,9 @@ static int rv_smc_enable_vcn(struct pp_smumgr *smumgr)
return 0;
}
-static int rv_smc_disable_vcn(struct pp_smumgr *smumgr)
+static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr)
{
- PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerDownVcn, 0),
"Attempt to power down vcn Failed!",
return -EINVAL);
@@ -284,38 +284,38 @@ static int rv_smc_disable_vcn(struct pp_smumgr *smumgr)
return 0;
}
-static int rv_smu_fini(struct pp_smumgr *smumgr)
+static int rv_smu_fini(struct pp_hwmgr *hwmgr)
{
struct rv_smumgr *priv =
- (struct rv_smumgr *)(smumgr->backend);
+ (struct rv_smumgr *)(hwmgr->smu_backend);
if (priv) {
- rv_smc_disable_sdma(smumgr);
- rv_smc_disable_vcn(smumgr);
- cgs_free_gpu_mem(smumgr->device,
+ rv_smc_disable_sdma(hwmgr);
+ rv_smc_disable_vcn(hwmgr);
+ cgs_free_gpu_mem(hwmgr->device,
priv->smu_tables.entry[WMTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
priv->smu_tables.entry[CLOCKTABLE].handle);
- kfree(smumgr->backend);
- smumgr->backend = NULL;
+ kfree(hwmgr->smu_backend);
+ hwmgr->smu_backend = NULL;
}
return 0;
}
-static int rv_start_smu(struct pp_smumgr *smumgr)
+static int rv_start_smu(struct pp_hwmgr *hwmgr)
{
- if (rv_verify_smc_interface(smumgr))
+ if (rv_verify_smc_interface(hwmgr))
return -EINVAL;
- if (rv_smc_enable_sdma(smumgr))
+ if (rv_smc_enable_sdma(hwmgr))
return -EINVAL;
- if (rv_smc_enable_vcn(smumgr))
+ if (rv_smc_enable_vcn(hwmgr))
return -EINVAL;
return 0;
}
-static int rv_smu_init(struct pp_smumgr *smumgr)
+static int rv_smu_init(struct pp_hwmgr *hwmgr)
{
struct rv_smumgr *priv;
uint64_t mc_addr;
@@ -327,10 +327,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
if (!priv)
return -ENOMEM;
- smumgr->backend = priv;
+ hwmgr->smu_backend = priv;
/* allocate space for watermarks table */
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
sizeof(Watermarks_t),
CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE,
@@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr,
"[rv_smu_init] Out of memory for wmtable.",
- kfree(smumgr->backend);
- smumgr->backend = NULL;
+ kfree(hwmgr->smu_backend);
+ hwmgr->smu_backend = NULL;
return -EINVAL);
priv->smu_tables.entry[WMTABLE].version = 0x01;
@@ -355,7 +355,7 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
priv->smu_tables.entry[WMTABLE].handle = handle;
/* allocate space for watermarks table */
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
sizeof(DpmClocks_t),
CGS_GPU_MEM_TYPE__GART_CACHEABLE,
PAGE_SIZE,
@@ -365,10 +365,10 @@ static int rv_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr,
"[rv_smu_init] Out of memory for CLOCKTABLE.",
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
- kfree(smumgr->backend);
- smumgr->backend = NULL;
+ kfree(hwmgr->smu_backend);
+ hwmgr->smu_backend = NULL;
return -EINVAL);
priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
index 262c8de..5888840 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
@@ -51,11 +51,11 @@ struct rv_smumgr {
struct smu_table_array smu_tables;
};
-int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
-bool rv_is_smc_ram_running(struct pp_smumgr *smumgr);
-int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
+int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
+bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr);
+int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id);
-int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
+int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index c49a6f2..7f5359a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -25,27 +25,28 @@
#include "pp_debug.h"
#include "smumgr.h"
#include "smu_ucode_xfer_vi.h"
-#include "smu/smu_7_1_3_d.h"
-#include "smu/smu_7_1_3_sh_mask.h"
#include "ppatomctrl.h"
#include "cgs_common.h"
#include "smu7_ppsmc.h"
#include "smu7_smumgr.h"
+#include "smu7_common.h"
+
+#include "polaris10_pwrvirus.h"
#define SMU7_SMC_SIZE 0x20000
-static int smu7_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
+static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)
{
PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
- cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
+ cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
return 0;
}
-int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
+int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
{
uint32_t data;
uint32_t addr;
@@ -59,7 +60,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
addr = smc_start_address;
while (byte_count >= 4) {
- smu7_read_smc_sram_dword(smumgr, addr, &data, limit);
+ smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
*dest = PP_SMC_TO_HOST_UL(data);
@@ -69,7 +70,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
}
if (byte_count) {
- smu7_read_smc_sram_dword(smumgr, addr, &data, limit);
+ smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
*pdata = PP_SMC_TO_HOST_UL(data);
/* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
dest_byte = (uint8_t *)dest;
@@ -81,7 +82,7 @@ int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_addres
}
-int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
+int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit)
{
int result;
@@ -99,12 +100,12 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
/* Bytes are written into the SMC addres space with the MSB first. */
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
- result = smu7_set_smc_sram_address(smumgr, addr, limit);
+ result = smu7_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result)
return result;
- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
src += 4;
byte_count -= 4;
@@ -115,13 +116,13 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
data = 0;
- result = smu7_set_smc_sram_address(smumgr, addr, limit);
+ result = smu7_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result)
return result;
- original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
+ original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
extra_shift = 8 * (4 - byte_count);
@@ -135,53 +136,53 @@ int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
data |= (original_data & ~((~0UL) << extra_shift));
- result = smu7_set_smc_sram_address(smumgr, addr, limit);
+ result = smu7_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result)
return result;
- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
}
return 0;
}
-int smu7_program_jump_on_start(struct pp_smumgr *smumgr)
+int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)
{
static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
- smu7_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
+ smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
return 0;
}
-bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr)
+bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{
- return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
- && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
+ return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
+ && (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
}
-int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
int ret;
- if (!smu7_is_smc_ram_running(smumgr))
+ if (!smu7_is_smc_ram_running(hwmgr))
return -EINVAL;
- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
+ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
+ ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1)
pr_info("\n failed to send pre message %x ret is %d \n", msg, ret);
- cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
+ cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
+ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
+ ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1)
pr_info("\n failed to send message %x ret is %d \n", msg, ret);
@@ -189,53 +190,53 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
return 0;
}
-int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
+int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg)
{
- cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
+ cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
return 0;
}
-int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
+int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
{
- if (!smu7_is_smc_ram_running(smumgr)) {
+ if (!smu7_is_smc_ram_running(hwmgr)) {
return -EINVAL;
}
- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
+ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
+ cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
- return smu7_send_msg_to_smc(smumgr, msg);
+ return smu7_send_msg_to_smc(hwmgr, msg);
}
-int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
+int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
{
- cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
+ cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
- return smu7_send_msg_to_smc_without_waiting(smumgr, msg);
+ return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);
}
-int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
+int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
{
- cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
+ cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
- cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
+ cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
- SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
+ PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
+ if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
pr_info("Failed to send Message.\n");
return 0;
}
-int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr)
+int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr)
{
- if (!smu7_is_smc_ram_running(smumgr))
+ if (!smu7_is_smc_ram_running(hwmgr))
return -EINVAL;
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
return 0;
}
@@ -289,29 +290,29 @@ enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type)
}
-int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
+int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
{
int result;
- result = smu7_set_smc_sram_address(smumgr, smc_addr, limit);
+ result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
if (result)
return result;
- *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
+ *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
return 0;
}
-int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
+int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
{
int result;
- result = smu7_set_smc_sram_address(smumgr, smc_addr, limit);
+ result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
if (result)
return result;
- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);
return 0;
}
@@ -354,14 +355,14 @@ static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
return result;
}
-static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
+static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
uint32_t fw_type,
struct SMU_Entry *entry)
{
int result = 0;
struct cgs_firmware_info info = {0};
- result = cgs_get_firmware_info(smumgr->device,
+ result = cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(fw_type),
&info);
@@ -374,7 +375,7 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
entry->meta_data_addr_low = 0;
/* digest need be excluded out */
- if (cgs_is_virtualization_enabled(smumgr->device))
+ if (cgs_is_virtualization_enabled(hwmgr->device))
info.image_size -= 20;
entry->data_size_byte = info.image_size;
entry->num_register_entries = 0;
@@ -389,30 +390,30 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
return 0;
}
-int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
+int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
uint32_t fw_to_load;
int result = 0;
struct SMU_DRAMData_TOC *toc;
- if (!smumgr->reload_fw) {
+ if (!hwmgr->reload_fw) {
pr_info("skip reloading...\n");
return 0;
}
if (smu_data->soft_regs_start)
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
- smu_data->soft_regs_start + smum_get_offsetof(smumgr,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, UcodeLoadStatus),
0x0);
- if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
- if (!cgs_is_virtualization_enabled(smumgr->device)) {
- smu7_send_msg_to_smc_with_parameter(smumgr,
+ if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
+ if (!cgs_is_virtualization_enabled(hwmgr->device)) {
+ smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SMU_DRAM_ADDR_HI,
smu_data->smu_buffer.mc_addr_high);
- smu7_send_msg_to_smc_with_parameter(smumgr,
+ smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SMU_DRAM_ADDR_LO,
smu_data->smu_buffer.mc_addr_low);
}
@@ -439,122 +440,162 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
toc->num_entries = 0;
toc->structure_version = 1;
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- if (cgs_is_virtualization_enabled(smumgr->device))
- PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
+ if (cgs_is_virtualization_enabled(hwmgr->device))
+ PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
- smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
+ smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
+ smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
- if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
+ if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
pr_err("Fail to Request SMU Load uCode");
return result;
}
/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
-int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
+int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
uint32_t ret;
- ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
- smu_data->soft_regs_start + smum_get_offsetof(smumgr,
+ ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
+ smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
SMU_SoftRegisters, UcodeLoadStatus),
fw_mask, fw_mask);
-
return ret;
}
-int smu7_reload_firmware(struct pp_smumgr *smumgr)
+int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
{
- return smumgr->smumgr_funcs->start_smu(smumgr);
+ return hwmgr->smumgr_funcs->start_smu(hwmgr);
}
-static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
+static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
{
uint32_t byte_count = length;
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
- cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
+ cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
for (; byte_count >= 4; byte_count -= 4)
- cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
+ cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
- SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
+ PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
- PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
+ PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
return 0;
}
-int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr)
+int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
{
int result = 0;
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
struct cgs_firmware_info info = {0};
if (smu_data->security_hard_key == 1)
- cgs_get_firmware_info(smumgr->device,
+ cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
else
- cgs_get_firmware_info(smumgr->device,
+ cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
- smumgr->is_kicker = info.is_kicker;
+ hwmgr->is_kicker = info.is_kicker;
- result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
+ result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
return result;
}
-int smu7_init(struct pp_smumgr *smumgr)
+static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)
+{
+ int i;
+ uint32_t reg, data;
+
+ for (i = 0; i < size; i++) {
+ reg = pvirus->reg;
+ data = pvirus->data;
+ if (reg != 0xffffffff)
+ cgs_write_register(hwmgr->device, reg, data);
+ else
+ break;
+ pvirus++;
+ }
+}
+
+static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)
+{
+ int i;
+
+ cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);
+ cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);
+ cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);
+ for (i = 0; i < section->dfy_size; i++)
+ cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);
+}
+
+int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)
+{
+ execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);
+ execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);
+ execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));
+
+ return 0;
+}
+
+int smu7_init(struct pp_hwmgr *hwmgr)
{
struct smu7_smumgr *smu_data;
uint8_t *internal_buf;
uint64_t mc_addr = 0;
/* Allocate memory for backend private data */
- smu_data = (struct smu7_smumgr *)(smumgr->backend);
+ smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
smu_data->header_buffer.data_size =
((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
/* Allocate FW image data structure and header buffer and
* send the header buffer address to SMU */
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
smu_data->header_buffer.data_size,
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE,
@@ -568,16 +609,16 @@ int smu7_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE((NULL != smu_data->header),
"Out of memory.",
- kfree(smumgr->backend);
- cgs_free_gpu_mem(smumgr->device,
+ kfree(hwmgr->smu_backend);
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)smu_data->header_buffer.handle);
return -EINVAL);
- if (cgs_is_virtualization_enabled(smumgr->device))
+ if (cgs_is_virtualization_enabled(hwmgr->device))
return 0;
smu_data->smu_buffer.data_size = 200*4096;
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
smu_data->smu_buffer.data_size,
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE,
@@ -591,12 +632,12 @@ int smu7_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE((NULL != internal_buf),
"Out of memory.",
- kfree(smumgr->backend);
- cgs_free_gpu_mem(smumgr->device,
+ kfree(hwmgr->smu_backend);
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)smu_data->smu_buffer.handle);
return -EINVAL);
- if (smum_is_hw_avfs_present(smumgr))
+ if (smum_is_hw_avfs_present(hwmgr))
smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
else
smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
@@ -605,12 +646,10 @@ int smu7_init(struct pp_smumgr *smumgr)
}
-int smu7_smu_fini(struct pp_smumgr *smumgr)
+int smu7_smu_fini(struct pp_hwmgr *hwmgr)
{
- if (smumgr->backend) {
- kfree(smumgr->backend);
- smumgr->backend = NULL;
- }
- cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
+ kfree(hwmgr->smu_backend);
+ hwmgr->smu_backend = NULL;
+ cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
index ee5e32d..c87263b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
@@ -60,32 +60,34 @@ struct smu7_smumgr {
};
-int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
+int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
uint32_t *dest, uint32_t byte_count, uint32_t limit);
-int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
+int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit);
-int smu7_program_jump_on_start(struct pp_smumgr *smumgr);
-bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr);
-int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
-int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg);
-int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg,
+int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
+bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
+int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
+int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg);
+int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
uint32_t parameter);
-int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr,
+int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
-int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr);
-int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr);
+int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
+int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr);
enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
-int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
+int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t *value, uint32_t limit);
-int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
+int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t value, uint32_t limit);
-int smu7_request_smu_load_fw(struct pp_smumgr *smumgr);
-int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type);
-int smu7_reload_firmware(struct pp_smumgr *smumgr);
-int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr);
-int smu7_init(struct pp_smumgr *smumgr);
-int smu7_smu_fini(struct pp_smumgr *smumgr);
+int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
+int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
+int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
+int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
+int smu7_init(struct pp_hwmgr *hwmgr);
+int smu7_smu_fini(struct pp_hwmgr *hwmgr);
-#endif
\ No newline at end of file
+int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr);
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 3bdf647..8673884 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -27,7 +27,6 @@
#include <linux/slab.h>
#include <linux/types.h>
#include <drm/amdgpu_drm.h>
-#include "pp_instance.h"
#include "smumgr.h"
#include "cgs_common.h"
@@ -46,88 +45,18 @@ MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
-int smum_early_init(struct pp_instance *handle)
+int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
{
- struct pp_smumgr *smumgr;
-
- if (handle == NULL)
- return -EINVAL;
-
- smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
- if (smumgr == NULL)
- return -ENOMEM;
-
- smumgr->device = handle->device;
- smumgr->chip_family = handle->chip_family;
- smumgr->chip_id = handle->chip_id;
- smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
- smumgr->reload_fw = 1;
- handle->smu_mgr = smumgr;
-
- switch (smumgr->chip_family) {
- case AMDGPU_FAMILY_CZ:
- smumgr->smumgr_funcs = &cz_smu_funcs;
- break;
- case AMDGPU_FAMILY_VI:
- switch (smumgr->chip_id) {
- case CHIP_TOPAZ:
- smumgr->smumgr_funcs = &iceland_smu_funcs;
- break;
- case CHIP_TONGA:
- smumgr->smumgr_funcs = &tonga_smu_funcs;
- break;
- case CHIP_FIJI:
- smumgr->smumgr_funcs = &fiji_smu_funcs;
- break;
- case CHIP_POLARIS11:
- case CHIP_POLARIS10:
- case CHIP_POLARIS12:
- smumgr->smumgr_funcs = &polaris10_smu_funcs;
- break;
- default:
- return -EINVAL;
- }
- break;
- case AMDGPU_FAMILY_AI:
- switch (smumgr->chip_id) {
- case CHIP_VEGA10:
- smumgr->smumgr_funcs = &vega10_smu_funcs;
- break;
- default:
- return -EINVAL;
- }
- break;
- case AMDGPU_FAMILY_RV:
- switch (smumgr->chip_id) {
- case CHIP_RAVEN:
- smumgr->smumgr_funcs = &rv_smu_funcs;
- break;
- default:
- return -EINVAL;
- }
- break;
- default:
- kfree(smumgr);
- return -EINVAL;
- }
+ if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable)
+ return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
return 0;
}
-int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
+int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable)
- return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
-
- return 0;
-}
-
-int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
- void *input, void *output, void *storage, int result)
-{
- if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table)
- return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table)
+ return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
return 0;
}
@@ -135,8 +64,8 @@ int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold)
- return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold)
+ return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr);
return 0;
}
@@ -144,163 +73,75 @@ int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table)
- return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type);
+ if (NULL != hwmgr->smumgr_funcs->update_smc_table)
+ return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type);
return 0;
}
-uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member)
+uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
{
- if (NULL != smumgr->smumgr_funcs->get_offsetof)
- return smumgr->smumgr_funcs->get_offsetof(type, member);
+ if (NULL != hwmgr->smumgr_funcs->get_offsetof)
+ return hwmgr->smumgr_funcs->get_offsetof(type, member);
return 0;
}
int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header)
- return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->process_firmware_header)
+ return hwmgr->smumgr_funcs->process_firmware_header(hwmgr);
return 0;
}
-int smum_get_argument(struct pp_smumgr *smumgr)
+int smum_get_argument(struct pp_hwmgr *hwmgr)
{
- if (NULL != smumgr->smumgr_funcs->get_argument)
- return smumgr->smumgr_funcs->get_argument(smumgr);
+ if (NULL != hwmgr->smumgr_funcs->get_argument)
+ return hwmgr->smumgr_funcs->get_argument(hwmgr);
return 0;
}
-uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value)
+uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
{
- if (NULL != smumgr->smumgr_funcs->get_mac_definition)
- return smumgr->smumgr_funcs->get_mac_definition(value);
+ if (NULL != hwmgr->smumgr_funcs->get_mac_definition)
+ return hwmgr->smumgr_funcs->get_mac_definition(value);
return 0;
}
-int smum_download_powerplay_table(struct pp_smumgr *smumgr,
- void **table)
+int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
{
- if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
- return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
+ if (NULL != hwmgr->smumgr_funcs->download_pptable_settings)
+ return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr,
table);
return 0;
}
-int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
+int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
{
- if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
- return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
+ if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings)
+ return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr);
return 0;
}
-int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
- if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
+ if (hwmgr == NULL || hwmgr->smumgr_funcs->send_msg_to_smc == NULL)
return -EINVAL;
- return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
+ return hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
}
-int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
+int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter)
{
- if (smumgr == NULL ||
- smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
+ if (hwmgr == NULL ||
+ hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
return -EINVAL;
- return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
- smumgr, msg, parameter);
-}
-
-/*
- * Returns once the part of the register indicated by the mask has
- * reached the given value.
- */
-int smum_wait_on_register(struct pp_smumgr *smumgr,
- uint32_t index,
- uint32_t value, uint32_t mask)
-{
- uint32_t i;
- uint32_t cur_value;
-
- if (smumgr == NULL || smumgr->device == NULL)
- return -EINVAL;
-
- for (i = 0; i < smumgr->usec_timeout; i++) {
- cur_value = cgs_read_register(smumgr->device, index);
- if ((cur_value & mask) == (value & mask))
- break;
- udelay(1);
- }
-
- /* timeout means wrong logic*/
- if (i == smumgr->usec_timeout)
- return -1;
-
- return 0;
-}
-
-int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
- uint32_t index,
- uint32_t value, uint32_t mask)
-{
- uint32_t i;
- uint32_t cur_value;
-
- if (smumgr == NULL)
- return -EINVAL;
-
- for (i = 0; i < smumgr->usec_timeout; i++) {
- cur_value = cgs_read_register(smumgr->device,
- index);
- if ((cur_value & mask) != (value & mask))
- break;
- udelay(1);
- }
-
- /* timeout means wrong logic */
- if (i == smumgr->usec_timeout)
- return -1;
-
- return 0;
-}
-
-
-/*
- * Returns once the part of the register indicated by the mask
- * has reached the given value.The indirect space is described by
- * giving the memory-mapped index of the indirect index register.
- */
-int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask)
-{
- if (smumgr == NULL || smumgr->device == NULL)
- return -EINVAL;
-
- cgs_write_register(smumgr->device, indirect_port, index);
- return smum_wait_on_register(smumgr, indirect_port + 1,
- mask, value);
-}
-
-void smum_wait_for_indirect_register_unequal(
- struct pp_smumgr *smumgr,
- uint32_t indirect_port,
- uint32_t index,
- uint32_t value,
- uint32_t mask)
-{
- if (smumgr == NULL || smumgr->device == NULL)
- return;
- cgs_write_register(smumgr->device, indirect_port, index);
- smum_wait_for_register_unequal(smumgr, indirect_port + 1,
- value, mask);
+ return hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter(
+ hwmgr, msg, parameter);
}
int smu_allocate_memory(void *device, uint32_t size,
@@ -316,7 +157,7 @@ int smu_allocate_memory(void *device, uint32_t size,
return -EINVAL;
ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
- 0, 0, (cgs_handle_t *)handle);
+ (cgs_handle_t *)handle);
if (ret)
return -ENOMEM;
@@ -356,24 +197,24 @@ int smu_free_memory(void *device, void *handle)
int smum_init_smc_table(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table)
- return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->init_smc_table)
+ return hwmgr->smumgr_funcs->init_smc_table(hwmgr);
return 0;
}
int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels)
- return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels)
+ return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
return 0;
}
int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels)
- return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels)
+ return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
return 0;
}
@@ -381,16 +222,16 @@ int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
/*this interface is needed by island ci/vi */
int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table)
- return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table)
+ return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
return 0;
}
bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running)
- return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr);
+ if (NULL != hwmgr->smumgr_funcs->is_dpm_running)
+ return hwmgr->smumgr_funcs->is_dpm_running(hwmgr);
return true;
}
@@ -398,17 +239,17 @@ bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request)
{
- if (hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels)
- return hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels(
+ if (hwmgr->smumgr_funcs->populate_requested_graphic_levels)
+ return hwmgr->smumgr_funcs->populate_requested_graphic_levels(
hwmgr, request);
return 0;
}
-bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr)
+bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
{
- if (smumgr->smumgr_funcs->is_hw_avfs_present)
- return smumgr->smumgr_funcs->is_hw_avfs_present(smumgr);
+ if (hwmgr->smumgr_funcs->is_hw_avfs_present)
+ return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
return false;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
deleted file mode 100644
index 65d3a48..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
+++ /dev/null
@@ -1,3275 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- *
- */
-
-#include "pp_debug.h"
-#include "tonga_smc.h"
-#include "smu7_dyn_defaults.h"
-
-#include "smu7_hwmgr.h"
-#include "hardwaremanager.h"
-#include "ppatomctrl.h"
-#include "cgs_common.h"
-#include "atombios.h"
-#include "tonga_smumgr.h"
-#include "pppcielanes.h"
-#include "pp_endian.h"
-#include "smu7_ppsmc.h"
-
-#include "smu72_discrete.h"
-
-#include "smu/smu_7_1_2_d.h"
-#include "smu/smu_7_1_2_sh_mask.h"
-
-#include "gmc/gmc_8_1_d.h"
-#include "gmc/gmc_8_1_sh_mask.h"
-
-#include "bif/bif_5_0_d.h"
-#include "bif/bif_5_0_sh_mask.h"
-
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-
-
-#define VOLTAGE_SCALE 4
-#define POWERTUNE_DEFAULT_SET_MAX 1
-#define VOLTAGE_VID_OFFSET_SCALE1 625
-#define VOLTAGE_VID_OFFSET_SCALE2 100
-#define MC_CG_ARB_FREQ_F1 0x0b
-#define VDDC_VDDCI_DELTA 200
-
-
-static const struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
- * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
- */
- {1, 0xF, 0xFD, 0x19,
- 5, 45, 0, 0xB0000,
- {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8,
- 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
- {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203,
- 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
- },
-};
-
-/* [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
-static const uint16_t tonga_clock_stretcher_lookup_table[2][4] = {
- {600, 1050, 3, 0},
- {600, 1050, 6, 1}
-};
-
-/* [FF, SS] type, [] 4 voltage ranges,
- * and [Floor Freq, Boundary Freq, VID min , VID max]
- */
-static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = {
- { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
- { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} }
-};
-
-/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */
-static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = {
- {0, 1, 3, 2, 4, 5},
- {0, 2, 4, 5, 6, 5}
-};
-
-/* PPGen has the gain setting generated in x * 100 unit
- * This function is to convert the unit to x * 4096(0x1000) unit.
- * This is the unit expected by SMC firmware
- */
-
-
-static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
- phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
- uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-{
- uint32_t i = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- /* clock - voltage dependency table is empty table */
- if (allowed_clock_voltage_table->count == 0)
- return -EINVAL;
-
- for (i = 0; i < allowed_clock_voltage_table->count; i++) {
- /* find first sclk bigger than request */
- if (allowed_clock_voltage_table->entries[i].clk >= clock) {
- voltage->VddGfx = phm_get_voltage_index(
- pptable_info->vddgfx_lookup_table,
- allowed_clock_voltage_table->entries[i].vddgfx);
- voltage->Vddc = phm_get_voltage_index(
- pptable_info->vddc_lookup_table,
- allowed_clock_voltage_table->entries[i].vddc);
-
- if (allowed_clock_voltage_table->entries[i].vddci)
- voltage->Vddci =
- phm_get_voltage_id(&data->vddci_voltage_table, allowed_clock_voltage_table->entries[i].vddci);
- else
- voltage->Vddci =
- phm_get_voltage_id(&data->vddci_voltage_table,
- allowed_clock_voltage_table->entries[i].vddc - VDDC_VDDCI_DELTA);
-
-
- if (allowed_clock_voltage_table->entries[i].mvdd)
- *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
-
- voltage->Phases = 1;
- return 0;
- }
- }
-
- /* sclk is bigger than max sclk in the dependence table */
- voltage->VddGfx = phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
- allowed_clock_voltage_table->entries[i-1].vddgfx);
- voltage->Vddc = phm_get_voltage_index(pptable_info->vddc_lookup_table,
- allowed_clock_voltage_table->entries[i-1].vddc);
-
- if (allowed_clock_voltage_table->entries[i-1].vddci)
- voltage->Vddci = phm_get_voltage_id(&data->vddci_voltage_table,
- allowed_clock_voltage_table->entries[i-1].vddci);
-
- if (allowed_clock_voltage_table->entries[i-1].mvdd)
- *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
-
- return 0;
-}
-
-
-/**
- * Vddc table preparation for SMC.
- *
- * @param hwmgr the address of the hardware manager
- * @param table the SMC DPM table structure to be populated
- * @return always 0
- */
-static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- unsigned int count;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
- table->VddcLevelCount = data->vddc_voltage_table.count;
- for (count = 0; count < table->VddcLevelCount; count++) {
- table->VddcTable[count] =
- PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
- }
- CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
- }
- return 0;
-}
-
-/**
- * VddGfx table preparation for SMC.
- *
- * @param hwmgr the address of the hardware manager
- * @param table the SMC DPM table structure to be populated
- * @return always 0
- */
-static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- unsigned int count;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
- table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
- for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
- table->VddGfxTable[count] =
- PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
- }
- CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
- }
- return 0;
-}
-
-/**
- * Vddci table preparation for SMC.
- *
- * @param *hwmgr The address of the hardware manager.
- * @param *table The SMC DPM table structure to be populated.
- * @return 0
- */
-static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t count;
-
- table->VddciLevelCount = data->vddci_voltage_table.count;
- for (count = 0; count < table->VddciLevelCount; count++) {
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
- table->VddciTable[count] =
- PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
- } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
- table->SmioTable1.Pattern[count].Voltage =
- PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
- /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
- table->SmioTable1.Pattern[count].Smio =
- (uint8_t) count;
- table->Smio[count] |=
- data->vddci_voltage_table.entries[count].smio_low;
- table->VddciTable[count] =
- PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
- }
- }
-
- table->SmioMask1 = data->vddci_voltage_table.mask_low;
- CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
-
- return 0;
-}
-
-/**
- * Mvdd table preparation for SMC.
- *
- * @param *hwmgr The address of the hardware manager.
- * @param *table The SMC DPM table structure to be populated.
- * @return 0
- */
-static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t count;
-
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
- table->MvddLevelCount = data->mvdd_voltage_table.count;
- for (count = 0; count < table->MvddLevelCount; count++) {
- table->SmioTable2.Pattern[count].Voltage =
- PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
- /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
- table->SmioTable2.Pattern[count].Smio =
- (uint8_t) count;
- table->Smio[count] |=
- data->mvdd_voltage_table.entries[count].smio_low;
- }
- table->SmioMask2 = data->mvdd_voltage_table.mask_low;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
- }
-
- return 0;
-}
-
-/**
- * Preparation of vddc and vddgfx CAC tables for SMC.
- *
- * @param hwmgr the address of the hardware manager
- * @param table the SMC DPM table structure to be populated
- * @return always 0
- */
-static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- uint32_t count;
- uint8_t index = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table =
- pptable_info->vddgfx_lookup_table;
- struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table =
- pptable_info->vddc_lookup_table;
-
- /* table is already swapped, so in order to use the value from it
- * we need to swap it back.
- */
- uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
- uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
-
- for (count = 0; count < vddc_level_count; count++) {
- /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
- index = phm_get_voltage_index(vddc_lookup_table,
- data->vddc_voltage_table.entries[count].value);
- table->BapmVddcVidLoSidd[count] =
- convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
- table->BapmVddcVidHiSidd[count] =
- convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
- table->BapmVddcVidHiSidd2[count] =
- convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
- }
-
- if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) {
- /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
- for (count = 0; count < vddgfx_level_count; count++) {
- index = phm_get_voltage_index(vddgfx_lookup_table,
- convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid));
- table->BapmVddGfxVidHiSidd2[count] =
- convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
- }
- } else {
- for (count = 0; count < vddc_level_count; count++) {
- index = phm_get_voltage_index(vddc_lookup_table,
- data->vddc_voltage_table.entries[count].value);
- table->BapmVddGfxVidLoSidd[count] =
- convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
- table->BapmVddGfxVidHiSidd[count] =
- convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
- table->BapmVddGfxVidHiSidd2[count] =
- convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
- }
- }
-
- return 0;
-}
-
-/**
- * Preparation of voltage tables for SMC.
- *
- * @param hwmgr the address of the hardware manager
- * @param table the SMC DPM table structure to be populated
- * @return always 0
- */
-
-static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- int result;
-
- result = tonga_populate_smc_vddc_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "can not populate VDDC voltage table to SMC",
- return -EINVAL);
-
- result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "can not populate VDDCI voltage table to SMC",
- return -EINVAL);
-
- result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "can not populate VDDGFX voltage table to SMC",
- return -EINVAL);
-
- result = tonga_populate_smc_mvdd_table(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "can not populate MVDD voltage table to SMC",
- return -EINVAL);
-
- result = tonga_populate_cac_tables(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "can not populate CAC voltage tables to SMC",
- return -EINVAL);
-
- return 0;
-}
-
-static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr,
- struct SMU72_Discrete_Ulv *state)
-{
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- state->CcPwrDynRm = 0;
- state->CcPwrDynRm1 = 0;
-
- state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
- state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
- VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-
- state->VddcPhase = 1;
-
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
- CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-
- return 0;
-}
-
-static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr,
- struct SMU72_Discrete_DpmTable *table)
-{
- return tonga_populate_ulv_level(hwmgr, &table->Ulv);
-}
-
-static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- uint32_t i;
-
- /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
- for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
- table->LinkLevel[i].PcieGenSpeed =
- (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
- table->LinkLevel[i].PcieLaneCount =
- (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
- table->LinkLevel[i].EnabledForActivity =
- 1;
- table->LinkLevel[i].SPC =
- (uint8_t)(data->pcie_spc_cap & 0xff);
- table->LinkLevel[i].DownThreshold =
- PP_HOST_TO_SMC_UL(5);
- table->LinkLevel[i].UpThreshold =
- PP_HOST_TO_SMC_UL(30);
- }
-
- smu_data->smc_state_table.LinkLevelCount =
- (uint8_t)dpm_table->pcie_speed_table.count;
- data->dpm_level_enable_mask.pcie_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-
- return 0;
-}
-
-/**
- * Calculates the SCLK dividers using the provided engine clock
- *
- * @param hwmgr the address of the hardware manager
- * @param engine_clock the engine clock to use to populate the structure
- * @param sclk the SMC SCLK structure to be populated
- */
-static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
-{
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- pp_atomctrl_clock_dividers_vi dividers;
- uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
- uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
- uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
- uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
- uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
- uint32_t reference_clock;
- uint32_t reference_divider;
- uint32_t fbdiv;
- int result;
-
- /* get the engine clock dividers for this clock value*/
- result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
-
- PP_ASSERT_WITH_CODE(result == 0,
- "Error retrieving Engine Clock dividers from VBIOS.", return result);
-
- /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
- reference_clock = atomctrl_get_reference_clock(hwmgr);
-
- reference_divider = 1 + dividers.uc_pll_ref_div;
-
- /* low 14 bits is fraction and high 12 bits is divider*/
- fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-
- /* SPLL_FUNC_CNTL setup*/
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
- CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
- CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
-
- /* SPLL_FUNC_CNTL_3 setup*/
- spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
- CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
-
- /* set to use fractional accumulation*/
- spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
- CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
- pp_atomctrl_internal_ss_info ss_info;
-
- uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
- if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
- /*
- * ss_info.speed_spectrum_percentage -- in unit of 0.01%
- * ss_info.speed_spectrum_rate -- in unit of khz
- */
- /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
- uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
-
- /* clkv = 2 * D * fbdiv / NS */
- uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
-
- cg_spll_spread_spectrum =
- PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
- cg_spll_spread_spectrum =
- PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
- cg_spll_spread_spectrum_2 =
- PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
- }
- }
-
- sclk->SclkFrequency = engine_clock;
- sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
- sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
- sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
- sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
- sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
-
- return 0;
-}
-
-/**
- * Populates single SMC SCLK structure using the provided engine clock
- *
- * @param hwmgr the address of the hardware manager
- * @param engine_clock the engine clock to use to populate the structure
- * @param sclk the SMC SCLK structure to be populated
- */
-static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
- uint32_t engine_clock,
- uint16_t sclk_activity_level_threshold,
- SMU72_Discrete_GraphicsLevel *graphic_level)
-{
- int result;
- uint32_t mvdd;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
-
- /* populate graphics levels*/
- result = tonga_get_dependecy_volt_by_clk(hwmgr,
- pptable_info->vdd_dep_on_sclk, engine_clock,
- &graphic_level->MinVoltage, &mvdd);
- PP_ASSERT_WITH_CODE((!result),
- "can not find VDDC voltage value for VDDC "
- "engine clock dependency table", return result);
-
- /* SCLK frequency in units of 10KHz*/
- graphic_level->SclkFrequency = engine_clock;
- /* Indicates maximum activity level for this performance level. 50% for now*/
- graphic_level->ActivityLevel = sclk_activity_level_threshold;
-
- graphic_level->CcPwrDynRm = 0;
- graphic_level->CcPwrDynRm1 = 0;
- /* this level can be used if activity is high enough.*/
- graphic_level->EnabledForActivity = 0;
- /* this level can be used for throttling.*/
- graphic_level->EnabledForThrottle = 1;
- graphic_level->UpHyst = 0;
- graphic_level->DownHyst = 0;
- graphic_level->VoltageDownHyst = 0;
- graphic_level->PowerThrottle = 0;
-
- data->display_timing.min_clock_in_sr =
- hwmgr->display_config.min_core_set_clock_in_sr;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkDeepSleep))
- graphic_level->DeepSleepDivId =
- smu7_get_sleep_divider_id_from_clock(engine_clock,
- data->display_timing.min_clock_in_sr);
-
- /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
- graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
- if (!result) {
- /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
- /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
- }
-
- return result;
-}
-
-/**
- * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
- *
- * @param hwmgr the address of the hardware manager
- */
-int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
- uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
- uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
-
- uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
- SMU72_MAX_LEVELS_GRAPHICS;
-
- SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
-
- uint32_t i, max_entry;
- uint8_t highest_pcie_level_enabled = 0;
- uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
- uint8_t count = 0;
- int result = 0;
-
- memset(levels, 0x00, level_array_size);
-
- for (i = 0; i < dpm_table->sclk_table.count; i++) {
- result = tonga_populate_single_graphic_level(hwmgr,
- dpm_table->sclk_table.dpm_levels[i].value,
- (uint16_t)smu_data->activity_target[i],
- &(smu_data->smc_state_table.GraphicsLevel[i]));
- if (result != 0)
- return result;
-
- /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
- if (i > 1)
- smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
- }
-
- /* Only enable level 0 for now. */
- smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-
- /* set highest level watermark to high */
- if (dpm_table->sclk_table.count > 1)
- smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
- PPSMC_DISPLAY_WATERMARK_HIGH;
-
- smu_data->smc_state_table.GraphicsDpmLevelCount =
- (uint8_t)dpm_table->sclk_table.count;
- data->dpm_level_enable_mask.sclk_dpm_enable_mask =
- phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-
- if (pcie_table != NULL) {
- PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
- "There must be 1 or more PCIE levels defined in PPTable.",
- return -EINVAL);
- max_entry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
- for (i = 0; i < dpm_table->sclk_table.count; i++) {
- smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
- (uint8_t) ((i < max_entry) ? i : max_entry);
- }
- } else {
- if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
- pr_err("Pcie Dpm Enablemask is 0 !");
-
- while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
- ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1<<(highest_pcie_level_enabled+1))) != 0)) {
- highest_pcie_level_enabled++;
- }
-
- while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
- ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1<<lowest_pcie_level_enabled)) == 0)) {
- lowest_pcie_level_enabled++;
- }
-
- while ((count < highest_pcie_level_enabled) &&
- ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
- (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
- count++;
- }
- mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
- (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
-
-
- /* set pcieDpmLevel to highest_pcie_level_enabled*/
- for (i = 2; i < dpm_table->sclk_table.count; i++)
- smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
-
- /* set pcieDpmLevel to lowest_pcie_level_enabled*/
- smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
-
- /* set pcieDpmLevel to mid_pcie_level_enabled*/
- smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
- }
- /* level count will send to smc once at init smc table and never change*/
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_address,
- (uint8_t *)levels, (uint32_t)level_array_size,
- SMC_RAM_END);
-
- return result;
-}
-
-/**
- * Populates the SMC MCLK structure using the provided memory clock
- *
- * @param hwmgr the address of the hardware manager
- * @param memory_clock the memory clock to use to populate the structure
- * @param sclk the SMC SCLK structure to be populated
- */
-static int tonga_calculate_mclk_params(
- struct pp_hwmgr *hwmgr,
- uint32_t memory_clock,
- SMU72_Discrete_MemoryLevel *mclk,
- bool strobe_mode,
- bool dllStateOn
- )
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
- uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
- uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
- uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
- uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
- uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
- uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
- uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
- uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
-
- pp_atomctrl_memory_clock_param mpll_param;
- int result;
-
- result = atomctrl_get_memory_pll_dividers_si(hwmgr,
- memory_clock, &mpll_param, strobe_mode);
- PP_ASSERT_WITH_CODE(
- !result,
- "Error retrieving Memory Clock Parameters from VBIOS.",
- return result);
-
- /* MPLL_FUNC_CNTL setup*/
- mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL,
- mpll_param.bw_ctrl);
-
- /* MPLL_FUNC_CNTL_1 setup*/
- mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
- MPLL_FUNC_CNTL_1, CLKF,
- mpll_param.mpll_fb_divider.cl_kf);
- mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
- MPLL_FUNC_CNTL_1, CLKFRAC,
- mpll_param.mpll_fb_divider.clk_frac);
- mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
- MPLL_FUNC_CNTL_1, VCO_MODE,
- mpll_param.vco_mode);
-
- /* MPLL_AD_FUNC_CNTL setup*/
- mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
- MPLL_AD_FUNC_CNTL, YCLK_POST_DIV,
- mpll_param.mpll_post_divider);
-
- if (data->is_memory_gddr5) {
- /* MPLL_DQ_FUNC_CNTL setup*/
- mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
- MPLL_DQ_FUNC_CNTL, YCLK_SEL,
- mpll_param.yclk_sel);
- mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
- MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV,
- mpll_param.mpll_post_divider);
- }
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
- /*
- ************************************
- Fref = Reference Frequency
- NF = Feedback divider ratio
- NR = Reference divider ratio
- Fnom = Nominal VCO output frequency = Fref * NF / NR
- Fs = Spreading Rate
- D = Percentage down-spread / 2
- Fint = Reference input frequency to PFD = Fref / NR
- NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
- CLKS = NS - 1 = ISS_STEP_NUM[11:0]
- NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
- CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
- *************************************
- */
- pp_atomctrl_internal_ss_info ss_info;
- uint32_t freq_nom;
- uint32_t tmp;
- uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
-
- /* for GDDR5 for all modes and DDR3 */
- if (1 == mpll_param.qdr)
- freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
- else
- freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
-
- /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
- tmp = (freq_nom / reference_clock);
- tmp = tmp * tmp;
-
- if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
- /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
- /* ss.Info.speed_spectrum_rate -- in unit of khz */
- /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
- /* = reference_clock * 5 / speed_spectrum_rate */
- uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
-
- /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
- /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
- uint32_t clkv =
- (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
- ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
-
- mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
- mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
- }
- }
-
- /* MCLK_PWRMGT_CNTL setup */
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
-
- /* Save the result data to outpupt memory level structure */
- mclk->MclkFrequency = memory_clock;
- mclk->MpllFuncCntl = mpll_func_cntl;
- mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
- mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
- mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
- mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
- mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
- mclk->DllCntl = dll_cntl;
- mclk->MpllSs1 = mpll_ss1;
- mclk->MpllSs2 = mpll_ss2;
-
- return 0;
-}
-
-static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
- bool strobe_mode)
-{
- uint8_t mc_para_index;
-
- if (strobe_mode) {
- if (memory_clock < 12500)
- mc_para_index = 0x00;
- else if (memory_clock > 47500)
- mc_para_index = 0x0f;
- else
- mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
- } else {
- if (memory_clock < 65000)
- mc_para_index = 0x00;
- else if (memory_clock > 135000)
- mc_para_index = 0x0f;
- else
- mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
- }
-
- return mc_para_index;
-}
-
-static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
-{
- uint8_t mc_para_index;
-
- if (memory_clock < 10000)
- mc_para_index = 0;
- else if (memory_clock >= 80000)
- mc_para_index = 0x0f;
- else
- mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
-
- return mc_para_index;
-}
-
-
-static int tonga_populate_single_memory_level(
- struct pp_hwmgr *hwmgr,
- uint32_t memory_clock,
- SMU72_Discrete_MemoryLevel *memory_level
- )
-{
- uint32_t mvdd = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- int result = 0;
- bool dll_state_on;
- struct cgs_display_info info = {0};
- uint32_t mclk_edc_wr_enable_threshold = 40000;
- uint32_t mclk_stutter_mode_threshold = 30000;
- uint32_t mclk_edc_enable_threshold = 40000;
- uint32_t mclk_strobe_mode_threshold = 40000;
-
- if (NULL != pptable_info->vdd_dep_on_mclk) {
- result = tonga_get_dependecy_volt_by_clk(hwmgr,
- pptable_info->vdd_dep_on_mclk,
- memory_clock,
- &memory_level->MinVoltage, &mvdd);
- PP_ASSERT_WITH_CODE(
- !result,
- "can not find MinVddc voltage value from memory VDDC "
- "voltage dependency table",
- return result);
- }
-
- if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
- memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
- else
- memory_level->MinMvdd = mvdd;
-
- memory_level->EnabledForThrottle = 1;
- memory_level->EnabledForActivity = 0;
- memory_level->UpHyst = 0;
- memory_level->DownHyst = 100;
- memory_level->VoltageDownHyst = 0;
-
- /* Indicates maximum activity level for this performance level.*/
- memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
- memory_level->StutterEnable = 0;
- memory_level->StrobeEnable = 0;
- memory_level->EdcReadEnable = 0;
- memory_level->EdcWriteEnable = 0;
- memory_level->RttEnable = 0;
-
- /* default set to low watermark. Highest level will be set to high later.*/
- memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
- cgs_get_active_displays_info(hwmgr->device, &info);
- data->display_timing.num_existing_displays = info.display_count;
-
- if ((mclk_stutter_mode_threshold != 0) &&
- (memory_clock <= mclk_stutter_mode_threshold) &&
- (!data->is_uvd_enabled)
- && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
- && (data->display_timing.num_existing_displays <= 2)
- && (data->display_timing.num_existing_displays != 0))
- memory_level->StutterEnable = 1;
-
- /* decide strobe mode*/
- memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
- (memory_clock <= mclk_strobe_mode_threshold);
-
- /* decide EDC mode and memory clock ratio*/
- if (data->is_memory_gddr5) {
- memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
- memory_level->StrobeEnable);
-
- if ((mclk_edc_enable_threshold != 0) &&
- (memory_clock > mclk_edc_enable_threshold)) {
- memory_level->EdcReadEnable = 1;
- }
-
- if ((mclk_edc_wr_enable_threshold != 0) &&
- (memory_clock > mclk_edc_wr_enable_threshold)) {
- memory_level->EdcWriteEnable = 1;
- }
-
- if (memory_level->StrobeEnable) {
- if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
- ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
- dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
- } else {
- dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
- }
-
- } else {
- dll_state_on = data->dll_default_on;
- }
- } else {
- memory_level->StrobeRatio =
- tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
- dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
- }
-
- result = tonga_calculate_mclk_params(hwmgr,
- memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
-
- if (!result) {
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
- /* MCLK frequency in units of 10KHz*/
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
- /* Indicates maximum activity level for this performance level.*/
- CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
- CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
- }
-
- return result;
-}
-
-int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- struct smu7_dpm_table *dpm_table = &data->dpm_table;
- int result;
-
- /* populate MCLK dpm table to SMU7 */
- uint32_t level_array_address =
- smu_data->smu7_data.dpm_table_start +
- offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
- uint32_t level_array_size =
- sizeof(SMU72_Discrete_MemoryLevel) *
- SMU72_MAX_LEVELS_MEMORY;
- SMU72_Discrete_MemoryLevel *levels =
- smu_data->smc_state_table.MemoryLevel;
- uint32_t i;
-
- memset(levels, 0x00, level_array_size);
-
- for (i = 0; i < dpm_table->mclk_table.count; i++) {
- PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
- "can not populate memory level as memory clock is zero",
- return -EINVAL);
- result = tonga_populate_single_memory_level(
- hwmgr,
- dpm_table->mclk_table.dpm_levels[i].value,
- &(smu_data->smc_state_table.MemoryLevel[i]));
- if (result)
- return result;
- }
-
- /* Only enable level 0 for now.*/
- smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-
- /*
- * in order to prevent MC activity from stutter mode to push DPM up.
- * the UVD change complements this by putting the MCLK in a higher state
- * by default such that we are not effected by up threshold or and MCLK DPM latency.
- */
- smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
-
- smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
- data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
- /* set highest level watermark to high*/
- smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-
- /* level count will send to smc once at init smc table and never change*/
- result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
- level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
- SMC_RAM_END);
-
- return result;
-}
-
-static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr,
- uint32_t mclk, SMIO_Pattern *smio_pattern)
-{
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint32_t i = 0;
-
- if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
- /* find mvdd value which clock is more than request */
- for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
- if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
- /* Always round to higher voltage. */
- smio_pattern->Voltage =
- data->mvdd_voltage_table.entries[i].value;
- break;
- }
- }
-
- PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
- "MVDD Voltage is outside the supported range.",
- return -EINVAL);
- } else {
- return -EINVAL;
- }
-
- return 0;
-}
-
-
-static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- int result = 0;
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct pp_atomctrl_clock_dividers_vi dividers;
-
- SMIO_Pattern voltage_level;
- uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
- uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
- uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
- uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
-
- /* The ACPI state should not do DPM on DC (or ever).*/
- table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-
- table->ACPILevel.MinVoltage =
- smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;
-
- /* assign zero for now*/
- table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
-
- /* get the engine clock dividers for this clock value*/
- result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
- table->ACPILevel.SclkFrequency, ÷rs);
-
- PP_ASSERT_WITH_CODE(result == 0,
- "Error retrieving Engine Clock dividers from VBIOS.",
- return result);
-
- /* divider ID for required SCLK*/
- table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
- table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
- table->ACPILevel.DeepSleepDivId = 0;
-
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
- SPLL_PWRON, 0);
- spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
- SPLL_RESET, 1);
- spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
- SCLK_MUX_SEL, 4);
-
- table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
- table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
- table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
- table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
- table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
- table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
- table->ACPILevel.CcPwrDynRm = 0;
- table->ACPILevel.CcPwrDynRm1 = 0;
-
-
- /* For various features to be enabled/disabled while this level is active.*/
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
- /* SCLK frequency in units of 10KHz*/
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
- CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-
- /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
- table->MemoryACPILevel.MinVoltage =
- smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
-
- /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
-
- if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
- table->MemoryACPILevel.MinMvdd =
- PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
- else
- table->MemoryACPILevel.MinMvdd = 0;
-
- /* Force reset on DLL*/
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
-
- /* Disable DLL in ACPIState*/
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
- mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
- MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
-
- /* Enable DLL bypass signal*/
- dll_cntl = PHM_SET_FIELD(dll_cntl,
- DLL_CNTL, MRDCK0_BYPASS, 0);
- dll_cntl = PHM_SET_FIELD(dll_cntl,
- DLL_CNTL, MRDCK1_BYPASS, 0);
-
- table->MemoryACPILevel.DllCntl =
- PP_HOST_TO_SMC_UL(dll_cntl);
- table->MemoryACPILevel.MclkPwrmgtCntl =
- PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
- table->MemoryACPILevel.MpllAdFuncCntl =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
- table->MemoryACPILevel.MpllDqFuncCntl =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
- table->MemoryACPILevel.MpllFuncCntl =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
- table->MemoryACPILevel.MpllFuncCntl_1 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
- table->MemoryACPILevel.MpllFuncCntl_2 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
- table->MemoryACPILevel.MpllSs1 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
- table->MemoryACPILevel.MpllSs2 =
- PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
-
- table->MemoryACPILevel.EnabledForThrottle = 0;
- table->MemoryACPILevel.EnabledForActivity = 0;
- table->MemoryACPILevel.UpHyst = 0;
- table->MemoryACPILevel.DownHyst = 100;
- table->MemoryACPILevel.VoltageDownHyst = 0;
- /* Indicates maximum activity level for this performance level.*/
- table->MemoryACPILevel.ActivityLevel =
- PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-
- table->MemoryACPILevel.StutterEnable = 0;
- table->MemoryACPILevel.StrobeEnable = 0;
- table->MemoryACPILevel.EdcReadEnable = 0;
- table->MemoryACPILevel.EdcWriteEnable = 0;
- table->MemoryACPILevel.RttEnable = 0;
-
- return result;
-}
-
-static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- int result = 0;
-
- uint8_t count;
- pp_atomctrl_clock_dividers_vi dividers;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- pptable_info->mm_dep_table;
-
- table->UvdLevelCount = (uint8_t) (mm_table->count);
- table->UvdBootLevel = 0;
-
- for (count = 0; count < table->UvdLevelCount; count++) {
- table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
- table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
- table->UvdLevel[count].MinVoltage.Vddc =
- phm_get_voltage_index(pptable_info->vddc_lookup_table,
- mm_table->entries[count].vddc);
- table->UvdLevel[count].MinVoltage.VddGfx =
- (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
- phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
- mm_table->entries[count].vddgfx) : 0;
- table->UvdLevel[count].MinVoltage.Vddci =
- phm_get_voltage_id(&data->vddci_voltage_table,
- mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
- table->UvdLevel[count].MinVoltage.Phases = 1;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(
- hwmgr,
- table->UvdLevel[count].VclkFrequency,
- ÷rs);
-
- PP_ASSERT_WITH_CODE((!result),
- "can not find divide id for Vclk clock",
- return result);
-
- table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->UvdLevel[count].DclkFrequency, ÷rs);
- PP_ASSERT_WITH_CODE((!result),
- "can not find divide id for Dclk clock",
- return result);
-
- table->UvdLevel[count].DclkDivider =
- (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
- CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
- }
-
- return result;
-
-}
-
-static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- int result = 0;
-
- uint8_t count;
- pp_atomctrl_clock_dividers_vi dividers;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- pptable_info->mm_dep_table;
-
- table->VceLevelCount = (uint8_t) (mm_table->count);
- table->VceBootLevel = 0;
-
- for (count = 0; count < table->VceLevelCount; count++) {
- table->VceLevel[count].Frequency =
- mm_table->entries[count].eclk;
- table->VceLevel[count].MinVoltage.Vddc =
- phm_get_voltage_index(pptable_info->vddc_lookup_table,
- mm_table->entries[count].vddc);
- table->VceLevel[count].MinVoltage.VddGfx =
- (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
- phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
- mm_table->entries[count].vddgfx) : 0;
- table->VceLevel[count].MinVoltage.Vddci =
- phm_get_voltage_id(&data->vddci_voltage_table,
- mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
- table->VceLevel[count].MinVoltage.Phases = 1;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->VceLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((!result),
- "can not find divide id for VCE engine clock",
- return result);
-
- table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
- }
-
- return result;
-}
-
-static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- int result = 0;
- uint8_t count;
- pp_atomctrl_clock_dividers_vi dividers;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- pptable_info->mm_dep_table;
-
- table->AcpLevelCount = (uint8_t) (mm_table->count);
- table->AcpBootLevel = 0;
-
- for (count = 0; count < table->AcpLevelCount; count++) {
- table->AcpLevel[count].Frequency =
- pptable_info->mm_dep_table->entries[count].aclk;
- table->AcpLevel[count].MinVoltage.Vddc =
- phm_get_voltage_index(pptable_info->vddc_lookup_table,
- mm_table->entries[count].vddc);
- table->AcpLevel[count].MinVoltage.VddGfx =
- (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
- phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
- mm_table->entries[count].vddgfx) : 0;
- table->AcpLevel[count].MinVoltage.Vddci =
- phm_get_voltage_id(&data->vddci_voltage_table,
- mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
- table->AcpLevel[count].MinVoltage.Phases = 1;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->AcpLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((!result),
- "can not find divide id for engine clock", return result);
-
- table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
- }
-
- return result;
-}
-
-static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- int result = 0;
- uint8_t count;
- pp_atomctrl_clock_dividers_vi dividers;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct phm_ppt_v1_information *pptable_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- pptable_info->mm_dep_table;
-
- table->SamuBootLevel = 0;
- table->SamuLevelCount = (uint8_t) (mm_table->count);
-
- for (count = 0; count < table->SamuLevelCount; count++) {
- /* not sure whether we need evclk or not */
- table->SamuLevel[count].Frequency =
- pptable_info->mm_dep_table->entries[count].samclock;
- table->SamuLevel[count].MinVoltage.Vddc =
- phm_get_voltage_index(pptable_info->vddc_lookup_table,
- mm_table->entries[count].vddc);
- table->SamuLevel[count].MinVoltage.VddGfx =
- (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
- phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
- mm_table->entries[count].vddgfx) : 0;
- table->SamuLevel[count].MinVoltage.Vddci =
- phm_get_voltage_id(&data->vddci_voltage_table,
- mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
- table->SamuLevel[count].MinVoltage.Phases = 1;
-
- /* retrieve divider value for VBIOS */
- result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
- table->SamuLevel[count].Frequency, ÷rs);
- PP_ASSERT_WITH_CODE((!result),
- "can not find divide id for samu clock", return result);
-
- table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
- }
-
- return result;
-}
-
-static int tonga_populate_memory_timing_parameters(
- struct pp_hwmgr *hwmgr,
- uint32_t engine_clock,
- uint32_t memory_clock,
- struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
- )
-{
- uint32_t dramTiming;
- uint32_t dramTiming2;
- uint32_t burstTime;
- int result;
-
- result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
- engine_clock, memory_clock);
-
- PP_ASSERT_WITH_CODE(result == 0,
- "Error calling VBIOS to set DRAM_TIMING.", return result);
-
- dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
- dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
- burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-
- arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
- arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
- arb_regs->McArbBurstTime = (uint8_t)burstTime;
-
- return 0;
-}
-
-/**
- * Setup parameters for the MC ARB.
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @return always 0
- * This function is to be called from the SetPowerState table.
- */
-static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- int result = 0;
- SMU72_Discrete_MCArbDramTimingTable arb_regs;
- uint32_t i, j;
-
- memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
-
- for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
- for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
- result = tonga_populate_memory_timing_parameters
- (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
- data->dpm_table.mclk_table.dpm_levels[j].value,
- &arb_regs.entries[i][j]);
-
- if (result)
- break;
- }
- }
-
- if (!result) {
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.arb_table_start,
- (uint8_t *)&arb_regs,
- sizeof(SMU72_Discrete_MCArbDramTimingTable),
- SMC_RAM_END
- );
- }
-
- return result;
-}
-
-static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- int result = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- table->GraphicsBootLevel = 0;
- table->MemoryBootLevel = 0;
-
- /* find boot level from dpm table*/
- result = phm_find_boot_level(&(data->dpm_table.sclk_table),
- data->vbios_boot_state.sclk_bootup_value,
- (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
-
- if (result != 0) {
- smu_data->smc_state_table.GraphicsBootLevel = 0;
- pr_err("[powerplay] VBIOS did not find boot engine "
- "clock value in dependency table. "
- "Using Graphics DPM level 0 !");
- result = 0;
- }
-
- result = phm_find_boot_level(&(data->dpm_table.mclk_table),
- data->vbios_boot_state.mclk_bootup_value,
- (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
-
- if (result != 0) {
- smu_data->smc_state_table.MemoryBootLevel = 0;
- pr_err("[powerplay] VBIOS did not find boot "
- "engine clock value in dependency table."
- "Using Memory DPM level 0 !");
- result = 0;
- }
-
- table->BootVoltage.Vddc =
- phm_get_voltage_id(&(data->vddc_voltage_table),
- data->vbios_boot_state.vddc_bootup_value);
- table->BootVoltage.VddGfx =
- phm_get_voltage_id(&(data->vddgfx_voltage_table),
- data->vbios_boot_state.vddgfx_bootup_value);
- table->BootVoltage.Vddci =
- phm_get_voltage_id(&(data->vddci_voltage_table),
- data->vbios_boot_state.vddci_bootup_value);
- table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
-
- CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-
- return result;
-}
-
-static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-{
- uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
- volt_with_cks, value;
- uint16_t clock_freq_u16;
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
- volt_offset = 0;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
- table_info->vdd_dep_on_sclk;
- uint32_t hw_revision, dev_id;
- struct cgs_system_info sys_info = {0};
-
- stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-
- sys_info.size = sizeof(struct cgs_system_info);
-
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
- cgs_query_system_info(hwmgr->device, &sys_info);
- hw_revision = (uint32_t)sys_info.value;
-
- sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
- cgs_query_system_info(hwmgr->device, &sys_info);
- dev_id = (uint32_t)sys_info.value;
-
- /* Read SMU_Eefuse to read and calculate RO and determine
- * if the part is SS or FF. if RO >= 1660MHz, part is FF.
- */
- efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixSMU_EFUSE_0 + (146 * 4));
- efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixSMU_EFUSE_0 + (148 * 4));
- efuse &= 0xFF000000;
- efuse = efuse >> 24;
- efuse2 &= 0xF;
-
- if (efuse2 == 1)
- ro = (2300 - 1350) * efuse / 255 + 1350;
- else
- ro = (2500 - 1000) * efuse / 255 + 1000;
-
- if (ro >= 1660)
- type = 0;
- else
- type = 1;
-
- /* Populate Stretch amount */
- smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
-
-
- /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
- for (i = 0; i < sclk_table->count; i++) {
- smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
- sclk_table->entries[i].cks_enable << i;
- if (ASICID_IS_TONGA_P(dev_id, hw_revision)) {
- volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 *
- (sclk_table->entries[i].clk/100) / 10000) * 1000 /
- (8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000)));
- volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 *
- (sclk_table->entries[i].clk/100) / 100000) * 1000 /
- (6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000)));
- } else {
- volt_without_cks = (uint32_t)((14041 *
- (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
- (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
- volt_with_cks = (uint32_t)((13946 *
- (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
- (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
- }
- if (volt_without_cks >= volt_with_cks)
- volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
- sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
- smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
- }
-
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- STRETCH_ENABLE, 0x0);
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- masterReset, 0x1);
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- staticEnable, 0x1);
- PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
- masterReset, 0x0);
-
- /* Populate CKS Lookup Table */
- if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
- stretch_amount2 = 0;
- else if (stretch_amount == 3 || stretch_amount == 4)
- stretch_amount2 = 1;
- else {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ClockStretcher);
- PP_ASSERT_WITH_CODE(false,
- "Stretch Amount in PPTable not supported\n",
- return -EINVAL);
- }
-
- value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixPWR_CKS_CNTL);
- value &= 0xFFC2FF87;
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
- tonga_clock_stretcher_lookup_table[stretch_amount2][0];
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
- tonga_clock_stretcher_lookup_table[stretch_amount2][1];
- clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
- GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
- SclkFrequency) / 100);
- if (tonga_clock_stretcher_lookup_table[stretch_amount2][0] <
- clock_freq_u16 &&
- tonga_clock_stretcher_lookup_table[stretch_amount2][1] >
- clock_freq_u16) {
- /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
- value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
- /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
- value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
- /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
- value |= (tonga_clock_stretch_amount_conversion
- [tonga_clock_stretcher_lookup_table[stretch_amount2][3]]
- [stretch_amount]) << 3;
- }
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
- CKS_LOOKUPTableEntry[0].minFreq);
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
- CKS_LOOKUPTableEntry[0].maxFreq);
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
- tonga_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
- smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
- (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixPWR_CKS_CNTL, value);
-
- /* Populate DDT Lookup Table */
- for (i = 0; i < 4; i++) {
- /* Assign the minimum and maximum VID stored
- * in the last row of Clock Stretcher Voltage Table.
- */
- smu_data->smc_state_table.ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].minVID =
- (uint8_t) tonga_clock_stretcher_ddt_table[type][i][2];
- smu_data->smc_state_table.ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].maxVID =
- (uint8_t) tonga_clock_stretcher_ddt_table[type][i][3];
- /* Loop through each SCLK and check the frequency
- * to see if it lies within the frequency for clock stretcher.
- */
- for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
- cks_setting = 0;
- clock_freq = PP_SMC_TO_HOST_UL(
- smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
- /* Check the allowed frequency against the sclk level[j].
- * Sclk's endianness has already been converted,
- * and it's in 10Khz unit,
- * as opposed to Data table, which is in Mhz unit.
- */
- if (clock_freq >= tonga_clock_stretcher_ddt_table[type][i][0] * 100) {
- cks_setting |= 0x2;
- if (clock_freq < tonga_clock_stretcher_ddt_table[type][i][1] * 100)
- cks_setting |= 0x1;
- }
- smu_data->smc_state_table.ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
- }
- CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
- ClockStretcherDataTable.
- ClockStretcherDataTableEntry[i].setting);
- }
-
- value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixPWR_CKS_CNTL);
- value &= 0xFFFFFFFE;
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixPWR_CKS_CNTL, value);
-
- return 0;
-}
-
-/**
- * Populates the SMC VRConfig field in DPM table.
- *
- * @param hwmgr the address of the hardware manager
- * @param table the SMC DPM table structure to be populated
- * @return always 0
- */
-static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_DpmTable *table)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint16_t config;
-
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
- /* Splitted mode */
- config = VR_SVI2_PLANE_1;
- table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
-
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
- config = VR_SVI2_PLANE_2;
- table->VRConfig |= config;
- } else {
- pr_err("VDDC and VDDGFX should "
- "be both on SVI2 control in splitted mode !\n");
- }
- } else {
- /* Merged mode */
- config = VR_MERGED_WITH_VDDC;
- table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
-
- /* Set Vddc Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
- config = VR_SVI2_PLANE_1;
- table->VRConfig |= config;
- } else {
- pr_err("VDDC should be on "
- "SVI2 control in merged mode !\n");
- }
- }
-
- /* Set Vddci Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
- config = VR_SVI2_PLANE_2; /* only in merged mode */
- table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
- } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
- config = VR_SMIO_PATTERN_1;
- table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
- }
-
- /* Set Mvdd Voltage Controller */
- if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
- config = VR_SMIO_PATTERN_2;
- table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
- }
-
- return 0;
-}
-
-
-/**
- * Initialize the ARB DRAM timing table's index field.
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @return always 0
- */
-static int tonga_init_arb_table_index(struct pp_smumgr *smumgr)
-{
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
- uint32_t tmp;
- int result;
-
- /*
- * This is a read-modify-write on the first byte of the ARB table.
- * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure
- * is the field 'current'.
- * This solution is ugly, but we never write the whole table only
- * individual fields in it.
- * In reality this field should not be in that structure
- * but in a soft register.
- */
- result = smu7_read_smc_sram_dword(smumgr,
- smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
-
- if (result != 0)
- return result;
-
- tmp &= 0x00FFFFFF;
- tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-
- return smu7_write_smc_sram_dword(smumgr,
- smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
-}
-
-
-static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
- SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
- int i, j, k;
- const uint16_t *pdef1, *pdef2;
-
- dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
- (uint16_t)(cac_dtp_table->usTDP * 256));
- dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
- (uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
-
- PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
- "Target Operating Temp is out of Range !",
- );
-
- dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
- dpm_table->GpuTjHyst = 8;
-
- dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
-
- dpm_table->BAPM_TEMP_GRADIENT =
- PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient);
- pdef1 = defaults->bapmti_r;
- pdef2 = defaults->bapmti_rc;
-
- for (i = 0; i < SMU72_DTE_ITERATIONS; i++) {
- for (j = 0; j < SMU72_DTE_SOURCES; j++) {
- for (k = 0; k < SMU72_DTE_SINKS; k++) {
- dpm_table->BAPMTI_R[i][j][k] =
- PP_HOST_TO_SMC_US(*pdef1);
- dpm_table->BAPMTI_RC[i][j][k] =
- PP_HOST_TO_SMC_US(*pdef2);
- pdef1++;
- pdef2++;
- }
- }
- }
-
- return 0;
-}
-
-static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
-
- smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
- smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
- smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
- smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-
- return 0;
-}
-
-static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-{
- uint16_t tdc_limit;
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- /* TDC number of fraction bits are changed from 8 to 7
- * for Fiji as requested by SMC team
- */
- tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 256);
- smu_data->power_tune_table.TDC_VDDC_PkgLimit =
- CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
- smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
- defaults->tdc_vddc_throttle_release_limit_perc;
- smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
-
- return 0;
-}
-
-static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
- uint32_t temp;
-
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- fuse_table_offset +
- offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
- (uint32_t *)&temp, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to read PmFuses.DW6 "
- "(SviLoadLineEn) from SMC Failed !",
- return -EINVAL);
- else
- smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
-
- return 0;
-}
-
-static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
-
- /* Currently not used. Set all to zero. */
- for (i = 0; i < 16; i++)
- smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-
- return 0;
-}
-
-static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
-
- if ((hwmgr->thermal_controller.advanceFanControlParameters.
- usFanOutputSensitivity & (1 << 15)) ||
- (hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
- hwmgr->thermal_controller.advanceFanControlParameters.
- usFanOutputSensitivity = hwmgr->thermal_controller.
- advanceFanControlParameters.usDefaultFanOutputSensitivity;
-
- smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
- PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
- advanceFanControlParameters.usFanOutputSensitivity);
- return 0;
-}
-
-static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-{
- int i;
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
-
- /* Currently not used. Set all to zero. */
- for (i = 0; i < 16; i++)
- smu_data->power_tune_table.GnbLPML[i] = 0;
-
- return 0;
-}
-
-static int tonga_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
- return 0;
-}
-
-static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
- uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
- uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
- struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-
- hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
- lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-
- smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
- CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
- smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
- CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
-
- return 0;
-}
-
-static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- uint32_t pm_fuse_table_offset;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment)) {
- if (smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU72_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU72_Firmware_Header, PmFuseTable),
- &pm_fuse_table_offset, SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to get pm_fuse_table_offset Failed !",
- return -EINVAL);
-
- /* DW6 */
- if (tonga_populate_svi_load_line(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate SviLoadLine Failed !",
- return -EINVAL);
- /* DW7 */
- if (tonga_populate_tdc_limit(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TDCLimit Failed !",
- return -EINVAL);
- /* DW8 */
- if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate TdcWaterfallCtl Failed !",
- return -EINVAL);
-
- /* DW9-DW12 */
- if (tonga_populate_temperature_scaler(hwmgr) != 0)
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate LPMLTemperatureScaler Failed !",
- return -EINVAL);
-
- /* DW13-DW14 */
- if (tonga_populate_fuzzy_fan(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate Fuzzy Fan "
- "Control parameters Failed !",
- return -EINVAL);
-
- /* DW15-DW18 */
- if (tonga_populate_gnb_lpml(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML Failed !",
- return -EINVAL);
-
- /* DW19 */
- if (tonga_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to populate GnbLPML "
- "Min and Max Vid Failed !",
- return -EINVAL);
-
- /* DW20 */
- if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
- PP_ASSERT_WITH_CODE(
- false,
- "Attempt to populate BapmVddCBaseLeakage "
- "Hi and Lo Sidd Failed !",
- return -EINVAL);
-
- if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
- (uint8_t *)&smu_data->power_tune_table,
- sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END))
- PP_ASSERT_WITH_CODE(false,
- "Attempt to download PmFuseTable Failed !",
- return -EINVAL);
- }
- return 0;
-}
-
-static int tonga_populate_mc_reg_address(struct pp_smumgr *smumgr,
- SMU72_Discrete_MCRegisters *mc_reg_table)
-{
- const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)smumgr->backend;
-
- uint32_t i, j;
-
- for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
- if (smu_data->mc_reg_table.validflag & 1<<j) {
- PP_ASSERT_WITH_CODE(
- i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
- "Index of mc_reg_table->address[] array "
- "out of boundary",
- return -EINVAL);
- mc_reg_table->address[i].s0 =
- PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
- mc_reg_table->address[i].s1 =
- PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
- i++;
- }
- }
-
- mc_reg_table->last = (uint8_t)i;
-
- return 0;
-}
-
-/*convert register values from driver to SMC format */
-static void tonga_convert_mc_registers(
- const struct tonga_mc_reg_entry *entry,
- SMU72_Discrete_MCRegisterSet *data,
- uint32_t num_entries, uint32_t valid_flag)
-{
- uint32_t i, j;
-
- for (i = 0, j = 0; j < num_entries; j++) {
- if (valid_flag & 1<<j) {
- data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
- i++;
- }
- }
-}
-
-static int tonga_convert_mc_reg_table_entry_to_smc(
- struct pp_smumgr *smumgr,
- const uint32_t memory_clock,
- SMU72_Discrete_MCRegisterSet *mc_reg_table_data
- )
-{
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
- uint32_t i = 0;
-
- for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
- if (memory_clock <=
- smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
- break;
- }
- }
-
- if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
- --i;
-
- tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
- mc_reg_table_data, smu_data->mc_reg_table.last,
- smu_data->mc_reg_table.validflag);
-
- return 0;
-}
-
-static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
- SMU72_Discrete_MCRegisters *mc_regs)
-{
- int result = 0;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- int res;
- uint32_t i;
-
- for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
- res = tonga_convert_mc_reg_table_entry_to_smc(
- hwmgr->smumgr,
- data->dpm_table.mclk_table.dpm_levels[i].value,
- &mc_regs->data[i]
- );
-
- if (0 != res)
- result = res;
- }
-
- return result;
-}
-
-static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
-{
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t address;
- int32_t result;
-
- if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
- return 0;
-
-
- memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters));
-
- result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
-
- if (result != 0)
- return result;
-
-
- address = smu_data->smu7_data.mc_reg_table_start +
- (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
-
- return smu7_copy_bytes_to_smc(
- hwmgr->smumgr, address,
- (uint8_t *)&smu_data->mc_regs.data[0],
- sizeof(SMU72_Discrete_MCRegisterSet) *
- data->dpm_table.mclk_table.count,
- SMC_RAM_END);
-}
-
-static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct pp_smumgr *smumgr = hwmgr->smumgr;
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);
-
- memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
- result = tonga_populate_mc_reg_address(smumgr, &(smu_data->mc_regs));
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize MCRegTable for the MC register addresses !",
- return result;);
-
- result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize MCRegTable for driver state !",
- return result;);
-
- return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start,
- (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
-}
-
-static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- if (table_info &&
- table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
- table_info->cac_dtp_table->usPowerTuneDataSetID)
- smu_data->power_tune_defaults =
- &tonga_power_tune_data_set_array
- [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
- else
- smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0];
-}
-
-static void tonga_save_default_power_profile(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- struct SMU72_Discrete_GraphicsLevel *levels =
- data->smc_state_table.GraphicsLevel;
- unsigned min_level = 1;
-
- hwmgr->default_gfx_power_profile.activity_threshold =
- be16_to_cpu(levels[0].ActivityLevel);
- hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
- hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
- hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
-
- hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
- hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
-
- /* Workaround compute SDMA instability: disable lowest SCLK
- * DPM level. Optimize compute power profile: Use only highest
- * 2 power levels (if more than 2 are available), Hysteresis:
- * 0ms up, 5ms down
- */
- if (data->smc_state_table.GraphicsDpmLevelCount > 2)
- min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
- else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
- min_level = 1;
- else
- min_level = 0;
- hwmgr->default_compute_power_profile.min_sclk =
- be32_to_cpu(levels[min_level].SclkFrequency);
- hwmgr->default_compute_power_profile.up_hyst = 0;
- hwmgr->default_compute_power_profile.down_hyst = 5;
-
- hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
- hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
-}
-
-/**
- * Initializes the SMC table and uploads it
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @param pInput the pointer to input data (PowerState)
- * @return always 0
- */
-int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- uint8_t i;
- pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
-
-
- memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
-
- tonga_initialize_power_tune_defaults(hwmgr);
-
- if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
- tonga_populate_smc_voltage_tables(hwmgr, table);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StepVddc))
- table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-
- if (data->is_memory_gddr5)
- table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-
- i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
-
- if (i == 1 || i == 0)
- table->SystemFlags |= 0x40;
-
- if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
- result = tonga_populate_ulv_state(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize ULV state !",
- return result;);
-
- cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- ixCG_ULV_PARAMETER, 0x40035);
- }
-
- result = tonga_populate_smc_link_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize Link Level !", return result);
-
- result = tonga_populate_all_graphic_levels(hwmgr);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize Graphics Level !", return result);
-
- result = tonga_populate_all_memory_levels(hwmgr);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize Memory Level !", return result);
-
- result = tonga_populate_smc_acpi_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize ACPI Level !", return result);
-
- result = tonga_populate_smc_vce_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize VCE Level !", return result);
-
- result = tonga_populate_smc_acp_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize ACP Level !", return result);
-
- result = tonga_populate_smc_samu_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize SAMU Level !", return result);
-
- /* Since only the initial state is completely set up at this
- * point (the other states are just copies of the boot state) we only
- * need to populate the ARB settings for the initial state.
- */
- result = tonga_program_memory_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to Write ARB settings for the initial state.",
- return result;);
-
- result = tonga_populate_smc_uvd_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize UVD Level !", return result);
-
- result = tonga_populate_smc_boot_level(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to initialize Boot Level !", return result);
-
- tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to populate BAPM Parameters !", return result);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ClockStretcher)) {
- result = tonga_populate_clock_stretcher_data_table(hwmgr);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to populate Clock Stretcher Data Table !",
- return result;);
- }
- table->GraphicsVoltageChangeEnable = 1;
- table->GraphicsThermThrottleEnable = 1;
- table->GraphicsInterval = 1;
- table->VoltageInterval = 1;
- table->ThermalInterval = 1;
- table->TemperatureLimitHigh =
- table_info->cac_dtp_table->usTargetOperatingTemp *
- SMU7_Q88_FORMAT_CONVERSION_UNIT;
- table->TemperatureLimitLow =
- (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
- SMU7_Q88_FORMAT_CONVERSION_UNIT;
- table->MemoryVoltageChangeEnable = 1;
- table->MemoryInterval = 1;
- table->VoltageResponseTime = 0;
- table->PhaseResponseTime = 0;
- table->MemoryThermThrottleEnable = 1;
-
- /*
- * Cail reads current link status and reports it as cap (we cannot
- * change this due to some previous issues we had)
- * SMC drops the link status to lowest level after enabling
- * DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
- * but this time Cail reads current link status which was set to low by
- * SMC and reports it as cap to powerplay
- * To avoid it, we set PCIeBootLinkLevel to highest dpm level
- */
- PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
- "There must be 1 or more PCIE levels defined in PPTable.",
- return -EINVAL);
-
- table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
-
- table->PCIeGenInterval = 1;
-
- result = tonga_populate_vr_config(hwmgr, table);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to populate VRConfig setting !", return result);
-
- table->ThermGpio = 17;
- table->SclkStepSize = 0x4000;
-
- if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
- &gpio_pin_assignment)) {
- table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot);
- } else {
- table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot);
- }
-
- if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
- &gpio_pin_assignment)) {
- table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition);
- } else {
- table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition);
- }
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_Falcon_QuickTransition);
-
- if (0) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_AutomaticDCTransition);
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_Falcon_QuickTransition);
- }
-
- if (atomctrl_get_pp_assign_pin(hwmgr,
- THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment)) {
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ThermalOutGPIO);
-
- table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
-
- table->ThermOutPolarity =
- (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
- (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1 : 0;
-
- table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-
- /* if required, combine VRHot/PCC with thermal out GPIO*/
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_RegulatorHot) &&
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_CombinePCCWithThermalSignal)){
- table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
- }
- } else {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_ThermalOutGPIO);
-
- table->ThermOutGpio = 17;
- table->ThermOutPolarity = 1;
- table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
- }
-
- for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++)
- table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-
- CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
- CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
- CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
- CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
- CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
- CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-
- /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
- (uint8_t *)&(table->SystemFlags),
- sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController),
- SMC_RAM_END);
-
- PP_ASSERT_WITH_CODE(!result,
- "Failed to upload dpm data to SMC memory !", return result;);
-
- result = tonga_init_arb_table_index(hwmgr->smumgr);
- PP_ASSERT_WITH_CODE(!result,
- "Failed to upload arb data to SMC memory !", return result);
-
- tonga_populate_pm_fuses(hwmgr);
- PP_ASSERT_WITH_CODE((!result),
- "Failed to populate initialize pm fuses !", return result);
-
- result = tonga_populate_initial_mc_reg_table(hwmgr);
- PP_ASSERT_WITH_CODE((!result),
- "Failed to populate initialize MC Reg table !", return result);
-
- tonga_save_default_power_profile(hwmgr);
-
- return 0;
-}
-
-/**
-* Set up the fan table to control the fan using the SMC.
-* @param hwmgr the address of the powerplay hardware manager.
-* @param pInput the pointer to input data
-* @param pOutput the pointer to output data
-* @param pStorage the pointer to temporary storage
-* @param Result the last failure code
-* @return result from set temperature range routine
-*/
-int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
- uint32_t duty100;
- uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
- uint16_t fdo_min, slope1, slope2;
- uint32_t reference_clock;
- int res;
- uint64_t tmp64;
-
- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl))
- return 0;
-
- if (hwmgr->thermal_controller.fanInfo.bNoFan) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- if (0 == smu_data->smu7_data.fan_table_start) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC,
- CG_FDO_CTRL1, FMAX_DUTY100);
-
- if (0 == duty100) {
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_MicrocodeFanControl);
- return 0;
- }
-
- tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
- do_div(tmp64, 10000);
- fdo_min = (uint16_t)tmp64;
-
- t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
- hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
- t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
- hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-
- pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
- hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
- pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
- hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-
- slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
- slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-
- fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
- fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
- fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
-
- fan_table.Slope1 = cpu_to_be16(slope1);
- fan_table.Slope2 = cpu_to_be16(slope2);
-
- fan_table.FdoMin = cpu_to_be16(fdo_min);
-
- fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
-
- fan_table.HystUp = cpu_to_be16(1);
-
- fan_table.HystSlope = cpu_to_be16(1);
-
- fan_table.TempRespLim = cpu_to_be16(5);
-
- reference_clock = smu7_get_xclk(hwmgr);
-
- fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
-
- fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-
- fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
-
- fan_table.FanControl_GL_Flag = 1;
-
- res = smu7_copy_bytes_to_smc(hwmgr->smumgr,
- smu_data->smu7_data.fan_table_start,
- (uint8_t *)&fan_table,
- (uint32_t)sizeof(fan_table),
- SMC_RAM_END);
-
- return 0;
-}
-
-
-static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- if (data->need_update_smu7_dpm_table &
- (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
- return tonga_program_memory_timing_parameters(hwmgr);
-
- return 0;
-}
-
-int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
-
- int result = 0;
- uint32_t low_sclk_interrupt_threshold = 0;
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkThrottleLowNotification)
- && (hwmgr->gfx_arbiter.sclk_threshold !=
- data->low_sclk_interrupt_threshold)) {
- data->low_sclk_interrupt_threshold =
- hwmgr->gfx_arbiter.sclk_threshold;
- low_sclk_interrupt_threshold =
- data->low_sclk_interrupt_threshold;
-
- CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-
- result = smu7_copy_bytes_to_smc(
- hwmgr->smumgr,
- smu_data->smu7_data.dpm_table_start +
- offsetof(SMU72_Discrete_DpmTable,
- LowSclkInterruptThreshold),
- (uint8_t *)&low_sclk_interrupt_threshold,
- sizeof(uint32_t),
- SMC_RAM_END);
- }
-
- result = tonga_update_and_upload_mc_reg_table(hwmgr);
-
- PP_ASSERT_WITH_CODE((!result),
- "Failed to upload MC reg table !",
- return result);
-
- result = tonga_program_mem_timing_parameters(hwmgr);
- PP_ASSERT_WITH_CODE((result == 0),
- "Failed to program memory timing parameters !",
- );
-
- return result;
-}
-
-uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
-{
- switch (type) {
- case SMU_SoftRegisters:
- switch (member) {
- case HandshakeDisables:
- return offsetof(SMU72_SoftRegisters, HandshakeDisables);
- case VoltageChangeTimeout:
- return offsetof(SMU72_SoftRegisters, VoltageChangeTimeout);
- case AverageGraphicsActivity:
- return offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
- case PreVBlankGap:
- return offsetof(SMU72_SoftRegisters, PreVBlankGap);
- case VBlankTimeout:
- return offsetof(SMU72_SoftRegisters, VBlankTimeout);
- case UcodeLoadStatus:
- return offsetof(SMU72_SoftRegisters, UcodeLoadStatus);
- }
- case SMU_Discrete_DpmTable:
- switch (member) {
- case UvdBootLevel:
- return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
- case VceBootLevel:
- return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
- case SamuBootLevel:
- return offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
- case LowSclkInterruptThreshold:
- return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
- }
- }
- pr_warn("can't get the offset of type %x member %x\n", type, member);
- return 0;
-}
-
-uint32_t tonga_get_mac_definition(uint32_t value)
-{
- switch (value) {
- case SMU_MAX_LEVELS_GRAPHICS:
- return SMU72_MAX_LEVELS_GRAPHICS;
- case SMU_MAX_LEVELS_MEMORY:
- return SMU72_MAX_LEVELS_MEMORY;
- case SMU_MAX_LEVELS_LINK:
- return SMU72_MAX_LEVELS_LINK;
- case SMU_MAX_ENTRIES_SMIO:
- return SMU72_MAX_ENTRIES_SMIO;
- case SMU_MAX_LEVELS_VDDC:
- return SMU72_MAX_LEVELS_VDDC;
- case SMU_MAX_LEVELS_VDDGFX:
- return SMU72_MAX_LEVELS_VDDGFX;
- case SMU_MAX_LEVELS_VDDCI:
- return SMU72_MAX_LEVELS_VDDCI;
- case SMU_MAX_LEVELS_MVDD:
- return SMU72_MAX_LEVELS_MVDD;
- }
- pr_warn("can't get the mac value %x\n", value);
-
- return 0;
-}
-
-
-static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
- smu_data->smc_state_table.UvdBootLevel = 0;
- if (table_info->mm_dep_table->count > 0)
- smu_data->smc_state_table.UvdBootLevel =
- (uint8_t) (table_info->mm_dep_table->count - 1);
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0x00FFFFFF;
- mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC,
- mm_boot_level_offset, mm_boot_level_value);
-
- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_UVDDPM) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_UVDDPM_SetEnabledMask,
- (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
- return 0;
-}
-
-static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data =
- (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
- struct phm_ppt_v1_information *table_info =
- (struct phm_ppt_v1_information *)(hwmgr->pptable);
-
-
- smu_data->smc_state_table.VceBootLevel =
- (uint8_t) (table_info->mm_dep_table->count - 1);
-
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0xFF00FFFF;
- mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_VCEDPM_SetEnabledMask,
- (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
- return 0;
-}
-
-static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-{
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- uint32_t mm_boot_level_offset, mm_boot_level_value;
-
- smu_data->smc_state_table.SamuBootLevel = 0;
- mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
-
- mm_boot_level_offset /= 4;
- mm_boot_level_offset *= 4;
- mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset);
- mm_boot_level_value &= 0xFFFFFF00;
- mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
- cgs_write_ind_register(hwmgr->device,
- CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_StablePState))
- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- PPSMC_MSG_SAMUDPM_SetEnabledMask,
- (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
- return 0;
-}
-
-int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
-{
- switch (type) {
- case SMU_UVD_TABLE:
- tonga_update_uvd_smc_table(hwmgr);
- break;
- case SMU_VCE_TABLE:
- tonga_update_vce_smc_table(hwmgr);
- break;
- case SMU_SAMU_TABLE:
- tonga_update_samu_smc_table(hwmgr);
- break;
- default:
- break;
- }
- return 0;
-}
-
-
-/**
- * Get the location of various tables inside the FW image.
- *
- * @param hwmgr the address of the powerplay hardware manager.
- * @return always 0
- */
-int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
-{
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
-
- uint32_t tmp;
- int result;
- bool error = false;
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU72_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU72_Firmware_Header, DpmTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.dpm_table_start = tmp;
-
- error |= (result != 0);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU72_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU72_Firmware_Header, SoftRegisters),
- &tmp, SMC_RAM_END);
-
- if (!result) {
- data->soft_regs_start = tmp;
- smu_data->smu7_data.soft_regs_start = tmp;
- }
-
- error |= (result != 0);
-
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU72_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU72_Firmware_Header, mcRegisterTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.mc_reg_table_start = tmp;
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU72_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU72_Firmware_Header, FanTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.fan_table_start = tmp;
-
- error |= (result != 0);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU72_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
- &tmp, SMC_RAM_END);
-
- if (!result)
- smu_data->smu7_data.arb_table_start = tmp;
-
- error |= (result != 0);
-
- result = smu7_read_smc_sram_dword(hwmgr->smumgr,
- SMU72_FIRMWARE_HEADER_LOCATION +
- offsetof(SMU72_Firmware_Header, Version),
- &tmp, SMC_RAM_END);
-
- if (!result)
- hwmgr->microcode_version_info.SMC = tmp;
-
- error |= (result != 0);
-
- return error ? 1 : 0;
-}
-
-/*---------------------------MC----------------------------*/
-
-static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
-{
- return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
-}
-
-static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
-{
- bool result = true;
-
- switch (in_reg) {
- case mmMC_SEQ_RAS_TIMING:
- *out_reg = mmMC_SEQ_RAS_TIMING_LP;
- break;
-
- case mmMC_SEQ_DLL_STBY:
- *out_reg = mmMC_SEQ_DLL_STBY_LP;
- break;
-
- case mmMC_SEQ_G5PDX_CMD0:
- *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
- break;
-
- case mmMC_SEQ_G5PDX_CMD1:
- *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
- break;
-
- case mmMC_SEQ_G5PDX_CTRL:
- *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
- break;
-
- case mmMC_SEQ_CAS_TIMING:
- *out_reg = mmMC_SEQ_CAS_TIMING_LP;
- break;
-
- case mmMC_SEQ_MISC_TIMING:
- *out_reg = mmMC_SEQ_MISC_TIMING_LP;
- break;
-
- case mmMC_SEQ_MISC_TIMING2:
- *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
- break;
-
- case mmMC_SEQ_PMG_DVS_CMD:
- *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
- break;
-
- case mmMC_SEQ_PMG_DVS_CTL:
- *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
- break;
-
- case mmMC_SEQ_RD_CTL_D0:
- *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
- break;
-
- case mmMC_SEQ_RD_CTL_D1:
- *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
- break;
-
- case mmMC_SEQ_WR_CTL_D0:
- *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
- break;
-
- case mmMC_SEQ_WR_CTL_D1:
- *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
- break;
-
- case mmMC_PMG_CMD_EMRS:
- *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
- break;
-
- case mmMC_PMG_CMD_MRS:
- *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
- break;
-
- case mmMC_PMG_CMD_MRS1:
- *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
- break;
-
- case mmMC_SEQ_PMG_TIMING:
- *out_reg = mmMC_SEQ_PMG_TIMING_LP;
- break;
-
- case mmMC_PMG_CMD_MRS2:
- *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
- break;
-
- case mmMC_SEQ_WR_CTL_2:
- *out_reg = mmMC_SEQ_WR_CTL_2_LP;
- break;
-
- default:
- result = false;
- break;
- }
-
- return result;
-}
-
-static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table)
-{
- uint32_t i;
- uint16_t address;
-
- for (i = 0; i < table->last; i++) {
- table->mc_reg_address[i].s0 =
- tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
- &address) ?
- address :
- table->mc_reg_address[i].s1;
- }
- return 0;
-}
-
-static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
- struct tonga_mc_reg_table *ni_table)
-{
- uint8_t i, j;
-
- PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
- "Invalid VramInfo table.", return -EINVAL);
-
- for (i = 0; i < table->last; i++)
- ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
-
- ni_table->last = table->last;
-
- for (i = 0; i < table->num_entries; i++) {
- ni_table->mc_reg_table_entry[i].mclk_max =
- table->mc_reg_table_entry[i].mclk_max;
- for (j = 0; j < table->last; j++) {
- ni_table->mc_reg_table_entry[i].mc_data[j] =
- table->mc_reg_table_entry[i].mc_data[j];
- }
- }
-
- ni_table->num_entries = table->num_entries;
-
- return 0;
-}
-
-/**
- * VBIOS omits some information to reduce size, we need to recover them here.
- * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to
- * mmMC_PMG_CMD_EMRS /_LP[15:0]. Bit[15:0] MRS, need to be update
- * mmMC_PMG_CMD_MRS/_LP[15:0]
- * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to
- * mmMC_PMG_CMD_MRS1/_LP[15:0].
- * 3. need to set these data for each clock range
- * @param hwmgr the address of the powerplay hardware manager.
- * @param table the address of MCRegTable
- * @return always 0
- */
-static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
- struct tonga_mc_reg_table *table)
-{
- uint8_t i, j, k;
- uint32_t temp_reg;
- struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
- for (i = 0, j = table->last; i < table->last; i++) {
- PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
-
- switch (table->mc_reg_address[i].s1) {
-
- case mmMC_SEQ_MISC1:
- temp_reg = cgs_read_register(hwmgr->device,
- mmMC_PMG_CMD_EMRS);
- table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
- table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
- for (k = 0; k < table->num_entries; k++) {
- table->mc_reg_table_entry[k].mc_data[j] =
- ((temp_reg & 0xffff0000)) |
- ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
- }
- j++;
- PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
-
- temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
- table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
- table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
- for (k = 0; k < table->num_entries; k++) {
- table->mc_reg_table_entry[k].mc_data[j] =
- (temp_reg & 0xffff0000) |
- (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-
- if (!data->is_memory_gddr5)
- table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
- }
- j++;
- PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
-
- if (!data->is_memory_gddr5) {
- table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
- table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
- for (k = 0; k < table->num_entries; k++)
- table->mc_reg_table_entry[k].mc_data[j] =
- (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
- j++;
- PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- }
-
- break;
-
- case mmMC_SEQ_RESERVE_M:
- temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
- table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
- table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
- for (k = 0; k < table->num_entries; k++) {
- table->mc_reg_table_entry[k].mc_data[j] =
- (temp_reg & 0xffff0000) |
- (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
- }
- j++;
- PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
- "Invalid VramInfo table.", return -EINVAL);
- break;
-
- default:
- break;
- }
-
- }
-
- table->last = j;
-
- return 0;
-}
-
-static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)
-{
- uint8_t i, j;
-
- for (i = 0; i < table->last; i++) {
- for (j = 1; j < table->num_entries; j++) {
- if (table->mc_reg_table_entry[j-1].mc_data[i] !=
- table->mc_reg_table_entry[j].mc_data[i]) {
- table->validflag |= (1<<i);
- break;
- }
- }
- }
-
- return 0;
-}
-
-int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-{
- int result;
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
- pp_atomctrl_mc_reg_table *table;
- struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table;
- uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
-
- table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
-
- if (table == NULL)
- return -ENOMEM;
-
- /* Program additional LP registers that are no longer programmed by VBIOS */
- cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
- cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
- cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
- cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP,
- cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP,
- cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP,
- cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
- cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
- cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
- cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP,
- cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
- cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
- cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
-
- memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-
- result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
-
- if (!result)
- result = tonga_copy_vbios_smc_reg_table(table, ni_table);
-
- if (!result) {
- tonga_set_s0_mc_reg_index(ni_table);
- result = tonga_set_mc_special_registers(hwmgr, ni_table);
- }
-
- if (!result)
- tonga_set_valid_flag(ni_table);
-
- kfree(table);
-
- return result;
-}
-
-bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
-{
- return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
- ? true : false;
-}
-
-int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request)
-{
- struct tonga_smumgr *smu_data = (struct tonga_smumgr *)
- (hwmgr->smumgr->backend);
- struct SMU72_Discrete_GraphicsLevel *levels =
- smu_data->smc_state_table.GraphicsLevel;
- uint32_t array = smu_data->smu7_data.dpm_table_start +
- offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
- uint32_t array_size = sizeof(struct SMU72_Discrete_GraphicsLevel) *
- SMU72_MAX_LEVELS_GRAPHICS;
- uint32_t i;
-
- for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
- levels[i].ActivityLevel =
- cpu_to_be16(request->activity_threshold);
- levels[i].EnabledForActivity = 1;
- levels[i].UpHyst = request->up_hyst;
- levels[i].DownHyst = request->down_hyst;
- }
-
- return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
- array_size, SMC_RAM_END);
-}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h
deleted file mode 100644
index 962860f..0000000
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _TONGA_SMC_H
-#define _TONGA_SMC_H
-
-#include "smumgr.h"
-#include "smu72.h"
-
-
-#define ASICID_IS_TONGA_P(wDID, bRID) \
- (((wDID == 0x6930) && ((bRID == 0xF0) || (bRID == 0xF1) || (bRID == 0xFF))) \
- || ((wDID == 0x6920) && ((bRID == 0) || (bRID == 1))))
-
-
-struct tonga_pt_defaults {
- uint8_t svi_load_line_en;
- uint8_t svi_load_line_vddC;
- uint8_t tdc_vddc_throttle_release_limit_perc;
- uint8_t tdc_mawt;
- uint8_t tdc_waterfall_ctl;
- uint8_t dte_ambient_temp_base;
- uint32_t display_cac;
- uint32_t bamp_temp_gradient;
- uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
- uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
-};
-
-int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
-int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
-int tonga_init_smc_table(struct pp_hwmgr *hwmgr);
-int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
-int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
-int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr);
-uint32_t tonga_get_offsetof(uint32_t type, uint32_t member);
-uint32_t tonga_get_mac_definition(uint32_t value);
-int tonga_process_firmware_header(struct pp_hwmgr *hwmgr);
-int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
-bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr);
-int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- struct amd_pp_profile *request);
-#endif
-
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index c35f4c3..0a8e48b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -33,141 +33,193 @@
#include "smu/smu_7_1_2_d.h"
#include "smu/smu_7_1_2_sh_mask.h"
#include "cgs_common.h"
-#include "tonga_smc.h"
#include "smu7_smumgr.h"
+#include "smu7_dyn_defaults.h"
-static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
+#include "smu7_hwmgr.h"
+#include "hardwaremanager.h"
+#include "ppatomctrl.h"
+
+#include "atombios.h"
+
+#include "pppcielanes.h"
+#include "pp_endian.h"
+
+#include "gmc/gmc_8_1_d.h"
+#include "gmc/gmc_8_1_sh_mask.h"
+
+#include "bif/bif_5_0_d.h"
+#include "bif/bif_5_0_sh_mask.h"
+
+#include "dce/dce_10_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+
+
+#define VOLTAGE_SCALE 4
+#define POWERTUNE_DEFAULT_SET_MAX 1
+#define VOLTAGE_VID_OFFSET_SCALE1 625
+#define VOLTAGE_VID_OFFSET_SCALE2 100
+#define MC_CG_ARB_FREQ_F1 0x0b
+#define VDDC_VDDCI_DELTA 200
+
+
+static const struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
+/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
+ * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
+ */
+ {1, 0xF, 0xFD, 0x19,
+ 5, 45, 0, 0xB0000,
+ {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8,
+ 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
+ {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203,
+ 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
+ },
+};
+
+/* [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
+static const uint16_t tonga_clock_stretcher_lookup_table[2][4] = {
+ {600, 1050, 3, 0},
+ {600, 1050, 6, 1}
+};
+
+/* [FF, SS] type, [] 4 voltage ranges,
+ * and [Floor Freq, Boundary Freq, VID min , VID max]
+ */
+static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = {
+ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
+ { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} }
+};
+
+/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */
+static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = {
+ {0, 1, 3, 2, 4, 5},
+ {0, 2, 4, 5, 6, 5}
+};
+
+static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
{
int result;
/* Assert reset */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- result = smu7_upload_smu_firmware_image(smumgr);
+ result = smu7_upload_smu_firmware_image(hwmgr);
if (result)
return result;
/* Clear status */
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_STATUS, 0);
/* Enable clock */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Set SMU Auto Start */
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_INPUT_DATA, AUTO_START, 1);
/* Clear firmware interrupt enable flag */
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
/**
* Call Test SMU message with 0x20000 offset to trigger SMU start
*/
- smu7_send_msg_to_smc_offset(smumgr);
+ smu7_send_msg_to_smc_offset(hwmgr);
/* Wait for done bit to be set */
- SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
SMU_STATUS, SMU_DONE, 0);
/* Check pass/failed indicator */
- if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
+ if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
pr_err("SMU Firmware start failed\n");
return -EINVAL;
}
/* Wait for firmware to initialize */
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return 0;
}
-
-static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
+static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* wait for smc boot up */
- SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
/*Clear firmware interrupt enable flag*/
- cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- result = smu7_upload_smu_firmware_image(smumgr);
+ result = smu7_upload_smu_firmware_image(hwmgr);
if (result != 0)
return result;
/* Set smc instruct start point at 0x0 */
- smu7_program_jump_on_start(smumgr);
+ smu7_program_jump_on_start(hwmgr);
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/*De-assert reset*/
- SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */
- SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
+ PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
-static int tonga_start_smu(struct pp_smumgr *smumgr)
+static int tonga_start_smu(struct pp_hwmgr *hwmgr)
{
int result;
/* Only start SMC if SMC RAM is not running */
- if (!(smu7_is_smc_ram_running(smumgr) ||
- cgs_is_virtualization_enabled(smumgr->device))) {
+ if (!(smu7_is_smc_ram_running(hwmgr) ||
+ cgs_is_virtualization_enabled(hwmgr->device))) {
/*Check if SMU is running in protected mode*/
- if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
+ if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) {
- result = tonga_start_in_non_protection_mode(smumgr);
+ result = tonga_start_in_non_protection_mode(hwmgr);
if (result)
return result;
} else {
- result = tonga_start_in_protection_mode(smumgr);
+ result = tonga_start_in_protection_mode(hwmgr);
if (result)
return result;
}
}
- result = smu7_request_smu_load_fw(smumgr);
+ result = smu7_request_smu_load_fw(hwmgr);
return result;
}
-/**
- * Write a 32bit value to the SMC SRAM space.
- * ALL PARAMETERS ARE IN HOST BYTE ORDER.
- * @param smumgr the address of the powerplay hardware manager.
- * @param smcAddress the address in the SMC RAM to access.
- * @param value to write to the SMC SRAM.
- */
-static int tonga_smu_init(struct pp_smumgr *smumgr)
+static int tonga_smu_init(struct pp_hwmgr *hwmgr)
{
struct tonga_smumgr *tonga_priv = NULL;
int i;
@@ -176,9 +228,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
if (tonga_priv == NULL)
return -ENOMEM;
- smumgr->backend = tonga_priv;
+ hwmgr->smu_backend = tonga_priv;
- if (smu7_init(smumgr))
+ if (smu7_init(hwmgr))
return -EINVAL;
for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
@@ -187,6 +239,3053 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
return 0;
}
+
+static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
+ phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
+ uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
+{
+ uint32_t i = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ /* clock - voltage dependency table is empty table */
+ if (allowed_clock_voltage_table->count == 0)
+ return -EINVAL;
+
+ for (i = 0; i < allowed_clock_voltage_table->count; i++) {
+ /* find first sclk bigger than request */
+ if (allowed_clock_voltage_table->entries[i].clk >= clock) {
+ voltage->VddGfx = phm_get_voltage_index(
+ pptable_info->vddgfx_lookup_table,
+ allowed_clock_voltage_table->entries[i].vddgfx);
+ voltage->Vddc = phm_get_voltage_index(
+ pptable_info->vddc_lookup_table,
+ allowed_clock_voltage_table->entries[i].vddc);
+
+ if (allowed_clock_voltage_table->entries[i].vddci)
+ voltage->Vddci =
+ phm_get_voltage_id(&data->vddci_voltage_table, allowed_clock_voltage_table->entries[i].vddci);
+ else
+ voltage->Vddci =
+ phm_get_voltage_id(&data->vddci_voltage_table,
+ allowed_clock_voltage_table->entries[i].vddc - VDDC_VDDCI_DELTA);
+
+
+ if (allowed_clock_voltage_table->entries[i].mvdd)
+ *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
+
+ voltage->Phases = 1;
+ return 0;
+ }
+ }
+
+ /* sclk is bigger than max sclk in the dependence table */
+ voltage->VddGfx = phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
+ allowed_clock_voltage_table->entries[i-1].vddgfx);
+ voltage->Vddc = phm_get_voltage_index(pptable_info->vddc_lookup_table,
+ allowed_clock_voltage_table->entries[i-1].vddc);
+
+ if (allowed_clock_voltage_table->entries[i-1].vddci)
+ voltage->Vddci = phm_get_voltage_id(&data->vddci_voltage_table,
+ allowed_clock_voltage_table->entries[i-1].vddci);
+
+ if (allowed_clock_voltage_table->entries[i-1].mvdd)
+ *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
+
+ return 0;
+}
+
+static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ unsigned int count;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
+ table->VddcLevelCount = data->vddc_voltage_table.count;
+ for (count = 0; count < table->VddcLevelCount; count++) {
+ table->VddcTable[count] =
+ PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
+ }
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
+ }
+ return 0;
+}
+
+static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ unsigned int count;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
+ table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
+ for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
+ table->VddGfxTable[count] =
+ PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
+ }
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
+ }
+ return 0;
+}
+
+static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t count;
+
+ table->VddciLevelCount = data->vddci_voltage_table.count;
+ for (count = 0; count < table->VddciLevelCount; count++) {
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
+ table->VddciTable[count] =
+ PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
+ } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ table->SmioTable1.Pattern[count].Voltage =
+ PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
+ /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
+ table->SmioTable1.Pattern[count].Smio =
+ (uint8_t) count;
+ table->Smio[count] |=
+ data->vddci_voltage_table.entries[count].smio_low;
+ table->VddciTable[count] =
+ PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
+ }
+ }
+
+ table->SmioMask1 = data->vddci_voltage_table.mask_low;
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
+
+ return 0;
+}
+
+static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t count;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+ table->MvddLevelCount = data->mvdd_voltage_table.count;
+ for (count = 0; count < table->MvddLevelCount; count++) {
+ table->SmioTable2.Pattern[count].Voltage =
+ PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
+ /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
+ table->SmioTable2.Pattern[count].Smio =
+ (uint8_t) count;
+ table->Smio[count] |=
+ data->mvdd_voltage_table.entries[count].smio_low;
+ }
+ table->SmioMask2 = data->mvdd_voltage_table.mask_low;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
+ }
+
+ return 0;
+}
+
+static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ uint32_t count;
+ uint8_t index = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table =
+ pptable_info->vddgfx_lookup_table;
+ struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table =
+ pptable_info->vddc_lookup_table;
+
+ /* table is already swapped, so in order to use the value from it
+ * we need to swap it back.
+ */
+ uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
+ uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
+
+ for (count = 0; count < vddc_level_count; count++) {
+ /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
+ index = phm_get_voltage_index(vddc_lookup_table,
+ data->vddc_voltage_table.entries[count].value);
+ table->BapmVddcVidLoSidd[count] =
+ convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
+ table->BapmVddcVidHiSidd[count] =
+ convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
+ table->BapmVddcVidHiSidd2[count] =
+ convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
+ }
+
+ if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) {
+ /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
+ for (count = 0; count < vddgfx_level_count; count++) {
+ index = phm_get_voltage_index(vddgfx_lookup_table,
+ convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid));
+ table->BapmVddGfxVidHiSidd2[count] =
+ convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
+ }
+ } else {
+ for (count = 0; count < vddc_level_count; count++) {
+ index = phm_get_voltage_index(vddc_lookup_table,
+ data->vddc_voltage_table.entries[count].value);
+ table->BapmVddGfxVidLoSidd[count] =
+ convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
+ table->BapmVddGfxVidHiSidd[count] =
+ convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
+ table->BapmVddGfxVidHiSidd2[count] =
+ convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
+ }
+ }
+
+ return 0;
+}
+
+static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ int result;
+
+ result = tonga_populate_smc_vddc_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "can not populate VDDC voltage table to SMC",
+ return -EINVAL);
+
+ result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "can not populate VDDCI voltage table to SMC",
+ return -EINVAL);
+
+ result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "can not populate VDDGFX voltage table to SMC",
+ return -EINVAL);
+
+ result = tonga_populate_smc_mvdd_table(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "can not populate MVDD voltage table to SMC",
+ return -EINVAL);
+
+ result = tonga_populate_cac_tables(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "can not populate CAC voltage tables to SMC",
+ return -EINVAL);
+
+ return 0;
+}
+
+static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr,
+ struct SMU72_Discrete_Ulv *state)
+{
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ state->CcPwrDynRm = 0;
+ state->CcPwrDynRm1 = 0;
+
+ state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
+ state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
+ VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
+
+ state->VddcPhase = 1;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
+ CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
+
+ return 0;
+}
+
+static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr,
+ struct SMU72_Discrete_DpmTable *table)
+{
+ return tonga_populate_ulv_level(hwmgr, &table->Ulv);
+}
+
+static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint32_t i;
+
+ /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
+ for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
+ table->LinkLevel[i].PcieGenSpeed =
+ (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
+ table->LinkLevel[i].PcieLaneCount =
+ (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
+ table->LinkLevel[i].EnabledForActivity =
+ 1;
+ table->LinkLevel[i].SPC =
+ (uint8_t)(data->pcie_spc_cap & 0xff);
+ table->LinkLevel[i].DownThreshold =
+ PP_HOST_TO_SMC_UL(5);
+ table->LinkLevel[i].UpThreshold =
+ PP_HOST_TO_SMC_UL(30);
+ }
+
+ smu_data->smc_state_table.LinkLevelCount =
+ (uint8_t)dpm_table->pcie_speed_table.count;
+ data->dpm_level_enable_mask.pcie_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
+
+ return 0;
+}
+
+static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
+ uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ pp_atomctrl_clock_dividers_vi dividers;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ uint32_t reference_clock;
+ uint32_t reference_divider;
+ uint32_t fbdiv;
+ int result;
+
+ /* get the engine clock dividers for this clock value*/
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.", return result);
+
+ /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
+ reference_clock = atomctrl_get_reference_clock(hwmgr);
+
+ reference_divider = 1 + dividers.uc_pll_ref_div;
+
+ /* low 14 bits is fraction and high 12 bits is divider*/
+ fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
+
+ /* SPLL_FUNC_CNTL setup*/
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
+ CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
+
+ /* SPLL_FUNC_CNTL_3 setup*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
+ CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
+
+ /* set to use fractional accumulation*/
+ spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
+ CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
+ pp_atomctrl_internal_ss_info ss_info;
+
+ uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
+ if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
+ /*
+ * ss_info.speed_spectrum_percentage -- in unit of 0.01%
+ * ss_info.speed_spectrum_rate -- in unit of khz
+ */
+ /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
+ uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
+
+ /* clkv = 2 * D * fbdiv / NS */
+ uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
+
+ cg_spll_spread_spectrum =
+ PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
+ cg_spll_spread_spectrum =
+ PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
+ cg_spll_spread_spectrum_2 =
+ PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
+ }
+ }
+
+ sclk->SclkFrequency = engine_clock;
+ sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
+ sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
+ sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
+ sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
+ sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
+
+ return 0;
+}
+
+static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ uint32_t engine_clock,
+ uint16_t sclk_activity_level_threshold,
+ SMU72_Discrete_GraphicsLevel *graphic_level)
+{
+ int result;
+ uint32_t mvdd;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
+
+ /* populate graphics levels*/
+ result = tonga_get_dependency_volt_by_clk(hwmgr,
+ pptable_info->vdd_dep_on_sclk, engine_clock,
+ &graphic_level->MinVoltage, &mvdd);
+ PP_ASSERT_WITH_CODE((!result),
+ "can not find VDDC voltage value for VDDC "
+ "engine clock dependency table", return result);
+
+ /* SCLK frequency in units of 10KHz*/
+ graphic_level->SclkFrequency = engine_clock;
+ /* Indicates maximum activity level for this performance level. 50% for now*/
+ graphic_level->ActivityLevel = sclk_activity_level_threshold;
+
+ graphic_level->CcPwrDynRm = 0;
+ graphic_level->CcPwrDynRm1 = 0;
+ /* this level can be used if activity is high enough.*/
+ graphic_level->EnabledForActivity = 0;
+ /* this level can be used for throttling.*/
+ graphic_level->EnabledForThrottle = 1;
+ graphic_level->UpHyst = 0;
+ graphic_level->DownHyst = 0;
+ graphic_level->VoltageDownHyst = 0;
+ graphic_level->PowerThrottle = 0;
+
+ data->display_timing.min_clock_in_sr =
+ hwmgr->display_config.min_core_set_clock_in_sr;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkDeepSleep))
+ graphic_level->DeepSleepDivId =
+ smu7_get_sleep_divider_id_from_clock(engine_clock,
+ data->display_timing.min_clock_in_sr);
+
+ /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
+ graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ if (!result) {
+ /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
+ /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
+ }
+
+ return result;
+}
+
+static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
+ uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
+ uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
+
+ uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
+ SMU72_MAX_LEVELS_GRAPHICS;
+
+ SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
+
+ uint32_t i, max_entry;
+ uint8_t highest_pcie_level_enabled = 0;
+ uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
+ uint8_t count = 0;
+ int result = 0;
+
+ memset(levels, 0x00, level_array_size);
+
+ for (i = 0; i < dpm_table->sclk_table.count; i++) {
+ result = tonga_populate_single_graphic_level(hwmgr,
+ dpm_table->sclk_table.dpm_levels[i].value,
+ (uint16_t)smu_data->activity_target[i],
+ &(smu_data->smc_state_table.GraphicsLevel[i]));
+ if (result != 0)
+ return result;
+
+ /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
+ if (i > 1)
+ smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
+ }
+
+ /* Only enable level 0 for now. */
+ smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
+
+ /* set highest level watermark to high */
+ if (dpm_table->sclk_table.count > 1)
+ smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
+ PPSMC_DISPLAY_WATERMARK_HIGH;
+
+ smu_data->smc_state_table.GraphicsDpmLevelCount =
+ (uint8_t)dpm_table->sclk_table.count;
+ data->dpm_level_enable_mask.sclk_dpm_enable_mask =
+ phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
+
+ if (pcie_table != NULL) {
+ PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
+ "There must be 1 or more PCIE levels defined in PPTable.",
+ return -EINVAL);
+ max_entry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
+ for (i = 0; i < dpm_table->sclk_table.count; i++) {
+ smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
+ (uint8_t) ((i < max_entry) ? i : max_entry);
+ }
+ } else {
+ if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
+ pr_err("Pcie Dpm Enablemask is 0 !");
+
+ while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
+ ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1<<(highest_pcie_level_enabled+1))) != 0)) {
+ highest_pcie_level_enabled++;
+ }
+
+ while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
+ ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1<<lowest_pcie_level_enabled)) == 0)) {
+ lowest_pcie_level_enabled++;
+ }
+
+ while ((count < highest_pcie_level_enabled) &&
+ ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
+ (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
+ count++;
+ }
+ mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
+ (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
+
+
+ /* set pcieDpmLevel to highest_pcie_level_enabled*/
+ for (i = 2; i < dpm_table->sclk_table.count; i++)
+ smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to lowest_pcie_level_enabled*/
+ smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
+
+ /* set pcieDpmLevel to mid_pcie_level_enabled*/
+ smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
+ }
+ /* level count will send to smc once at init smc table and never change*/
+ result = smu7_copy_bytes_to_smc(hwmgr, level_array_address,
+ (uint8_t *)levels, (uint32_t)level_array_size,
+ SMC_RAM_END);
+
+ return result;
+}
+
+static int tonga_calculate_mclk_params(
+ struct pp_hwmgr *hwmgr,
+ uint32_t memory_clock,
+ SMU72_Discrete_MemoryLevel *mclk,
+ bool strobe_mode,
+ bool dllStateOn
+ )
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
+ uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
+ uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
+ uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
+ uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
+ uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
+ uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
+ uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
+ uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
+
+ pp_atomctrl_memory_clock_param mpll_param;
+ int result;
+
+ result = atomctrl_get_memory_pll_dividers_si(hwmgr,
+ memory_clock, &mpll_param, strobe_mode);
+ PP_ASSERT_WITH_CODE(
+ !result,
+ "Error retrieving Memory Clock Parameters from VBIOS.",
+ return result);
+
+ /* MPLL_FUNC_CNTL setup*/
+ mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL,
+ mpll_param.bw_ctrl);
+
+ /* MPLL_FUNC_CNTL_1 setup*/
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, CLKF,
+ mpll_param.mpll_fb_divider.cl_kf);
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, CLKFRAC,
+ mpll_param.mpll_fb_divider.clk_frac);
+ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
+ MPLL_FUNC_CNTL_1, VCO_MODE,
+ mpll_param.vco_mode);
+
+ /* MPLL_AD_FUNC_CNTL setup*/
+ mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
+ MPLL_AD_FUNC_CNTL, YCLK_POST_DIV,
+ mpll_param.mpll_post_divider);
+
+ if (data->is_memory_gddr5) {
+ /* MPLL_DQ_FUNC_CNTL setup*/
+ mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
+ MPLL_DQ_FUNC_CNTL, YCLK_SEL,
+ mpll_param.yclk_sel);
+ mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
+ MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV,
+ mpll_param.mpll_post_divider);
+ }
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
+ /*
+ ************************************
+ Fref = Reference Frequency
+ NF = Feedback divider ratio
+ NR = Reference divider ratio
+ Fnom = Nominal VCO output frequency = Fref * NF / NR
+ Fs = Spreading Rate
+ D = Percentage down-spread / 2
+ Fint = Reference input frequency to PFD = Fref / NR
+ NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
+ CLKS = NS - 1 = ISS_STEP_NUM[11:0]
+ NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
+ CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
+ *************************************
+ */
+ pp_atomctrl_internal_ss_info ss_info;
+ uint32_t freq_nom;
+ uint32_t tmp;
+ uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
+
+ /* for GDDR5 for all modes and DDR3 */
+ if (1 == mpll_param.qdr)
+ freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
+ else
+ freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
+
+ /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
+ tmp = (freq_nom / reference_clock);
+ tmp = tmp * tmp;
+
+ if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
+ /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
+ /* ss.Info.speed_spectrum_rate -- in unit of khz */
+ /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
+ /* = reference_clock * 5 / speed_spectrum_rate */
+ uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
+
+ /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
+ /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
+ uint32_t clkv =
+ (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
+ ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
+
+ mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
+ mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
+ }
+ }
+
+ /* MCLK_PWRMGT_CNTL setup */
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
+
+ /* Save the result data to outpupt memory level structure */
+ mclk->MclkFrequency = memory_clock;
+ mclk->MpllFuncCntl = mpll_func_cntl;
+ mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
+ mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
+ mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
+ mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
+ mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
+ mclk->DllCntl = dll_cntl;
+ mclk->MpllSs1 = mpll_ss1;
+ mclk->MpllSs2 = mpll_ss2;
+
+ return 0;
+}
+
+static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
+ bool strobe_mode)
+{
+ uint8_t mc_para_index;
+
+ if (strobe_mode) {
+ if (memory_clock < 12500)
+ mc_para_index = 0x00;
+ else if (memory_clock > 47500)
+ mc_para_index = 0x0f;
+ else
+ mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
+ } else {
+ if (memory_clock < 65000)
+ mc_para_index = 0x00;
+ else if (memory_clock > 135000)
+ mc_para_index = 0x0f;
+ else
+ mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
+ }
+
+ return mc_para_index;
+}
+
+static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
+{
+ uint8_t mc_para_index;
+
+ if (memory_clock < 10000)
+ mc_para_index = 0;
+ else if (memory_clock >= 80000)
+ mc_para_index = 0x0f;
+ else
+ mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
+
+ return mc_para_index;
+}
+
+
+static int tonga_populate_single_memory_level(
+ struct pp_hwmgr *hwmgr,
+ uint32_t memory_clock,
+ SMU72_Discrete_MemoryLevel *memory_level
+ )
+{
+ uint32_t mvdd = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ int result = 0;
+ bool dll_state_on;
+ struct cgs_display_info info = {0};
+ uint32_t mclk_edc_wr_enable_threshold = 40000;
+ uint32_t mclk_stutter_mode_threshold = 30000;
+ uint32_t mclk_edc_enable_threshold = 40000;
+ uint32_t mclk_strobe_mode_threshold = 40000;
+
+ if (NULL != pptable_info->vdd_dep_on_mclk) {
+ result = tonga_get_dependency_volt_by_clk(hwmgr,
+ pptable_info->vdd_dep_on_mclk,
+ memory_clock,
+ &memory_level->MinVoltage, &mvdd);
+ PP_ASSERT_WITH_CODE(
+ !result,
+ "can not find MinVddc voltage value from memory VDDC "
+ "voltage dependency table",
+ return result);
+ }
+
+ if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
+ memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
+ else
+ memory_level->MinMvdd = mvdd;
+
+ memory_level->EnabledForThrottle = 1;
+ memory_level->EnabledForActivity = 0;
+ memory_level->UpHyst = 0;
+ memory_level->DownHyst = 100;
+ memory_level->VoltageDownHyst = 0;
+
+ /* Indicates maximum activity level for this performance level.*/
+ memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
+ memory_level->StutterEnable = 0;
+ memory_level->StrobeEnable = 0;
+ memory_level->EdcReadEnable = 0;
+ memory_level->EdcWriteEnable = 0;
+ memory_level->RttEnable = 0;
+
+ /* default set to low watermark. Highest level will be set to high later.*/
+ memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+
+ cgs_get_active_displays_info(hwmgr->device, &info);
+ data->display_timing.num_existing_displays = info.display_count;
+
+ if ((mclk_stutter_mode_threshold != 0) &&
+ (memory_clock <= mclk_stutter_mode_threshold) &&
+ (!data->is_uvd_enabled)
+ && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
+ && (data->display_timing.num_existing_displays <= 2)
+ && (data->display_timing.num_existing_displays != 0))
+ memory_level->StutterEnable = 1;
+
+ /* decide strobe mode*/
+ memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
+ (memory_clock <= mclk_strobe_mode_threshold);
+
+ /* decide EDC mode and memory clock ratio*/
+ if (data->is_memory_gddr5) {
+ memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
+ memory_level->StrobeEnable);
+
+ if ((mclk_edc_enable_threshold != 0) &&
+ (memory_clock > mclk_edc_enable_threshold)) {
+ memory_level->EdcReadEnable = 1;
+ }
+
+ if ((mclk_edc_wr_enable_threshold != 0) &&
+ (memory_clock > mclk_edc_wr_enable_threshold)) {
+ memory_level->EdcWriteEnable = 1;
+ }
+
+ if (memory_level->StrobeEnable) {
+ if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
+ ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
+ } else {
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
+ }
+
+ } else {
+ dll_state_on = data->dll_default_on;
+ }
+ } else {
+ memory_level->StrobeRatio =
+ tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
+ dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
+ }
+
+ result = tonga_calculate_mclk_params(hwmgr,
+ memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
+
+ if (!result) {
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
+ /* MCLK frequency in units of 10KHz*/
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
+ /* Indicates maximum activity level for this performance level.*/
+ CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
+ CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
+ }
+
+ return result;
+}
+
+int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ struct smu7_dpm_table *dpm_table = &data->dpm_table;
+ int result;
+
+ /* populate MCLK dpm table to SMU7 */
+ uint32_t level_array_address =
+ smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
+ uint32_t level_array_size =
+ sizeof(SMU72_Discrete_MemoryLevel) *
+ SMU72_MAX_LEVELS_MEMORY;
+ SMU72_Discrete_MemoryLevel *levels =
+ smu_data->smc_state_table.MemoryLevel;
+ uint32_t i;
+
+ memset(levels, 0x00, level_array_size);
+
+ for (i = 0; i < dpm_table->mclk_table.count; i++) {
+ PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
+ "can not populate memory level as memory clock is zero",
+ return -EINVAL);
+ result = tonga_populate_single_memory_level(
+ hwmgr,
+ dpm_table->mclk_table.dpm_levels[i].value,
+ &(smu_data->smc_state_table.MemoryLevel[i]));
+ if (result)
+ return result;
+ }
+
+ /* Only enable level 0 for now.*/
+ smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
+
+ /*
+ * in order to prevent MC activity from stutter mode to push DPM up.
+ * the UVD change complements this by putting the MCLK in a higher state
+ * by default such that we are not effected by up threshold or and MCLK DPM latency.
+ */
+ smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
+
+ smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
+ data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
+ /* set highest level watermark to high*/
+ smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
+
+ /* level count will send to smc once at init smc table and never change*/
+ result = smu7_copy_bytes_to_smc(hwmgr,
+ level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
+ SMC_RAM_END);
+
+ return result;
+}
+
+static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr,
+ uint32_t mclk, SMIO_Pattern *smio_pattern)
+{
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint32_t i = 0;
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
+ /* find mvdd value which clock is more than request */
+ for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
+ if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
+ /* Always round to higher voltage. */
+ smio_pattern->Voltage =
+ data->mvdd_voltage_table.entries[i].value;
+ break;
+ }
+ }
+
+ PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
+ "MVDD Voltage is outside the supported range.",
+ return -EINVAL);
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+
+static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ int result = 0;
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct pp_atomctrl_clock_dividers_vi dividers;
+
+ SMIO_Pattern voltage_level;
+ uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
+ uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
+ uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
+ uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
+
+ /* The ACPI state should not do DPM on DC (or ever).*/
+ table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
+
+ table->ACPILevel.MinVoltage =
+ smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;
+
+ /* assign zero for now*/
+ table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
+
+ /* get the engine clock dividers for this clock value*/
+ result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
+ table->ACPILevel.SclkFrequency, ÷rs);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error retrieving Engine Clock dividers from VBIOS.",
+ return result);
+
+ /* divider ID for required SCLK*/
+ table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
+ table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
+ table->ACPILevel.DeepSleepDivId = 0;
+
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_PWRON, 0);
+ spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
+ SPLL_RESET, 1);
+ spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
+ SCLK_MUX_SEL, 4);
+
+ table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
+ table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
+ table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
+ table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
+ table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
+ table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
+ table->ACPILevel.CcPwrDynRm = 0;
+ table->ACPILevel.CcPwrDynRm1 = 0;
+
+
+ /* For various features to be enabled/disabled while this level is active.*/
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
+ /* SCLK frequency in units of 10KHz*/
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
+
+ /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
+ table->MemoryACPILevel.MinVoltage =
+ smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
+
+ /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
+
+ if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
+ table->MemoryACPILevel.MinMvdd =
+ PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
+ else
+ table->MemoryACPILevel.MinMvdd = 0;
+
+ /* Force reset on DLL*/
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
+
+ /* Disable DLL in ACPIState*/
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
+ mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
+ MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
+
+ /* Enable DLL bypass signal*/
+ dll_cntl = PHM_SET_FIELD(dll_cntl,
+ DLL_CNTL, MRDCK0_BYPASS, 0);
+ dll_cntl = PHM_SET_FIELD(dll_cntl,
+ DLL_CNTL, MRDCK1_BYPASS, 0);
+
+ table->MemoryACPILevel.DllCntl =
+ PP_HOST_TO_SMC_UL(dll_cntl);
+ table->MemoryACPILevel.MclkPwrmgtCntl =
+ PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
+ table->MemoryACPILevel.MpllAdFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
+ table->MemoryACPILevel.MpllDqFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
+ table->MemoryACPILevel.MpllFuncCntl =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
+ table->MemoryACPILevel.MpllFuncCntl_1 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
+ table->MemoryACPILevel.MpllFuncCntl_2 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
+ table->MemoryACPILevel.MpllSs1 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
+ table->MemoryACPILevel.MpllSs2 =
+ PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
+
+ table->MemoryACPILevel.EnabledForThrottle = 0;
+ table->MemoryACPILevel.EnabledForActivity = 0;
+ table->MemoryACPILevel.UpHyst = 0;
+ table->MemoryACPILevel.DownHyst = 100;
+ table->MemoryACPILevel.VoltageDownHyst = 0;
+ /* Indicates maximum activity level for this performance level.*/
+ table->MemoryACPILevel.ActivityLevel =
+ PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
+
+ table->MemoryACPILevel.StutterEnable = 0;
+ table->MemoryACPILevel.StrobeEnable = 0;
+ table->MemoryACPILevel.EdcReadEnable = 0;
+ table->MemoryACPILevel.EdcWriteEnable = 0;
+ table->MemoryACPILevel.RttEnable = 0;
+
+ return result;
+}
+
+static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ int result = 0;
+
+ uint8_t count;
+ pp_atomctrl_clock_dividers_vi dividers;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ pptable_info->mm_dep_table;
+
+ table->UvdLevelCount = (uint8_t) (mm_table->count);
+ table->UvdBootLevel = 0;
+
+ for (count = 0; count < table->UvdLevelCount; count++) {
+ table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
+ table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
+ table->UvdLevel[count].MinVoltage.Vddc =
+ phm_get_voltage_index(pptable_info->vddc_lookup_table,
+ mm_table->entries[count].vddc);
+ table->UvdLevel[count].MinVoltage.VddGfx =
+ (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
+ phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
+ mm_table->entries[count].vddgfx) : 0;
+ table->UvdLevel[count].MinVoltage.Vddci =
+ phm_get_voltage_id(&data->vddci_voltage_table,
+ mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+ table->UvdLevel[count].MinVoltage.Phases = 1;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(
+ hwmgr,
+ table->UvdLevel[count].VclkFrequency,
+ ÷rs);
+
+ PP_ASSERT_WITH_CODE((!result),
+ "can not find divide id for Vclk clock",
+ return result);
+
+ table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
+
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->UvdLevel[count].DclkFrequency, ÷rs);
+ PP_ASSERT_WITH_CODE((!result),
+ "can not find divide id for Dclk clock",
+ return result);
+
+ table->UvdLevel[count].DclkDivider =
+ (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
+ }
+
+ return result;
+
+}
+
+static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ int result = 0;
+
+ uint8_t count;
+ pp_atomctrl_clock_dividers_vi dividers;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ pptable_info->mm_dep_table;
+
+ table->VceLevelCount = (uint8_t) (mm_table->count);
+ table->VceBootLevel = 0;
+
+ for (count = 0; count < table->VceLevelCount; count++) {
+ table->VceLevel[count].Frequency =
+ mm_table->entries[count].eclk;
+ table->VceLevel[count].MinVoltage.Vddc =
+ phm_get_voltage_index(pptable_info->vddc_lookup_table,
+ mm_table->entries[count].vddc);
+ table->VceLevel[count].MinVoltage.VddGfx =
+ (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
+ phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
+ mm_table->entries[count].vddgfx) : 0;
+ table->VceLevel[count].MinVoltage.Vddci =
+ phm_get_voltage_id(&data->vddci_voltage_table,
+ mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+ table->VceLevel[count].MinVoltage.Phases = 1;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->VceLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((!result),
+ "can not find divide id for VCE engine clock",
+ return result);
+
+ table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
+ }
+
+ return result;
+}
+
+static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ int result = 0;
+ uint8_t count;
+ pp_atomctrl_clock_dividers_vi dividers;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ pptable_info->mm_dep_table;
+
+ table->AcpLevelCount = (uint8_t) (mm_table->count);
+ table->AcpBootLevel = 0;
+
+ for (count = 0; count < table->AcpLevelCount; count++) {
+ table->AcpLevel[count].Frequency =
+ pptable_info->mm_dep_table->entries[count].aclk;
+ table->AcpLevel[count].MinVoltage.Vddc =
+ phm_get_voltage_index(pptable_info->vddc_lookup_table,
+ mm_table->entries[count].vddc);
+ table->AcpLevel[count].MinVoltage.VddGfx =
+ (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
+ phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
+ mm_table->entries[count].vddgfx) : 0;
+ table->AcpLevel[count].MinVoltage.Vddci =
+ phm_get_voltage_id(&data->vddci_voltage_table,
+ mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+ table->AcpLevel[count].MinVoltage.Phases = 1;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->AcpLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((!result),
+ "can not find divide id for engine clock", return result);
+
+ table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
+ }
+
+ return result;
+}
+
+static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ int result = 0;
+ uint8_t count;
+ pp_atomctrl_clock_dividers_vi dividers;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *pptable_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+ pptable_info->mm_dep_table;
+
+ table->SamuBootLevel = 0;
+ table->SamuLevelCount = (uint8_t) (mm_table->count);
+
+ for (count = 0; count < table->SamuLevelCount; count++) {
+ /* not sure whether we need evclk or not */
+ table->SamuLevel[count].Frequency =
+ pptable_info->mm_dep_table->entries[count].samclock;
+ table->SamuLevel[count].MinVoltage.Vddc =
+ phm_get_voltage_index(pptable_info->vddc_lookup_table,
+ mm_table->entries[count].vddc);
+ table->SamuLevel[count].MinVoltage.VddGfx =
+ (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
+ phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
+ mm_table->entries[count].vddgfx) : 0;
+ table->SamuLevel[count].MinVoltage.Vddci =
+ phm_get_voltage_id(&data->vddci_voltage_table,
+ mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+ table->SamuLevel[count].MinVoltage.Phases = 1;
+
+ /* retrieve divider value for VBIOS */
+ result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+ table->SamuLevel[count].Frequency, ÷rs);
+ PP_ASSERT_WITH_CODE((!result),
+ "can not find divide id for samu clock", return result);
+
+ table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
+ }
+
+ return result;
+}
+
+static int tonga_populate_memory_timing_parameters(
+ struct pp_hwmgr *hwmgr,
+ uint32_t engine_clock,
+ uint32_t memory_clock,
+ struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
+ )
+{
+ uint32_t dramTiming;
+ uint32_t dramTiming2;
+ uint32_t burstTime;
+ int result;
+
+ result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
+ engine_clock, memory_clock);
+
+ PP_ASSERT_WITH_CODE(result == 0,
+ "Error calling VBIOS to set DRAM_TIMING.", return result);
+
+ dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
+ dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
+ burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
+
+ arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
+ arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
+ arb_regs->McArbBurstTime = (uint8_t)burstTime;
+
+ return 0;
+}
+
+static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ int result = 0;
+ SMU72_Discrete_MCArbDramTimingTable arb_regs;
+ uint32_t i, j;
+
+ memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
+
+ for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
+ for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
+ result = tonga_populate_memory_timing_parameters
+ (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
+ data->dpm_table.mclk_table.dpm_levels[j].value,
+ &arb_regs.entries[i][j]);
+
+ if (result)
+ break;
+ }
+ }
+
+ if (!result) {
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.arb_table_start,
+ (uint8_t *)&arb_regs,
+ sizeof(SMU72_Discrete_MCArbDramTimingTable),
+ SMC_RAM_END
+ );
+ }
+
+ return result;
+}
+
+static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ table->GraphicsBootLevel = 0;
+ table->MemoryBootLevel = 0;
+
+ /* find boot level from dpm table*/
+ result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+ data->vbios_boot_state.sclk_bootup_value,
+ (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
+
+ if (result != 0) {
+ smu_data->smc_state_table.GraphicsBootLevel = 0;
+ pr_err("[powerplay] VBIOS did not find boot engine "
+ "clock value in dependency table. "
+ "Using Graphics DPM level 0 !");
+ result = 0;
+ }
+
+ result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+ data->vbios_boot_state.mclk_bootup_value,
+ (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
+
+ if (result != 0) {
+ smu_data->smc_state_table.MemoryBootLevel = 0;
+ pr_err("[powerplay] VBIOS did not find boot "
+ "engine clock value in dependency table."
+ "Using Memory DPM level 0 !");
+ result = 0;
+ }
+
+ table->BootVoltage.Vddc =
+ phm_get_voltage_id(&(data->vddc_voltage_table),
+ data->vbios_boot_state.vddc_bootup_value);
+ table->BootVoltage.VddGfx =
+ phm_get_voltage_id(&(data->vddgfx_voltage_table),
+ data->vbios_boot_state.vddgfx_bootup_value);
+ table->BootVoltage.Vddci =
+ phm_get_voltage_id(&(data->vddci_voltage_table),
+ data->vbios_boot_state.vddci_bootup_value);
+ table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
+
+ CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
+
+ return result;
+}
+
+static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+{
+ uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
+ volt_with_cks, value;
+ uint16_t clock_freq_u16;
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
+ volt_offset = 0;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+ table_info->vdd_dep_on_sclk;
+ uint32_t hw_revision, dev_id;
+ struct cgs_system_info sys_info = {0};
+
+ stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
+
+ sys_info.size = sizeof(struct cgs_system_info);
+
+ sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
+ cgs_query_system_info(hwmgr->device, &sys_info);
+ hw_revision = (uint32_t)sys_info.value;
+
+ sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
+ cgs_query_system_info(hwmgr->device, &sys_info);
+ dev_id = (uint32_t)sys_info.value;
+
+ /* Read SMU_Eefuse to read and calculate RO and determine
+ * if the part is SS or FF. if RO >= 1660MHz, part is FF.
+ */
+ efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixSMU_EFUSE_0 + (146 * 4));
+ efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixSMU_EFUSE_0 + (148 * 4));
+ efuse &= 0xFF000000;
+ efuse = efuse >> 24;
+ efuse2 &= 0xF;
+
+ if (efuse2 == 1)
+ ro = (2300 - 1350) * efuse / 255 + 1350;
+ else
+ ro = (2500 - 1000) * efuse / 255 + 1000;
+
+ if (ro >= 1660)
+ type = 0;
+ else
+ type = 1;
+
+ /* Populate Stretch amount */
+ smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
+
+
+ /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
+ for (i = 0; i < sclk_table->count; i++) {
+ smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
+ sclk_table->entries[i].cks_enable << i;
+ if (ASICID_IS_TONGA_P(dev_id, hw_revision)) {
+ volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 *
+ (sclk_table->entries[i].clk/100) / 10000) * 1000 /
+ (8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000)));
+ volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 *
+ (sclk_table->entries[i].clk/100) / 100000) * 1000 /
+ (6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000)));
+ } else {
+ volt_without_cks = (uint32_t)((14041 *
+ (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
+ (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
+ volt_with_cks = (uint32_t)((13946 *
+ (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
+ (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
+ }
+ if (volt_without_cks >= volt_with_cks)
+ volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
+ sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
+ smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
+ }
+
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ STRETCH_ENABLE, 0x0);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ masterReset, 0x1);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ staticEnable, 0x1);
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
+ masterReset, 0x0);
+
+ /* Populate CKS Lookup Table */
+ if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
+ stretch_amount2 = 0;
+ else if (stretch_amount == 3 || stretch_amount == 4)
+ stretch_amount2 = 1;
+ else {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ClockStretcher);
+ PP_ASSERT_WITH_CODE(false,
+ "Stretch Amount in PPTable not supported\n",
+ return -EINVAL);
+ }
+
+ value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixPWR_CKS_CNTL);
+ value &= 0xFFC2FF87;
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
+ tonga_clock_stretcher_lookup_table[stretch_amount2][0];
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
+ tonga_clock_stretcher_lookup_table[stretch_amount2][1];
+ clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
+ GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
+ SclkFrequency) / 100);
+ if (tonga_clock_stretcher_lookup_table[stretch_amount2][0] <
+ clock_freq_u16 &&
+ tonga_clock_stretcher_lookup_table[stretch_amount2][1] >
+ clock_freq_u16) {
+ /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
+ value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
+ /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
+ value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
+ /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
+ value |= (tonga_clock_stretch_amount_conversion
+ [tonga_clock_stretcher_lookup_table[stretch_amount2][3]]
+ [stretch_amount]) << 3;
+ }
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
+ CKS_LOOKUPTableEntry[0].minFreq);
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
+ CKS_LOOKUPTableEntry[0].maxFreq);
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
+ tonga_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
+ smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
+ (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixPWR_CKS_CNTL, value);
+
+ /* Populate DDT Lookup Table */
+ for (i = 0; i < 4; i++) {
+ /* Assign the minimum and maximum VID stored
+ * in the last row of Clock Stretcher Voltage Table.
+ */
+ smu_data->smc_state_table.ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].minVID =
+ (uint8_t) tonga_clock_stretcher_ddt_table[type][i][2];
+ smu_data->smc_state_table.ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].maxVID =
+ (uint8_t) tonga_clock_stretcher_ddt_table[type][i][3];
+ /* Loop through each SCLK and check the frequency
+ * to see if it lies within the frequency for clock stretcher.
+ */
+ for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
+ cks_setting = 0;
+ clock_freq = PP_SMC_TO_HOST_UL(
+ smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
+ /* Check the allowed frequency against the sclk level[j].
+ * Sclk's endianness has already been converted,
+ * and it's in 10Khz unit,
+ * as opposed to Data table, which is in Mhz unit.
+ */
+ if (clock_freq >= tonga_clock_stretcher_ddt_table[type][i][0] * 100) {
+ cks_setting |= 0x2;
+ if (clock_freq < tonga_clock_stretcher_ddt_table[type][i][1] * 100)
+ cks_setting |= 0x1;
+ }
+ smu_data->smc_state_table.ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
+ }
+ CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
+ ClockStretcherDataTable.
+ ClockStretcherDataTableEntry[i].setting);
+ }
+
+ value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixPWR_CKS_CNTL);
+ value &= 0xFFFFFFFE;
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixPWR_CKS_CNTL, value);
+
+ return 0;
+}
+
+static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_DpmTable *table)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint16_t config;
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
+ /* Splitted mode */
+ config = VR_SVI2_PLANE_1;
+ table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
+
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
+ config = VR_SVI2_PLANE_2;
+ table->VRConfig |= config;
+ } else {
+ pr_err("VDDC and VDDGFX should "
+ "be both on SVI2 control in splitted mode !\n");
+ }
+ } else {
+ /* Merged mode */
+ config = VR_MERGED_WITH_VDDC;
+ table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
+
+ /* Set Vddc Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
+ config = VR_SVI2_PLANE_1;
+ table->VRConfig |= config;
+ } else {
+ pr_err("VDDC should be on "
+ "SVI2 control in merged mode !\n");
+ }
+ }
+
+ /* Set Vddci Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
+ config = VR_SVI2_PLANE_2; /* only in merged mode */
+ table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
+ } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
+ config = VR_SMIO_PATTERN_1;
+ table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
+ }
+
+ /* Set Mvdd Voltage Controller */
+ if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+ config = VR_SMIO_PATTERN_2;
+ table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
+ }
+
+ return 0;
+}
+
+static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint32_t tmp;
+ int result;
+
+ /*
+ * This is a read-modify-write on the first byte of the ARB table.
+ * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure
+ * is the field 'current'.
+ * This solution is ugly, but we never write the whole table only
+ * individual fields in it.
+ * In reality this field should not be in that structure
+ * but in a soft register.
+ */
+ result = smu7_read_smc_sram_dword(hwmgr,
+ smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
+
+ if (result != 0)
+ return result;
+
+ tmp &= 0x00FFFFFF;
+ tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
+
+ return smu7_write_smc_sram_dword(hwmgr,
+ smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
+}
+
+
+static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
+ SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
+ int i, j, k;
+ const uint16_t *pdef1, *pdef2;
+
+ dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
+ (uint16_t)(cac_dtp_table->usTDP * 256));
+ dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
+ (uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
+
+ PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
+ "Target Operating Temp is out of Range !",
+ );
+
+ dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
+ dpm_table->GpuTjHyst = 8;
+
+ dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
+
+ dpm_table->BAPM_TEMP_GRADIENT =
+ PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
+ pdef1 = defaults->bapmti_r;
+ pdef2 = defaults->bapmti_rc;
+
+ for (i = 0; i < SMU72_DTE_ITERATIONS; i++) {
+ for (j = 0; j < SMU72_DTE_SOURCES; j++) {
+ for (k = 0; k < SMU72_DTE_SINKS; k++) {
+ dpm_table->BAPMTI_R[i][j][k] =
+ PP_HOST_TO_SMC_US(*pdef1);
+ dpm_table->BAPMTI_RC[i][j][k] =
+ PP_HOST_TO_SMC_US(*pdef2);
+ pdef1++;
+ pdef2++;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
+
+ smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
+ smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
+ smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
+ smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
+
+ return 0;
+}
+
+static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
+{
+ uint16_t tdc_limit;
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ /* TDC number of fraction bits are changed from 8 to 7
+ * for Fiji as requested by SMC team
+ */
+ tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 256);
+ smu_data->power_tune_table.TDC_VDDC_PkgLimit =
+ CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
+ smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
+ defaults->tdc_vddc_throttle_release_limit_perc;
+ smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
+
+ return 0;
+}
+
+static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
+ uint32_t temp;
+
+ if (smu7_read_smc_sram_dword(hwmgr,
+ fuse_table_offset +
+ offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
+ (uint32_t *)&temp, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to read PmFuses.DW6 "
+ "(SviLoadLineEn) from SMC Failed !",
+ return -EINVAL);
+ else
+ smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
+
+ return 0;
+}
+
+static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+
+ /* Currently not used. Set all to zero. */
+ for (i = 0; i < 16; i++)
+ smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
+
+ return 0;
+}
+
+static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+
+ if ((hwmgr->thermal_controller.advanceFanControlParameters.
+ usFanOutputSensitivity & (1 << 15)) ||
+ (hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
+ hwmgr->thermal_controller.advanceFanControlParameters.
+ usFanOutputSensitivity = hwmgr->thermal_controller.
+ advanceFanControlParameters.usDefaultFanOutputSensitivity;
+
+ smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
+ PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
+ advanceFanControlParameters.usFanOutputSensitivity);
+ return 0;
+}
+
+static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
+{
+ int i;
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+
+ /* Currently not used. Set all to zero. */
+ for (i = 0; i < 16; i++)
+ smu_data->power_tune_table.GnbLPML[i] = 0;
+
+ return 0;
+}
+
+static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
+ uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
+ struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
+
+ hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
+ lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
+
+ smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
+ smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
+ CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
+
+ return 0;
+}
+
+static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint32_t pm_fuse_table_offset;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment)) {
+ if (smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, PmFuseTable),
+ &pm_fuse_table_offset, SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to get pm_fuse_table_offset Failed !",
+ return -EINVAL);
+
+ /* DW6 */
+ if (tonga_populate_svi_load_line(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate SviLoadLine Failed !",
+ return -EINVAL);
+ /* DW7 */
+ if (tonga_populate_tdc_limit(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TDCLimit Failed !",
+ return -EINVAL);
+ /* DW8 */
+ if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate TdcWaterfallCtl Failed !",
+ return -EINVAL);
+
+ /* DW9-DW12 */
+ if (tonga_populate_temperature_scaler(hwmgr) != 0)
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate LPMLTemperatureScaler Failed !",
+ return -EINVAL);
+
+ /* DW13-DW14 */
+ if (tonga_populate_fuzzy_fan(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate Fuzzy Fan "
+ "Control parameters Failed !",
+ return -EINVAL);
+
+ /* DW15-DW18 */
+ if (tonga_populate_gnb_lpml(hwmgr))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to populate GnbLPML Failed !",
+ return -EINVAL);
+
+ /* DW20 */
+ if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
+ PP_ASSERT_WITH_CODE(
+ false,
+ "Attempt to populate BapmVddCBaseLeakage "
+ "Hi and Lo Sidd Failed !",
+ return -EINVAL);
+
+ if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
+ (uint8_t *)&smu_data->power_tune_table,
+ sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END))
+ PP_ASSERT_WITH_CODE(false,
+ "Attempt to download PmFuseTable Failed !",
+ return -EINVAL);
+ }
+ return 0;
+}
+
+static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_MCRegisters *mc_reg_table)
+{
+ const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend;
+
+ uint32_t i, j;
+
+ for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
+ if (smu_data->mc_reg_table.validflag & 1<<j) {
+ PP_ASSERT_WITH_CODE(
+ i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
+ "Index of mc_reg_table->address[] array "
+ "out of boundary",
+ return -EINVAL);
+ mc_reg_table->address[i].s0 =
+ PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
+ mc_reg_table->address[i].s1 =
+ PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
+ i++;
+ }
+ }
+
+ mc_reg_table->last = (uint8_t)i;
+
+ return 0;
+}
+
+/*convert register values from driver to SMC format */
+static void tonga_convert_mc_registers(
+ const struct tonga_mc_reg_entry *entry,
+ SMU72_Discrete_MCRegisterSet *data,
+ uint32_t num_entries, uint32_t valid_flag)
+{
+ uint32_t i, j;
+
+ for (i = 0, j = 0; j < num_entries; j++) {
+ if (valid_flag & 1<<j) {
+ data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
+ i++;
+ }
+ }
+}
+
+static int tonga_convert_mc_reg_table_entry_to_smc(
+ struct pp_hwmgr *hwmgr,
+ const uint32_t memory_clock,
+ SMU72_Discrete_MCRegisterSet *mc_reg_table_data
+ )
+{
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint32_t i = 0;
+
+ for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
+ if (memory_clock <=
+ smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
+ break;
+ }
+ }
+
+ if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
+ --i;
+
+ tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
+ mc_reg_table_data, smu_data->mc_reg_table.last,
+ smu_data->mc_reg_table.validflag);
+
+ return 0;
+}
+
+static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
+ SMU72_Discrete_MCRegisters *mc_regs)
+{
+ int result = 0;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ int res;
+ uint32_t i;
+
+ for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
+ res = tonga_convert_mc_reg_table_entry_to_smc(
+ hwmgr,
+ data->dpm_table.mclk_table.dpm_levels[i].value,
+ &mc_regs->data[i]
+ );
+
+ if (0 != res)
+ result = res;
+ }
+
+ return result;
+}
+
+static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ uint32_t address;
+ int32_t result;
+
+ if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
+ return 0;
+
+
+ memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters));
+
+ result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
+
+ if (result != 0)
+ return result;
+
+
+ address = smu_data->smu7_data.mc_reg_table_start +
+ (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
+
+ return smu7_copy_bytes_to_smc(
+ hwmgr, address,
+ (uint8_t *)&smu_data->mc_regs.data[0],
+ sizeof(SMU72_Discrete_MCRegisterSet) *
+ data->dpm_table.mclk_table.count,
+ SMC_RAM_END);
+}
+
+static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+
+ memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
+ result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize MCRegTable for the MC register addresses !",
+ return result;);
+
+ result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize MCRegTable for driver state !",
+ return result;);
+
+ return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
+ (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
+}
+
+static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ if (table_info &&
+ table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
+ table_info->cac_dtp_table->usPowerTuneDataSetID)
+ smu_data->power_tune_defaults =
+ &tonga_power_tune_data_set_array
+ [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
+ else
+ smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0];
+}
+
+static void tonga_save_default_power_profile(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ struct SMU72_Discrete_GraphicsLevel *levels =
+ data->smc_state_table.GraphicsLevel;
+ unsigned min_level = 1;
+
+ hwmgr->default_gfx_power_profile.activity_threshold =
+ be16_to_cpu(levels[0].ActivityLevel);
+ hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
+ hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
+ hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
+
+ hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
+ hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
+
+ /* Workaround compute SDMA instability: disable lowest SCLK
+ * DPM level. Optimize compute power profile: Use only highest
+ * 2 power levels (if more than 2 are available), Hysteresis:
+ * 0ms up, 5ms down
+ */
+ if (data->smc_state_table.GraphicsDpmLevelCount > 2)
+ min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
+ else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
+ min_level = 1;
+ else
+ min_level = 0;
+ hwmgr->default_compute_power_profile.min_sclk =
+ be32_to_cpu(levels[min_level].SclkFrequency);
+ hwmgr->default_compute_power_profile.up_hyst = 0;
+ hwmgr->default_compute_power_profile.down_hyst = 5;
+
+ hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
+ hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
+}
+
+static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ uint8_t i;
+ pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
+
+
+ memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
+
+ tonga_initialize_power_tune_defaults(hwmgr);
+
+ if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
+ tonga_populate_smc_voltage_tables(hwmgr, table);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
+
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StepVddc))
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
+
+ if (data->is_memory_gddr5)
+ table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
+
+ i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
+
+ if (i == 1 || i == 0)
+ table->SystemFlags |= 0x40;
+
+ if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
+ result = tonga_populate_ulv_state(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize ULV state !",
+ return result;);
+
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+ ixCG_ULV_PARAMETER, 0x40035);
+ }
+
+ result = tonga_populate_smc_link_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize Link Level !", return result);
+
+ result = tonga_populate_all_graphic_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize Graphics Level !", return result);
+
+ result = tonga_populate_all_memory_levels(hwmgr);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize Memory Level !", return result);
+
+ result = tonga_populate_smc_acpi_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize ACPI Level !", return result);
+
+ result = tonga_populate_smc_vce_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize VCE Level !", return result);
+
+ result = tonga_populate_smc_acp_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize ACP Level !", return result);
+
+ result = tonga_populate_smc_samu_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize SAMU Level !", return result);
+
+ /* Since only the initial state is completely set up at this
+ * point (the other states are just copies of the boot state) we only
+ * need to populate the ARB settings for the initial state.
+ */
+ result = tonga_program_memory_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to Write ARB settings for the initial state.",
+ return result;);
+
+ result = tonga_populate_smc_uvd_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize UVD Level !", return result);
+
+ result = tonga_populate_smc_boot_level(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to initialize Boot Level !", return result);
+
+ tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to populate BAPM Parameters !", return result);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ClockStretcher)) {
+ result = tonga_populate_clock_stretcher_data_table(hwmgr);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to populate Clock Stretcher Data Table !",
+ return result;);
+ }
+ table->GraphicsVoltageChangeEnable = 1;
+ table->GraphicsThermThrottleEnable = 1;
+ table->GraphicsInterval = 1;
+ table->VoltageInterval = 1;
+ table->ThermalInterval = 1;
+ table->TemperatureLimitHigh =
+ table_info->cac_dtp_table->usTargetOperatingTemp *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT;
+ table->TemperatureLimitLow =
+ (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
+ SMU7_Q88_FORMAT_CONVERSION_UNIT;
+ table->MemoryVoltageChangeEnable = 1;
+ table->MemoryInterval = 1;
+ table->VoltageResponseTime = 0;
+ table->PhaseResponseTime = 0;
+ table->MemoryThermThrottleEnable = 1;
+
+ /*
+ * Cail reads current link status and reports it as cap (we cannot
+ * change this due to some previous issues we had)
+ * SMC drops the link status to lowest level after enabling
+ * DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
+ * but this time Cail reads current link status which was set to low by
+ * SMC and reports it as cap to powerplay
+ * To avoid it, we set PCIeBootLinkLevel to highest dpm level
+ */
+ PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
+ "There must be 1 or more PCIE levels defined in PPTable.",
+ return -EINVAL);
+
+ table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
+
+ table->PCIeGenInterval = 1;
+
+ result = tonga_populate_vr_config(hwmgr, table);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to populate VRConfig setting !", return result);
+
+ table->ThermGpio = 17;
+ table->SclkStepSize = 0x4000;
+
+ if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
+ &gpio_pin_assignment)) {
+ table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+ } else {
+ table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+ }
+
+ if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
+ &gpio_pin_assignment)) {
+ table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+ } else {
+ table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+ }
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_Falcon_QuickTransition);
+
+ if (0) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_Falcon_QuickTransition);
+ }
+
+ if (atomctrl_get_pp_assign_pin(hwmgr,
+ THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment)) {
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ThermalOutGPIO);
+
+ table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
+
+ table->ThermOutPolarity =
+ (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
+ (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1 : 0;
+
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
+
+ /* if required, combine VRHot/PCC with thermal out GPIO*/
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot) &&
+ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_CombinePCCWithThermalSignal)){
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
+ }
+ } else {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ThermalOutGPIO);
+
+ table->ThermOutGpio = 17;
+ table->ThermOutPolarity = 1;
+ table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
+ }
+
+ for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++)
+ table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
+
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
+ CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
+ CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
+ CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
+ CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
+
+ /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
+ (uint8_t *)&(table->SystemFlags),
+ sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController),
+ SMC_RAM_END);
+
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to upload dpm data to SMC memory !", return result;);
+
+ result = tonga_init_arb_table_index(hwmgr);
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to upload arb data to SMC memory !", return result);
+
+ tonga_populate_pm_fuses(hwmgr);
+ PP_ASSERT_WITH_CODE((!result),
+ "Failed to populate initialize pm fuses !", return result);
+
+ result = tonga_populate_initial_mc_reg_table(hwmgr);
+ PP_ASSERT_WITH_CODE((!result),
+ "Failed to populate initialize MC Reg table !", return result);
+
+ tonga_save_default_power_profile(hwmgr);
+
+ return 0;
+}
+
+static int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
+ uint32_t duty100;
+ uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
+ uint16_t fdo_min, slope1, slope2;
+ uint32_t reference_clock;
+ int res;
+ uint64_t tmp64;
+
+ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl))
+ return 0;
+
+ if (hwmgr->thermal_controller.fanInfo.bNoFan) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ if (0 == smu_data->smu7_data.fan_table_start) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC,
+ CG_FDO_CTRL1, FMAX_DUTY100);
+
+ if (0 == duty100) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl);
+ return 0;
+ }
+
+ tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
+ do_div(tmp64, 10000);
+ fdo_min = (uint16_t)tmp64;
+
+ t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
+ hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
+ t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
+ hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
+
+ pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
+ hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
+ pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
+ hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
+
+ slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
+ slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
+
+ fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
+ fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
+ fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
+
+ fan_table.Slope1 = cpu_to_be16(slope1);
+ fan_table.Slope2 = cpu_to_be16(slope2);
+
+ fan_table.FdoMin = cpu_to_be16(fdo_min);
+
+ fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
+
+ fan_table.HystUp = cpu_to_be16(1);
+
+ fan_table.HystSlope = cpu_to_be16(1);
+
+ fan_table.TempRespLim = cpu_to_be16(5);
+
+ reference_clock = smu7_get_xclk(hwmgr);
+
+ fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
+
+ fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
+
+ fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
+
+ fan_table.FanControl_GL_Flag = 1;
+
+ res = smu7_copy_bytes_to_smc(hwmgr,
+ smu_data->smu7_data.fan_table_start,
+ (uint8_t *)&fan_table,
+ (uint32_t)sizeof(fan_table),
+ SMC_RAM_END);
+
+ return 0;
+}
+
+
+static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (data->need_update_smu7_dpm_table &
+ (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
+ return tonga_program_memory_timing_parameters(hwmgr);
+
+ return 0;
+}
+
+static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+
+ int result = 0;
+ uint32_t low_sclk_interrupt_threshold = 0;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkThrottleLowNotification)
+ && (hwmgr->gfx_arbiter.sclk_threshold !=
+ data->low_sclk_interrupt_threshold)) {
+ data->low_sclk_interrupt_threshold =
+ hwmgr->gfx_arbiter.sclk_threshold;
+ low_sclk_interrupt_threshold =
+ data->low_sclk_interrupt_threshold;
+
+ CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
+
+ result = smu7_copy_bytes_to_smc(
+ hwmgr,
+ smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU72_Discrete_DpmTable,
+ LowSclkInterruptThreshold),
+ (uint8_t *)&low_sclk_interrupt_threshold,
+ sizeof(uint32_t),
+ SMC_RAM_END);
+ }
+
+ result = tonga_update_and_upload_mc_reg_table(hwmgr);
+
+ PP_ASSERT_WITH_CODE((!result),
+ "Failed to upload MC reg table !",
+ return result);
+
+ result = tonga_program_mem_timing_parameters(hwmgr);
+ PP_ASSERT_WITH_CODE((result == 0),
+ "Failed to program memory timing parameters !",
+ );
+
+ return result;
+}
+
+static uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
+{
+ switch (type) {
+ case SMU_SoftRegisters:
+ switch (member) {
+ case HandshakeDisables:
+ return offsetof(SMU72_SoftRegisters, HandshakeDisables);
+ case VoltageChangeTimeout:
+ return offsetof(SMU72_SoftRegisters, VoltageChangeTimeout);
+ case AverageGraphicsActivity:
+ return offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
+ case PreVBlankGap:
+ return offsetof(SMU72_SoftRegisters, PreVBlankGap);
+ case VBlankTimeout:
+ return offsetof(SMU72_SoftRegisters, VBlankTimeout);
+ case UcodeLoadStatus:
+ return offsetof(SMU72_SoftRegisters, UcodeLoadStatus);
+ case DRAM_LOG_ADDR_H:
+ return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_H);
+ case DRAM_LOG_ADDR_L:
+ return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_L);
+ case DRAM_LOG_PHY_ADDR_H:
+ return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+ case DRAM_LOG_PHY_ADDR_L:
+ return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+ case DRAM_LOG_BUFF_SIZE:
+ return offsetof(SMU72_SoftRegisters, DRAM_LOG_BUFF_SIZE);
+ }
+ case SMU_Discrete_DpmTable:
+ switch (member) {
+ case UvdBootLevel:
+ return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
+ case VceBootLevel:
+ return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
+ case SamuBootLevel:
+ return offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
+ case LowSclkInterruptThreshold:
+ return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
+ }
+ }
+ pr_warn("can't get the offset of type %x member %x\n", type, member);
+ return 0;
+}
+
+static uint32_t tonga_get_mac_definition(uint32_t value)
+{
+ switch (value) {
+ case SMU_MAX_LEVELS_GRAPHICS:
+ return SMU72_MAX_LEVELS_GRAPHICS;
+ case SMU_MAX_LEVELS_MEMORY:
+ return SMU72_MAX_LEVELS_MEMORY;
+ case SMU_MAX_LEVELS_LINK:
+ return SMU72_MAX_LEVELS_LINK;
+ case SMU_MAX_ENTRIES_SMIO:
+ return SMU72_MAX_ENTRIES_SMIO;
+ case SMU_MAX_LEVELS_VDDC:
+ return SMU72_MAX_LEVELS_VDDC;
+ case SMU_MAX_LEVELS_VDDGFX:
+ return SMU72_MAX_LEVELS_VDDGFX;
+ case SMU_MAX_LEVELS_VDDCI:
+ return SMU72_MAX_LEVELS_VDDCI;
+ case SMU_MAX_LEVELS_MVDD:
+ return SMU72_MAX_LEVELS_MVDD;
+ }
+ pr_warn("can't get the mac value %x\n", value);
+
+ return 0;
+}
+
+static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+ smu_data->smc_state_table.UvdBootLevel = 0;
+ if (table_info->mm_dep_table->count > 0)
+ smu_data->smc_state_table.UvdBootLevel =
+ (uint8_t) (table_info->mm_dep_table->count - 1);
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0x00FFFFFF;
+ mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC,
+ mm_boot_level_offset, mm_boot_level_value);
+
+ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDDPM) ||
+ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_UVDDPM_SetEnabledMask,
+ (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
+ return 0;
+}
+
+static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data =
+ (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+
+
+ smu_data->smc_state_table.VceBootLevel =
+ (uint8_t) (table_info->mm_dep_table->count - 1);
+
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0xFF00FFFF;
+ mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_VCEDPM_SetEnabledMask,
+ (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
+ return 0;
+}
+
+static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
+{
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ uint32_t mm_boot_level_offset, mm_boot_level_value;
+
+ smu_data->smc_state_table.SamuBootLevel = 0;
+ mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
+
+ mm_boot_level_offset /= 4;
+ mm_boot_level_offset *= 4;
+ mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset);
+ mm_boot_level_value &= 0xFFFFFF00;
+ mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
+ cgs_write_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_StablePState))
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SAMUDPM_SetEnabledMask,
+ (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
+ return 0;
+}
+
+static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
+{
+ switch (type) {
+ case SMU_UVD_TABLE:
+ tonga_update_uvd_smc_table(hwmgr);
+ break;
+ case SMU_VCE_TABLE:
+ tonga_update_vce_smc_table(hwmgr);
+ break;
+ case SMU_SAMU_TABLE:
+ tonga_update_samu_smc_table(hwmgr);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+
+ uint32_t tmp;
+ int result;
+ bool error = false;
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, DpmTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.dpm_table_start = tmp;
+
+ error |= (result != 0);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, SoftRegisters),
+ &tmp, SMC_RAM_END);
+
+ if (!result) {
+ data->soft_regs_start = tmp;
+ smu_data->smu7_data.soft_regs_start = tmp;
+ }
+
+ error |= (result != 0);
+
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, mcRegisterTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.mc_reg_table_start = tmp;
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, FanTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.fan_table_start = tmp;
+
+ error |= (result != 0);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ smu_data->smu7_data.arb_table_start = tmp;
+
+ error |= (result != 0);
+
+ result = smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, Version),
+ &tmp, SMC_RAM_END);
+
+ if (!result)
+ hwmgr->microcode_version_info.SMC = tmp;
+
+ error |= (result != 0);
+
+ return error ? 1 : 0;
+}
+
+/*---------------------------MC----------------------------*/
+
+static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
+{
+ return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
+}
+
+static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
+{
+ bool result = true;
+
+ switch (in_reg) {
+ case mmMC_SEQ_RAS_TIMING:
+ *out_reg = mmMC_SEQ_RAS_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_DLL_STBY:
+ *out_reg = mmMC_SEQ_DLL_STBY_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CMD0:
+ *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CMD1:
+ *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
+ break;
+
+ case mmMC_SEQ_G5PDX_CTRL:
+ *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
+ break;
+
+ case mmMC_SEQ_CAS_TIMING:
+ *out_reg = mmMC_SEQ_CAS_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_MISC_TIMING:
+ *out_reg = mmMC_SEQ_MISC_TIMING_LP;
+ break;
+
+ case mmMC_SEQ_MISC_TIMING2:
+ *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
+ break;
+
+ case mmMC_SEQ_PMG_DVS_CMD:
+ *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
+ break;
+
+ case mmMC_SEQ_PMG_DVS_CTL:
+ *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
+ break;
+
+ case mmMC_SEQ_RD_CTL_D0:
+ *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
+ break;
+
+ case mmMC_SEQ_RD_CTL_D1:
+ *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_D0:
+ *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_D1:
+ *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
+ break;
+
+ case mmMC_PMG_CMD_EMRS:
+ *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS1:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
+ break;
+
+ case mmMC_SEQ_PMG_TIMING:
+ *out_reg = mmMC_SEQ_PMG_TIMING_LP;
+ break;
+
+ case mmMC_PMG_CMD_MRS2:
+ *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
+ break;
+
+ case mmMC_SEQ_WR_CTL_2:
+ *out_reg = mmMC_SEQ_WR_CTL_2_LP;
+ break;
+
+ default:
+ result = false;
+ break;
+ }
+
+ return result;
+}
+
+static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table)
+{
+ uint32_t i;
+ uint16_t address;
+
+ for (i = 0; i < table->last; i++) {
+ table->mc_reg_address[i].s0 =
+ tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
+ &address) ?
+ address :
+ table->mc_reg_address[i].s1;
+ }
+ return 0;
+}
+
+static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
+ struct tonga_mc_reg_table *ni_table)
+{
+ uint8_t i, j;
+
+ PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ for (i = 0; i < table->last; i++)
+ ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
+
+ ni_table->last = table->last;
+
+ for (i = 0; i < table->num_entries; i++) {
+ ni_table->mc_reg_table_entry[i].mclk_max =
+ table->mc_reg_table_entry[i].mclk_max;
+ for (j = 0; j < table->last; j++) {
+ ni_table->mc_reg_table_entry[i].mc_data[j] =
+ table->mc_reg_table_entry[i].mc_data[j];
+ }
+ }
+
+ ni_table->num_entries = table->num_entries;
+
+ return 0;
+}
+
+static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ struct tonga_mc_reg_table *table)
+{
+ uint8_t i, j, k;
+ uint32_t temp_reg;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ for (i = 0, j = table->last; i < table->last; i++) {
+ PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ switch (table->mc_reg_address[i].s1) {
+
+ case mmMC_SEQ_MISC1:
+ temp_reg = cgs_read_register(hwmgr->device,
+ mmMC_PMG_CMD_EMRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ ((temp_reg & 0xffff0000)) |
+ ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (temp_reg & 0xffff0000) |
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+
+ if (!data->is_memory_gddr5)
+ table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+
+ if (!data->is_memory_gddr5) {
+ table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
+ table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
+ for (k = 0; k < table->num_entries; k++)
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ }
+
+ break;
+
+ case mmMC_SEQ_RESERVE_M:
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
+ for (k = 0; k < table->num_entries; k++) {
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (temp_reg & 0xffff0000) |
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+ }
+ j++;
+ PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+ break;
+
+ default:
+ break;
+ }
+
+ }
+
+ table->last = j;
+
+ return 0;
+}
+
+static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)
+{
+ uint8_t i, j;
+
+ for (i = 0; i < table->last; i++) {
+ for (j = 1; j < table->num_entries; j++) {
+ if (table->mc_reg_table_entry[j-1].mc_data[i] !=
+ table->mc_reg_table_entry[j].mc_data[i]) {
+ table->validflag |= (1<<i);
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
+ pp_atomctrl_mc_reg_table *table;
+ struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table;
+ uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
+
+ table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
+
+ if (table == NULL)
+ return -ENOMEM;
+
+ /* Program additional LP registers that are no longer programmed by VBIOS */
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP,
+ cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP,
+ cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP,
+ cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP,
+ cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
+ cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
+ cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
+
+ memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
+
+ result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
+
+ if (!result)
+ result = tonga_copy_vbios_smc_reg_table(table, ni_table);
+
+ if (!result) {
+ tonga_set_s0_mc_reg_index(ni_table);
+ result = tonga_set_mc_special_registers(hwmgr, ni_table);
+ }
+
+ if (!result)
+ tonga_set_valid_flag(ni_table);
+
+ kfree(table);
+
+ return result;
+}
+
+static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
+{
+ return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
+ ? true : false;
+}
+
+static int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
+ struct amd_pp_profile *request)
+{
+ struct tonga_smumgr *smu_data = (struct tonga_smumgr *)
+ (hwmgr->smu_backend);
+ struct SMU72_Discrete_GraphicsLevel *levels =
+ smu_data->smc_state_table.GraphicsLevel;
+ uint32_t array = smu_data->smu7_data.dpm_table_start +
+ offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
+ uint32_t array_size = sizeof(struct SMU72_Discrete_GraphicsLevel) *
+ SMU72_MAX_LEVELS_GRAPHICS;
+ uint32_t i;
+
+ for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+ levels[i].ActivityLevel =
+ cpu_to_be16(request->activity_threshold);
+ levels[i].EnabledForActivity = 1;
+ levels[i].UpHyst = request->up_hyst;
+ levels[i].DownHyst = request->down_hyst;
+ }
+
+ return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
+ array_size, SMC_RAM_END);
+}
+
const struct pp_smumgr_func tonga_smu_funcs = {
.smu_init = &tonga_smu_init,
.smu_fini = &smu7_smu_fini,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
index 8c4f761..5d70a00 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
@@ -25,8 +25,26 @@
#define _TONGA_SMUMGR_H_
#include "smu72_discrete.h"
-
#include "smu7_smumgr.h"
+#include "smu72.h"
+
+
+#define ASICID_IS_TONGA_P(wDID, bRID) \
+ (((wDID == 0x6930) && ((bRID == 0xF0) || (bRID == 0xF1) || (bRID == 0xFF))) \
+ || ((wDID == 0x6920) && ((bRID == 0) || (bRID == 1))))
+
+struct tonga_pt_defaults {
+ uint8_t svi_load_line_en;
+ uint8_t svi_load_line_vddC;
+ uint8_t tdc_vddc_throttle_release_limit_perc;
+ uint8_t tdc_mawt;
+ uint8_t tdc_waterfall_ctl;
+ uint8_t dte_ambient_temp_base;
+ uint32_t display_cac;
+ uint32_t bapm_temp_gradient;
+ uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
+ uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
+};
struct tonga_mc_reg_entry {
uint32_t mclk_max;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 408514c..2f979fb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -53,20 +53,20 @@
#define smnMP0_FW_INTF 0x3010104
#define smnMP1_PUB_CTRL 0x3010b14
-static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr)
+static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{
uint32_t mp1_fw_flags, reg;
reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
- cgs_write_register(smumgr->device, reg,
+ cgs_write_register(hwmgr->device, reg,
(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
reg = soc15_get_register_offset(NBIF_HWID, 0,
mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
- mp1_fw_flags = cgs_read_register(smumgr->device, reg);
+ mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
return true;
@@ -80,20 +80,20 @@ static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr)
* @param smumgr the address of the powerplay hardware manager.
* @return TRUE SMC has responded, FALSE otherwise.
*/
-static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
+static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr)
{
uint32_t reg;
- if (!vega10_is_smc_ram_running(smumgr))
+ if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- smum_wait_for_register_unequal(smumgr, reg,
+ phm_wait_for_register_unequal(hwmgr, reg,
0, MP1_C2PMSG_90__CONTENT_MASK);
- return cgs_read_register(smumgr->device, reg);
+ return cgs_read_register(hwmgr->device, reg);
}
/*
@@ -102,43 +102,43 @@ static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
* @param msg the message to send.
* @return Always return 0.
*/
-int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
+int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg)
{
uint32_t reg;
- if (!vega10_is_smc_ram_running(smumgr))
+ if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
- cgs_write_register(smumgr->device, reg, msg);
+ cgs_write_register(hwmgr->device, reg, msg);
return 0;
}
/*
* Send a message to the SMC, and wait for its response.
- * @param smumgr the address of the powerplay hardware manager.
+ * @param hwmgr the address of the powerplay hardware manager.
* @param msg the message to send.
* @return Always return 0.
*/
-int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
uint32_t reg;
- if (!vega10_is_smc_ram_running(smumgr))
+ if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL;
- vega10_wait_for_response(smumgr);
+ vega10_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- cgs_write_register(smumgr->device, reg, 0);
+ cgs_write_register(hwmgr->device, reg, 0);
- vega10_send_msg_to_smc_without_waiting(smumgr, msg);
+ vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
- if (vega10_wait_for_response(smumgr) != 1)
+ if (vega10_wait_for_response(hwmgr) != 1)
pr_err("Failed to send message: 0x%x\n", msg);
return 0;
@@ -146,32 +146,32 @@ int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
/*
* Send a message to the SMC with parameter
- * @param smumgr: the address of the powerplay hardware manager.
+ * @param hwmgr: the address of the powerplay hardware manager.
* @param msg: the message to send.
* @param parameter: the parameter to send
* @return Always return 0.
*/
-int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
+int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter)
{
uint32_t reg;
- if (!vega10_is_smc_ram_running(smumgr))
+ if (!vega10_is_smc_ram_running(hwmgr))
return -EINVAL;
- vega10_wait_for_response(smumgr);
+ vega10_wait_for_response(hwmgr);
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- cgs_write_register(smumgr->device, reg, 0);
+ cgs_write_register(hwmgr->device, reg, 0);
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
- cgs_write_register(smumgr->device, reg, parameter);
+ cgs_write_register(hwmgr->device, reg, parameter);
- vega10_send_msg_to_smc_without_waiting(smumgr, msg);
+ vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
- if (vega10_wait_for_response(smumgr) != 1)
+ if (vega10_wait_for_response(hwmgr) != 1)
pr_err("Failed to send message: 0x%x\n", msg);
return 0;
@@ -180,51 +180,51 @@ int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
/*
* Send a message to the SMC with parameter, do not wait for response
- * @param smumgr: the address of the powerplay hardware manager.
+ * @param hwmgr: the address of the powerplay hardware manager.
* @param msg: the message to send.
* @param parameter: the parameter to send
* @return The response that came from the SMC.
*/
int vega10_send_msg_to_smc_with_parameter_without_waiting(
- struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
+ struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
{
uint32_t reg;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
- cgs_write_register(smumgr->device, reg, parameter);
+ cgs_write_register(hwmgr->device, reg, parameter);
- return vega10_send_msg_to_smc_without_waiting(smumgr, msg);
+ return vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
}
/*
* Retrieve an argument from SMC.
- * @param smumgr the address of the powerplay hardware manager.
+ * @param hwmgr the address of the powerplay hardware manager.
* @param arg pointer to store the argument from SMC.
* @return Always return 0.
*/
-int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
+int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
{
uint32_t reg;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
- *arg = cgs_read_register(smumgr->device, reg);
+ *arg = cgs_read_register(hwmgr->device, reg);
return 0;
}
/*
* Copy table from SMC into driver FB
- * @param smumgr the address of the SMC manager
+ * @param hwmgr the address of the HW manager
* @param table_id the driver's table ID to copy from
*/
-int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
+int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id)
{
struct vega10_smumgr *priv =
- (struct vega10_smumgr *)(smumgr->backend);
+ (struct vega10_smumgr *)(hwmgr->smu_backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL);
@@ -232,16 +232,16 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
"Invalid SMU Table version!", return -EINVAL);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
"Invalid SMU Table Length!", return -EINVAL);
- PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
- PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL);
- PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableSmu2Dram,
priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
@@ -255,14 +255,14 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
/*
* Copy table from Driver FB into SMC
- * @param smumgr the address of the SMC manager
+ * @param hwmgr the address of the HW manager
* @param table_id the table to copy from
*/
-int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
+int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id)
{
struct vega10_smumgr *priv =
- (struct vega10_smumgr *)(smumgr->backend);
+ (struct vega10_smumgr *)(hwmgr->smu_backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
"Invalid SMU Table ID!", return -EINVAL);
@@ -274,17 +274,17 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
memcpy(priv->smu_tables.entry[table_id].table, table,
priv->smu_tables.entry[table_id].size);
- PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
return -EINVAL;);
- PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
return -EINVAL);
- PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
+ PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_TransferTableDram2Smu,
priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
@@ -293,87 +293,87 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
return 0;
}
-int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
+int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
{
PP_ASSERT_WITH_CODE(avfs_table,
"No access to SMC AVFS Table",
return -EINVAL);
- return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE);
+ return vega10_copy_table_from_smc(hwmgr, avfs_table, AVFSTABLE);
}
-int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
+int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
{
PP_ASSERT_WITH_CODE(avfs_table,
"No access to SMC AVFS Table",
return -EINVAL);
- return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE);
+ return vega10_copy_table_to_smc(hwmgr, avfs_table, AVFSTABLE);
}
-int vega10_enable_smc_features(struct pp_smumgr *smumgr,
+int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
bool enable, uint32_t feature_mask)
{
int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
PPSMC_MSG_DisableSmuFeatures;
- return vega10_send_msg_to_smc_with_parameter(smumgr,
+ return vega10_send_msg_to_smc_with_parameter(hwmgr,
msg, feature_mask);
}
-int vega10_get_smc_features(struct pp_smumgr *smumgr,
+int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
uint32_t *features_enabled)
{
if (features_enabled == NULL)
return -EINVAL;
- if (!vega10_send_msg_to_smc(smumgr,
+ if (!vega10_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetEnabledSmuFeatures)) {
- vega10_read_arg_from_smc(smumgr, features_enabled);
+ vega10_read_arg_from_smc(hwmgr, features_enabled);
return 0;
}
return -EINVAL;
}
-int vega10_set_tools_address(struct pp_smumgr *smumgr)
+int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
{
struct vega10_smumgr *priv =
- (struct vega10_smumgr *)(smumgr->backend);
+ (struct vega10_smumgr *)(hwmgr->smu_backend);
if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
- if (!vega10_send_msg_to_smc_with_parameter(smumgr,
+ if (!vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetToolsDramAddrHigh,
priv->smu_tables.entry[TOOLSTABLE].table_addr_high))
- vega10_send_msg_to_smc_with_parameter(smumgr,
+ vega10_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetToolsDramAddrLow,
priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
}
return 0;
}
-static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
+static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
{
uint32_t smc_driver_if_version;
struct cgs_system_info sys_info = {0};
uint32_t dev_id;
uint32_t rev_id;
- PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr,
+ PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetDriverIfVersion),
"Attempt to get SMC IF Version Number Failed!",
return -EINVAL);
- vega10_read_arg_from_smc(smumgr, &smc_driver_if_version);
+ vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version);
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
- cgs_query_system_info(smumgr->device, &sys_info);
+ cgs_query_system_info(hwmgr->device, &sys_info);
dev_id = (uint32_t)sys_info.value;
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
- cgs_query_system_info(smumgr->device, &sys_info);
+ cgs_query_system_info(hwmgr->device, &sys_info);
rev_id = (uint32_t)sys_info.value;
if (!((dev_id == 0x687f) &&
@@ -392,7 +392,7 @@ static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
return 0;
}
-static int vega10_smu_init(struct pp_smumgr *smumgr)
+static int vega10_smu_init(struct pp_hwmgr *hwmgr)
{
struct vega10_smumgr *priv;
uint64_t mc_addr;
@@ -401,7 +401,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
int ret;
struct cgs_firmware_info info = {0};
- ret = cgs_get_firmware_info(smumgr->device,
+ ret = cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
&info);
if (ret || !info.kptr)
@@ -412,10 +412,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
if (!priv)
return -ENOMEM;
- smumgr->backend = priv;
+ hwmgr->smu_backend = priv;
/* allocate space for pptable */
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
sizeof(PPTable_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE,
@@ -425,8 +425,8 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for pptable.",
- kfree(smumgr->backend);
- cgs_free_gpu_mem(smumgr->device,
+ kfree(hwmgr->smu_backend);
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle);
return -EINVAL);
@@ -441,7 +441,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
priv->smu_tables.entry[PPTABLE].handle = handle;
/* allocate space for watermarks table */
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
sizeof(Watermarks_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE,
@@ -451,10 +451,10 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for wmtable.",
- kfree(smumgr->backend);
- cgs_free_gpu_mem(smumgr->device,
+ kfree(hwmgr->smu_backend);
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle);
return -EINVAL);
@@ -469,7 +469,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
priv->smu_tables.entry[WMTABLE].handle = handle;
/* allocate space for AVFS table */
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
sizeof(AvfsTable_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE,
@@ -479,12 +479,12 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for avfs table.",
- kfree(smumgr->backend);
- cgs_free_gpu_mem(smumgr->device,
+ kfree(hwmgr->smu_backend);
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle);
return -EINVAL);
@@ -500,7 +500,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
tools_size = 0x19000;
if (tools_size) {
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
tools_size,
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE,
@@ -522,7 +522,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
}
/* allocate space for AVFS Fuse table */
- smu_allocate_memory(smumgr->device,
+ smu_allocate_memory(hwmgr->device,
sizeof(AvfsFuseOverride_t),
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
PAGE_SIZE,
@@ -532,16 +532,16 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(kaddr,
"[vega10_smu_init] Out of memory for avfs fuse table.",
- kfree(smumgr->backend);
- cgs_free_gpu_mem(smumgr->device,
+ kfree(hwmgr->smu_backend);
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)handle);
return -EINVAL);
@@ -558,36 +558,36 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
return 0;
}
-static int vega10_smu_fini(struct pp_smumgr *smumgr)
+static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
{
struct vega10_smumgr *priv =
- (struct vega10_smumgr *)(smumgr->backend);
+ (struct vega10_smumgr *)(hwmgr->smu_backend);
if (priv) {
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
if (priv->smu_tables.entry[TOOLSTABLE].table)
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
- cgs_free_gpu_mem(smumgr->device,
+ cgs_free_gpu_mem(hwmgr->device,
(cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle);
- kfree(smumgr->backend);
- smumgr->backend = NULL;
+ kfree(hwmgr->smu_backend);
+ hwmgr->smu_backend = NULL;
}
return 0;
}
-static int vega10_start_smu(struct pp_smumgr *smumgr)
+static int vega10_start_smu(struct pp_hwmgr *hwmgr)
{
- PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr),
+ PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
"Failed to verify SMC interface!",
return -EINVAL);
- vega10_set_tools_address(smumgr);
+ vega10_set_tools_address(hwmgr);
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
index 821425c..0695455 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
@@ -52,19 +52,19 @@ struct vega10_smumgr {
struct smu_table_array smu_tables;
};
-int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
-int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
+int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
+int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id);
-int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
+int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id);
-int vega10_enable_smc_features(struct pp_smumgr *smumgr,
+int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
bool enable, uint32_t feature_mask);
-int vega10_get_smc_features(struct pp_smumgr *smumgr,
+int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
uint32_t *features_enabled);
-int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table);
-int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table);
+int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
+int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
-int vega10_set_tools_address(struct pp_smumgr *smumgr);
+int vega10_set_tools_address(struct pp_hwmgr *hwmgr);
#endif
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index a25f6c7..92ec663 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -133,6 +133,7 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
entity->rq = rq;
entity->sched = sched;
+ spin_lock_init(&entity->rq_lock);
spin_lock_init(&entity->queue_lock);
r = kfifo_alloc(&entity->job_queue, jobs * sizeof(void *), GFP_KERNEL);
if (r)
@@ -204,18 +205,38 @@ static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity)
void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
struct amd_sched_entity *entity)
{
- struct amd_sched_rq *rq = entity->rq;
+ int r;
if (!amd_sched_entity_is_initialized(sched, entity))
return;
-
/**
* The client will not queue more IBs during this fini, consume existing
- * queued IBs
+ * queued IBs or discard them on SIGKILL
*/
- wait_event(sched->job_scheduled, amd_sched_entity_is_idle(entity));
+ if ((current->flags & PF_SIGNALED) && current->exit_code == SIGKILL)
+ r = -ERESTARTSYS;
+ else
+ r = wait_event_killable(sched->job_scheduled,
+ amd_sched_entity_is_idle(entity));
+ amd_sched_entity_set_rq(entity, NULL);
+ if (r) {
+ struct amd_sched_job *job;
- amd_sched_rq_remove_entity(rq, entity);
+ /* Park the kernel for a moment to make sure it isn't processing
+ * our enity.
+ */
+ kthread_park(sched->thread);
+ kthread_unpark(sched->thread);
+ while (kfifo_out(&entity->job_queue, &job, sizeof(job))) {
+ struct amd_sched_fence *s_fence = job->s_fence;
+ amd_sched_fence_scheduled(s_fence);
+ dma_fence_set_error(&s_fence->finished, -ESRCH);
+ amd_sched_fence_finished(s_fence);
+ dma_fence_put(&s_fence->finished);
+ sched->ops->free_job(job);
+ }
+
+ }
kfifo_free(&entity->job_queue);
}
@@ -236,6 +257,24 @@ static void amd_sched_entity_clear_dep(struct dma_fence *f, struct dma_fence_cb
dma_fence_put(f);
}
+void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
+ struct amd_sched_rq *rq)
+{
+ if (entity->rq == rq)
+ return;
+
+ spin_lock(&entity->rq_lock);
+
+ if (entity->rq)
+ amd_sched_rq_remove_entity(entity->rq, entity);
+
+ entity->rq = rq;
+ if (rq)
+ amd_sched_rq_add_entity(rq, entity);
+
+ spin_unlock(&entity->rq_lock);
+}
+
bool amd_sched_dependency_optimized(struct dma_fence* fence,
struct amd_sched_entity *entity)
{
@@ -293,7 +332,7 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity)
}
static struct amd_sched_job *
-amd_sched_entity_pop_job(struct amd_sched_entity *entity)
+amd_sched_entity_peek_job(struct amd_sched_entity *entity)
{
struct amd_gpu_scheduler *sched = entity->sched;
struct amd_sched_job *sched_job;
@@ -333,14 +372,15 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
/* first job wakes up scheduler */
if (first) {
/* Add the entity to the run queue */
+ spin_lock(&entity->rq_lock);
amd_sched_rq_add_entity(entity->rq, entity);
+ spin_unlock(&entity->rq_lock);
amd_sched_wakeup(sched);
}
return added;
}
-/* job_finish is called after hw fence signaled, and
- * the job had already been deleted from ring_mirror_list
+/* job_finish is called after hw fence signaled
*/
static void amd_sched_job_finish(struct work_struct *work)
{
@@ -366,6 +406,7 @@ static void amd_sched_job_finish(struct work_struct *work)
schedule_delayed_work(&next->work_tdr, sched->timeout);
}
spin_unlock(&sched->job_list_lock);
+ dma_fence_put(&s_job->s_fence->finished);
sched->ops->free_job(s_job);
}
@@ -381,6 +422,9 @@ static void amd_sched_job_begin(struct amd_sched_job *s_job)
{
struct amd_gpu_scheduler *sched = s_job->sched;
+ dma_fence_add_callback(&s_job->s_fence->finished, &s_job->finish_cb,
+ amd_sched_job_finish_cb);
+
spin_lock(&sched->job_list_lock);
list_add_tail(&s_job->node, &sched->ring_mirror_list);
if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
@@ -473,8 +517,6 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
struct amd_sched_entity *entity = sched_job->s_entity;
trace_amd_sched_job(sched_job);
- dma_fence_add_callback(&sched_job->s_fence->finished, &sched_job->finish_cb,
- amd_sched_job_finish_cb);
wait_event(entity->sched->job_scheduled,
amd_sched_entity_in(sched_job));
}
@@ -545,6 +587,7 @@ static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb)
container_of(cb, struct amd_sched_fence, cb);
struct amd_gpu_scheduler *sched = s_fence->sched;
+ dma_fence_get(&s_fence->finished);
atomic_dec(&sched->hw_rq_count);
amd_sched_fence_finished(s_fence);
@@ -585,7 +628,7 @@ static int amd_sched_main(void *param)
if (!entity)
continue;
- sched_job = amd_sched_entity_pop_job(entity);
+ sched_job = amd_sched_entity_peek_job(entity);
if (!sched_job)
continue;
@@ -596,6 +639,7 @@ static int amd_sched_main(void *param)
fence = sched->ops->run_job(sched_job);
amd_sched_fence_scheduled(s_fence);
+
if (fence) {
s_fence->parent = dma_fence_get(fence);
r = dma_fence_add_callback(fence, &s_fence->cb,
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
index f9d8f28..52c8e54 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
@@ -39,6 +39,7 @@ struct amd_sched_rq;
struct amd_sched_entity {
struct list_head list;
struct amd_sched_rq *rq;
+ spinlock_t rq_lock;
struct amd_gpu_scheduler *sched;
spinlock_t queue_lock;
@@ -115,9 +116,14 @@ struct amd_sched_backend_ops {
enum amd_sched_priority {
AMD_SCHED_PRIORITY_MIN,
- AMD_SCHED_PRIORITY_NORMAL = AMD_SCHED_PRIORITY_MIN,
+ AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN,
+ AMD_SCHED_PRIORITY_NORMAL,
+ AMD_SCHED_PRIORITY_HIGH_SW,
+ AMD_SCHED_PRIORITY_HIGH_HW,
AMD_SCHED_PRIORITY_KERNEL,
- AMD_SCHED_PRIORITY_MAX
+ AMD_SCHED_PRIORITY_MAX,
+ AMD_SCHED_PRIORITY_INVALID = -1,
+ AMD_SCHED_PRIORITY_UNSET = -2
};
/**
@@ -150,6 +156,8 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
struct amd_sched_entity *entity);
void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
+void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
+ struct amd_sched_rq *rq);
int amd_sched_fence_slab_init(void);
void amd_sched_fence_slab_fini(void);
@@ -167,4 +175,11 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
bool amd_sched_dependency_optimized(struct dma_fence* fence,
struct amd_sched_entity *entity);
void amd_sched_job_kickout(struct amd_sched_job *s_job);
+
+static inline enum amd_sched_priority
+amd_sched_get_job_priority(struct amd_sched_job *job)
+{
+ return (job->s_entity->rq - job->sched->sched_rq);
+}
+
#endif