| commit | e651262477c6d8cba79dffc1a6039da43d9c96b0 | [log] [tgz] |
|---|---|---|
| author | Len Brown <len.brown@intel.com> | Wed Jan 11 23:17:24 2017 -0500 |
| committer | Len Brown <len.brown@intel.com> | Wed Mar 01 00:14:03 2017 -0500 |
| tree | 75628064980e6094ef835f540196b01d64558d66 | |
| parent | 710f273ba96182fd93ee8540ae06583c7d889d7c [diff] |
tools/power turbostat: further decode MSR_IA32_MISC_ENABLE Decode MISC_ENABLE.NO_TURBO, also use the #defines in msr-index.h for decoding this register cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO) Although it is not architectural, decode also MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9). documented to be present on: Core, P4, Intel-Xeon reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec. Signed-off-by: Len Brown <len.brown@intel.com>