DT: net: document Ethernet bindings in one place

This patch is an attempt to gather the Ethernet related bindings in one file,
like it's done in the MMC and some other subsystems. It should save some of
the trouble of documenting several properties over and over in each binding
document, instead only making reference to the main file.

I have used the Embedded Power Architecture(TM) Platform Requirements (ePAPR)
standard as a base for the properties description, also documenting some ad-hoc
properties that have been introduced over time despite having direct analogs in
ePAPR.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt b/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt
index 88c3d04..88fb958 100644
--- a/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt
+++ b/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt
@@ -7,9 +7,7 @@
 - interrupts: must be two cells, the first cell is the general purpose
   interrupt line, while the second cell is the interrupt for the ring
   RX and TX queues operating in ring mode
-- phy-mode: String, operation mode of the PHY interface. Supported values are
-  "mii", "rgmii", "rgmii-txid", "rev-mii", "moca". Analogous to ePAPR
-  "phy-connection-type" values
+- phy-mode: see ethernet.txt file in the same directory
 - address-cells: should be 1
 - size-cells: should be 1
 
@@ -20,9 +18,8 @@
 - clock-names: When provided, names of the functional clock phandles, first
   name should be "enet" and second should be "enet-wol".
 
-- phy-handle: A phandle to a phy node defining the PHY address (as the reg
-  property, a single integer), used to describe configurations where a PHY
-  (internal or external) is used.
+- phy-handle: See ethernet.txt file in the same directory; used to describe
+  configurations where a PHY (internal or external) is used.
 
 - fixed-link: When the GENET interface is connected to a MoCA hardware block or
   when operating in a RGMII to RGMII type of connection, or when the MDIO bus is