ALSA: dice: avoid superflous write at bus reset
When a bus reset happens, the enable register is automatically cleared,
so we do not need to clear it manually when stopping the stream.
Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
diff --git a/sound/firewire/dice.c b/sound/firewire/dice.c
index 59d5ca4..cfa98a8 100644
--- a/sound/firewire/dice.c
+++ b/sound/firewire/dice.c
@@ -246,6 +246,9 @@
{
__be32 value;
+ if (!dice->global_enabled)
+ return;
+
value = 0;
snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
global_address(dice, GLOBAL_ENABLE),
@@ -1009,6 +1012,8 @@
* manner.
*/
amdtp_out_stream_pcm_abort(&dice->stream);
+
+ dice->global_enabled = false;
dice_stream_stop_packets(dice);
dice_owner_update(dice);