| Hisilicon Platforms Device Tree Bindings |
| ---------------------------------------------------- |
| Hi6220 SoC |
| Required root node properties: |
| - compatible = "hisilicon,hi6220"; |
| |
| Hi4511 Board |
| Required root node properties: |
| - compatible = "hisilicon,hi3620-hi4511"; |
| |
| HiP04 D01 Board |
| Required root node properties: |
| - compatible = "hisilicon,hip04-d01"; |
| |
| HiP01 ca9x2 Board |
| Required root node properties: |
| - compatible = "hisilicon,hip01-ca9x2"; |
| |
| HiKey Board |
| Required root node properties: |
| - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; |
| |
| HiP05 D02 Board |
| Required root node properties: |
| - compatible = "hisilicon,hip05-d02"; |
| |
| Hisilicon system controller |
| |
| Required properties: |
| - compatible : "hisilicon,sysctrl" |
| - reg : Register address and size |
| |
| Optional properties: |
| - smp-offset : offset in sysctrl for notifying slave cpu booting |
| cpu 1, reg; |
| cpu 2, reg + 0x4; |
| cpu 3, reg + 0x8; |
| If reg value is not zero, cpun exit wfi and go |
| - resume-offset : offset in sysctrl for notifying cpu0 when resume |
| - reboot-offset : offset in sysctrl for system reboot |
| |
| Example: |
| |
| /* for Hi3620 */ |
| sysctrl: system-controller@fc802000 { |
| compatible = "hisilicon,sysctrl"; |
| reg = <0xfc802000 0x1000>; |
| smp-offset = <0x31c>; |
| resume-offset = <0x308>; |
| reboot-offset = <0x4>; |
| }; |
| |
| ----------------------------------------------------------------------- |
| Hisilicon Hi6220 system controller |
| |
| Required properties: |
| - compatible : "hisilicon,hi6220-sysctrl" |
| - reg : Register address and size |
| - #clock-cells: should be set to 1, many clock registers are defined |
| under this controller and this property must be present. |
| |
| Hisilicon designs this controller as one of the system controllers, |
| its main functions are the same as Hisilicon system controller, but |
| the register offset of some core modules are different. |
| |
| Example: |
| /*for Hi6220*/ |
| sys_ctrl: sys_ctrl@f7030000 { |
| compatible = "hisilicon,hi6220-sysctrl", "syscon"; |
| reg = <0x0 0xf7030000 0x0 0x2000>; |
| #clock-cells = <1>; |
| }; |
| |
| |
| Hisilicon Hi6220 Power Always ON domain controller |
| |
| Required properties: |
| - compatible : "hisilicon,hi6220-aoctrl" |
| - reg : Register address and size |
| - #clock-cells: should be set to 1, many clock registers are defined |
| under this controller and this property must be present. |
| |
| Hisilicon designs this system controller to control the power always |
| on domain for mobile platform. |
| |
| Example: |
| /*for Hi6220*/ |
| ao_ctrl: ao_ctrl@f7800000 { |
| compatible = "hisilicon,hi6220-aoctrl", "syscon"; |
| reg = <0x0 0xf7800000 0x0 0x2000>; |
| #clock-cells = <1>; |
| }; |
| |
| |
| Hisilicon Hi6220 Media domain controller |
| |
| Required properties: |
| - compatible : "hisilicon,hi6220-mediactrl" |
| - reg : Register address and size |
| - #clock-cells: should be set to 1, many clock registers are defined |
| under this controller and this property must be present. |
| |
| Hisilicon designs this system controller to control the multimedia |
| domain(e.g. codec, G3D ...) for mobile platform. |
| |
| Example: |
| /*for Hi6220*/ |
| media_ctrl: media_ctrl@f4410000 { |
| compatible = "hisilicon,hi6220-mediactrl", "syscon"; |
| reg = <0x0 0xf4410000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| |
| Hisilicon Hi6220 Power Management domain controller |
| |
| Required properties: |
| - compatible : "hisilicon,hi6220-pmctrl" |
| - reg : Register address and size |
| - #clock-cells: should be set to 1, some clock registers are define |
| under this controller and this property must be present. |
| |
| Hisilicon designs this system controller to control the power management |
| domain for mobile platform. |
| |
| Example: |
| /*for Hi6220*/ |
| pm_ctrl: pm_ctrl@f7032000 { |
| compatible = "hisilicon,hi6220-pmctrl", "syscon"; |
| reg = <0x0 0xf7032000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| |
| Hisilicon Hi6220 SRAM controller |
| |
| Required properties: |
| - compatible : "hisilicon,hi6220-sramctrl", "syscon" |
| - reg : Register address and size |
| |
| Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several |
| SRAM banks for power management, modem, security, etc. Further, use "syscon" |
| managing the common sram which can be shared by multiple modules. |
| |
| Example: |
| /*for Hi6220*/ |
| sram: sram@fff80000 { |
| compatible = "hisilicon,hi6220-sramctrl", "syscon"; |
| reg = <0x0 0xfff80000 0x0 0x12000>; |
| }; |
| |
| ----------------------------------------------------------------------- |
| Hisilicon HiP01 system controller |
| |
| Required properties: |
| - compatible : "hisilicon,hip01-sysctrl" |
| - reg : Register address and size |
| |
| The HiP01 system controller is mostly compatible with hisilicon |
| system controller,but it has some specific control registers for |
| HIP01 SoC family, such as slave core boot, and also some same |
| registers located at different offset. |
| |
| Example: |
| |
| /* for hip01-ca9x2 */ |
| sysctrl: system-controller@10000000 { |
| compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; |
| reg = <0x10000000 0x1000>; |
| reboot-offset = <0x4>; |
| }; |
| |
| ----------------------------------------------------------------------- |
| Hisilicon HiP05 PCIe-SAS system controller |
| |
| Required properties: |
| - compatible : "hisilicon,pcie-sas-subctrl", "syscon"; |
| - reg : Register address and size |
| |
| The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in |
| HiP05 Soc to implement some basic configurations. |
| |
| Example: |
| /* for HiP05 PCIe-SAS system */ |
| pcie_sas: system_controller@0xb0000000 { |
| compatible = "hisilicon,pcie-sas-subctrl", "syscon"; |
| reg = <0xb0000000 0x10000>; |
| }; |
| |
| Hisilicon HiP05 PERISUB system controller |
| |
| Required properties: |
| - compatible : "hisilicon,hip05-perisubc", "syscon"; |
| - reg : Register address and size |
| |
| The HiP05 PERISUB system controller is shared by peripheral controllers in |
| HiP05 Soc to implement some basic configurations. The peripheral |
| controllers include mdio, ddr, iic, uart, timer and so on. |
| |
| Example: |
| /* for HiP05 perisub-ctrl-c system */ |
| peri_c_subctrl: syscon@80000000 { |
| compatible = "hisilicon,hip05-perisubc", "syscon"; |
| reg = <0x0 0x80000000 0x0 0x10000>; |
| }; |
| ----------------------------------------------------------------------- |
| Hisilicon CPU controller |
| |
| Required properties: |
| - compatible : "hisilicon,cpuctrl" |
| - reg : Register address and size |
| |
| The clock registers and power registers of secondary cores are defined |
| in CPU controller, especially in HIX5HD2 SoC. |
| |
| ----------------------------------------------------------------------- |
| PCTRL: Peripheral misc control register |
| |
| Required Properties: |
| - compatible: "hisilicon,pctrl" |
| - reg: Address and size of pctrl. |
| |
| Example: |
| |
| /* for Hi3620 */ |
| pctrl: pctrl@fca09000 { |
| compatible = "hisilicon,pctrl"; |
| reg = <0xfca09000 0x1000>; |
| }; |
| |
| ----------------------------------------------------------------------- |
| Fabric: |
| |
| Required Properties: |
| - compatible: "hisilicon,hip04-fabric"; |
| - reg: Address and size of Fabric |
| |
| ----------------------------------------------------------------------- |
| Bootwrapper boot method (software protocol on SMP): |
| |
| Required Properties: |
| - compatible: "hisilicon,hip04-bootwrapper"; |
| - boot-method: Address and size of boot method. |
| [0]: bootwrapper physical address |
| [1]: bootwrapper size |
| [2]: relocation physical address |
| [3]: relocation size |