tree ef3481a81d2caeac6daab5528db2abca56fb986b
parent 88411dea0f4e01896b902568f94c03266be9f666
author Jerome Brunet <jbrunet@baylibre.com> 1503930543 +0200
committer Ulf Hansson <ulf.hansson@linaro.org> 1504098226 +0200

mmc: meson-gx: initialize sane clk default before clock register

On boot, the clock divider value is 0 which is a weird unsupported value.
For example, accessing the cfg register with this value set would crash
the SoC.

Previous change removed 0 as possible value for CCF but forgot to properly
initialize the register before registering the clock. This leads to the
CCF finding an illegal value, which it complains about.

Initialize the register properly in a standalone patch so the fix can be
picked up if necessary. The change this fixed is: "mmc: meson-gx: remove
CLK_DIVIDER_ALLOW_ZERO clock flag".

Reported-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>