| commit | ef833eab1ddec06982ea620086b03d67ef4ddf9b | [log] [tgz] |
|---|---|---|
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | Mon Sep 04 12:48:43 2017 +0300 |
| committer | Vineet Gupta <vgupta@synopsys.com> | Tue Oct 03 20:36:49 2017 -0700 |
| tree | 6d96b27c0b4e90d107c7ecf5a0853364d01a9402 | |
| parent | 9583833e9e3628177661e815e5ce80dd3955d82f [diff] |
ARC: [plat-hsdk] use actual clk driver to manage cpu clk With corresponding clk driver now merged upstream, switch to it. - core_clk now represent the PLL (vs. fixed clk before) - input_clk represent the clk signal src for PLL (basically xtal) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>