tree af3fb6ce32ed79649ee2f8ce76cd3f82ddb02675
parent 67d1c0a25c05e2105d12abd9c0172d2d5c0e7654
author Alexandre Courbot <acourbot@nvidia.com> 1452826404 +0900
committer Ben Skeggs <bskeggs@redhat.com> 1457914266 +1000

drm/nouveau/ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait

Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit
of the CTRL1 register instead of writing it entirely in
gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also
be modified to wait on that single bit only, otherwise a timeout may
occur if some other bit of that register is set. This happened at least
on GM206 when running glmark2-drm.

While we are at it, use the more compact nvkm_wait_msec() to wait for
the bit to clear.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>