tree b4e6aec3ce3765f5c6692abec131768ffa8110bc
parent 934fe5f48ae52841f8a5f5e0411147a8ccd171c1
author Chen-Yu Tsai <wens@csie.org> 1427217728 +0800
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1427309201 -0700

clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6

The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>