| commit | f2032f24c0e51487d88c3555db12e27d561e4f14 | [log] [tgz] |
|---|---|---|
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | Wed Aug 19 14:49:26 2015 +0900 |
| committer | Olof Johansson <olof@lixom.net> | Thu Aug 20 18:28:39 2015 -0700 |
| tree | d7b2cf20932073c6c7589a4d2b94dddffaaf2166 | |
| parent | 62060a3548c5ea038b4ade518cce92be32a6718d [diff] |
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings document says that the bits[15:8] of the 3rd cell of the interrupts property represents PPI interrupt CPU mask. Because the timer interrupts are wired to all of the 4 cores, bits[15:8] should be set to 0xf. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>