| commit | f2131d348f0bd252801f641018a90d59c987ce48 | [log] [tgz] |
|---|---|---|
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | Thu Feb 08 20:46:20 2007 +0000 |
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | Thu Feb 08 20:46:20 2007 +0000 |
| tree | 536676e6189742b0c268c5bfcc3f55dd7f5b00c3 | |
| parent | 3e1a80f11f89f318e892694b501735abb51ef626 [diff] |
[ARM] Always mark ARMv6 PTWs outer cacheable Other platforms other than SMP may have an outer cache. For these, we also need to mark the page table walks outer cacheable. Since marking the walks always outer cacheable apparantly has no side effects, we might as well always mark them so. However, we continue to only mark PTWs shared if we have SMP enabled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>