stmmac: move stmmac_clk, pclk, clk_ptp_ref and stmmac_rst to platform structure
This patch moves stmmac_clk, pclk, clk_ptp_ref and stmmac_rst to the
plat_stmmacenet_data structure. It also moves these platform variables
initialization to stmmac_platform. This was done for two reasons:
a) If PCI is used, platform related code is being executed in stmmac_main
resulting in warnings that have no sense and conceptually was not right
b) stmmac as a synopsys reference ethernet driver stack will be hosting
more and more drivers to its structure like synopsys/dwc_eth_qos.c.
These drivers have their own DT bindings that are not compatible with
stmmac's. One of the most important are the clock names, and so they need
to be parsed in the glue logic and initialized there, and that is the main
reason why the clocks were passed to the platform structure.
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Tested-by: Niklas Cassel <niklas.cassel@axis.com>
Reviewed-by: Lars Persson <larper@axis.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index fa0b4de..02808e8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -158,7 +158,7 @@
{
u32 clk_rate;
- clk_rate = clk_get_rate(priv->stmmac_clk);
+ clk_rate = clk_get_rate(priv->plat->stmmac_clk);
/* Platform provided default clk_csr would be assumed valid
* for all other cases except for the below mentioned ones.
@@ -607,7 +607,7 @@
/* program Sub Second Increment reg */
sec_inc = priv->hw->ptp->config_sub_second_increment(
- priv->ptpaddr, priv->clk_ptp_rate,
+ priv->ptpaddr, priv->plat->clk_ptp_rate,
priv->plat->has_gmac4);
temp = div_u64(1000000000ULL, sec_inc);
@@ -617,7 +617,7 @@
* where, freq_div_ratio = 1e9ns/sec_inc
*/
temp = (u64)(temp << 32);
- priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
+ priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
priv->hw->ptp->config_addend(priv->ptpaddr,
priv->default_addend);
@@ -645,18 +645,6 @@
if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
return -EOPNOTSUPP;
- /* Fall-back to main clock in case of no PTP ref is passed */
- priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
- if (IS_ERR(priv->clk_ptp_ref)) {
- priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
- priv->clk_ptp_ref = NULL;
- netdev_dbg(priv->dev, "PTP uses main clock\n");
- } else {
- clk_prepare_enable(priv->clk_ptp_ref);
- priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
- netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
- }
-
priv->adv_ts = 0;
/* Check if adv_ts can be enabled for dwmac 4.x core */
if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
@@ -683,8 +671,8 @@
static void stmmac_release_ptp(struct stmmac_priv *priv)
{
- if (priv->clk_ptp_ref)
- clk_disable_unprepare(priv->clk_ptp_ref);
+ if (priv->plat->clk_ptp_ref)
+ clk_disable_unprepare(priv->plat->clk_ptp_ref);
stmmac_ptp_unregister(priv);
}
@@ -3278,44 +3266,8 @@
if ((phyaddr >= 0) && (phyaddr <= 31))
priv->plat->phy_addr = phyaddr;
- priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
- if (IS_ERR(priv->stmmac_clk)) {
- netdev_warn(priv->dev, "%s: warning: cannot get CSR clock\n",
- __func__);
- /* If failed to obtain stmmac_clk and specific clk_csr value
- * is NOT passed from the platform, probe fail.
- */
- if (!priv->plat->clk_csr) {
- ret = PTR_ERR(priv->stmmac_clk);
- goto error_clk_get;
- } else {
- priv->stmmac_clk = NULL;
- }
- }
- clk_prepare_enable(priv->stmmac_clk);
-
- priv->pclk = devm_clk_get(priv->device, "pclk");
- if (IS_ERR(priv->pclk)) {
- if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
- ret = -EPROBE_DEFER;
- goto error_pclk_get;
- }
- priv->pclk = NULL;
- }
- clk_prepare_enable(priv->pclk);
-
- priv->stmmac_rst = devm_reset_control_get(priv->device,
- STMMAC_RESOURCE_NAME);
- if (IS_ERR(priv->stmmac_rst)) {
- if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
- ret = -EPROBE_DEFER;
- goto error_hw_init;
- }
- dev_info(priv->device, "no reset control found\n");
- priv->stmmac_rst = NULL;
- }
- if (priv->stmmac_rst)
- reset_control_deassert(priv->stmmac_rst);
+ if (priv->plat->stmmac_rst)
+ reset_control_deassert(priv->plat->stmmac_rst);
/* Init MAC and get the capabilities */
ret = stmmac_hw_init(priv);
@@ -3409,10 +3361,6 @@
error_mdio_register:
netif_napi_del(&priv->napi);
error_hw_init:
- clk_disable_unprepare(priv->pclk);
-error_pclk_get:
- clk_disable_unprepare(priv->stmmac_clk);
-error_clk_get:
free_netdev(ndev);
return ret;
@@ -3438,10 +3386,10 @@
stmmac_set_mac(priv->ioaddr, false);
netif_carrier_off(ndev);
unregister_netdev(ndev);
- if (priv->stmmac_rst)
- reset_control_assert(priv->stmmac_rst);
- clk_disable_unprepare(priv->pclk);
- clk_disable_unprepare(priv->stmmac_clk);
+ if (priv->plat->stmmac_rst)
+ reset_control_assert(priv->plat->stmmac_rst);
+ clk_disable_unprepare(priv->plat->pclk);
+ clk_disable_unprepare(priv->plat->stmmac_clk);
if (priv->hw->pcs != STMMAC_PCS_RGMII &&
priv->hw->pcs != STMMAC_PCS_TBI &&
priv->hw->pcs != STMMAC_PCS_RTBI)
@@ -3490,8 +3438,8 @@
stmmac_set_mac(priv->ioaddr, false);
pinctrl_pm_select_sleep_state(priv->device);
/* Disable clock in case of PWM is off */
- clk_disable(priv->pclk);
- clk_disable(priv->stmmac_clk);
+ clk_disable(priv->plat->pclk);
+ clk_disable(priv->plat->stmmac_clk);
}
spin_unlock_irqrestore(&priv->lock, flags);
@@ -3531,8 +3479,8 @@
} else {
pinctrl_pm_select_default_state(priv->device);
/* enable the clk prevously disabled */
- clk_enable(priv->stmmac_clk);
- clk_enable(priv->pclk);
+ clk_enable(priv->plat->stmmac_clk);
+ clk_enable(priv->plat->pclk);
/* reset the phy so that it's ready */
if (priv->mii)
stmmac_mdio_reset(priv->mii);