MIPS: math-emu: Set FIR feature flags for full emulation
Implement FIR feature flags in the FPU emulator according to features
supported and architecture level requirements. The W, L and F64 bits
have only been added at level #2 even though the features they refer to
were also included with the MIPS64r1 ISA and the W fixed-point format
also with the MIPS32r1 ISA.
This is only relevant for the full emulation mode and the emulated CFC1
instruction as well as ptrace(2) accesses.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9707/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index acfef06..7aa42b2 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -45,6 +45,7 @@
#include <asm/signal.h>
#include <asm/uaccess.h>
+#include <asm/cpu-info.h>
#include <asm/processor.h>
#include <asm/fpu_emulator.h>
#include <asm/fpu.h>
@@ -853,7 +854,7 @@
(void *)xcp->cp0_epc,
MIPSInst_RT(ir), value);
} else if (MIPSInst_RD(ir) == FPCREG_RID)
- value = 0;
+ value = current_cpu_data.fpu_id;
else
value = 0;
if (MIPSInst_RT(ir))