commit f77f13e22df4a40d237697df496152c8c37f3f2b
author Gilles Espinasse <g.esp@free.fr> Mon Mar 29 15:41:47 2010 +0200
committer Jiri Kosina <jkosina@suse.cz> Mon Mar 29 15:41:47 2010 +0200
tree beccbb0214078d68027f7a17b57be556292475bd
parent 5239c4ff4ae9e810ba761518ad71b463f0ccbf3c

Fix comment and Kconfig typos for 'require' and 'fragment'

Signed-off-by: Gilles Espinasse <g.esp@free.fr>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>

arch/mips/sibyte/bcm1480/irq.c

diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 06e25d9..3fbb033 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -254,7 +254,7 @@
  * On the second cpu, everything is set to IP5, which is
  * ignored, EXCEPT the mailbox interrupt.  That one is
  * set to IP[2] so it is handled.  This is needed so we
- * can do cross-cpu function calls, as requred by SMP
+ * can do cross-cpu function calls, as required by SMP
  */
 
 #define IMR_IP2_VAL	K_BCM1480_INT_MAP_I0

arch/mips/sibyte/sb1250/irq.c

diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index ab44a2f..b452e3c 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -237,7 +237,7 @@
  * On the second cpu, everything is set to IP5, which is
  * ignored, EXCEPT the mailbox interrupt.  That one is
  * set to IP[2] so it is handled.  This is needed so we
- * can do cross-cpu function calls, as requred by SMP
+ * can do cross-cpu function calls, as required by SMP
  */
 
 #define IMR_IP2_VAL	K_INT_MAP_I0